From newsfish@newsfish Wed Aug 19 13:23:38 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: oktem@su.sabanciuniv.edu Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register Date: Thu, 5 Mar 2009 01:07:04 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236244024 20382 127.0.0.1 (5 Mar 2009 09:07:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Mar 2009 09:07:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:591 On Mar 4, 5:40=A0pm, Ken Cecka wrote: > ok...@su.sabanciuniv.edu wrote: > > I want to automatically put the current date (year,month,day maybe > > hour) in a 32 bit register during the synthesis stage. I am using > > Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target > > fpga is Spartan 3. > > > Can someone explain me is there an easy way to implement? > > I add a timestamp like this to my builds by generating a package in the m= akefile I drive the build with. =A0Here's an excerpt: > > version.vhd: Makefile > =A0 =A0 =A0 =A0 @echo "generating $@" > =A0 =A0 =A0 =A0 @rm -f $@ > =A0 =A0 =A0 =A0 @echo "PACKAGE version IS" > $@ > =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_DESIGN =A0 =A0: INTEGER :=3D $(= VER_DESIGN);" >> $@ > =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MAJOR =A0 =A0 : INTEGER :=3D $(= VER_MAJOR);" >> $@ > =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MINOR =A0 =A0 : INTEGER :=3D $(= VER_MINOR);" >> $@ > =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_REV =A0 =A0 =A0 : INTEGER :=3D = $(VER_REV);" >> $@ > =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_TIMESTAMP : INTEGER :=3D $(shel= l date +%s);">> $@ > =A0 =A0 =A0 =A0 @echo "END version;" >> $@ > > The C_VER_TIMESTAMP is a constant containing the number of seconds since = the epoch (1970-01-01 00:00:00 GMT). > > This only guarantees an up-to-date timestamp if I build with make. =A0Whe= n I'm building from an ISE project, all bets are off. > > Ken Now i have a tcl script which takes current date and convert it to a binary I can run this tcl script from the tcl shell menu of xilinx project navigator I added a generic current_date variable on my top module I added this varible to generics, parameters part of Synthesis Options menu of Xilinx. So everythime i want to synthesize, I need to run the tcl script, get the output of the function, copy and paste it to the current_date at the generics tab of synthesis options and run. Actually I was not able to do it with the makefile approach since it seems harder for me. I need a little more explanation. best regards From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 05 Mar 2009 03:26:08 -0600 Date: Thu, 05 Mar 2009 09:26:06 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 74 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-J5fEtjUGGrAK5oOR7WBnaqjUhh5DLl20GZdOWvOMC7zzy21Xdp1woc+WbigT1Ddg8CBWrJcFkPlV4Di!aSNn6U80PhNevihdixBmsYAbx3nhaNqgOdvMZJPwm0q+OiVRC01Vyfk4e9YQ3iexPhuZeo4Ziz6k!LelfAHC2cjA= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:592 oktem@su.sabanciuniv.edu wrote: > On Mar 4, 5:40 pm, Ken Cecka wrote: >> ok...@su.sabanciuniv.edu wrote: >>> I want to automatically put the current date (year,month,day maybe >>> hour) in a 32 bit register during the synthesis stage. I am using >>> Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target >>> fpga is Spartan 3. >>> Can someone explain me is there an easy way to implement? >> I add a timestamp like this to my builds by generating a package in the makefile I drive the build with. Here's an excerpt: >> >> version.vhd: Makefile >> @echo "generating $@" >> @rm -f $@ >> @echo "PACKAGE version IS" > $@ >> @echo " CONSTANT C_VER_DESIGN : INTEGER := $(VER_DESIGN);" >> $@ >> @echo " CONSTANT C_VER_MAJOR : INTEGER := $(VER_MAJOR);" >> $@ >> @echo " CONSTANT C_VER_MINOR : INTEGER := $(VER_MINOR);" >> $@ >> @echo " CONSTANT C_VER_REV : INTEGER := $(VER_REV);" >> $@ >> @echo " CONSTANT C_VER_TIMESTAMP : INTEGER := $(shell date +%s);">> $@ >> @echo "END version;" >> $@ >> >> The C_VER_TIMESTAMP is a constant containing the number of seconds since the epoch (1970-01-01 00:00:00 GMT). >> >> This only guarantees an up-to-date timestamp if I build with make. When I'm building from an ISE project, all bets are off. >> >> Ken > > Now i have a tcl script which takes current date and convert it to a > binary > I can run this tcl script from the tcl shell menu of xilinx project > navigator > I added a generic current_date variable on my top module > I added this varible to generics, parameters part of Synthesis Options > menu of Xilinx. > > So everythime i want to synthesize, I need to run the tcl script, get > the output of the function, copy and paste it to the current_date at > the generics tab of synthesis options and run. > Actually I was not able to do it with the makefile approach since it > seems harder for me. I need a little more explanation. > > best regards > You can set the generics within ISE using the Xilinx specific Tcl command project set "Generics, Parameters" "Max=10" -process "Synthesize - XST" where Max is an integer generic with the value 10. If your generic is a string, you'll need to work out the quoting syntax. If you want to see how Xilinx has stored your generic, export your project settings using the ISE menu Project > Generate Tcl Script... You can then put your own Tcl script at the front to generate the time value, and then run it using the command xtclsh script.tcl xtclsh is the Xilinx Tcl interpreter, which understands the Xilinx Tcl extensions, as well as plain Tcl. regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v6g2000vbb.googlegroups.com!not-for-mail From: oktem@su.sabanciuniv.edu Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register Date: Thu, 5 Mar 2009 02:22:43 -0800 (PST) Organization: http://groups.google.com Lines: 100 Message-ID: References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236248564 30314 127.0.0.1 (5 Mar 2009 10:22:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Mar 2009 10:22:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v6g2000vbb.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:593 On Mar 5, 11:26=A0am, Alan Fitch wrote: > ok...@su.sabanciuniv.edu wrote: > > On Mar 4, 5:40 pm, Ken Cecka wrote: > >> ok...@su.sabanciuniv.edu wrote: > >>> I want to automatically put the current date (year,month,day maybe > >>> hour) in a 32 bit register during the synthesis stage. I am using > >>> Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target > >>> fpga is Spartan 3. > >>> Can someone explain me is there an easy way to implement? > >> I add a timestamp like this to my builds by generating a package in th= e makefile I drive the build with. =A0Here's an excerpt: > > >> version.vhd: Makefile > >> =A0 =A0 =A0 =A0 @echo "generating $@" > >> =A0 =A0 =A0 =A0 @rm -f $@ > >> =A0 =A0 =A0 =A0 @echo "PACKAGE version IS" > $@ > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_DESIGN =A0 =A0: INTEGER :=3D= $(VER_DESIGN);" >> $@ > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MAJOR =A0 =A0 : INTEGER :=3D= $(VER_MAJOR);" >> $@ > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MINOR =A0 =A0 : INTEGER :=3D= $(VER_MINOR);" >> $@ > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_REV =A0 =A0 =A0 : INTEGER := =3D $(VER_REV);" >> $@ > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_TIMESTAMP : INTEGER :=3D $(s= hell date +%s);">> $@ > >> =A0 =A0 =A0 =A0 @echo "END version;" >> $@ > > >> The C_VER_TIMESTAMP is a constant containing the number of seconds sin= ce the epoch (1970-01-01 00:00:00 GMT). > > >> This only guarantees an up-to-date timestamp if I build with make. =A0= When I'm building from an ISE project, all bets are off. > > >> Ken > > > Now i have a tcl script which takes current date and convert it to a > > binary > > I can run this tcl script from the tcl shell menu of xilinx project > > navigator > > I added a generic current_date variable on my top module > > I added this varible to generics, parameters part of Synthesis Options > > menu of Xilinx. > > > So everythime i want to synthesize, I need to run the tcl script, get > > the output of the function, copy and paste it to the current_date at > > the generics tab of synthesis options and run. > > Actually I was not able to do it with the makefile approach since it > > seems harder for me. I need a little more explanation. > > > best regards > > You can set the generics within ISE using the Xilinx specific Tcl command > > project set "Generics, Parameters" "Max=3D10" -process "Synthesize - XST" > > where Max is an integer generic with the value 10. > > If your generic is a string, you'll need to work out the quoting syntax. > If you want to see how Xilinx has stored your generic, export your > project settings using the ISE menu > > Project > Generate Tcl Script... > > You can then put your own Tcl script at the front to generate the time > value, and then run it using the command > > xtclsh script.tcl > > xtclsh is the Xilinx Tcl interpreter, which understands the Xilinx Tcl > extensions, as well as plain Tcl. > > regards > Alan > > -- > Alan Fitch > Douloshttp://www.doulos.com Project > Generate Tcl Script... You can then put your own Tcl script at the front to generate the time value, and then run it using the command Regarding this statement I have some newbie questions so when go to ISE menu > project > create a Tcl script to regenerate the project file 1- Do i have to exclude anything from the export list. There is a vhd file,my tcl script,there is a ncd file and lastly a timesim_vhw file. 2- What difference does it make if I add output files and add report files. 3- After I finish exporting I noticed an import.tcl and an export tcl file in my project directory. Should I run these from the tcl shell menu of project navigator. What do I do with these files. If I run these files is it posible to not copy paste the date for each synthesis I started using tcl yesterday so sorry for the foolish questions. From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!f33g2000vbf.googlegroups.com!not-for-mail From: oktem@su.sabanciuniv.edu Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register Date: Thu, 5 Mar 2009 02:55:41 -0800 (PST) Organization: http://groups.google.com Lines: 122 Message-ID: <21069658-0d5f-447c-84af-7b20a2781cea@f33g2000vbf.googlegroups.com> References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236250541 8868 127.0.0.1 (5 Mar 2009 10:55:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Mar 2009 10:55:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000vbf.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:594 On Mar 5, 12:22=A0pm, ok...@su.sabanciuniv.edu wrote: > On Mar 5, 11:26=A0am, Alan Fitch wrote: > > > > > ok...@su.sabanciuniv.edu wrote: > > > On Mar 4, 5:40 pm, Ken Cecka wrote: > > >> ok...@su.sabanciuniv.edu wrote: > > >>> I want to automatically put the current date (year,month,day maybe > > >>> hour) in a 32 bit register during the synthesis stage. I am using > > >>> Modelsim as a simulator and Xilinx Xst as a synthesis tool. My targ= et > > >>> fpga is Spartan 3. > > >>> Can someone explain me is there an easy way to implement? > > >> I add a timestamp like this to my builds by generating a package in = the makefile I drive the build with. =A0Here's an excerpt: > > > >> version.vhd: Makefile > > >> =A0 =A0 =A0 =A0 @echo "generating $@" > > >> =A0 =A0 =A0 =A0 @rm -f $@ > > >> =A0 =A0 =A0 =A0 @echo "PACKAGE version IS" > $@ > > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_DESIGN =A0 =A0: INTEGER := =3D $(VER_DESIGN);" >> $@ > > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MAJOR =A0 =A0 : INTEGER := =3D $(VER_MAJOR);" >> $@ > > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_MINOR =A0 =A0 : INTEGER := =3D $(VER_MINOR);" >> $@ > > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_REV =A0 =A0 =A0 : INTEGER = :=3D $(VER_REV);" >> $@ > > >> =A0 =A0 =A0 =A0 @echo " =A0CONSTANT C_VER_TIMESTAMP : INTEGER :=3D $= (shell date +%s);">> $@ > > >> =A0 =A0 =A0 =A0 @echo "END version;" >> $@ > > > >> The C_VER_TIMESTAMP is a constant containing the number of seconds s= ince the epoch (1970-01-01 00:00:00 GMT). > > > >> This only guarantees an up-to-date timestamp if I build with make. = =A0When I'm building from an ISE project, all bets are off. > > > >> Ken > > > > Now i have a tcl script which takes current date and convert it to a > > > binary > > > I can run this tcl script from the tcl shell menu of xilinx project > > > navigator > > > I added a generic current_date variable on my top module > > > I added this varible to generics, parameters part of Synthesis Option= s > > > menu of Xilinx. > > > > So everythime i want to synthesize, I need to run the tcl script, get > > > the output of the function, copy and paste it to the current_date at > > > the generics tab of synthesis options and run. > > > Actually I was not able to do it with the makefile approach since it > > > seems harder for me. I need a little more explanation. > > > > best regards > > > You can set the generics within ISE using the Xilinx specific Tcl comma= nd > > > project set "Generics, Parameters" "Max=3D10" -process "Synthesize - XS= T" > > > where Max is an integer generic with the value 10. > > > If your generic is a string, you'll need to work out the quoting syntax= . > > If you want to see how Xilinx has stored your generic, export your > > project settings using the ISE menu > > > Project > Generate Tcl Script... > > > You can then put your own Tcl script at the front to generate the time > > value, and then run it using the command > > > xtclsh script.tcl > > > xtclsh is the Xilinx Tcl interpreter, which understands the Xilinx Tcl > > extensions, as well as plain Tcl. > > > regards > > Alan > > > -- > > Alan Fitch > > Douloshttp://www.doulos.com > > =A0Project > Generate Tcl Script... > =A0You can then put your own Tcl script at the front to generate the > time value, and then run it using the command > > =A0Regarding this statement I have some newbie questions > > =A0so when go to ISE menu > project > create a Tcl script to regenerate > the project file > 1- Do i have to =A0exclude anything from the export list. There is a vhd > file,my tcl script,there is a ncd file and lastly a timesim_vhw file. > 2- What difference does it make if I add output files and add report > files. > 3- After I finish exporting I noticed an import.tcl and an export tcl > file in my project directory. Should I run these from the tcl shell > menu of project navigator. What do I do with these files. If I run > these files is it posible to not copy paste the date for each > synthesis > > I started using tcl yesterday so sorry for the foolish questions. I put this line project set "Generics, Parameters" "ID=3Dmy_date" -process "Synthesize - XST" at the end of my tcl script so that i do not have to copy and paste it everytime. so now i need to undertand these import.tcl and export.tcl files. Also im having problem with integer to binary conversion. Is there a tcl function that I can determine the width of the output. if I convert 3 to binary can I get an output of exactly 4 bits like this (0011) not 2 bits (11) or 8 bits (00000011) or 32 bits (00000000000000000000000000000011) From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 05 Mar 2009 07:50:00 -0600 Date: Thu, 05 Mar 2009 13:50:07 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 69 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-DZr4XoDIy3lQNcXQnREhUEbrx+Hwf1/946oX0q7NYS9USNo1fQF8Iz2Izd8IbZw9680/9L0Lz6Ygwtu!GiB0Bh+aGJ1A2WtG7dhXTmDVbnVGH3ZRD5/NmAHYBI55rJapJYk7Ze06eMt6D02G08nrPmoqr9w8!wJsO8EiYSRI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:595 oktem@su.sabanciuniv.edu wrote: >> You can set the generics within ISE using the Xilinx specific Tcl command >> >> project set "Generics, Parameters" "Max=10" -process "Synthesize - XST" >> >> where Max is an integer generic with the value 10. >> >> If your generic is a string, you'll need to work out the quoting syntax. >> If you want to see how Xilinx has stored your generic, export your >> project settings using the ISE menu >> >> Project > Generate Tcl Script... >> >> You can then put your own Tcl script at the front to generate the time >> value, and then run it using the command >> >> xtclsh script.tcl >> >> xtclsh is the Xilinx Tcl interpreter, which understands the Xilinx Tcl >> extensions, as well as plain Tcl. > > > Project > Generate Tcl Script... > You can then put your own Tcl script at the front to generate the > time value, and then run it using the command > > Regarding this statement I have some newbie questions > > so when go to ISE menu > project > create a Tcl script to regenerate > the project file > 1- Do i have to exclude anything from the export list. There is a vhd > file,my tcl script,there is a ncd file and lastly a timesim_vhw file. I don't know - I don't seem to see those options. I'm running 10.1 SP3 though. > 2- What difference does it make if I add output files and add report > files. Sorry I don't know. > 3- After I finish exporting I noticed an import.tcl and an export tcl > file in my project directory. Should I run these from the tcl shell > menu of project navigator. What do I do with these files. If I run > these files is it posible to not copy paste the date for each > synthesis > That just sounds different - which version of Xilinx are you using? You might just have to look in the help - I found the Generate Tcl Script option was not available in the pdf help, I had to look in the help from the Xilinx GUI i.e. use menu Help > Help Topics then follow the struction Getting Started Using Project Navigator Working with Projects Generating a Tcl script regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.ycache.com!ihunger.news.ycache.com!news.ycache.com!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 05 Mar 2009 07:54:24 -0600 Date: Thu, 05 Mar 2009 13:54:32 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> <21069658-0d5f-447c-84af-7b20a2781cea@f33g2000vbf.googlegroups.com> In-Reply-To: <21069658-0d5f-447c-84af-7b20a2781cea@f33g2000vbf.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 32 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Ewnm/e/m2n8anQQv5cf84nqkYT9vxxTN9S6gfniofhahghPf4FX40IJ/6qdxlcr+nNvpYtKw8DYb+om!p6HBi1ROuSmuOVQyHnY9fVjKq0PR13XLuqg9xCT8ajNdTPOJky3JGdifda+zdUffu3haCh7IC6nD!IJEaz4aPJZs= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:596 oktem@su.sabanciuniv.edu wrote: > On Mar 5, 12:22 pm, ok...@su.sabanciuniv.edu wrote: > > I put this line > project set "Generics, Parameters" "ID=my_date" -process "Synthesize - > XST" > at the end of my tcl script so that i do not have to copy and paste it > everytime. > > so now i need to undertand these import.tcl and export.tcl files. > > Also im having problem with integer to binary conversion. Is there a > tcl function that I can determine the width of the output. if I > convert 3 to binary can I get an output of exactly 4 bits like this > (0011) not 2 bits (11) or 8 bits (00000011) or 32 bits > (00000000000000000000000000000011) You need format - see this page http://tmml.sourceforge.net/doc/tcl/format.html regards Alan P.S. I am not a Tcl expert - just to warn you... -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!c11g2000yqj.googlegroups.com!not-for-mail From: oktem@su.sabanciuniv.edu Newsgroups: comp.lang.vhdl Subject: Re: writing current date to a 32 bit register Date: Thu, 5 Mar 2009 06:01:23 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: <3f3341e9-0d58-413e-9048-f801e57b045d@c11g2000yqj.googlegroups.com> References: <0ixrl.1219$%u5.625@nwrddc01.gnilink.net> <21069658-0d5f-447c-84af-7b20a2781cea@f33g2000vbf.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236261683 12733 127.0.0.1 (5 Mar 2009 14:01:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Mar 2009 14:01:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c11g2000yqj.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:597 On Mar 5, 3:54=A0pm, Alan Fitch wrote: > ok...@su.sabanciuniv.edu wrote: > > On Mar 5, 12:22 pm, ok...@su.sabanciuniv.edu wrote: > > > I put this line > > project set "Generics, Parameters" "ID=3Dmy_date" -process "Synthesize = - > > XST" > > at the end of my tcl script so that i do not have to copy and paste it > > everytime. > > > so now i need to undertand these import.tcl and export.tcl files. > > > Also im having problem with integer to binary conversion. Is there a > > tcl function that I can determine the width of the output. if I > > convert 3 to binary can I get an output of exactly 4 bits like this > > (0011) not 2 bits (11) or 8 bits (00000011) or 32 bits > > (00000000000000000000000000000011) > > You need format - see this page > > http://tmml.sourceforge.net/doc/tcl/format.html > > regards > Alan > > P.S. I am not a Tcl expert - just to warn you... > > -- > Alan Fitch > Douloshttp://www.doulos.com Thank you Alan. It is very much appreciated. Serkan From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!i2g2000prd.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Writing Test Bench Date: Thu, 5 Mar 2009 13:23:29 -0800 (PST) Organization: http://groups.google.com Lines: 329 Message-ID: <6e8f994f-5edb-40a8-a895-54c61419c0d5@i2g2000prd.googlegroups.com> NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236288209 28390 127.0.0.1 (5 Mar 2009 21:23:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Mar 2009 21:23:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i2g2000prd.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:598 HI, I interfaced a USB device with the FPGA. The USB device outputs 8 bit of parallel data at the falling edge of the USB_CLK. The 8 bit port that carries that Data is called " USB_Data". I am trying to write the VHDL Test Bench for this code, but no luck. The 8 bit data gets valid at least 10 ns before the falling edge of the USB_CLK. Please advice! I was also thinking that may be I can build a text file with binary numbers that I want to send to USB_CLK but I do not know how will it work or how can I do that using ISE 10.1. The VHDL code and Test Bench are given below Thanks John My VHDL CODE : Library IEEE; USE IEEE.Std_logic_1164 .ALL; USE IEEE.Numeric_std .ALL; USE IEEE.STD_LOGIC_TEXTIO .ALL; --use ieee.numeric_bit.all; USE IEEE.std_logic_unsigned .all; Entity DPR_Writer is port ( Data_Bus : out std_logic_vector (13 downto 0 ); Address_bus : out std_logic_vector (18 downto 0 ); Read_write : out std_logic; Output_Enable : out std_logic; CE0 : out std_logic; CE1 : out std_logic; LBL : out std_logic; UBL : out std_logic; USB_Data : in std_logic_vector (7 downto 0 ); USB_CLK : in std_logic; ZZL : out std_logic:='0'; SEML : out std_logic; OPTL : in std_logic; Reset : in std_logic; Indicator_LED : out std_logic; State_status : out std_logic_vector ( 1 downto 0) ); End DPR_Writer; Architecture Writer of DPR_Writer is Signal State : std_logic_vector (1 downto 0); Signal Next_State : std_logic_vector(1 downto 0); Constant G0 :std_logic_vector (1 downto 0):="00"; Constant G1 : std_logic_vector (1 downto 0):="01"; Constant G2 : std_logic_vector (1 downto 0):="10"; Constant G3 : std_logic_vector(1 downto 0):="11"; Signal Incr : std_logic; Signal Stop : std_logic; Signal Counter : std_logic_vector ( 18 downto 0); Signal Ld_high : std_logic; Signal Ld_Low : std_logic; Signal Reset_out : std_logic; Signal incr_out : std_logic; Signal Ld_high_out : std_logic; Signal Ld_Low_out : std_logic; ------------------------------------ Begin --CE0 <= '0'; --CE1 <= '1'; CE0 <= Ld_high; CE1 <= Ld_Low; Output_Enable <= '1'; Read_write <= '0'; SEML <=Reset_out; Address_bus <= Counter; ZZL <= incr ; State_status <= State; ------------------------------------- State_Machine: Process (State) Begin Case State is When G0=> Ld_high <= '1'; Ld_Low <= '0'; --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 ); UBL <='0'; --1 old value LBL <='0'; --0 0ld value Next_State <=G1; -- Address Bus did not change When G1 => Incr <='0'; Ld_high <= '0'; Ld_Low <= '1'; --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 ); UBL <='0'; --0 old value LBL <='0'; --1 old value Next_State <=G2; -- Address Bus did not change When G2 => Incr <='1'; Ld_high <= '1'; Ld_Low <= '0'; --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 ); ---- Data_Bus ( 5 downto 0) <= USB_Data ( 5 downto 0 ); UBL <='0'; LBL <='0'; Next_State <=G3; -- Address Bus changes When G3 => Incr <='0'; Ld_high <= '0'; Ld_Low <= '1'; --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 ); ---- Data_Bus ( 13 downto 6) <= USB_Data ( 7 downto 0 ); UBL <='0'; LBL <='0'; Next_State <=G2; -- Address Bus did not change When others => Next_State <=G0; End case; End Process; ---------------------------------------- FSM : Process (USB_CLK,Reset_out) Begin If ( Reset_out= '1' ) Then Indicator_LED <= '1'; State <= G0; elsIf (USB_CLK 'Event And USB_CLK = '1')Then Indicator_LED <= '0'; State <= Next_State; End If; End Process; ---------------------------------------- Count: Process ( USB_CLK,Reset_out, incr) Begin If ( Reset_out= '1' ) Then Counter <= (others => '0'); elsif (USB_CLK 'Event And USB_CLK = '1')Then If ( Counter = 255008 )Then -- Counter will stop counting -- elsif ( Incr = '1') then Counter <= Counter + 1; else Counter <= Counter; End if; End if; End Process; ---------------------------------------- Data_Bus_Load: Process( USB_CLK, Ld_high, Ld_Low,Reset_out,USB_Data) Begin If ( Reset_out= '1' ) Then Data_Bus ( 13 downto 8) <=(others =>'0'); Data_Bus ( 7 downto 0) <=(others =>'0'); elsif (USB_CLK = '1')Then If ( Ld_high = '1' ) Then Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 ); elsif (Ld_Low ='1') then Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 ); elsif ( Ld_high = '0' ) Then elsif(Ld_Low ='0') then else end if; else end if; End Process; ---------------------------------------- Reset_Scheme : Process( USB_CLK, Reset) variable Reset_in : std_logic; variable Reset_out_1 :std_logic; Begin If ( Reset = '1') then Reset_in := '1'; Reset_out_1 := '1'; Elsif rising_edge ( USB_CLK ) then Reset_out_1 := Reset_in; Reset_in :='0'; End if ; Reset_out <= Reset_out_1; End Process; VHDL TEST BENCH LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; --USE ieee.numeric_std.ALL; USE IEEE.STD_LOGIC_TEXTIO .ALL; use ieee.numeric_bit.all; ENTITY ABC_TEST IS END ABC_TEST; ARCHITECTURE behavior OF ABC_TEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT DPR_Writer PORT( Data_Bus : OUT std_logic_vector (13 downto 0); Address_bus : OUT std_logic_vector (18 downto 0); Read_write : OUT std_logic; Output_Enable : OUT std_logic; CE0 : OUT std_logic; CE1 : OUT std_logic; LBL : OUT std_logic; UBL : OUT std_logic; USB_Data : IN std_logic_vector (7 downto 0); USB_CLK : IN std_logic; ZZL : OUT std_logic; SEML : OUT std_logic; OPTL : IN std_logic; Reset : IN std_logic; Indicator_LED : OUT std_logic; State_status : out std_logic_vector ( 1 downto 0) ); END COMPONENT; --Inputs signal USB_Data :std_logic_vector (7 downto 0) := (others => '0'); signal USB_CLK : std_logic := '0'; signal OPTL : std_logic := '0'; signal Reset : std_logic := '0'; --Outputs signal Data_Bus : std_logic_vector (13 downto 0); signal Address_bus : std_logic_vector (18 downto 0); signal Read_write : std_logic; signal Output_Enable : std_logic; signal CE0 : std_logic; signal CE1 : std_logic; signal LBL : std_logic; signal UBL : std_logic; signal ZZL : std_logic; signal SEML : std_logic; signal Indicator_LED : std_logic; signal State_status : std_logic_vector ( 1 downto 0); constant USB_CLK_period : time := 42 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: DPR_Writer PORT MAP ( Data_Bus => Data_Bus, Address_bus => Address_bus, Read_write => Read_write, Output_Enable => Output_Enable, CE0 => CE0, CE1 => CE1, LBL => LBL, UBL => UBL, USB_Data => USB_Data, USB_CLK => USB_CLK, ZZL => ZZL, SEML => SEML, OPTL => OPTL, Reset => Reset, Indicator_LED => Indicator_LED, State_status => State_status ); ------------------------------------------------- USB_CLK_process :process begin USB_CLK<= '0'; wait for USB_CLK_period/2; USB_CLK <= '1'; wait for USB_CLK_period/2; end process; ----------------------------------------------- -- Stimulus process stim_proc: process begin -- hold reset state for 100ms. wait for 100ms; wait for USB_CLK_period*10; -- insert stimulus here wait; end process; ------------------------------------------------- Reset_Process: Process Begin Reset <= '1'; wait for 100 ns; Reset <='0'; wait for 6000 ns; End Process; ----------------------------------------------- USB_Data_Stream: Process Begin wait on USB_CLK; USB_Data(0)<= '1' after 10ns; USB_Data(1)<='0' after 10ns; USB_Data(2)<= '1' after 10ns; USB_Data(3)<= '0' after 10ns; USB_Data(4)<= '1' after 10ns; USB_Data(5)<= '0' after 10ns; USB_Data(6)<= '1' after 10ns; USB_Data(7)<= '0' after 10ns; end process; --------------------------------------------- END behavior; From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!h5g2000yqh.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: Writing Test Bench Date: Thu, 5 Mar 2009 23:12:51 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: <4d42e1ca-21b2-484b-a528-61672482f954@h5g2000yqh.googlegroups.com> References: <6e8f994f-5edb-40a8-a895-54c61419c0d5@i2g2000prd.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236323571 11377 127.0.0.1 (6 Mar 2009 07:12:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Mar 2009 07:12:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h5g2000yqh.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.6) Gecko/2009020409 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:599 Hi John You wrote: The USB device outputs 8 bit of parallel data at the falling edge of the USB_CLK. So, if you are using this clock for your FSM it should also use the falling clock edge in all processes. elsIf (USB_CLK 'Event And USB_CLK = '0')Then or elsif falling_edge(USB_CLK) then One more thing: What is it with this strange Data_Bus_Load Process?? Why are you building latches using: elsif (USB_CLK = '1')Then This process seems to be some crap to replace the data multiplexor scheme in your FSM. Well, the multiplexor there would work, but where are the registers to store the data? (State_Machine is a combinatorical process!) Also you will get a wrong simulation of that process, because the Input USB_Data is not in the sensitivity list. (I know, the lines are commented out now. But before that?) Rethink your approach and clean up your code. Have a nice synthesis Eilert From newsfish@newsfish Wed Aug 19 13:23:39 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!41g2000yqf.googlegroups.com!not-for-mail From: Yannick Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library Date: Sat, 7 Mar 2009 23:56:22 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> NNTP-Posting-Host: 88.169.37.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236498982 30454 127.0.0.1 (8 Mar 2009 07:56:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 8 Mar 2009 07:56:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 41g2000yqf.googlegroups.com; posting-host=88.169.37.107; posting-account=AnwwuQoAAAA0TgmjlOPRF8wZVlHhbblJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:600 On 2 mar, 20:50, Andy Peters wrote: > On Feb 27, 5:46=A0am, Yannick wrote: > > > I need to use arithmetic.std_logic_arith > > No, you don't ... > > -a I know that I can use iee library iee but this is not a acceptable solution. If you don't know where I can find it, please don't reply! Nobody know where I can find this library ? (This is the question) Thanks From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sun, 08 Mar 2009 04:24:22 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library Date: Sun, 08 Mar 2009 09:22:48 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 57 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-pmjRdVjpQkSRxidRVxEln2HA/v5fSTRfLt+PjRsilG8id2drYNgIAkrKHaTH+UVdNqa5E95YlJBqq+M!z2LP6KAFkqDyP0kkuQAYfOQ7p4pFn6IIOkkrvh62gZyVJv88iXxdpy2/JooWPxYBop7tL5ERNKyY!0i/n X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:601 On Sat, 7 Mar 2009 23:56:22 -0800 (PST), Yannick wrote: >> > I need to use arithmetic.std_logic_arith >> >> No, you don't ... > >I know that I can use iee library iee but this is not a acceptable >solution. It is much more acceptable than using some non-standard library and package. For a new project, using std_logic_arith is wrong; as Tricky correctly told you, you should use ieee.numeric_std instead. Before snapping back at people, you should explain why that is "not acceptable" - it works well for tens of thousands of experienced users. >If you don't know where I can find it, please don't reply! Andy knows far better than you how to find packages. >Nobody know where I can find this library ? Just about everyone on this group. A brief search would have turned up a ton of threads that you could examine to learn more about the issues; I am not sure I understand why you did not do that. >(This is the question) Please take the trouble to write questions carefully; yours was so vague that it invited frivolous and sarcastic responses. There is no such "library" as arithmetic.std_logic_arith; if it exists at all, it is a package in the library "arithmetic". That is not a standard library. It is possible that your company/school/project has created such a library; if so, then putting the std_logic_arith package into it is strange, but possible. Open your simulator's GUI, and look at its list of libraries. Do you find "arithmetic" there? I doubt it. All simulators have a precompiled std_logic_arith package; as you have already been told, it will be in the ieee library. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sun, 08 Mar 2009 11:31:27 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: use alias in port declaration? Date: Sun, 08 Mar 2009 16:29:53 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <47s7r4pl6fgj1m2rnteaj1uvovmooevlcb@4ax.com> References: <92c6b822-f97e-4d38-bba7-0975353c7c5c@b16g2000yqb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 60 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-pPLZ+TeYlZ1GxeI+EY2q+oYwAw/uWAX+RvWp/QOG8F26nbOFfPITvUCXIkRUgzHvpkCFzmb1HBSiLEz!+zdnZpT32mBK38E6tXlm4Fmlk1Kn4MQkTjSqV7f/VgLCV243fOT6iJNuMgGGw0Nnr28vtj2lUqti!8zUp X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:602 On Fri, 27 Feb 2009 00:48:50 -0800 (PST), Mike Dearman wrote: >> > I have the following vector in my design: >> >> > signal  CONTROL_PINS                    : std_logic_vector(69 downto 0); >> >> > I want to connect certain bits of this vector to pins, and i want to >> > give them meaningfull names, for example i want a pin called "ABC" >> > connected to CONTROL_PINS(4) [...] >sorry, i should have mentioned the bi-directional thing in the >original post. I don't think there is any way in VHDL to do exactly what you are asking. Verilog has the concept of "port expressions" which allow you to map a named port to a different-named signal inside the module, but VHDL can't do that. However, you can get very much the same effect either with components and configurations or with a wrapper entity. Suppose you have entity UsesVector; port (V: inout std_logic_vector(3 downto 0); end; but you would prefer it to look like this: entity NamedPorts; port (V3: inout std_logic; V21: inout std_logic_vector(1 downto 0); V0: inout std_logic); end; then all you need is architecture Wrapper of NamedPorts is begin guts: entity work.UsesVector port map (V(3) => V3, V(2 downto 1) => V21, V(0) => V0 ); end; Somewhat messy, but easy to do. Hope this helps - sorry it's so late. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!m36g2000vbp.googlegroups.com!not-for-mail From: "Mad I.D." Newsgroups: comp.lang.vhdl Subject: ERROR: Selector is an unconstrained array Date: Sun, 8 Mar 2009 13:18:51 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> NNTP-Posting-Host: 89.164.40.76 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236543532 10791 127.0.0.1 (8 Mar 2009 20:18:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 8 Mar 2009 20:18:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m36g2000vbp.googlegroups.com; posting-host=89.164.40.76; posting-account=zjk9VgoAAAB6zN99AVTum9W2bsjuNK2j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:603 ERROR MESSAGE : "Selector (Signal 'addr' of type std_logic_vector) is an unconstrained array." Architecture body, declarative part (before begin) can use entity generics but statement part can't ? I'm I right? Little explanation on this please. entity rom1 is generic ( ADDR_WIDTH : integer :=4; DATA_WIDTH : integer :=8 ); port ( addr : in std_logic_vector (ADDR_WIDTH-1 downto 0); dout : out std_logic_vector (DATA_WIDTH-1 downto 0) ); end rom1; architecture beh of rom1 is begin with addr select dout <= "11001101" when "0000", "01011100" when "0001", "01010101" when "0010", "00000000" when "0011", .............. .............. From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sun, 08 Mar 2009 15:33:35 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: ERROR: Selector is an unconstrained array Date: Sun, 08 Mar 2009 20:32:00 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <73a8r4hrn1mna2nshn9hsl2701j10vo4qq@4ax.com> References: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 74 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-mvqr30O8vA4MyVht9RsiDUkST8v0ol5bGZPRCaG3aWxHnlleoIeNRu1czK/vYvSiye61B7gdUXPCUv8!WRMlY5fK2cz1RyNSxnHXrBZ98v9gkMrNSPyCpWgu1mgvciKUtlkRcB9U31htmIrjP8SJHyKYuyrY!XTnc X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:604 On Sun, 8 Mar 2009 13:18:51 -0700 (PDT), "Mad I.D." wrote: >"Selector (Signal 'addr' of type std_logic_vector) is an unconstrained >array." > >Architecture body, declarative part (before begin) can use entity >generics but statement part can't ? > >I'm I right? Little explanation on this please. > > > >entity rom1 is > generic ( > ADDR_WIDTH : integer :=4; > DATA_WIDTH : integer :=8 > ); > port ( > addr : in std_logic_vector (ADDR_WIDTH-1 downto 0); > dout : out std_logic_vector (DATA_WIDTH-1 downto 0) > ); >end rom1; > >architecture beh of rom1 is >begin > with addr select > dout <= "11001101" when "0000", with...select is equivalent to a case statement inside a process. Case statements require their selector to have a constrained subtype. This is sometimes irritating, but it allows the compiler to do various things with the case statement that it couldn't easily do otherwise. Strictly, the selector's type must be "locally static". In truth you don't need the generic in the code you showed us. Your with...select evidently assumes that the selector is 4 bits wide, and won't work if it is not. There are other approaches that neatly solve this problem. For example, you could convert the incoming address to an integer, and use integers as the choices in your case or with...select statement. Also, the code you present is basically a lookup table so you could code that explicitly as a table of constants; this is more likely to map to memory in an FPGA: use ieee.numeric_std.all; ........ subtype addr_i_type is integer range 0 to 2**ADDR_WIDTH - 1; subtype data_type is std_logic_vector(DATA_WIDTH-1 downto 0); type rom_table_type is array (addr_i_type) of data_type; constant rom1_table: rom_table_type := ( 0 => "11001101" , 1 => "01011100" , ... , others => (others => '0') ); ..... ---- do lookup in the table dout <= rom1_table(to_integer(unsigned(addr))); -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: ERROR: Selector is an unconstrained array Date: Sun, 08 Mar 2009 15:19:13 -0700 Lines: 35 Message-ID: <49B44461.7010403@gmail.com> References: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 1lfz/wbzfKHU4bdiCW72PQswerJSIfuV/nVp9LDwB4pCCMIKWX Cancel-Lock: sha1:wv6/wYQooQCfSWndykVHLpyG3/E= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:605 Mad I.D. wrote: > ERROR MESSAGE : > "Selector (Signal 'addr' of type std_logic_vector) is an unconstrained > array." > > Architecture body, declarative part (before begin) can use entity > generics but statement part can't ? I would code a constant array as Jonathan did. http://mysite.verizon.net/miketreseler/sync_rom.vhd Generic dimensions are ok for arrays, but not for case selections. The only way to make an asynchronous one-liner, is to use fixed widths as shown below. -- Mike Treseler __________________ library ieee; use ieee.std_logic_1164.all; entity rom1 is port ( dout : out std_logic_vector(7 downto 0); addr : in std_logic_vector(3 downto 0)); end entity case_vs_if; architecture sim of rom1 is begin with addr select dout <= "11001101" when "0000", "01011100" when "0001", "01010101" when "0010", "00000000" when "0011", "00000000" when others; end architecture sim; From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 09 Mar 2009 05:05:09 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: help with FSM Date: Mon, 9 Mar 2009 03:02:59 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 89.172.247.74 Lines: 239 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-TFISsa/SioPioa7YMsuXg8gLpPuI9Z9CutGUIPjDcqxMcKxeezh2UlpgFcnhHJBlDAaR4WOWeI9ecU2!STdd2Er3opLVZdpOcuW+uN4xuGNBQF81Sx7oprcdt77m5Lf+CCo0fBYGAtA= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 206 Xref: news.eternal-september.org comp.lang.vhdl:606 hello, I need help with my code.... I have made a code for input numbers from ps2 keyboard, and i have a problem with state machine, witch will use for calculating... this is how should it look. '[image: http://img520.imageshack.us/img520/2250/53337338.jpg]' (http://img520.imageshack.us/my.php?image=53337338.jpg) By 'goranbm' (http://profile.imageshack.us/user/goranbm) When i am in state one, i enter numbers from keyboard , in code it is variable Numbers . then when i press one of this letters (Z, O, M, D, it is letters for mathematical operations) i need to jump to state two, and save my first number in reg A, and to reset Numbers, then when i am in state two, i need to enter second number from keyboard, then i press enter, second number is saved in reg B, and i get on the display the result of operation, /, *, + or -, ofcourse when we jump from sate one, to state two, we declare our operation.... This is main part of my code.... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keyboardVhdl is Port ( CLK, RST, KD, KC: in std_logic; Digits : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); minus : out std_logic); end keyboardVhdl; architecture Behavioral of keyboardVhdl is ------------------------------------------------------------------------ -- Component Declarations ------------------------------------------------------------------------ ------------------------------------------------------------------------ -- Signal Declarations ------------------------------------------------------------------------ signal clkDiv : std_logic_vector (3 downto 0); signal pclk : std_logic; signal KDI, KCI : std_logic; signal DFF1, DFF2 : std_logic; signal shiftRegSig1: std_logic_vector(10 downto 0); signal shiftRegSig2: std_logic_vector(10 downto 1); signal iDigits : std_logic_vector(15 downto 0); signal iOperacija : std_logic_vector(3 downto 0); signal iEnter : std_logic_vector(3 downto 0); signal A, B, S, R : std_logic_vector(15 downto 0); type state is (PRVIBROJ, DRUGIBROJ, REZULTAT); signal pr_state, nx_state : state; ------------------------------------------------------------------------ -- Module Implementation ------------------------------------------------------------------------ begin --Divide the master clock down to a lower frequency-- CLKDivider: Process (CLK) begin if (CLK = '1' and CLK'Event) then clkDiv <= clkDiv +1; end if; end Process; pclk <= clkDiv(3); --Flip Flops used to condition siglans coming from PS2-- Process (pclk, RST, KC, KD) begin if(RST = '1') then DFF1 <= '0'; DFF2 <= '0'; KDI <= '0'; KCI <= '0'; else if (pclk = '1' and pclk'Event) then DFF1 <= KD; KDI <= DFF1; DFF2 <= KC; KCI <= DFF2; end if; end if; end process; --Shift Registers used to clock in scan codes from PS2-- Process(KDI, KCI, RST) --DFF2 carries KD and DFF4, and DFF4 carries KC begin if (RST = '1') then ShiftRegSig1 <= "00000000000"; ShiftRegSig2 <= "0000000000"; else if (KCI = '0' and KCI'Event) then ShiftRegSig1(10 downto 0) <= KDI & ShiftRegSig1(10 downto 1); ShiftRegSig2(10 downto 1) <= ShiftRegSig1(0) & ShiftRegSig2(10 downto 2); end if; end if; end process; --Wait Register process(ShiftRegSig1, ShiftRegSig2, RST, KCI) VARIABLE Number : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE Numbers : STD_LOGIC_VECTOR(15 DOWNTO 0); VARIABLE Operacija : STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE Enter : STD_LOGIC_VECTOR(3 DOWNTO 0); begin if(RST = '1')then Number := (OTHERS => '0'); Numbers := (OTHERS => '0'); else if(KCI'event and KCI = '1' and ShiftRegSig2(8 downto 1) = "11110000")then Case ShiftRegSig1(8 downto 1) is when X"45" => Number := "0000"; Operacija := "0000"; when X"16" => Number := "0001"; Operacija := "0000"; when X"1E" => Number := "0010"; Operacija := "0000"; when X"26" => Number := "0011"; Operacija := "0000"; when X"25" => Number := "0100"; Operacija := "0000"; when X"2E" => Number := "0101"; Operacija := "0000"; when X"36" => Number := "0110"; Operacija := "0000"; when X"3D" => Number := "0111"; Operacija := "0000"; when X"3E" => Number := "1000"; Operacija := "0000"; when X"46" => Number := "1001"; Operacija := "0000"; when X"35" => Operacija := "0001"; Number := "0000"; when X"44" => Operacija := "0010"; Number := "0000"; when X"3A" => Operacija := "0100"; Number := "0000"; when X"23" => Operacija := "1000"; Number := "0000"; when X"5A" => Operacija := "1001"; Number := "0000"; when Others => Number := "1111"; end case; if (Operacija /= "0000") then iA <= Numbers; Numbers := (others => '0'); else Numbers := Numbers(11 DOWNTO 0) & Number; end if; end if; iDigits <= Numbers; iOperacija <= Operacija; end if; end Process; Digits <= iDigits; process (rst) begin if (rst = '1') then pr_state <= PRVIBROJ; end if; end process; -----Gornji dio---------- process (pr_state, rst) begin case pr_state is when PRVIBROJ => if (iOperacija /= "0000") then A <= iDigits; nx_state <= DRUGIBROJ; else nx_state <= PRVIBROJ; end if; when DRUGIBROJ => if (iEnter /= "0000") then B <= iDigits; nx_state <= REZULTAT; else nx_state <= DRUGIBROJ; end if; when REZULTAT => if (iOperacija = "0001") then R <= A+B; elsif (iOperacija /= "0010") then if (A >= B) then R <= A-B; minus <= '0'; else R <=B-A; minus <= '1'; end if; elsif (iOperacija /= "0100") then R <= A*B; elsif (iOperacija /= "1000") then R <= A and B; end if; end case; end process; Red part represents entering numbers from keyboard, and the blue part is attempt of my state machine , and it is not good, please can you help me, and write me a part that im am mising, please i am desperate... thanks in advance.... -- goranbm ------------------------------------------------------------------------ goranbm's Profile: http://www.fpgacentral.com/group/member.php?userid=11 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88411 From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 09 Mar 2009 06:05:49 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: ERROR: Selector is an unconstrained array Date: Mon, 09 Mar 2009 11:06:41 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> <49B44461.7010403@gmail.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 54 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-nVyPBK8IZq2xJF1T1Q5JpFxJM1WP3Voc0ul7iTIXKFRs5x6xi2RpRZthlbetqU4BHWpiRnV66P8hYM7!Gt0nWBaoBmRt5woTUuAPvdDQjRbKy0n5b+cEi6w9zlKVQVugAkV/qxXQhppj8Zoalwtnw9zlAXkj!npon X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:607 On Sun, 08 Mar 2009 15:19:13 -0700, Mike Treseler wrote: >Mad I.D. wrote: >> ERROR MESSAGE : >> "Selector (Signal 'addr' of type std_logic_vector) is an unconstrained >> array." >> >> Architecture body, declarative part (before begin) can use entity >> generics but statement part can't ? > > >I would code a constant array as Jonathan did. >http://mysite.verizon.net/miketreseler/sync_rom.vhd >Generic dimensions are ok for arrays, but not for case selections. >The only way to make an asynchronous one-liner, >is to use fixed widths as shown below. > > -- Mike Treseler >__________________ >library ieee; >use ieee.std_logic_1164.all; >entity rom1 is > port ( > dout : out std_logic_vector(7 downto 0); > addr : in std_logic_vector(3 downto 0)); >end entity case_vs_if; > >architecture sim of rom1 is >begin > with addr select > dout <= > "11001101" when "0000", ... > "00000000" when others; >end architecture sim; With generic ports you can do it but you have to cover two bases: The first is as Mike says: the case expression must have a fixed width: with addr(3 downto 0) select -- this expression width must match the literals The second is to cover the cases where the generic doesn't satisfy this condition e.g. assert ADDR_WIDTH > 3 report "Address bus too small" severity FAILURE; will verify that the address bus is large enough and map the ROM multiple times if it is larger than necessary. That may or may not be the behaviour you want. - Brian From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: help with FSM Date: Mon, 09 Mar 2009 07:37:57 -0700 Lines: 16 Message-ID: <49B529C5.6040807@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Frg1eS6PWjRTJzb9Ywa9BweiYdnY9Qum9qizEuEcM0Ql9Duu9l Cancel-Lock: sha1:kq4WrtU5BHB7f28/MjQsw8xF0Jg= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:608 'use_real_email' wrote: > hello, I need help with my code.... I have made a code for input numbers > from ps2 keyboard, and i have a problem with state machine, witch will > use for calculating > pclk <= clkDiv(3); This creates skew. Use CLK directly. > --Flip Flops used to condition siglans coming from PS2-- > Process (pclk, RST, KC, KD) Make that process(CLK, RST) -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:40 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!17g2000vbf.googlegroups.com!not-for-mail From: "Mad I.D." Newsgroups: comp.lang.vhdl Subject: Re: ERROR: Selector is an unconstrained array Date: Mon, 9 Mar 2009 10:34:13 -0700 (PDT) Organization: http://groups.google.com Lines: 1 Message-ID: References: <22fe725f-4032-474d-94a5-7377c609b14a@m36g2000vbp.googlegroups.com> <49B44461.7010403@gmail.com> NNTP-Posting-Host: 89.164.52.146 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236620054 29591 127.0.0.1 (9 Mar 2009 17:34:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Mar 2009 17:34:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000vbf.googlegroups.com; posting-host=89.164.52.146; posting-account=zjk9VgoAAAB6zN99AVTum9W2bsjuNK2j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.6) Gecko/2009011913 Firefox/3.0.6,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:609 Thanks all ! From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!j38g2000yqa.googlegroups.com!not-for-mail From: Will Newsgroups: comp.lang.vhdl Subject: How could I output a real signal to std_logic_vector? Date: Mon, 9 Mar 2009 11:01:04 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <818a738e-7dc4-43b7-9020-4b16edf8c204@j38g2000yqa.googlegroups.com> NNTP-Posting-Host: 75.4.10.0 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236621664 2426 127.0.0.1 (9 Mar 2009 18:01:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Mar 2009 18:01:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j38g2000yqa.googlegroups.com; posting-host=75.4.10.0; posting-account=60dbswkAAAB_IKWyM6GxJOH_uKs_vDww User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.48 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:610 Hi all, I'm really new to VHDL. I need to output a real signal. How could I convert it to std_logic_vector? Or, could I output a real number directly? BTW, is there any way that I could monitor variables during test bench simulation like debugging in other language? Thanks and bow. From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.z74.net!news.z74.net!news.glorb.com!postnews.google.com!w35g2000yqm.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library Date: Mon, 9 Mar 2009 11:51:57 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <9aeab337-c5c8-4f10-b7aa-15ccbd92711a@w35g2000yqm.googlegroups.com> References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236624718 28123 127.0.0.1 (9 Mar 2009 18:51:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Mar 2009 18:51:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000yqm.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:611 On 27 Feb, 12:46, Yannick wrote: > Hi, > > I need to use the arithmetic library but I don't find it! > > I need to use arithmetic.std_logic_arith and I don't want change for > another library. > > Where I can find it? > > Thks Useually for standard libraries they will be in the ieee tree. I say use which ever you want, they are very similar, but some type conversion issues exist. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; you could use ieee.numeric_std.all as well or instead of this will slightly change the code needed, i.e. a slight cast changing, but not much else will differ. The packages differ IIRC in that std_logic_arith has arithmetic functions which produce std_logic_vector, where as numeric_std is focused on producing numeric results, which then can be cast/autocast to std_logic_vector. There are many opinions, but i have had no concrete rational as to why one is better than the other. cheers jacko From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 09 Mar 2009 14:25:09 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: Re: help with FSM Date: Mon, 9 Mar 2009 12:22:49 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 89.172.247.74 References: <49B529C5.6040807@gmail.com> Lines: 32 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-RgivUy/i4Rb11Y5nsYvtWvUK0U3BZ3z2T5e+E8Q/LhsVp5ZT3i7Ecyb2EVcXWuUaoHE7NYYUyX/EyXb!0/rc/Xrt9tGapa/2tt9D1LQ3XSSGODmmgykyFpEvD9erVf+2q9qiAhbdY2c= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 20 Xref: news.eternal-september.org comp.lang.vhdl:612 Mike Treseler;470029 Wrote: > 'use_real_email' wrote: > > hello, I need help with my code.... I have made a code for input > numbers > > from ps2 keyboard, and i have a problem with state machine, witch > will > > use for calculating > > > pclk <= clkDiv(3); > > This creates skew. Use CLK directly. > > > --Flip Flops used to condition siglans coming from PS2-- > > Process (pclk, RST, KC, KD) > > Make that > process(CLK, RST) > > -- Mike Treseler I am not quite sure what to do, can you be more specific, and can you tell me where is my problem with FSM ?? the rest of the code is ok...... -- goranbm ------------------------------------------------------------------------ goranbm's Profile: http://www.fpgacentral.com/group/member.php?userid=11 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88411 From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!newsfeed.straub-nv.de!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!d19g2000prh.googlegroups.com!not-for-mail From: Will Newsgroups: comp.lang.vhdl Subject: I can use std_logic_vector only as input signal in Xilinx? Date: Mon, 9 Mar 2009 13:30:16 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 75.4.10.0 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236630616 31325 127.0.0.1 (9 Mar 2009 20:30:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Mar 2009 20:30:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000prh.googlegroups.com; posting-host=75.4.10.0; posting-account=60dbswkAAAB_IKWyM6GxJOH_uKs_vDww User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.48 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:613 Hi all, When I assign an input signal as integer or real, I can only change its value as a bit in test bench using Xilinx ISE 9.2i. Is std_logic_vector the only right type for an input signal to input an integer? Thanks and bow. From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!de-l.enfer-du-nord.net!feeder.erje.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: help with FSM Date: Mon, 09 Mar 2009 15:15:02 -0700 Lines: 6 Message-ID: <49B594E6.7070109@gmail.com> References: <49B529C5.6040807@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net v1rL4+QBLRrWt5VvaP04Tw2GU5DgXiYi8Z+ugsYrXgfYRLVH2K Cancel-Lock: sha1:lewDEW4YqeuZLDBqJQVd5GQqnWU= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:614 'use_real_email' wrote: > I am not quite sure what to do, can you be more specific, and can you > tell me where is my problem with FSM ?? the rest of the code is ok...... http://groups.google.com/groups/search?q=vhdl+clock+enable+gated From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.tanoz.com!news.albasani.net!news2.arglkargh.de!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 09 Mar 2009 18:30:10 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: Re: help with FSM Date: Mon, 9 Mar 2009 16:26:22 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 89.172.247.74 References: <49B529C5.6040807@gmail.com> <49B594E6.7070109@gmail.com> Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-QIYOoMMWH4vmD+hKi3VSw8/4eVkMod8IOH2b8yKZjJkaHMjtEeldW+1ay0uLF5zJ/78NNiHeg4quTel!RCkmXYRozK6EzlDai7gFLUV0mvMIytX+v/VoCU8pi6LUKsSlHRsn6i3Yyvs= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:615 Can you find me a problem in blu colored part of the code??? pliz,this is suposed to be a calculator??? and i cant get the FSM to do this -*"When i am in state one, i enter numbers from keyboard , in code it is variable Numbers . then when i press one of this letters (Z, O, M, D, it is letters for mathematical operations) i need to jump to state two, and save my first number in reg A, and to reset Numbers, then when i am in state two, i need to enter second number from keyboard, then i press enter, second number is saved in reg B, and i get on the display the result of operation, /, *, + or -, ofcourse when we jump from sate one, to state two, we declare our operation...."*- it is drawn on the picture in my first post..... -- goranbm ------------------------------------------------------------------------ goranbm's Profile: http://www.fpgacentral.com/group/member.php?userid=11 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88411 From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Tue, 10 Mar 2009 04:43:30 -0500 Date: Tue, 10 Mar 2009 09:43:26 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: How could I output a real signal to std_logic_vector? References: <818a738e-7dc4-43b7-9020-4b16edf8c204@j38g2000yqa.googlegroups.com> In-Reply-To: <818a738e-7dc4-43b7-9020-4b16edf8c204@j38g2000yqa.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <7IidnbvyuPTfqyvUnZ2dnUVZ8qGWnZ2d@posted.plusnet> Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-lU0a4woAgKHYS/oufaZA9ukBw6IXkxLz5cCLzjYR7opKhjJQo0mUl7mwzLQMnU002Q66O2XevHq2WcE!boU8poXw9j0lsh5NfnRUvlkSOUYKPf3mN1f0dHRDs3fsH5LdMSIdTbN0y7rbBVLaxvOwON2uFd4p!urFgjTjxe0I= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:616 Will wrote: > Hi all, > > I'm really new to VHDL. I need to output a real signal. How could I > convert it to std_logic_vector? Or, could I output a real number > directly? It depends whether you want to create hardware. Real numbers aren't synthesisable. For simulation, you can convert from real to std_logic_vector using library ieee; use ieee.numeric_std.all; .... s <= Std_logic_vector(to_unsigned(INTEGER(r), s'LENGTH); where s is a std_logic_vector and r is real. This assumes are represents a real value greater or equal to zero, and that it fits into a certain size of std_logic_vector. > BTW, is there any way that I could monitor variables during test bench > simulation like debugging in other language? > Yes, it's tool dependent. Most tools can display variables on the waveform display, and also have the facility to set breakpoints and single step. Make sure you include debugging symbols when you analyze your code, regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!feeder6.cambrium.nl!feeder4.cambrium.nl!feed.tweaknews.nl!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 10 Mar 2009 15:03:58 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga Subject: Integer arithmetic in HDLs Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 24 Message-ID: <49b67351$0$2856$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: e57c16e9.news.skynet.be X-Trace: 1236693841 news.skynet.be 2856 217.136.193.14:39261 X-Complaints-To: usenet-abuse@skynet.be Xref: news.eternal-september.org comp.lang.vhdl:617 comp.lang.verilog:181 comp.arch.fpga:1595 If you are doing HDL-based design, you are probably using integer arithmetic regularly. In doing so, you may often be struggling with mysterious behaviour, sign bit extensions, resizings and type conversions, in order to get things to work as you want. I believe such efforts are a waste of your valuable engineering time, caused by bad language design choices in Verilog and VHDL. I have written an essay that explores these issues in detail, and proposes a solution: http://www.jandecaluwe.com/hdldesign/counting.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org From newsfish@newsfish Wed Aug 19 13:23:41 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feed.xsnews.nl!border-2.ams.xsnews.nl!feeder.news-service.com!postnews.google.com!v15g2000yqn.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga Subject: Re: Integer arithmetic in HDLs Date: Tue, 10 Mar 2009 07:57:17 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <49b67351$0$2856$ba620e4c@news.skynet.be> NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236697037 2066 127.0.0.1 (10 Mar 2009 14:57:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Mar 2009 14:57:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v15g2000yqn.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:618 comp.lang.verilog:182 comp.arch.fpga:1596 Hi This is a good argument. It is why I prefered ieee.std_logic_arith an staying with bit vectors. It means the cast signed or unsigened is placed around each input std_logic_vector, and the output automatically casts to the required std_logic_vector. Ooooooh, don't you just miss the division operators from numeric_std? No. I don't even miss the multiplication operators. If I get to needing such things, I will use one from either synopsis free distribution files, or a homebrew one. So put simply the signed or unsigned just specifies the sign extension for the arithmetic. I find no problem in thinking in terms of std_logic_vector. It does not suffer from integer's lack of width generics. Although useful for generate statements integers be, ya , yoda. cheers jacko From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!news.lindneronline.de!news.uni-stuttgart.de!newsfeed.in-ulm.de!not-for-mail From: Steffen Koepf Newsgroups: comp.lang.vhdl Subject: Timing Problems with counter Date: Tue, 10 Mar 2009 19:44:27 +0100 (CET) Organization: [ posted via ] IN-Ulm Lines: 57 Sender: Steffen Koepf Message-ID: X-Trace: news.in-ulm.de F549FAEB3EC9F41E73E7DC7124ACF89E User-Agent: tin/pre-1.4-19990805 ("Preacher Man") (UNIX) (Linux/2.6.25.10 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:619 Hello, what i need is a counter that counts from a preset value down to 0 with a clock outside of the system clock domain. The counter run on a Cyclone III, 15 out of 16 of the counters work well, but one counts much too slow. Here is the relevant part of the code: -- transfer clock domain, fcntnext is in the system clockdomain cntrclk: process (clk, rst) begin if (rst = '1') then fcntnext <= '0'; fcnttoggle <= '0'; elsif falling_edge(clk) then fcntnext <= '0'; if fcnttoggle /= fcounter then fcnttoggle <= fcnttoggle xor '1'; if fcnttoggle = '1' then fcntnext <= '1'; end if; end if; end if; end process cntrclk; delaycounter: process (clk, rst) begin if (rst = '1') then dcntFin <= '0'; dcounter <= (others => '0'); elsif rising_edge(clk) then if cntr_reload = '1' then dcntFin <= '0'; -- Load counter with previous stored value dcounter <= dcounterLoadVal; elsif dcounter = std_logic_vector(to_unsigned(0, dcounter_bits)) then dcntFin <= '1'; elsif fcntnext = '1' then dcounter <= std_logic_vector(unsigned(dcounter) - 1); end if; end if; end process delaycounter; all signals are std_logic, and dcounter, dcounterLoadVal are std_logic_vector. The FPGA runs with a system clock (clk) of 100 MHz. The fcntnext signal is one clock cycle high (from falling_edge to falling_edge) after every rising clock edge of the fcounter clock. The fcounter clock is much slower than the system clock (max 1 MHz with a Duty-Cycle of 50%). Has anyone advices? Best regards, Steffen From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!v1g2000prd.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga Subject: Re: Integer arithmetic in HDLs Date: Tue, 10 Mar 2009 16:20:35 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <1a0c3206-481d-4773-b5bb-3f7ecf0861f3@v1g2000prd.googlegroups.com> References: <49b67351$0$2856$ba620e4c@news.skynet.be> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236727235 3529 127.0.0.1 (10 Mar 2009 23:20:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Mar 2009 23:20:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v1g2000prd.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:620 comp.lang.verilog:187 comp.arch.fpga:1602 On Mar 10, 7:03=A0am, Jan Decaluwe wrote: > If you are doing HDL-based design, you are probably using > integer arithmetic regularly. In doing so, you may often be > struggling with mysterious behaviour, sign bit extensions, > resizings and type conversions, in order to get things > to work as you want. > > I believe such efforts are a waste of your valuable > engineering time, caused by bad language design choices > in Verilog and VHDL. > > I have written an essay that explores these issues in > detail, and proposes a solution: > > http://www.jandecaluwe.com/hdldesign/counting.html Excellent treatise although I'm not convinced I want to use Python for hardware development. I use integers and naturals, with appropriate ranges, all the time. Perhaps the people on the VHDL committee could promulgate the following for the next update to the language, whenever that might be: a) the arbitrary 32-bit limit on the size of integers and naturals should be relaxed or eliminated, for the obvious reasons. And it's probably also obvious that everyone who does use integers and naturals in VHDL code already uses ranges. b) when dealing with signed and unsigned types, sign-extension should be implicit (no need for resize() calls) such that all operands on the RHS get extended to the size of LHS result. An error should be thrown if any operand on the RHS is larger than the LHS result -- no need for obscure truncation rules a-la Verilog. -a From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Timing Problems with counter Date: Tue, 10 Mar 2009 22:22:45 -0700 Lines: 10 Message-ID: <49B74AA5.1050500@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net mvjms2WT6wnB8RV17aKzOwxcQGKTRt3ajiEFQcDW5RdGoqI6nV Cancel-Lock: sha1:EA4J1TPt0blcErcehWjkQ074K4M= User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:621 Steffen Koepf wrote: > what i need is a counter that counts from a preset value down to 0 > with a clock outside of the system clock domain. A clock outside of the system clock domain must be used as in input and synchronized to the system clock. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!v19g2000yqn.googlegroups.com!not-for-mail From: saousouna.ing@gmail.com Newsgroups: comp.lang.vhdl Subject: how can i extract a part of an image using VHDL !! Date: Wed, 11 Mar 2009 04:28:55 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <29521dc1-a343-4dad-9e44-4d2f7e29b0a0@v19g2000yqn.googlegroups.com> NNTP-Posting-Host: 41.229.71.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236770935 13945 127.0.0.1 (11 Mar 2009 11:28:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 11:28:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqn.googlegroups.com; posting-host=41.229.71.9; posting-account=AQpTVgoAAACxIEgoRrIE7gz0b8ffU8Me User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:622 Hi , I am realizing a project which consists in making a program in VHDL of the treatment of image (detection of face in a stream video / image) in VHDL and implement it on FPGA Xilinx Spartan III. ..Now the problem is here : I need to extract a part of my origin image which is stored in a ROM. but I am clamped !! Can anyone helps me to program this extraction PLEASE !! & thank you very much ..i appreciate it have a great day From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!z1g2000yqn.googlegroups.com!not-for-mail From: saousouna.ing@gmail.com Newsgroups: comp.lang.vhdl Subject: Look for documentation Date: Wed, 11 Mar 2009 04:37:16 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <8cfea046-a30f-4834-9507-047d21052b90@z1g2000yqn.googlegroups.com> NNTP-Posting-Host: 41.229.71.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236771436 15650 127.0.0.1 (11 Mar 2009 11:37:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 11:37:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z1g2000yqn.googlegroups.com; posting-host=41.229.71.9; posting-account=AQpTVgoAAACxIEgoRrIE7gz0b8ffU8Me User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:623 Hi, can you please give me some links or useful courses onto the VHDL image processing ( i'm doing a final year project which consists of a face extraction from in an image or a stream video).. Thank you in advance and have good day :) From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!o2g2000prl.googlegroups.com!not-for-mail From: LittleAlex Newsgroups: comp.lang.vhdl Subject: Re: Look for documentation Date: Wed, 11 Mar 2009 07:39:28 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <8cfea046-a30f-4834-9507-047d21052b90@z1g2000yqn.googlegroups.com> NNTP-Posting-Host: 132.190.112.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236782368 29841 127.0.0.1 (11 Mar 2009 14:39:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 14:39:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o2g2000prl.googlegroups.com; posting-host=132.190.112.111; posting-account=htNwywoAAAAyrKHu0vPbiXZtaUyq3l0o User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:624 On Mar 11, 4:37 am, saousouna....@gmail.com wrote: > Hi, > can you please give me some links or useful courses onto the VHDL > image processing ( i'm doing a final year project which consists of a > face extraction from in an image or a stream video).. > > Thank you in advance and have good day :) Sigh. Ever heard of Google Search? 103,000 hits, including several similar final-year projects... From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!e38g2000yqa.googlegroups.com!not-for-mail From: Aiken Newsgroups: comp.lang.vhdl Subject: Re: how can i extract a part of an image using VHDL !! Date: Wed, 11 Mar 2009 07:57:09 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <6bfbbc94-3392-4f20-80d1-9d663845ab68@e38g2000yqa.googlegroups.com> References: <29521dc1-a343-4dad-9e44-4d2f7e29b0a0@v19g2000yqn.googlegroups.com> NNTP-Posting-Host: 199.10.150.33 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236783429 22047 127.0.0.1 (11 Mar 2009 14:57:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 14:57:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e38g2000yqa.googlegroups.com; posting-host=199.10.150.33; posting-account=o1NIRQoAAACD94UsAWOsHscwtNA8hiam User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:625 1. You need to know how is the mapping of your image in the ROM 2. Write a read ROM process for the ROM(read the ROM spec. and some basic vhdl book) 3. Make FSM to read where you want from the ROM to your RAM/what every your treatment for the image On Mar 11, 7:28=A0am, saousouna....@gmail.com wrote: > Hi , > I am realizing a project which consists in making a program in VHDL of > the treatment of image (detection of face in a stream video / image) > in VHDL and implement it on FPGA Xilinx Spartan III. > > ..Now the problem is here : I need to extract a part of my =A0 origin > image which is stored in a ROM. but I am clamped !! > =A0Can anyone =A0helps me to program =A0this extraction PLEASE !! & thank > you very much ..i appreciate it > > have a great day From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc01.gnilink.net.POSTED!f388d8ac!not-for-mail Newsgroups: comp.lang.vhdl Followup-To: comp.lang.vhdl Lines: 50 From: Ken Cecka Subject: combinatorial feedback loop User-Agent: KNode/0.99.01 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Message-ID: Date: Wed, 11 Mar 2009 18:39:51 GMT NNTP-Posting-Host: 98.117.108.7 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1236796791 98.117.108.7 (Wed, 11 Mar 2009 14:39:51 EDT) NNTP-Posting-Date: Wed, 11 Mar 2009 14:39:51 EDT Xref: news.eternal-september.org comp.lang.vhdl:626 I'm playing around with different ways to count the number of '1' bits in a vector. I'll only be dealing with 6 bit vectors, so I could just do this with a lookup table, but I started with the most readable implementation to see how it would synthesize (copied below). The Xilinx tools are synthesizing this into a single counter with a feedback loop, and then telling me me that the design can run at 700MHz. I'm a little skeptical - anyone know if it's reasonable to expect timing analysis to unroll a feedback loop like this? Ken ENTITY test IS GENERIC ( bits : INTEGER := 6 ); PORT ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; input : IN STD_LOGIC_VECTOR((bits - 1) DOWNTO 0); ones : OUT STD_LOGIC_VECTOR(log2(bits) DOWNTO 0) ); END test; ARCHITECTURE model OF test IS SIGNAL input_l : STD_LOGIC_VECTOR(input'RANGE); SIGNAL count : STD_LOGIC_VECTOR(ones'RANGE); BEGIN -- latch inputs and outputs for timing analysis PROCESS (reset, clk) BEGIN IF (reset = '1') THEN input_l <= (OTHERS => '0'); ones <= (OTHERS => '0'); ELSIF (clk'EVENT) AND (clk = '1') THEN input_l <= input; ones <= count; END IF; END PROCESS; -- count ones PROCESS (input_l, count) BEGIN FOR i IN input_l'RANGE LOOP IF (input_l(i) = '1') THEN count <= count + 1; END IF; END LOOP; END PROCESS; END; From newsfish@newsfish Wed Aug 19 13:23:42 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 Mar 2009 13:54:21 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: combinatorial feedback loop Date: Wed, 11 Mar 2009 18:52:42 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 63 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-cqTVGmBdwY7VFEp3oSHbMZJeEq05HirlzJzCumvNTE46D9thS1HHifR2eiNQmBGT2ko9P8aFllSUnud!FLe48T4ObihhNgJg9jg/RGPi4UplzLz8ev5NOd9yanm2wmPkNoKk18ZXU1P5i9bYn8eG361MShhE!Y1n0 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:627 On Wed, 11 Mar 2009 18:39:51 GMT, Ken Cecka wrote: >I'm playing around with different ways to count the number of '1' > bits in a vector. I'll only be dealing with 6 bit vectors, so > I could just do this with a lookup table, but I started with > the most readable implementation to see how it would > synthesize (copied below). > >The Xilinx tools are synthesizing this into a single > counter with a feedback loop, and then telling me > that the design can run at 700MHz. I'm a little > skeptical - anyone know if it's reasonable to expect > timing analysis to unroll a feedback loop like this? > >Ken [...] > -- count ones > PROCESS (input_l, count) > BEGIN > FOR i IN input_l'RANGE LOOP > IF (input_l(i) = '1') THEN > count <= count + 1; > END IF; > END LOOP; > END PROCESS; OUCH! You really, really don't want to do this! I suggest that your s[ck]epticism is entirely justified - there's no way that makes any sense. Indeed, a counter with combinational feedback makes no sense as a design - it isn't coherent. Of course you can re-code the loop with a variable: PROCESS (input_l) variable count: unsigned... BEGIN FOR i IN input_l'RANGE LOOP IF (input_l(i) = '1') THEN count := count + 1; END IF; END LOOP; count_signal <= count; END PROCESS; and now synthesis will properly unroll the for-loop (creating a chain of adders) and there is no combinational feedback. I'm guessing you know a load of other ways of doing it, too. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc01.gnilink.net.POSTED!f388d8ac!not-for-mail Newsgroups: comp.lang.vhdl Followup-To: comp.lang.vhdl Lines: 57 From: Ken Cecka Subject: Re: combinatorial feedback loop References: User-Agent: KNode/0.99.01 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Message-ID: Date: Wed, 11 Mar 2009 19:12:24 GMT NNTP-Posting-Host: 98.117.108.7 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1236798744 98.117.108.7 (Wed, 11 Mar 2009 15:12:24 EDT) NNTP-Posting-Date: Wed, 11 Mar 2009 15:12:24 EDT Xref: news.eternal-september.org comp.lang.vhdl:628 Jonathan Bromley wrote: > On Wed, 11 Mar 2009 18:39:51 GMT, Ken Cecka > wrote: > >>I'm playing around with different ways to count the number of '1' >> bits in a vector. I'll only be dealing with 6 bit vectors, so >> I could just do this with a lookup table, but I started with >> the most readable implementation to see how it would >> synthesize (copied below). >> >>The Xilinx tools are synthesizing this into a single >> counter with a feedback loop, and then telling me >> that the design can run at 700MHz. I'm a little >> skeptical - anyone know if it's reasonable to expect >> timing analysis to unroll a feedback loop like this? >> >>Ken > [...] >> -- count ones >> PROCESS (input_l, count) >> BEGIN >> FOR i IN input_l'RANGE LOOP >> IF (input_l(i) = '1') THEN >> count <= count + 1; >> END IF; >> END LOOP; >> END PROCESS; > > OUCH! You really, really don't want to do this! > > I suggest that your s[ck]epticism is entirely > justified - there's no way that makes any sense. > Indeed, a counter with combinational feedback > makes no sense as a design - it isn't coherent. > > Of course you can re-code the loop with a variable: > > PROCESS (input_l) > variable count: unsigned... > BEGIN > FOR i IN input_l'RANGE LOOP > IF (input_l(i) = '1') THEN > count := count + 1; > END IF; > END LOOP; > count_signal <= count; > END PROCESS; > > and now synthesis will properly unroll the for-loop > (creating a chain of adders) and there is no > combinational feedback. I'm guessing you know > a load of other ways of doing it, too. I was expecting it to unroll into a chain of adders in the first place and was surprised when it used feedback, but didn't stop think about the underlying adder implementation and whether this could even work. Thanks for the reality check! Ken From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!s20g2000yqh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: combinatorial feedback loop Date: Wed, 11 Mar 2009 12:21:36 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <9cd885de-33e9-45f9-b4f7-97f0698f5536@s20g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236799296 9188 127.0.0.1 (11 Mar 2009 19:21:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 19:21:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000yqh.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:629 On Mar 11, 1:52=A0pm, Jonathan Bromley wrote: > > Of course you can re-code the loop with a variable: > > =A0 PROCESS (input_l) > =A0 =A0 =A0variable count: unsigned... > =A0 BEGIN > =A0 =A0 FOR i IN input_l'RANGE LOOP > =A0 =A0 =A0 IF (input_l(i) =3D '1') THEN > =A0 =A0 =A0 =A0 count :=3D count + 1; > =A0 =A0 =A0 END IF; > =A0 =A0 END LOOP; > =A0 =A0 count_signal <=3D count; > =A0 END PROCESS; Don't forget to initialize count to zero before the loop... Andy From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 Mar 2009 14:28:26 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: combinatorial feedback loop Date: Wed, 11 Mar 2009 19:26:47 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <9cd885de-33e9-45f9-b4f7-97f0698f5536@s20g2000yqh.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-TFTrdpIqs2KT5iqZTYeUGRCDchmFNxGWnvdVx80sWOOFZW6dQKLLd6ku7XZZbyRzX9iRDCfoBtMIPwd!vpCt9Jd8yKg7UdfQ2eYcgD2jzTTc2Hzvb/im7lDT4R2HfCyjHFyCxJTwJZUGBCuWjeeQFFlbo52V!QzQG X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:630 On Wed, 11 Mar 2009 12:21:36 -0700 (PDT), Andy wrote: >> Of course you can re-code the loop with a variable: >> >>   PROCESS (input_l) >>      variable count: unsigned... >>   BEGIN >>     FOR i IN input_l'RANGE LOOP >>       IF (input_l(i) = '1') THEN >>         count := count + 1; >>       END IF; >>     END LOOP; >>     count_signal <= count; >>   END PROCESS; > >Don't forget to initialize count to zero before the loop... ah, yes, good plan. Of course that was left as an exercise for the student :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!o36g2000yqh.googlegroups.com!not-for-mail From: saousouna.ing@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Look for documentation Date: Wed, 11 Mar 2009 15:39:52 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <8cfea046-a30f-4834-9507-047d21052b90@z1g2000yqn.googlegroups.com> NNTP-Posting-Host: 41.226.199.185 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236811192 25784 127.0.0.1 (11 Mar 2009 22:39:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Mar 2009 22:39:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o36g2000yqh.googlegroups.com; posting-host=41.226.199.185; posting-account=AQpTVgoAAACxIEgoRrIE7gz0b8ffU8Me User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:631 On 11 mar, 15:39, LittleAlex wrote: > On Mar 11, 4:37 am, saousouna....@gmail.com wrote: > > > Hi, > > can you please =A0give me some links or useful courses =A0onto the =A0V= HDL > > image processing ( i'm doing a final year project which consists of a > > face extraction from in =A0an image or a stream video).. > > > Thank you in advance and =A0have good day :) > > Sigh. > > Ever heard of Google Search? =A0103,000 hits, including several similar > final-year projects... Sure i did manyyyyyyyyyyyy searchs but i can't find what i'm searching for !! or i should buy the book or there are nothing that can help !! anyway thank you . From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.germany.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Look for documentation Date: Wed, 11 Mar 2009 16:01:40 -0700 Lines: 19 Message-ID: <49B842D4.3080905@gmail.com> References: <8cfea046-a30f-4834-9507-047d21052b90@z1g2000yqn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net X3uT6/8vgGneaufcd1cAFAso/6k1M6V44Dhsrrb4Y5lnzDHT0p Cancel-Lock: sha1:G9OErxrTAiRK3b1qfN33udP9zeo= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:632 saousouna.ing@gmail.com wrote: >>> can you please give me some links or useful courses onto the VHDL >>> image processing VHDL describes digital logic. Image processing is usually done in software. Learn image processing first and decide what you want to do to the image. Then decide what logic that requires. Gate and flops or a soft processor? Then learn to describe that in vhdl. Keep it very simple -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!news.glorb.com!postnews.google.com!c11g2000yqj.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: combinatorial feedback loop Date: Wed, 11 Mar 2009 17:20:05 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: NNTP-Posting-Host: 74.12.53.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236817205 12769 127.0.0.1 (12 Mar 2009 00:20:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 00:20:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c11g2000yqj.googlegroups.com; posting-host=74.12.53.216; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:633 On Mar 11, 2:39=A0pm, Ken Cecka wrote: > I'm playing around with different ways to count the number of '1' bits in= a vector. =A0I'll only be dealing with 6 bit vectors, so I could just do t= his with a lookup table, but I started with the most readable implementatio= n to see how it would synthesize (copied below). > > The Xilinx tools are synthesizing this into a single counter with a feedb= ack loop, and then telling me me that the design can run at 700MHz. =A0I'm = =A0a little skeptical - anyone know if it's reasonable to expect timing ana= lysis to unroll a feedback loop like this? > > Ken > > ENTITY test IS > =A0 GENERIC > =A0 ( > =A0 =A0 bits : INTEGER :=3D 6 > =A0 ); > =A0 PORT > =A0 ( > =A0 =A0 reset : IN =A0STD_LOGIC; > =A0 =A0 clk =A0 : IN =A0STD_LOGIC; > =A0 =A0 input : IN =A0STD_LOGIC_VECTOR((bits - 1) DOWNTO 0); > =A0 =A0 ones =A0: OUT STD_LOGIC_VECTOR(log2(bits) DOWNTO 0) > =A0 ); > END test; > > ARCHITECTURE model OF test IS > > =A0 SIGNAL input_l : STD_LOGIC_VECTOR(input'RANGE); > =A0 SIGNAL count : STD_LOGIC_VECTOR(ones'RANGE); > > BEGIN > > =A0 -- latch inputs and outputs for timing analysis > =A0 PROCESS (reset, clk) > =A0 BEGIN > =A0 =A0 IF (reset =3D '1') THEN > =A0 =A0 =A0 input_l <=3D (OTHERS =3D> '0'); > =A0 =A0 =A0 ones <=3D (OTHERS =3D> '0'); > =A0 =A0 ELSIF (clk'EVENT) AND (clk =3D '1') THEN > =A0 =A0 =A0 input_l <=3D input; > =A0 =A0 =A0 ones <=3D count; > =A0 =A0 END IF; > =A0 END PROCESS; > > =A0 -- count ones > =A0 PROCESS (input_l, count) > =A0 BEGIN > =A0 =A0 FOR i IN input_l'RANGE LOOP > =A0 =A0 =A0 IF (input_l(i) =3D '1') THEN > =A0 =A0 =A0 =A0 count <=3D count + 1; > =A0 =A0 =A0 END IF; > =A0 =A0 END LOOP; > =A0 END PROCESS; > > END; There are also lots of nifty ways to count ones that the software guys like to use. I haven't though through them enough to say whether they merely represent a way to reclaim the inherent inefficiency of launching a big ole 32-bit ALU op (the minimum unit of work in the software pipeline) for each measly one-bit, or whether you could exploit some of the insights to make faster gate-level hardware. If you want insane speed, I'm not sure how you could beat a (possibly pipelined) log adder tree from an algorithmic viewpoint. Random google hit from "count the number of ones": http://gurmeetsingh.wordpress.com/2008/08/05/fast-bit-counting-routines/ There is also some interesting work on fast decoding of VLC codes (MPEG video for example) using combinatorial decoding of parts of the input word to switch muxes to re-align the remainder of the input word to a successive decode stage. If you had any indication of the statistics (and were willing to play the statistics game, which is not always an option), you might be able to exploit the same idea, say for fast lookahead carry generation of halves or quarters of your input width. I realize this is a slight tangent to your original question, though... sorry :-) - Kenn From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!border1.nntp.dca.giganews.com!nntp.giganews.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc02.gnilink.net.POSTED!f388d8ac!not-for-mail Newsgroups: comp.lang.vhdl Followup-To: comp.lang.vhdl Lines: 34 From: Ken Cecka Subject: Re: combinatorial feedback loop References: User-Agent: KNode/0.99.01 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Message-ID: Date: Thu, 12 Mar 2009 00:41:46 GMT NNTP-Posting-Host: 98.117.108.7 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1236818506 98.117.108.7 (Wed, 11 Mar 2009 20:41:46 EDT) NNTP-Posting-Date: Wed, 11 Mar 2009 20:41:46 EDT Xref: news.eternal-september.org comp.lang.vhdl:634 kennheinrich@sympatico.ca wrote: > There are also lots of nifty ways to count ones that the software guys > like to use. I haven't though through them enough to say whether they > merely represent a way to reclaim the inherent inefficiency of > launching a big ole 32-bit ALU op (the minimum unit of work in the > software pipeline) for each measly one-bit, or whether you could > exploit some of the insights to make faster gate-level hardware. If > you want insane speed, I'm not sure how you could beat a (possibly > pipelined) log adder tree from an algorithmic viewpoint. > > Random google hit from "count the number of ones": > > http://gurmeetsingh.wordpress.com/2008/08/05/fast-bit-counting-routines/ > > > There is also some interesting work on fast decoding of VLC codes > (MPEG video for example) using combinatorial decoding of parts of the > input word to switch muxes to re-align the remainder of the input word > to a successive decode stage. If you had any indication of the > statistics (and were willing to play the statistics game, which is not > always an option), you might be able to exploit the same idea, say for > fast lookahead carry generation of halves or quarters of your input > width. > > I realize this is a slight tangent to your original question, > though... sorry :-) > > - Kenn I spent a little time looking over some of the software tricks earlier today. They seem to be mostly geared around minimizing serial instructions. The specific case I'm addressing is counting ones in a relatively small vector where I want to do it in a single clock cycle. Interestingly, I tried coding it with a chain of adders and as a lookup table, and the Xilinx compiler faithfully implemented this in the RTL schematic (adder chain and a ROM respectively), but they both reduced to the exact same logic in the technology schematic. Ken From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!41g2000yqf.googlegroups.com!not-for-mail From: "Zheyu.Gao@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Error --unconstrained record or array type is not supported Date: Wed, 11 Mar 2009 19:03:50 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: <1e8bf031-0dcc-4997-b3bc-4345ddc68505@41g2000yqf.googlegroups.com> NNTP-Posting-Host: 129.31.243.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236823430 22721 127.0.0.1 (12 Mar 2009 02:03:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 02:03:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 41g2000yqf.googlegroups.com; posting-host=129.31.243.40; posting-account=aLNF0AoAAAARXsoC0ewcgEhIvqNV6YxW User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.48 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:635 I was trying to compile the VHDL code with generic (Width:positive:= 8); In Quartus, I got the following error. Error (10427): VHDL aggregate error at GCD.vhd(49): OTHERS choice used in aggregate for unconstrained record or array type is not supported ----------------------------------------------------------------- library IEEE; use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; entity GCD is generic (Width:positive:= 8); ---I have also tried natural and integer, but all failed. port (Clock,Reset,Load: in std_logic; A,B: in unsigned(Width-1 downto 0); Done: out std_logic; Y: out unsigned(Width-1 downto 0)); end entity GCD; architecture RTL of GCD is signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0); signal A_lessthan_B: std_logic; begin ---------------------------------------------------- -- Load 2 input registers and ensure B_Hold < A_Hold --------------------------------------------------- LOAD_SWAP: process (Clock) begin if rising_edge(Clock) then if (Reset = '0') then A_Hold <= (others => '0'); B_Hold <= (others => '0'); elsif (Load = '1') then A_Hold <= A; B_Hold <= B; elsif (A_lessthan_B = '1') then A_Hold <= B_Hold; B_Hold <= A_New; else A_Hold <= A_New; end if; end if; end process LOAD_SWAP; SUBTRACT_TEST: process (A_Hold, B_Hold) begin ------------------------------------------------------- -- Subtract B_Hold from A_Hold if A_Hold >= B_Hold ------------------------------------------------------ if (A_Hold >= B_Hold) then A_lessthan_B <= '0'; A_New <= A_Hold - B_Hold; else A_lessthan_B <= '1'; A_New <= A_Hold; end if; ------------------------------------------------- -- Greatest common divisor found if B_Hold = 0 ------------------------------------------------- if (B_Hold = (others => '0')) then -- here is the error B_Hold = (others => '0') Done <= '1'; Y <= A_Hold; else Done <= '0'; Y <= (others => '0'); end if; end process SUBTRACT_TEST; end architecture RTL; ------------------------------------------------------------------------------- I also googled some topic about it, is it true that when using generics, B_Hold = (others => '0') OTHERS choice used in aggregate for unconstrained record or array type is not supported? From newsfish@newsfish Wed Aug 19 13:23:43 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!l16g2000yqo.googlegroups.com!not-for-mail From: "Zheyu.Gao@googlemail.com" Newsgroups: comp.lang.vhdl Subject: why is this code wrong? generic or others? Date: Wed, 11 Mar 2009 21:32:10 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: NNTP-Posting-Host: 78.86.244.89 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236832330 18775 127.0.0.1 (12 Mar 2009 04:32:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 04:32:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l16g2000yqo.googlegroups.com; posting-host=78.86.244.89; posting-account=aLNF0AoAAAARXsoC0ewcgEhIvqNV6YxW User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; CIBA),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:636 library IEEE; use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; entity GCD is generic (Width: natural:=8); port (Clock,Reset,Load: in std_logic; A,B: in unsigned(Width-1 downto 0); Done: out std_logic; Y: out unsigned(Width-1 downto 0)); end entity GCD; architecture RTL of GCD is signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0); signal A_lessthan_B: std_logic; begin ---------------------------------------------------- -- Load 2 input registers and ensure B_Hold < A_Hold --------------------------------------------------- LOAD_SWAP: process (Clock) begin if rising_edge(Clock) then if (Reset = '0') then A_Hold <= (others => '0'); B_Hold <= (others => '0'); elsif (Load = '1') then A_Hold <= A; B_Hold <= B; elsif (A_lessthan_B = '1') then A_Hold <= B_Hold; B_Hold <= A_New; else A_Hold <= A_New; end if; end if; end process LOAD_SWAP; SUBTRACT_TEST: process (A_Hold, B_Hold) begin ------------------------------------------------------- -- Subtract B_Hold from A_Hold if A_Hold >= B_Hold ------------------------------------------------------ if (A_Hold >= B_Hold) then A_lessthan_B <= '0'; A_New <= A_Hold - B_Hold; else A_lessthan_B <= '1'; A_New <= A_Hold; end if; ------------------------------------------------- -- Greatest common divisor found if B_Hold = 0 ------------------------------------------------- if (B_Hold = (others => '0')) then Done <= '1'; Y <= A_Hold; else Done <= '0'; Y <= (others => '0'); end if; end process SUBTRACT_TEST; end architecture RTL; From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Mar 2009 04:14:24 -0500 Date: Thu, 12 Mar 2009 09:14:20 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Error --unconstrained record or array type is not supported References: <1e8bf031-0dcc-4997-b3bc-4345ddc68505@41g2000yqf.googlegroups.com> In-Reply-To: <1e8bf031-0dcc-4997-b3bc-4345ddc68505@41g2000yqf.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 58 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-YXTD3EFKVLPYxR4JZmVqab30+/nTvg9QWDtKEjU2FXiJfbxPpBliiUY07I+sMgi1q+kDH8VRkm5sUf7!CJQsTzyoXZty7scbS3jzN3jwToLhI0WOYhPbhzGXOdTqc+p1kIcQH5S4cx3fg8len1xx82OXFdiF!mnzRJcdwbK8= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:637 Zheyu.Gao@googlemail.com wrote: > I was trying to compile the VHDL code with generic (Width:positive:= > 8); > > In Quartus, I got the following error. > Error (10427): VHDL aggregate error at GCD.vhd(49): OTHERS choice used > in aggregate for unconstrained record or array type is not supported > ----------------------------------------------------------------- > library IEEE; > use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; > entity GCD is > generic (Width:positive:= 8); ---I have also tried natural and > integer, but all failed. > port (Clock,Reset,Load: in std_logic; > A,B: in unsigned(Width-1 downto 0); > Done: out std_logic; > Y: out unsigned(Width-1 downto 0)); > end entity GCD; > architecture RTL of GCD is > signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0); > signal A_lessthan_B: std_logic; > begin > if (B_Hold = (others => '0')) then -- here is the error B_Hold = > (others => '0') > ------------------------------------------------------------------------------- > I also googled some topic about it, is it true that when using > generics, B_Hold = (others => '0') OTHERS choice used in aggregate for > unconstrained record or array type is not supported? Yes it's true. The expression (others => '0') doesn't hold enough type information to make the compiler happy. There are various ways round this: 1. use a subtype, e.g. subtype vecT is unsigned (width -1 downto 0); ... if B_hold = VecT'(others => '0') 2. The other way is to use the aggregate itself by naming the aggregate choices, e.g. if B_hold = (Width -1 downto 0 => '0') then I haven't tried these in Quartus, regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!xlned.com!feeder3.xlned.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.82.MISMATCH!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-ID: <49B8D5AC.30906@xs4all.nl> Date: Thu, 12 Mar 2009 10:28:12 +0100 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Steffen Koepf Subject: Re: Timing Problems with counter References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 40 NNTP-Posting-Host: 80.127.156.245 X-Trace: 1236850092 news.xs4all.nl 196 [::ffff:80.127.156.245]:54868 X-Complaints-To: abuse@xs4all.nl Xref: news.eternal-september.org comp.lang.vhdl:638 Hello Steffen, > what i need is a counter that counts from a preset value down to 0 > with a clock outside of the system clock domain. The counter run > on a Cyclone III, 15 out of 16 of the counters work well, but one > counts much too slow. Here is the relevant part of the code: Please don't use both flanks of a clock, and properly transfer signals from one clock domain to the next before using them or you will run into timing and/or meta-stability issues. As an example (I hope I understood your code correctly, and I don't use asynchronous resets): delaycounter: PROCESS IS BEGIN WAIT UNTIL clk = '1'; fcounter_c2c <= fcounter; fcounter_meta <= fcounter_c2c; fcounter_d <= fcounter_meta; IF cntr_reload = '1' THEN dcntFin <= '0'; dcounter <= dcounterLoadVal; ELSIF unsigned( dcounter ) = 0 THEN dcntFin <= '1'; ELSIF fcounter_meta = '1' AND fcounter_d <= '0' THEN -- rising edge fcounter dcounter <= std_logic_vector( unsigned( dcounter ) - 1 ); END IF; IF rst = '1' THEN dcntFin <= '0'; dcounter <= (OTHERS => '0'); END IF; END PROCESS delaycounter; Keep in mind that since cntr_reload is not synchronized with regards to fcounter, your counter is never completely accurate. Also, are you sure you want the reset value of dcntFin to be 0 in stead of 1? What is that signal used for anyway? Kind regards, Pieter Hulshoff From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!gnilink.net!nx01.iad.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Mar 2009 10:22:10 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Error --unconstrained record or array type is not supported Date: Thu, 12 Mar 2009 15:23:08 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <1e8bf031-0dcc-4997-b3bc-4345ddc68505@41g2000yqf.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-wiN5Tbm4b8rlKAKpJYOQN0U33WclSviGDcOIf7bG4m3VSaUrvddjSP2hH4VYasoZhmhNVXkXa2pJovY!ZGvVUZ+wrEUUK21FXAqA+1F1Wk5BGdWTSJf5CAmBaXU0WjgSb+jpvfIkDpAP1Ja+GHk39OcfOkzQ!4Ps= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:639 On Wed, 11 Mar 2009 19:03:50 -0700 (PDT), "Zheyu.Gao@googlemail.com" wrote: >I was trying to compile the VHDL code with generic (Width:positive:= >8); > >In Quartus, I got the following error. >Error (10427): VHDL aggregate error at GCD.vhd(49): OTHERS choice used >in aggregate for unconstrained record or array type is not supported > if (B_Hold = (others => '0')) then -- here is the error It is an error because you can overload "=" with an "=" operator which works on different size operands (typically returning false if different size). Therefore the parser cannot possibly know how many "others" there are. The solution is to make the RHS operand explicitly the same size as the LHS operand, whatever that size is. One reliable way is simply if (B_Hold = (B_Hold'range => '0')) then - Brian From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!xlned.com!feeder3.xlned.com!feeder.news-service.com!news.astraweb.com!border5.newsrouter.astraweb.com!multikabel.net!newsfeed10.multikabel.net!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe13.iad.POSTED!7564ea0f!not-for-mail From: russ User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: "Independent" Simulation of Xilinx Project Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 13 Message-ID: NNTP-Posting-Host: mkfkbbjnhfndffocjdjfcjdicfphdbka X-Complaints-To: abuse@charter.net X-Trace: jkfjokholhdhgpccmcjobjcmnmlfmhhadnbcbjjmgdbbgafpmkfkbbjnhfndffocnaoimanamdgelmgdonpeckkmcgeplodoemlnafeehblopdjofkjkdhkapimgmgecfdlbpmaelemcakjp NNTP-Posting-Date: Thu, 12 Mar 2009 15:33:50 UTC Date: Thu, 12 Mar 2009 11:33:49 -0400 Xref: news.eternal-september.org comp.lang.vhdl:640 We are doing a simple pld using Xilinx ISE 9.2i. The project began with 9.2i and must be finished with 9.2i. We are working under DO-254 and need to do either tool qualification or independent verification and validation with another tool set. GHDL and GTKWave have been chosen as the second tool set. But the customer objects that we are still using the Xilinx VITAL, primsim, etc., libraries. Is there an independent implementation of these libraries for GHDL? I've googled and got lots of links, but sorting through them hasn't revealed much yet. Thanks From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j8g2000yql.googlegroups.com!not-for-mail From: Yannick Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library Date: Thu, 12 Mar 2009 09:21:06 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <02f45710-2bbe-4369-972f-495608c15a94@j8g2000yql.googlegroups.com> References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> <9aeab337-c5c8-4f10-b7aa-15ccbd92711a@w35g2000yqm.googlegroups.com> NNTP-Posting-Host: 57.67.17.100 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236874866 26318 127.0.0.1 (12 Mar 2009 16:21:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 16:21:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j8g2000yql.googlegroups.com; posting-host=57.67.17.100; posting-account=AnwwuQoAAAA0TgmjlOPRF8wZVlHhbblJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; GTB5; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:641 On 9 mar, 19:51, Jacko wrote: > On 27 Feb, 12:46, Yannick wrote: > > > Hi, > > > I need to use the arithmetic library but I don't find it! > > > I need to use arithmetic.std_logic_arith and I don't want change for > > another library. > > > Where I can find it? > > > Thks > > Useually for standard libraries they will be in the ieee tree. I say > use which ever you want, they are very similar, but some type > conversion issues exist. > > library ieee; > > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > > you could use ieee.numeric_std.all as well or instead of this will > slightly change the code needed, i.e. a slight cast changing, but not > much else will differ. The packages differ IIRC in that > std_logic_arith has arithmetic functions which produce > std_logic_vector, where as numeric_std is focused on producing numeric > results, which then can be cast/autocast to std_logic_vector. > > There are many opinions, but i have had no concrete rational as to why > one is better than the other. > > cheers jacko I try to simulate a old design on ACTEL. For safety and no more step, I need to use the same library than the first compilation in 1999. I know ieee library and I use it for all my design but I can't to use it here. I haven't any choice, it's the protocol. Voila thanks yannick From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!xlned.com!feeder3.xlned.com!news2.euro.net!zen.net.uk!demorgan.zen.co.uk!nx02.iad.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Mar 2009 11:34:21 -0500 Date: Thu, 12 Mar 2009 16:34:21 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> <9aeab337-c5c8-4f10-b7aa-15ccbd92711a@w35g2000yqm.googlegroups.com> <02f45710-2bbe-4369-972f-495608c15a94@j8g2000yql.googlegroups.com> In-Reply-To: <02f45710-2bbe-4369-972f-495608c15a94@j8g2000yql.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Ajuqy4igH42oEr1Emw7awFO5MSLrIcM7SC9OvSlDTL2URI2GyzJqP2ujTFe+JoWUyQAxVcIBcNUox3y!8KCyXlOY9eE9cB4ifltRPTsd52wLMRfvKUT2VxV4RwlLUi8cod08Fi/8gKnEHTKx5XnhwbQdiD/5!2w6T65o6EXw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:642 Yannick wrote: > On 9 mar, 19:51, Jacko wrote: > I try to simulate a old design on ACTEL. For safety and no more step, > I need to use the same > library than the first compilation in 1999. > > I know ieee library and I use it for all my design but I can't to use > it here. I haven't any choice, it's the protocol. > > Voila > > thanks > > yannick I would suggest you contact Actel Technical Support at tech@actel.com, they may be able to make obsolete versions of their design software available to you, regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!a39g2000yqc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga Subject: Re: Integer arithmetic in HDLs Date: Thu, 12 Mar 2009 09:34:46 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <84f1f41b-9eab-47bf-bfa7-21db59c873a8@a39g2000yqc.googlegroups.com> References: <49b67351$0$2856$ba620e4c@news.skynet.be> <1a0c3206-481d-4773-b5bb-3f7ecf0861f3@v1g2000prd.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236875686 5001 127.0.0.1 (12 Mar 2009 16:34:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 16:34:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a39g2000yqc.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:643 comp.lang.verilog:194 comp.arch.fpga:1657 If we use VHDL integer arithmetic as a model, all operations are promoted to 32 bit signed (i.e. the largest size available), regardless of the subranges or signedness of the operands. Then the results are automatically truncated upon assignment to a subranged (and either natural or integer) object. Synthesis will prune intermediate results based on the final truncation. One VHDL arithmetic type not mentioned in the paper is the new ieee fixed point types (ufixed & sfixed), which also work well for integers with a zero rightmost index (i.e. zero digits to the right of the binary point). What is different between fixed point (ufixed & sfixed) and numeric_std (signed & unsigned) arithmetic, is that addition/ subtraction is always promoted by one bit to handle potential overflow, which effectively duplicates the promotion part of the behavior of integer arithmetic. Unfortunately, what is not included is the promotion of ufixed operands to an sfixed result for subtraction. This is really interesting since subtraction of two ufixed operands still increases the bit size by one, but still does not make it signed. There is also no definition of any operators for mixed ufixed/ sfixed operands. I think "fixing" the automatic truncation of vectors on assignment is probably on the "too hard" list without changing a lot of existing behavior in the VHDL language, unless overloading the assignment operator was allowed. Promotion of all results to sfixed (save perhaps addition of two ufixed operands) is not too hard, and should be considered, especially since a truncation function is almost always needed anyway, and could be combined with a sfixed/ufixed conversion. With these additions/changes, the fixed point type model could go a long ways toward providing integer-like arithmetic with arbitrary width data. Andy From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!a5g2000pre.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project Date: Thu, 12 Mar 2009 10:32:47 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com> References: NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236879167 16360 127.0.0.1 (12 Mar 2009 17:32:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 17:32:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a5g2000pre.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:644 On Mar 12, 8:33=A0am, russ wrote: > We are doing a simple pld using Xilinx ISE 9.2i. The project began with > 9.2i and must be finished with 9.2i. > > We are working under DO-254 and need to do either tool qualification or > independent verification and validation with another tool set. GHDL and > GTKWave have been chosen as the second tool set. But the customer > objects that we are still using the Xilinx VITAL, primsim, etc., librarie= s. > > Is there an independent implementation of these libraries for GHDL? > I've googled and got lots of links, but sorting through them hasn't > revealed much yet. Sounds like your customer is the typical military type with his head up his ass. -a From newsfish@newsfish Wed Aug 19 13:23:44 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Mar 2009 12:38:37 -0500 Date: Thu, 12 Mar 2009 17:38:37 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-OCAxxP/xW6DZ1PR+F9jBH3hcGlWhLvG4MUmrncN1XCZC85WqQaWpZ0OdMfjK2Eg8lO7/9bb+R0FXKuX!LcoEHFpuTC/1Y7NKbCik8g6isa+YulftGuHccLCc1rBC4PmfUxLT2+Oyxx4GsvykdcyLzkjHtYKp!Olhhp3WgX2c= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:645 russ wrote: > We are doing a simple pld using Xilinx ISE 9.2i. The project began with > 9.2i and must be finished with 9.2i. > > We are working under DO-254 and need to do either tool qualification or > independent verification and validation with another tool set. GHDL and > GTKWave have been chosen as the second tool set. But the customer > objects that we are still using the Xilinx VITAL, primsim, etc., libraries. > > Is there an independent implementation of these libraries for GHDL? I've > googled and got lots of links, but sorting through them hasn't revealed > much yet. > > Thanks Can't you argue that gate level simulation in ISE is verified by the actual hardware? If the hardware behaves the same as the gate level simulation doesn't that mean something? Then you can restrict the two tool sets as a cross check of RTL behaviour. regards Alan -- Alan Fitch Doulos http://www.doulos.com From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe17.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com> Subject: Re: "Independent" Simulation of Xilinx Project Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.127.59 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe17.ams2 1236881810 86.16.127.59 (Thu, 12 Mar 2009 18:16:50 UTC) NNTP-Posting-Date: Thu, 12 Mar 2009 18:16:50 UTC Organization: virginmedia.com Date: Thu, 12 Mar 2009 18:16:38 -0000 Xref: news.eternal-september.org comp.lang.vhdl:646 "Andy Peters" wrote in message news:109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com... On Mar 12, 8:33 am, russ wrote: > We are doing a simple pld using Xilinx ISE 9.2i. The project began with > 9.2i and must be finished with 9.2i. > > We are working under DO-254 and need to do either tool qualification or > independent verification and validation with another tool set. GHDL and > GTKWave have been chosen as the second tool set. But the customer > objects that we are still using the Xilinx VITAL, primsim, etc., > libraries. > > Is there an independent implementation of these libraries for GHDL? > I've googled and got lots of links, but sorting through them hasn't > revealed much yet. >Sounds like your customer is the typical military type with his head >up his ass. very good, there isn't enough humour on this newsgroup :-) Russ, I would suggest you contact your DER and discuss the tools issue before going on a tangent with GHDL. Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!news-2.dfn.de!news.uni-stuttgart.de!newsfeed.in-ulm.de!not-for-mail From: Steffen Koepf Newsgroups: comp.lang.vhdl Subject: Re: Timing Problems with counter Date: Thu, 12 Mar 2009 23:10:50 +0100 (CET) Organization: [ posted via ] IN-Ulm Lines: 78 Sender: Steffen Koepf Message-ID: References: <49B8D5AC.30906@xs4all.nl> X-Trace: news.in-ulm.de 302F26FF98FB3570E4B173BE0598369D User-Agent: tin/pre-1.4-19990805 ("Preacher Man") (UNIX) (Linux/2.6.25.10 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:647 Hello Pieter, Pieter Hulshoff wrote: > Please don't use both flanks of a clock, Why should one not use this? I know falling edges are not supported on some devices, but when it is supported? > clock domain to the next before using them or you will run into timing and/or > meta-stability issues. As an example (I hope I understood your code correctly, > and I don't use asynchronous resets): In the mean time i improved my code a bit and added a rising-edge synchronizer: -- transfer clock domain, fcntnext is in the system clockdomain cntrclk: process (clk, rst) begin if (rst = '1') then clksyncstage1 <= '0'; clksyncstage2 <= '0'; edgedetectff <= '0'; elsif falling_edge(clk) then clksyncstage1 <= fcounter; clksyncstage2 <= clksyncstage1; edgedetectff <= clksyncstage2; end if; end process cntrclk; cntrclkedge: process (clksyncstage2, edgedetectff) begin fcntnext <= clksyncstage2 and (not edgedetectff); end process cntrclkedge; That solved my problem and the counter works fine now: delaycounter: process (clk, rst) begin if (rst = '1') then dcntFin <= '0'; dcounter <= (others => '0'); elsif rising_edge(clk) then if cntr_reload = '1' then dcntFin <= '0'; dcounter <= dcounterLoadVal; -- Load counter with previous stored val elsif dcounter = std_logic_vector(to_unsigned(0, dcounter_bits)) then dcntFin <= '1'; elsif fcntnext = '1' then dcounter <= std_logic_vector(unsigned(dcounter) - 1); end if; end if; end process delaycounter; Your code should do the same, thank you. > Keep in mind that since cntr_reload is not synchronized with regards to > fcounter, your counter is never completely accurate. Also, are you sure you want > the reset value of dcntFin to be 0 in stead of 1? What is that signal used for > anyway? The signal dcntFin is used as input for a gate for error-signals (from an analogous comparator outside of the fpga). After a enable signal is released, the counter starts to run. As long as enable is low (then cntr_reload = 1) or the counter is running for a certain time after enable switched to 1, the error-signals are "blanked out" so that a overshoot of switching power supplies after switching on (by enable) does not trigger an error. The counter is a 16 bit counter and it is not important if one or two clocks are not counted/wrong counted. Thank you, Steffen Koepf From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!a12g2000yqm.googlegroups.com!not-for-mail From: saousouna.ing@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Look for documentation Date: Thu, 12 Mar 2009 15:19:24 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <00d2e692-29dc-4ca1-8cc0-bdcd699f3a6a@a12g2000yqm.googlegroups.com> References: <8cfea046-a30f-4834-9507-047d21052b90@z1g2000yqn.googlegroups.com> <49B842D4.3080905@gmail.com> NNTP-Posting-Host: 41.226.85.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236896365 6931 127.0.0.1 (12 Mar 2009 22:19:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Mar 2009 22:19:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a12g2000yqm.googlegroups.com; posting-host=41.226.85.40; posting-account=AQpTVgoAAACxIEgoRrIE7gz0b8ffU8Me User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:648 On 12 mar, 00:01, Mike Treseler wrote: > saousouna....@gmail.com wrote: > >>> can you please =A0give me some links or useful courses =A0onto the = =A0VHDL > >>> image processing > > VHDL describes digital logic. > Image processing is usually done in software. > Learn image processing first > and decide what you want to > do to the image. > > Then decide what logic that requires. > Gate and flops or a soft processor? > > Then learn to describe that in vhdl. > Keep it very simple > > =A0 =A0 =A0-- Mike Treseler Thank you very much for your answer, but the use of a material solution is let us say imposed by my superintendent. We are going to work at the beginning with the hard (we program in VHDL and we implement on a FPGA) and later with the soft (we program with of C and we implement on a NIOS Processor) and at the end we have to compare both results(profits) From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!v15g2000yqn.googlegroups.com!not-for-mail From: Aiken Newsgroups: comp.lang.vhdl Subject: Re: why is this code wrong? generic or others? Date: Thu, 12 Mar 2009 17:31:10 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <9a7dac9c-4ff1-4bff-b9a6-d3395da1aa78@v15g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 199.10.150.41 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1236904270 24971 127.0.0.1 (13 Mar 2009 00:31:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Mar 2009 00:31:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v15g2000yqn.googlegroups.com; posting-host=199.10.150.41; posting-account=o1NIRQoAAACD94UsAWOsHscwtNA8hiam User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:649 What's the error? On Mar 12, 12:32=A0am, "Zheyu....@googlemail.com" wrote: > library IEEE; > use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; > entity GCD is > generic (Width: natural:=3D8); > port (Clock,Reset,Load: in std_logic; > =A0 =A0A,B: =A0 in unsigned(Width-1 downto 0); > =A0 =A0Done: =A0out std_logic; > =A0 =A0Y: =A0 =A0 out unsigned(Width-1 downto 0)); > end entity GCD; > architecture RTL of GCD is > =A0 =A0signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0); > =A0 =A0signal A_lessthan_B: std_logic; > begin > ---------------------------------------------------- > -- Load 2 input registers and ensure B_Hold < A_Hold > --------------------------------------------------- > LOAD_SWAP: process (Clock) > begin > =A0 =A0if rising_edge(Clock) then > =A0 =A0 =A0if (Reset =3D '0') then > =A0 =A0 =A0 =A0A_Hold <=3D (others =3D> '0'); > =A0 =A0 =A0 =A0B_Hold <=3D (others =3D> '0'); > =A0 =A0 =A0elsif (Load =3D '1') then > =A0 =A0 =A0 =A0A_Hold <=3D A; > =A0 =A0 =A0 =A0B_Hold <=3D B; > =A0 =A0 =A0elsif (A_lessthan_B =3D '1') then > =A0 =A0 =A0 =A0A_Hold <=3D B_Hold; > =A0 =A0 =A0 =A0B_Hold <=3D A_New; > =A0 =A0 =A0else A_Hold <=3D A_New; > =A0 =A0 =A0end if; > =A0 =A0end if; > end process LOAD_SWAP; > SUBTRACT_TEST: process (A_Hold, B_Hold) > begin > =A0 =A0------------------------------------------------------- > =A0 =A0-- Subtract B_Hold from A_Hold if A_Hold >=3D B_Hold > =A0 =A0------------------------------------------------------ > =A0 =A0if (A_Hold >=3D B_Hold) then > =A0 =A0 =A0 A_lessthan_B <=3D '0'; > =A0 =A0 =A0 A_New <=3D A_Hold - B_Hold; > =A0 =A0else > =A0 =A0 =A0 A_lessthan_B <=3D '1'; > =A0 =A0 =A0 A_New <=3D A_Hold; > =A0 =A0end if; > =A0 =A0------------------------------------------------- > =A0 =A0-- Greatest common divisor found if B_Hold =3D 0 > =A0 =A0------------------------------------------------- > =A0 =A0if (B_Hold =3D (others =3D> '0')) then > =A0 =A0 =A0 Done <=3D '1'; > =A0 =A0 =A0 Y <=3D A_Hold; > =A0 =A0else > =A0 =A0 =A0 Done <=3D '0'; > =A0 =A0 =A0 Y <=3D (others =3D> '0'); > =A0 =A0end if; > end process SUBTRACT_TEST; > end architecture RTL; From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o11g2000yql.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project Date: Fri, 13 Mar 2009 00:34:20 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <57569307-db64-42bd-9357-50bf82df46df@o11g2000yql.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236929660 15610 127.0.0.1 (13 Mar 2009 07:34:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Mar 2009 07:34:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yql.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.6) Gecko/2009020409 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:650 On 12 Mrz., 16:33, russ wrote: > We are doing a simple pld using Xilinx ISE 9.2i. The project began with > 9.2i and must be finished with 9.2i. > > We are working under DO-254 and need to do either tool qualification or > independent verification and validation with another tool set. GHDL and > GTKWave have been chosen as the second tool set. But the customer > objects that we are still using the Xilinx VITAL, primsim, etc., libraries. > > Is there an independent implementation of these libraries for GHDL? > I've googled and got lots of links, but sorting through them hasn't > revealed much yet. > > Thanks Hi russ, maybe you can point out to your customer, that libraries are part of the source code, not of the simulator tools. The mentioned libs are a description of the hardware you are using, and therefore as unique as your own source code. Or do you have multiple versions of your sources (e.g. one in vhdl, and another in verilog)? Well, the libs are also available in two HDLs, so you could do multilingual cross-simulation. e.g. vhdl soure with vhdl lib , verilog source with vhdl lib, vhdl source with verilog lib, verilog source with verilog lib Have a nice simulation Eilert From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!p20g2000yqi.googlegroups.com!not-for-mail From: Yannick Newsgroups: comp.lang.vhdl Subject: Re: Search arithmetic library Date: Fri, 13 Mar 2009 00:42:42 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <8e075c1a-7b01-4056-abe3-f7ff02034da0@g38g2000yqd.googlegroups.com> <9aeab337-c5c8-4f10-b7aa-15ccbd92711a@w35g2000yqm.googlegroups.com> <02f45710-2bbe-4369-972f-495608c15a94@j8g2000yql.googlegroups.com> NNTP-Posting-Host: 57.67.17.100 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236930162 10658 127.0.0.1 (13 Mar 2009 07:42:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Mar 2009 07:42:42 +0000 (UTC) Cc: Alan Fitch Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqi.googlegroups.com; posting-host=57.67.17.100; posting-account=AnwwuQoAAAA0TgmjlOPRF8wZVlHhbblJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; GTB5; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:651 On 12 mar, 17:34, Alan Fitch wrote: > Yannick wrote: > > On 9 mar, 19:51, Jacko wrote: > > > > > I try to simulate a old design on ACTEL. For safety and no more step, > > I need to use the same > > library than the first compilation in 1999. > > > I know ieee library and I use it for all my design but I can't to use > > it here. I haven't any choice, it's the protocol. > > > Voila > > > thanks > > > yannick > > I would suggest you contact Actel Technical Support at tech@actel.com, > they may be able to make obsolete versions of their design software > available to you, > > regards > Alan > > -- > Alan Fitch > Douloshttp://www.doulos.com I try to contact us!! Thanks From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!nntp.giganews.com!nx01.iad.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe14.iad.POSTED!7564ea0f!not-for-mail From: russ User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 30 Message-ID: <8crul.108583$fM1.60436@newsfe14.iad> NNTP-Posting-Host: mkfkbbjnhfndffocjdjfcjdicfphdbka X-Complaints-To: abuse@charter.net X-Trace: dohedhpnjnemncfkmcjobjcmnmlfmhhamokeocfmadfoeknkmkfkbbjnhfndffocmgbgbjgpjinhijmagfhelacieiedifdcemlnafeehblopdjommojmddnlddjjcdcfdlbpmaelemcakjp NNTP-Posting-Date: Fri, 13 Mar 2009 11:12:04 UTC Date: Fri, 13 Mar 2009 07:12:03 -0400 Xref: news.eternal-september.org comp.lang.vhdl:652 Alan Fitch wrote: > russ wrote: >> We are doing a simple pld using Xilinx ISE 9.2i. The project began >> with 9.2i and must be finished with 9.2i. >> >> We are working under DO-254 and need to do either tool qualification >> or independent verification and validation with another tool set. GHDL >> and GTKWave have been chosen as the second tool set. But the customer >> objects that we are still using the Xilinx VITAL, primsim, etc., >> libraries. >> >> Is there an independent implementation of these libraries for GHDL? >> I've googled and got lots of links, but sorting through them hasn't >> revealed much yet. >> >> Thanks > > Can't you argue that gate level simulation in ISE is verified by the > actual hardware? If the hardware behaves the same as the gate level > simulation doesn't that mean something? > > Then you can restrict the two tool sets as a cross check of RTL > behaviour. > > regards > Alan > That solution is our Plan A, and might be accepted. I'm working on plan B, just in case. Plan C is to get the tool qualified, which will be expensive. Then there is Plan 9... From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post02.iad.highwinds-media.com!newsfe14.iad.POSTED!7564ea0f!not-for-mail From: russ User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project References: <109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com> In-Reply-To: <109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 Message-ID: <6grul.108585$fM1.10152@newsfe14.iad> NNTP-Posting-Host: mkfkbbjnhfndffocjdjfcjdicfphdbka X-Complaints-To: abuse@charter.net X-Trace: dohedhpnjnemncfkmcjobjcmnmlfmhhaddakcgdmhfofnnaemkfkbbjnhfndffocmgbgbjgpjinhijmagfhelacieiedifdcemlnafeehblopdjooefjjdkhlojmdifefdlbpmaelemcakjp NNTP-Posting-Date: Fri, 13 Mar 2009 11:16:18 UTC Date: Fri, 13 Mar 2009 07:16:18 -0400 Xref: news.eternal-september.org comp.lang.vhdl:653 Andy Peters wrote: > On Mar 12, 8:33 am, russ wrote: >> We are doing a simple pld using Xilinx ISE 9.2i. The project began with >> 9.2i and must be finished with 9.2i. >> >> We are working under DO-254 and need to do either tool qualification or >> independent verification and validation with another tool set. GHDL and >> GTKWave have been chosen as the second tool set. But the customer >> objects that we are still using the Xilinx VITAL, primsim, etc., libraries. >> >> Is there an independent implementation of these libraries for GHDL? >> I've googled and got lots of links, but sorting through them hasn't >> revealed much yet. > > Sounds like your customer is the typical military type with his head > up his ass. > > -a The guy with the big checkbook never has his head up his ass. You play by his rules or find another game. From newsfish@newsfish Wed Aug 19 13:23:45 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe23.iad.POSTED!7564ea0f!not-for-mail From: russ User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project References: <109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 36 Message-ID: <2Srul.41812$l71.11010@newsfe23.iad> NNTP-Posting-Host: mkfkbbjnhfndffocjdjfcjdicfphdbka X-Complaints-To: abuse@charter.net X-Trace: aeeollfjikkhiokkmcjobjcmnmlfmhhamninopbnojmppjlmmkfkbbjnhfndffocmgbgbjgpjinhijmagfhelacieiedifdcemlnafeehblopdjoddfdphcehlkkcnckfdlbpmaelemcakjp NNTP-Posting-Date: Fri, 13 Mar 2009 11:56:46 UTC Date: Fri, 13 Mar 2009 07:56:46 -0400 Xref: news.eternal-september.org comp.lang.vhdl:654 HT-Lab wrote: > "Andy Peters" wrote in message > news:109cb2ab-b79a-470b-9c87-c9841159a9ed@a5g2000pre.googlegroups.com... > On Mar 12, 8:33 am, russ wrote: >> We are doing a simple pld using Xilinx ISE 9.2i. The project began with >> 9.2i and must be finished with 9.2i. >> >> We are working under DO-254 and need to do either tool qualification or >> independent verification and validation with another tool set. GHDL and >> GTKWave have been chosen as the second tool set. But the customer >> objects that we are still using the Xilinx VITAL, primsim, etc., >> libraries. >> >> Is there an independent implementation of these libraries for GHDL? >> I've googled and got lots of links, but sorting through them hasn't >> revealed much yet. > >> Sounds like your customer is the typical military type with his head >> up his ass. > > very good, there isn't enough humour on this newsgroup :-) > > Russ, I would suggest you contact your DER and discuss the tools issue > before going on a tangent with GHDL. > > Hans > www.ht-lab.com > > > > Thanks, that is under discussion. The object here is to present "alternatives" with costs. Also thrown into the mix is obsolescence planing and robustness. My root reason for this post is to propose two independent low-cost means of verifying the design. GHDL isn't a reqirement cast in stone. From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p20g2000yqi.googlegroups.com!not-for-mail From: "zooplibob@gmail.com" Newsgroups: comp.lang.vhdl Subject: State machine incrementing Date: Fri, 13 Mar 2009 16:06:23 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: NNTP-Posting-Host: 192.94.94.105 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236985584 32727 127.0.0.1 (13 Mar 2009 23:06:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Mar 2009 23:06:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqi.googlegroups.com; posting-host=192.94.94.105; posting-account=sIc8CgoAAAC7GIxo1LeRrr1HPqDKDdgx User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) X-HTTP-Via: 1.0 proxysb01 (NetCache NetApp/6.0.5) Xref: news.eternal-september.org comp.lang.vhdl:655 I have the following code in my state machine for an I2C controller. Basically when I get to state data_out4, I want to increment the variable "datacount" by 1. However I stay in that state for many clock cycles and it increments many times. How can I code it so that it increments the variable only once when I'm in that state? Thanks elsif state = data_out1 then sda_sig <= 'Z'; scl_sig <= '0'; elsif state = data_out2 then if data_out(7-datacount) = '0' then sda_sig <= '0'; else sda_sig <= 'Z'; end if; scl_sig <= '0'; elsif state = data_out3 then if data_out(7-datacount) = '0' then sda_sig <= '0'; else sda_sig <= 'Z'; end if; scl_sig <= '1'; elsif state = data_out4 then if data_out(7-datacount) = '0' then sda_sig <= '0'; else sda_sig <= 'Z'; end if; scl_sig <= '0'; datacount:=datacount+1; From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!postnews.google.com!w34g2000yqm.googlegroups.com!not-for-mail From: Jeff Newsgroups: comp.lang.vhdl Subject: Re: State machine incrementing Date: Fri, 13 Mar 2009 16:35:08 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: NNTP-Posting-Host: 192.94.94.105 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1236987308 5831 127.0.0.1 (13 Mar 2009 23:35:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Mar 2009 23:35:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w34g2000yqm.googlegroups.com; posting-host=192.94.94.105; posting-account=sIc8CgoAAAC7GIxo1LeRrr1HPqDKDdgx User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) X-HTTP-Via: 1.0 proxysb01 (NetCache NetApp/6.0.5) Xref: news.eternal-september.org comp.lang.vhdl:656 Its interesting that it simulates correctly in the Xilinx simulator, but when running on the CPLD, it increments as fast as possible. I think this is more of a synthesis problem, because I could just expand those lines instead of using the variable "datacount" hardcode it from 0 to 7 and just copy and paste the whole thing 7 times, but it seems like I should be able to write it like this and have it synthesize properly From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi148.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: Subject: Re: State machine incrementing Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi148.ffdc.sbc.com 1236991856 ST000 99.184.242.197 (Fri, 13 Mar 2009 20:50:56 EDT) NNTP-Posting-Date: Fri, 13 Mar 2009 20:50:56 EDT Organization: at&t http://my.att.net/ X-UserInfo1: S[OER[ODPRUORRPXIZOD]_\@VR]^@B@MCPWZKB]MPXHJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Fri, 13 Mar 2009 20:50:53 -0400 Xref: news.eternal-september.org comp.lang.vhdl:657 wrote in message news:cfda7a27-6949-48a8-9fad-a29bd6704a61@p20g2000yqi.googlegroups.com... >I have the following code in my state machine for an I2C controller. > Basically when I get to state data_out4, I want to increment the > variable "datacount" by 1. However I stay in that state for many clock > cycles and it increments many times. How can I code it so that it > increments the variable only once when I'm in that state? Thanks > 1. Use a synchronous process process(Clock) begin if rising_edge(Clock) then ... -- Put your code here end if; end process; 2. Synchronize all inputs the the clock before using 3. Simulate 4. Perform static timing analysis Kevin Jennings From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 14 Mar 2009 09:32:02 -0500 Date: Sat, 14 Mar 2009 10:31:29 -0400 From: Chris Abele User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: State machine incrementing References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <8L6dnQnfYbh_IibUnZ2dnUVZ_rrinZ2d@giganews.com> Lines: 42 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ZxEl4OZseqS+z8rX9nqQMcVJzLKTDjsbj5A2kBUOz+IyD8dTP5RtPQk6BWNggkzjGZMvPq3G2woXwui!1kR8eq8iyFhBwmkMKINuVUbA0nAKkHXnHKGXasQkGxHlAOyKGUNlm8UdlT4SimdFgYfFJ3+7Lg== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:658 zooplibob@gmail.com wrote: > I have the following code in my state machine for an I2C controller. > Basically when I get to state data_out4, I want to increment the > variable "datacount" by 1. However I stay in that state for many clock > cycles and it increments many times. How can I code it so that it > increments the variable only once when I'm in that state? Thanks > > elsif state = data_out1 then > sda_sig <= 'Z'; > scl_sig <= '0'; > elsif state = data_out2 then > if data_out(7-datacount) = '0' then > sda_sig <= '0'; > else > sda_sig <= 'Z'; > end if; > scl_sig <= '0'; > elsif state = data_out3 then > if data_out(7-datacount) = '0' then > sda_sig <= '0'; > else > sda_sig <= 'Z'; > end if; > scl_sig <= '1'; > elsif state = data_out4 then > if data_out(7-datacount) = '0' then > sda_sig <= '0'; > else > sda_sig <= 'Z'; > end if; > scl_sig <= '0'; > datacount:=datacount+1; One possibility would be to create another state, so that it is only in the data_out4 state for one cycle and then waits the additional cycles in a new state. Another possibility would be to increment "datacount" at the same point that you set the state to data_out4, assuming that only happens once. (Since you didn't include the code that changes state it's hard to tell.) Chris From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!40g2000yqe.googlegroups.com!not-for-mail From: "Juan A. Gomez-Pulido" Newsgroups: comp.lang.vhdl Subject: JSA - Special Issue on Hardware/Software Co-Design Date: Sun, 15 Mar 2009 15:29:30 -0700 (PDT) Organization: http://groups.google.com Lines: 88 Message-ID: NNTP-Posting-Host: 85.53.247.8 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237156170 23106 127.0.0.1 (15 Mar 2009 22:29:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 15 Mar 2009 22:29:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 40g2000yqe.googlegroups.com; posting-host=85.53.247.8; posting-account=B2VzRwoAAACpyxnJB68ISKVHsSaSttV- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:659 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D First Call for Papers Journal of Systems Architecture - Embedded Software Design (Elsevier) Special Issue on HARDWARE/SOFTWARE CO-DESIGN =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D General Information =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Design of embedded systems is an extended activity for different markets such as aeronautics, telecommunications, consumer electronics, audiovisual, automotive, etc. The strong requirements for many applications in these areas (real-time, power consumption, cost and many others) do necessary the simultaneous use of both hardware and software to design and implement in a successful product. Besides this, the more and more complex systems would need to be designed by engineers with deep knowledge in computer architecture if the software is not taken advantage of as powerful tool that facilitates the work of designing. Traditional methodologies for designing embedded systems distinguish hardware and software separately, avoiding the relationship of both during the first phases of the design cycle. Nowadays, fortunately Hardware/Software co-design involves many technologies and methods, making easier the electronic engineer=92s work. Nevertheless, there are still many challenges, trends and open possibilities in this area that it is necessary to know. According to the above-mentioned, this special issue seeks to explore the last advances in the Hardware/Software co-design. In this special issue, we seek original, high quality articles, clearly focused on theoretical or practical aspects of the Hardware/Software co-design of embedded systems, including but not limited to the topics shown below: * Frameworks for Hardware/Software co-design. * Architectures: - Embedded processors and Systems on Chip (SoC). - DSPs and systems for real-time. - Reconfigurable processors and FPGAs. - Multiprocessors and Multiprocessor System-on-Chip (MPSoC). - Networks on Chip (NoC). * Methodologies and tools for designing: - CAD tools. - Modelling HW/SW systems with hardware description languages. - Compilers, interfaces and protocols. - Operating system support. - Concurrency and parallel programming. * Co-verification and co-simulation. * Performance analysis. * Applications and case studies. Submission Information =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D All manuscripts and any supplementary material should be submitted via the online submission and peer review systems at http://ees.elsevier.com/js= a. Follow the submission instructions given on this site. Please select the article type as "Special Issue: Hardware/Software Co- Design". All manuscripts should comply with the journal's Guide for Authors. Please refer to the following site: http://www.elsevier.com/wps/find/journaldescription.cws_home/505616/authori= nstructions. Important Dates =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Submission Deadline: 30 Sep 2009 Acceptation Notification: 30 Dec 2009 Final Papers: 15 Jan 2010 Publication: Spring of 2010 (subject to JSA editorial calendar) JSA Editor-in-Chief =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Dr. Iain Bate Guest Editor for the JSA Special Issue on Hardware/Software Co-Design =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Dr. Juan A. G=F3mez-Pulido Associate professor Department of Technologies of Computers and Communications University of Extremadura Escuela Politecnica. Campus Universitario s/n 10071 =96 Caceres - Spain e-mail: jangomezpulido@gmail.com web: http://arco.unex.es/jangomez From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!f1g2000prb.googlegroups.com!not-for-mail From: "comp.lang.vhdl" Newsgroups: comp.lang.vhdl Subject: Pseudorandom Noise Generator.... Date: Mon, 16 Mar 2009 04:46:18 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <7e9c301a-5b42-4046-a0e3-c6b27fba4d31@f1g2000prb.googlegroups.com> NNTP-Posting-Host: 59.95.216.92 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237203978 10153 127.0.0.1 (16 Mar 2009 11:46:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 Mar 2009 11:46:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f1g2000prb.googlegroups.com; posting-host=59.95.216.92; posting-account=5G73hQoAAABF6IceBtE0mBmq6UPBHS-S User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.48 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:660 I m generating a PN Sequence in which for sake of simplicity i m taking three flip flops for 3 bit sequence...and the design is such that.....q(1) gets input from q(0)....q(2) gets input from q(1)....and q(0) gets input from the xor output of q(1) and q(2)....now the problem is that...i want to store the output of q(2) upto 7 cycles...so that i can get a 7-bit sequence....which is a PN Sequence....please help me...i need a VHDL code for this..... From newsfish@newsfish Wed Aug 19 13:23:46 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!publishnet.news-service.com!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Pseudorandom Noise Generator.... References: <7e9c301a-5b42-4046-a0e3-c6b27fba4d31@f1g2000prb.googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: X-Complaints-To: abuse@news-service.com Organization: Publishnet Date: Mon, 16 Mar 2009 13:52:54 +0100 Lines: 19 NNTP-Posting-Host: 84.246.49.113 (84.246.49.113) NNTP-Posting-Date: Mon, 16 Mar 2009 13:52:54 +0100 X-Trace: a070349be4ba6f15394d401349 Xref: news.eternal-september.org comp.lang.vhdl:661 In comp.lang.vhdl, comp.lang.vhdl wrote: > I m generating a PN Sequence in which for sake of simplicity i m > taking three flip flops for 3 bit sequence...and the design is such > that.....q(1) gets input from q(0)....q(2) gets input from q(1)....and > q(0) gets input from the xor output of q(1) and q(2)....now the > problem is that...i want to store the output of q(2) upto 7 > cycles...so that i can get a 7-bit sequence....which is a PN > Sequence....please help me...i need a VHDL code for this..... So you need VHDL code for a 7-bit shift register? Shouldn't be hard to find with a search engine. And there seems to be something wrong with your keyboard: It generates some extra punctuation at (pseudo?) random intervals. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) The Moral Majority is neither. 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Date: Mon, 16 Mar 2009 14:03:17 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: NNTP-Posting-Host: 192.94.94.105 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237237397 20667 127.0.0.1 (16 Mar 2009 21:03:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 Mar 2009 21:03:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 41g2000yqf.googlegroups.com; posting-host=192.94.94.105; posting-account=aR43BgoAAAAO0iCoN0Rw4J3_eN_le6kp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686 (x86_64); en-US; rv:1.8.1.12) Gecko/20080201 Firefox/2.0.0.12,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxysb01 (NetCache NetApp/6.0.5) Xref: news.eternal-september.org comp.lang.vhdl:663 Hey, I am new with using variables in VHDL and am wondering how it gets synthesized in the following case: If you understand it can you also please explain why it gets synthesized the way you think it does? process(a) variable x: integer; variable y:integer; variable z:integer; begin x:= 1; if (a=1) then x:=2; end if for i in 0 to 4 loop y := i+x; if(y>d) then y := y - d; end if end if if(b = 2) then z:= y; end if end process From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.linkpendium.com!news.linkpendium.com!feeder.erje.net!news-1.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 14:15:33 -0700 Lines: 12 Message-ID: <49BEC175.4070408@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net OM3rd82VXL4EEiWbki2UVwVuvYTxftwXYASH2v1GGlzvBItGxQ Cancel-Lock: sha1:lAJ2rYxMntpl9595tG0ZJmSi8TM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:664 Duke wrote: > Hey, > > I am new with using variables in VHDL and am wondering how it gets > synthesized in the following case: It doesn't. Synthesis is port to port. Add an entity. And maybe a synchronous process for useful synthesis. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 16 Mar 2009 16:24:34 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 21:22:51 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 78 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-4F2nVb6BNq1N+whpKR7EjbtUtz0D1JoEc7C5Jk0gkt+LuMqMe5paphZygN4ZK0uehdPRvZJB16daEME!hom8qYT/dsmS+7GysPYelEz7e7Lmm4KW8ErAx0LQKyoNRgHFTJPcTL1VtDokadUrTDrhVztnHv63!9Cb7 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:665 On Mon, 16 Mar 2009 14:03:17 -0700 (PDT), Duke wrote: >I am new with using variables in VHDL and am wondering how it gets >synthesized in the following case: If your synthesis tool is any good, it will get synthesised to nothing at all. See below. >If you understand it can you also please explain why it gets >synthesized the way you think it does? > >process(a) >variable x: integer; >variable y:integer; >variable z:integer; > begin > x:= 1; > if (a=1) then > x:=2; > end if > > for i in 0 to 4 loop > y := i+x; > if(y>d) then > y := y - d; > end if > end if > > if(b = 2) then > z:= y; > end if >end process A few sanity checks are in order first. (1) We can see that (a) is a signal, because the process is sensitised to it. By contrast, we know nothing about (b) and (d). If they are signals rather than constants, then it would probably be a cool idea to put them in the sensitivity list too. In fact, it's Bloody Stupid (tm) to do otherwise. (2) Variable z is written but never read. It is trivially obvious that z can be eliminated completely and the final "if (b=2)..." can be deleted. (3) Processes communicate with one another, and with the outside world, by means of signals. This process writes to no signals at all. Consequently it is a navel-contemplator; it has absolutely no effect on its environment, and therefore can be safely deleted. If this is homework, you might like to recommend to your prof that he come on one of our courses. If it's just you experimentally asking what would happen if you synthesise some code, I strongly recommend that you simply TRY IT - the free versions of Quartus and XST will do a fine job for you, and have perfectly serviceable RTL viewers that will show you what they build. Variables have been discussed at length here and elsewhere; a little bit of Google-effort will lead you to many threads that may be of interest. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 14:57:44 -0700 Lines: 10 Message-ID: <49BECB58.7060800@gmail.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net bWgqwZBvjFDug/CmfWIzjQPFpKHWSuCPwDJyqplyuH0xfsFl4H Cancel-Lock: sha1:ttmmB5sOAV7ccCPlX4ycTM6RFIk= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> Xref: news.eternal-september.org comp.lang.vhdl:666 Jonathan Bromley wrote: > Variables have been discussed at length here and > elsewhere; a little bit of Google-effort will > lead you to many threads that may be of interest. I think this was the last related thread: http://groups.google.com/groups/search?q=vhdl+%22variables+execute+like+software%22 -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 16 Mar 2009 17:24:41 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Pseudorandom Noise Generator.... Date: Mon, 16 Mar 2009 22:22:59 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <7e9c301a-5b42-4046-a0e3-c6b27fba4d31@f1g2000prb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-K0BZQt6nJIJ5cCMt9SyYq2pMQQ3QOqR/61YthM9IH5Ixvhb/PW3VFj9ZYCTiL4Ps0cqlCvHN9mu3yeT!ppY9EhLquVQpZzE9IGgBoq10XAguOlV5FdNoguTwZPqDe5OtIoRcsHmECQbx7LdMz1/ODoGW1kyZ!OJX/ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:667 On Mon, 16 Mar 2009 13:52:54 +0100, Stef wrote: >In comp.lang.vhdl, >comp.lang.vhdl wrote: >> I m generating a PN Sequence in which for sake of simplicity i m >> taking three flip flops for 3 bit sequence...and the design is such >> that.....q(1) gets input from q(0)....q(2) gets input from q(1)....and >> q(0) gets input from the xor output of q(1) and q(2)....now the >> problem is that...i want to store the output of q(2) upto 7 >> cycles...so that i can get a 7-bit sequence....which is a PN >> Sequence....please help me...i need a VHDL code for this..... > >So you need VHDL code for a 7-bit shift register? Only 4, I think. He has three of the bits already in his PRBS :-) So that makes the problem 43% easier. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.germany.com!postnews.google.com!h20g2000yqn.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 15:50:35 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> NNTP-Posting-Host: 217.171.129.70 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237243835 14823 127.0.0.1 (16 Mar 2009 22:50:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 Mar 2009 22:50:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h20g2000yqn.googlegroups.com; posting-host=217.171.129.70; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:668 Hi > (1) We can see that (a) is a signal, because the > process is sensitised to it. =A0By contrast, we > know nothing about (b) and (d). =A0If they are > signals rather than constants, then it would > probably be a cool idea to put them in the > sensitivity list too. =A0In fact, it's Bloody > Stupid (tm) to do otherwise. It implies simulation will be differnt from produced logic, but not necessarily create a different functioning. All reasonable sythesis tools produce logic as though they had been included in the sensitivity list, it's just easier. It main effect is to produce wrong transition counts for simulation, and possibly make power estimation density wrong. It does offer the possible implicit optimizations of not performing function stste changes if a signal changes which is not on the sensitivity list, as per simulation. Most synthesis tools ignore this possibility of power optimization. The code given will optimize to nothing with most tools. cheers jacko p.s. I can hear the screams at BloodyStupid(tm) head office. The typing , oooh the long names, the list growing, oooh no, not the list arrrrgh!! From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 16 Mar 2009 18:20:52 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 23:19:09 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 65 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-KrUdnXHmHFfwlTyCTeLYXWVn+4azuvS16ep409rWoK4NlTmKkX2ZlCfsIamhM99xxCULHXdfC84zrEg!FDWud07gtei5/2K/U93gMnf4P0z0e08nPVwTq6KGZV4I8EPPAz3Zf4rTe1BAI7FQzDdl2VqwxE0q!vtxS X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:669 On Mon, 16 Mar 2009 15:50:35 -0700 (PDT), Jacko wrote: [incomplete sensitivity list] >implies simulation will be differnt from produced logic, Indeed. That fits my understanding of Bloody Stupid pretty well. > but not necessarily create a different functioning. Could you kindly translate that for me? I have no idea what you mean. Either synthesis and simulation match, or they don't. You seem to be saying that there is some third alternative. >All reasonable sythesis >tools produce logic as though they had been included in the >sensitivity list, All tools I know do so, and produce a warning message precisely because it is not "reasonable". > it's just easier. Easy and wrong doesn't work for me. >It main effect is to produce wrong transition counts for simulation, >and possibly make power estimation density wrong. It does offer the >possible implicit optimizations of not performing function stste >changes if a signal changes which is not on the sensitivity list, as >per simulation. I can imagine asynchronous design techniques (latches) in which asynch processes could be given incomplete sensitivity lists to imply lack of state change on some signal transitions. In a sense that's precisely what the standard clocked process template does (in VHDL it is functionally unaffected if you include all inputs in the senstivity list). But given the present state of the synthesis art, I'm not keen to try that kind of asynchronous trick. >p.s. I can hear the screams at BloodyStupid(tm) head office. The >typing , oooh the long names, the list growing, oooh no, not the list >arrrrgh!! Which is why we all want wildcard sensitivity lists for the (few) occasions when we need combinational processes. Respect to SystemVerilog for getting it right with always_comb. Boo-hiss to VHDL for holding out for so many years against the obviously sensible process(all) so that now it's probably too late and no-one will take any notice of it. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 16 Mar 2009 19:10:08 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: cheap and hot wholesale jordan 1-23,Ato shoes,timberland,supra Welcome to our websit Date: Mon, 16 Mar 2009 17:06:51 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 117.26.207.237 Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-OzQ5xYqQMRB2Axzmz5Tjb4oTON++TMSPc3Fm86it11aBUnbJNHEPAxdG9dxdMloxLjegPogogDhWNd9!XtMssUNOC1KcpX+hIgCbE78WkGd/IyiHUDOmeHK0j+OHyC+NCpm8dAPCeds= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 7 Xref: news.eternal-september.org comp.lang.vhdl:670 Welcome to our website: http://www.nikeconfluence.com. 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Date: Mon, 16 Mar 2009 19:53:38 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: References: NNTP-Posting-Host: 74.12.53.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237258418 29288 127.0.0.1 (17 Mar 2009 02:53:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 Mar 2009 02:53:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v39g2000yqm.googlegroups.com; posting-host=74.12.53.216; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.6) Gecko/2009020409 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:671 On Mar 16, 5:03=A0pm, Duke wrote: > Hey, > > I am new with using variables in VHDL and am wondering how it gets > synthesized in the following case: > If you understand it can you also please explain why it gets > synthesized the way you think it does? > > process(a) > variable x: integer; > variable y:integer; > variable z:integer; > =A0 =A0 begin > =A0 =A0 =A0 x:=3D 1; > =A0 =A0 =A0 if (a=3D1) then > =A0 =A0 =A0 =A0 =A0x:=3D2; > =A0 =A0 =A0 end if > > =A0 =A0 =A0 for i in 0 to 4 loop > =A0 =A0 =A0 =A0 =A0 y :=3D i+x; > =A0 =A0 =A0 =A0 =A0 if(y>d) then > =A0 =A0 =A0 =A0 =A0 =A0 y :=3D y - d; > =A0 =A0 =A0 =A0 =A0end if > =A0 =A0 =A0end if > > =A0 =A0 =A0if(b =3D 2) then > =A0 =A0 =A0 z:=3D y; > =A0 =A0 end if > end process Duke, As has been mentioned, this code will get optimized away. But what you *might* have been asking (and I'm taking a shot in the dark here) is, were you to have forced the simulator to explicitly keep the process around, and trace what it did, what would you have seen? In that case, the values you would see would be more or less consistent with what you'd expect if x,y,z were plain ordinary variables in your favorite imperative programming language (C or perl or whatnot) - the fact that none of the values of any of the variables get re-used in successive executions of the process means there's nothing "interesting" going on from a synthesis point of view. By interesting, I mean inferring latches or flip-flops. And from a slightly more contrarian position: were "a","b" or "d" to have been declared as impure 0-ary functions performing I/O (textio, asserts, reports, etc), then one could argue that, from a *simulation* point of view, that the process is not, in the strictest sense, navel- gazing. But for synthesis, I concur with the majority opinion - your code will simply vanish. - Kenn From newsfish@newsfish Wed Aug 19 13:23:47 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!40g2000yqe.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 16 Mar 2009 21:12:11 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: References: NNTP-Posting-Host: 74.12.53.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237263131 5438 127.0.0.1 (17 Mar 2009 04:12:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 Mar 2009 04:12:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 40g2000yqe.googlegroups.com; posting-host=74.12.53.216; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.6) Gecko/2009020409 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:672 On Mar 16, 10:53=A0pm, kennheinr...@sympatico.ca wrote: > On Mar 16, 5:03=A0pm, Duke wrote: > > > > > Hey, > > > I am new with using variables in VHDL and am wondering how it gets > > synthesized in the following case: > > If you understand it can you also please explain why it gets > > synthesized the way you think it does? > > > process(a) > > variable x: integer; > > variable y:integer; > > variable z:integer; > > =A0 =A0 begin > > =A0 =A0 =A0 x:=3D 1; > > =A0 =A0 =A0 if (a=3D1) then > > =A0 =A0 =A0 =A0 =A0x:=3D2; > > =A0 =A0 =A0 end if > > > =A0 =A0 =A0 for i in 0 to 4 loop > > =A0 =A0 =A0 =A0 =A0 y :=3D i+x; > > =A0 =A0 =A0 =A0 =A0 if(y>d) then > > =A0 =A0 =A0 =A0 =A0 =A0 y :=3D y - d; > > =A0 =A0 =A0 =A0 =A0end if > > =A0 =A0 =A0end if > > > =A0 =A0 =A0if(b =3D 2) then > > =A0 =A0 =A0 z:=3D y; > > =A0 =A0 end if > > end process > > Duke, > > As has been mentioned, this code will get optimized away. =A0But what > you *might* have been asking (and I'm taking a shot in the dark here) > is, were you to have forced the simulator to explicitly keep the > process around, and trace what it did, what would you have seen? In > that case, the values you would see would be more or less consistent > with what you'd expect if x,y,z were plain ordinary variables in your > favorite imperative programming language (C or perl or whatnot) - the > fact that none of the values of any of the variables get re-used in > successive executions of the process means there's nothing > "interesting" going on from a synthesis point of view. By interesting, > I mean inferring latches or flip-flops. > > And from a slightly more contrarian position: were "a","b" or "d" to erratum: for "a","b", or "d" : read "b" or "d" > have been declared as impure 0-ary functions performing I/O (textio, > asserts, reports, etc), then one could argue that, from a *simulation* > point of view, that the process is not, in the strictest sense, navel- > gazing. But for synthesis, I concur with the majority opinion - your > code will simply vanish. > > =A0- Kenn From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j35g2000yqh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Tue, 17 Mar 2009 06:45:56 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: <99fcef4c-2117-4563-aa86-82042d6c999f@j35g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237297556 25628 127.0.0.1 (17 Mar 2009 13:45:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 Mar 2009 13:45:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j35g2000yqh.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:673 On Mar 16, 11:12=A0pm, kennheinr...@sympatico.ca wrote: > > Duke, > > > As has been mentioned, this code will get optimized away. =A0But what > > you *might* have been asking (and I'm taking a shot in the dark here) > > is, were you to have forced the simulator to explicitly keep the > > process around, and trace what it did, what would you have seen? In > > that case, the values you would see would be more or less consistent > > with what you'd expect if x,y,z were plain ordinary variables in your > > favorite imperative programming language (C or perl or whatnot) - the > > fact that none of the values of any of the variables get re-used in > > successive executions of the process means there's nothing > > "interesting" going on from a synthesis point of view. By interesting, > > I mean inferring latches or flip-flops. > > > And from a slightly more contrarian position: were "a","b" or "d" to > > erratum: for "a","b", or "d" : read "b" or "d" > > > > > have been declared as impure 0-ary functions performing I/O (textio, > > asserts, reports, etc), then one could argue that, from a *simulation* > > point of view, that the process is not, in the strictest sense, navel- > > gazing. But for synthesis, I concur with the majority opinion - your > > code will simply vanish. > > > =A0- Kenn- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Ignoring the impacts of optimization (deleting unused outputs, and everything that only drives them), there are some problems with the code. Specifically, z is not always assigned a value, which would result in a latch were z not to be optimized out in the first place, whether z were a variable or signal. Latches are an inherent risk in combinatorial processes. The same situation in a clocked process merely results in a clock disable on a register, and/or (with variables) a mux between the input and output of the register, where z might be referenced subsequently. Interestingly, the output of the implied clock-disabling feedback mux, before the register input, is exactly what is needed for successive references to the conditionally assigned variable. Because y is overwritten in each loop iteration, the whole loop collapses to just the last iteration of the loop, ignoring the previous iterations. This has nothing to do with signals vs variables. The typical impact on truly iterative loops of variables vs signals is that since signals do not get updated until the process suspends, there is no real iteration upon signals inside a loop (assuming there are no wait statements in the loop). Since variables do update immediately, iteration upon the variable is possible, it is just not demonstrated in the example. Just remember that all loops not containing wait statements are simply unrolled during synthesis. Not all synthesis tools can handle loops with wait statements (i.e. waiting on the next clock edge), but that is probably beyond the intended scope of discussion. Because sensitivity lists are ignored in synthesis, the synthesis of x is unrelated to variable vs signal behavior. Were x a signal, the synthesis result would assume x were also in the sensitivity list, and the resulting behavior would be identical to that of a variable x. In simulation, if x were a signal, and included in the process sensitivity list, it would cause the process to immediately run again with the updated value of x, thus allowing propagation to the subsequent references to x within the process. So, in effect, most of the behavior of the code, even ignoring the effects of optimization during synthesis, really does not have much to do with variable vs signal behavior. Andy From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j39g2000yqn.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Tue, 17 Mar 2009 07:18:51 -0700 (PDT) Organization: http://groups.google.com Lines: 90 Message-ID: <3bdd85e0-8c32-4a84-94c4-ba7d39a729e3@j39g2000yqn.googlegroups.com> References: <99fcef4c-2117-4563-aa86-82042d6c999f@j35g2000yqh.googlegroups.com> NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237299531 32081 127.0.0.1 (17 Mar 2009 14:18:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 Mar 2009 14:18:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j39g2000yqn.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: news.eternal-september.org comp.lang.vhdl:674 On Mar 17, 9:45=A0am, Andy wrote: > On Mar 16, 11:12=A0pm, kennheinr...@sympatico.ca wrote: > > > > > > Duke, > > > > As has been mentioned, this code will get optimized away. =A0But what > > > you *might* have been asking (and I'm taking a shot in the dark here) > > > is, were you to have forced the simulator to explicitly keep the > > > process around, and trace what it did, what would you have seen? In > > > that case, the values you would see would be more or less consistent > > > with what you'd expect if x,y,z were plain ordinary variables in your > > > favorite imperative programming language (C or perl or whatnot) - the > > > fact that none of the values of any of the variables get re-used in > > > successive executions of the process means there's nothing > > > "interesting" going on from a synthesis point of view. By interesting= , > > > I mean inferring latches or flip-flops. > > > > And from a slightly more contrarian position: were "a","b" or "d" to > > > erratum: for "a","b", or "d" : read "b" or "d" > > > > have been declared as impure 0-ary functions performing I/O (textio, > > > asserts, reports, etc), then one could argue that, from a *simulation= * > > > point of view, that the process is not, in the strictest sense, navel= - > > > gazing. But for synthesis, I concur with the majority opinion - your > > > code will simply vanish. > > > > =A0- Kenn- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > > - Show quoted text - > > Ignoring the impacts of optimization (deleting unused outputs, and > everything that only drives them), there are some problems with the > code. > > Specifically, z is not always assigned a value, which would result in > a latch were z not to be optimized out in the first place, whether z > were a variable or signal. Latches are an inherent risk in > combinatorial processes. The same situation in a clocked process > merely results in a clock disable on a register, and/or (with > variables) a mux between the input and output of the register, where z > might be referenced subsequently. Interestingly, the output of the > implied clock-disabling feedback mux, before the register input, is > exactly what is needed for successive references to the conditionally > assigned variable. > Of course, you're right. I missed seeing the loop in the def-use graph for "z". I like the description of how two paths through the dependency graph (one uninitialized, hence carried over from the last execution, and one initialized, hence from current execution) has a synthesis interpretation as a simple clock enable when used in a clocked process. > Because y is overwritten in each loop iteration, the whole loop > collapses to just the last iteration of the loop, ignoring the > previous iterations. This has nothing to do with signals vs variables. > The typical impact on truly iterative loops of variables vs signals is > that since signals do not get updated until the process suspends, > there is no real iteration upon signals inside a loop (assuming there > are no wait statements in the loop). Since variables do update > immediately, iteration upon the variable is possible, it is just not > demonstrated in the example. Just remember that all loops not > containing wait statements are simply unrolled during synthesis. Not > all synthesis tools can handle loops with wait statements (i.e. > waiting on the next clock edge), but that is probably beyond the > intended scope of discussion. > > Because sensitivity lists are ignored in synthesis, the synthesis of x > is unrelated to variable vs signal behavior. Were x a signal, the > synthesis result would assume x were also in the sensitivity list, and > the resulting behavior would be identical to that of a variable x. In > simulation, if x were a signal, and included in the process > sensitivity list, it would cause the process to immediately run again > with the updated value of x, thus allowing propagation to the > subsequent references to x within the process. > > So, in effect, most of the behavior of the code, even ignoring the > effects of optimization during synthesis, really does not have much to > do with variable vs signal behavior. > > Andy From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!r3g2000vbp.googlegroups.com!not-for-mail From: Jaco Naude Newsgroups: comp.lang.vhdl Subject: Is this state machine written correctly? Date: Wed, 18 Mar 2009 04:36:32 -0700 (PDT) Organization: http://groups.google.com Lines: 323 Message-ID: <33c11865-718a-4bbd-b349-ff0a0baeab52@r3g2000vbp.googlegroups.com> NNTP-Posting-Host: 146.64.81.22 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237376192 10015 127.0.0.1 (18 Mar 2009 11:36:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 11:36:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r3g2000vbp.googlegroups.com; posting-host=146.64.81.22; posting-account=zQcqRgoAAACFp7R5zvQcoCr_PPDlo1qs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 arrakis.csir.co.za:3128 (squid/2.5.STABLE12) Xref: news.eternal-september.org comp.lang.vhdl:675 Hi there I've been struggling with a design containing 3 state machines (Moore) working together to form a dynamic memory map. In behavioral simulation the simulation works perfectly but in structural simulation the design does not work. We've also rewrote the design from scratch and used the ISE Moore state machine templates as the basis of the 3 state machines. Our synthesis report does not give anything suspicious as far as I can see. We've checked in both XST and Synplify and both of them give a netlist which behaves different from the behavioral model (the XST netlist also behaves different compared to the Synplify netlist). I've attached the XST synthesis report which might be usefull, and I will give the code for one of our state machines below to see if anyone can find something fundamentally wrong in the way its been done. Any help would be greatly appreciated. Thanks Jaco State machine - In structural simulation the state machine gets stuck in the following state: st_init_response ============================================================================= ENTITY DMM_SPLITTER IS GENERIC( G_DATA_WIDTH : natural := 32; G_ADDR_WIDTH : natural := 24 ); PORT( S_DATA : IN transmit_bus; --! Data received from a splitter or interface feeding this splitter. S_RESPONSE : OUT response_bus; --! Data sent to a splitter or interface feeding this splitter. M0_DATA : OUT transmit_bus; --! Data sent from a leaf node which is fed by this splitter. M0_RESPONSE : IN response_bus; --! Data received from a leaf node which is fed by this splitter. M1_DATA : OUT transmit_bus; --! Data sent from a leaf node which is fed by this splitter. M1_RESPONSE : IN response_bus; --! Data received from a leaf node which is fed by this splitter. CLK : IN std_logic; --! Clock input. RESET_N : IN std_logic --! Active-low reset input. ); -- Declarations END DMM_SPLITTER ; -- hds interface_end -- hds interface_end --! @brief Architure definition DDM_SPLITTER --! @details This architecture definition should work on any device from any vendor. architecture RTL of DMM_SPLITTER is type state_type is (st_startup, st_init, st_init_m0, st_init_m1, st_init_response, st_ready, st_request_m0, st_request_m1, st_request_idle, st_response_m0, st_response_m1, st_error); signal state, next_state : state_type; signal new_state_valid_i : std_logic := '0'; signal m0_size : integer := 0; signal m1_size : integer := 0; signal s_data_i : transmit_bus := ((others => '0'), (others => '0'), '0', '0'); signal s_response_i : response_bus := ((others => '0'), '0'); signal m0_data_i : transmit_bus := ((others => '0'), (others => '0'), '0', '0'); signal m0_response_i : response_bus := ((others => '0'), '0'); signal m1_data_i : transmit_bus := ((others => '0'), (others => '0'), '0', '0'); signal m1_response_i : response_bus := ((others => '0'), '0'); signal tmp_addr : integer := 0; begin SYNC_PROC: process (CLK) begin if (CLK'event and CLK = '1') then if (RESET_N = '0') then state <= st_startup; S_RESPONSE.DATA <= (others => '0'); S_RESPONSE.DVAL <= '0'; M0_DATA.DATA <= (others => '0'); M0_DATA.ADDR <= (others => '0'); M0_DATA.DVAL <= '0'; M0_DATA.RNW <= '0'; M1_DATA.DATA <= (others => '0'); M1_DATA.ADDR <= (others => '0'); M1_DATA.DVAL <= '0'; M1_DATA.RNW <= '0'; else -- This will generate a valid pulse for new states. if next_state = state then new_state_valid_i <= '0'; else new_state_valid_i <= '1'; end if; -- Sets the current state equal to the next_state. state <= next_state; -- Assign other outputs to internal signals. S_RESPONSE <= s_response_i; M0_DATA <= m0_data_i; M1_DATA <= m1_data_i; end if; end if; end process; OUTPUT_DECODE: process (state) begin -- Insert statements to decode internal output signals if state = st_init_m0 then m0_data_i.DATA <= (others => '1'); m0_data_i.ADDR <= (others => '1'); m0_data_i.DVAL <= new_state_valid_i; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_init_m1 then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '1'); m1_data_i.ADDR <= (others => '1'); m1_data_i.DVAL <= new_state_valid_i; m1_data_i.RNW <= '0'; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_init_response then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= std_logic_vector(conv_unsigned (m0_size + m1_size, G_DATA_WIDTH)); s_response_i.DVAL <= new_state_valid_i; elsif state = st_ready then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_request_idle then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_request_m0 then m0_data_i.DATA <= s_data_i.DATA; m0_data_i.ADDR <= s_data_i.ADDR; m0_data_i.DVAL <= new_state_valid_i; m0_data_i.RNW <= s_data_i.RNW; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_request_m1 then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= s_data_i.DATA; -- Subtract m0_size from address to compensate for size of first leaf node. m1_data_i.ADDR <= std_logic_vector(conv_unsigned (tmp_addr,G_ADDR_WIDTH)); m1_data_i.DVAL <= new_state_valid_i; m1_data_i.RNW <= s_data_i.RNW; s_response_i.DATA <= (others => '0'); s_response_i.DVAL <= '0'; elsif state = st_response_m0 then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= m0_response_i.DATA ; s_response_i.DVAL <= m0_response_i.DVAL; elsif state = st_response_m1 then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; s_response_i.DATA <= m1_response_i.DATA ; s_response_i.DVAL <= m1_response_i.DVAL; elsif state = st_error then m0_data_i.DATA <= (others => '0'); m0_data_i.ADDR <= (others => '0'); m0_data_i.DVAL <= '0'; m0_data_i.RNW <= '0'; m1_data_i.DATA <= (others => '0'); m1_data_i.ADDR <= (others => '0'); m1_data_i.DVAL <= '0'; m1_data_i.RNW <= '0'; s_response_i.DATA <= error_code; s_response_i.DVAL <= new_state_valid_i; end if; end process; NEXT_STATE_DECODE: process (state, new_state_valid_i, RESET_N, S_DATA.DVAL, M0_RESPONSE.DVAL, M1_RESPONSE.DVAL) begin -- Declare default state for next_state to avoid latches next_state <= state; -- Default is to stay in current state case (state) is when st_startup => if RESET_N = '1' then next_state <= st_init; else next_state <= st_startup; end if; when st_init => if S_DATA.DVAL = '1' then next_state <= st_init_m0; end if; when st_init_m0 => if M0_RESPONSE.DVAL = '1' then m0_size <= conv_integer(unsigned(M0_RESPONSE.DATA(15 downto 0))); m0_response_i.DATA <= M0_RESPONSE.DATA; m0_response_i.DVAL <= M0_RESPONSE.DVAL; next_state <= st_init_m1; end if; when st_init_m1 => if M1_RESPONSE.DVAL = '1' then m1_size <= conv_integer(unsigned(M1_RESPONSE.DATA(15 downto 0))); m1_response_i.DATA <= M1_RESPONSE.DATA; m1_response_i.DVAL <= M1_RESPONSE.DVAL; next_state <= st_init_response; end if; when st_init_response => next_state <= st_ready; when st_ready => if (S_DATA.DVAL = '1' and (unsigned(S_DATA.ADDR) < conv_unsigned(m0_size,G_ADDR_WIDTH))) then s_data_i <= S_DATA; next_state <= st_request_m0; elsif (S_DATA.DVAL = '1' and (unsigned(S_DATA.ADDR) >= conv_unsigned(m0_size,G_ADDR_WIDTH)) and (unsigned(S_DATA.ADDR) < conv_unsigned(m1_size+m0_size,G_ADDR_WIDTH))) then s_data_i <= S_DATA; tmp_addr <= conv_integer(unsigned(S_DATA.ADDR)) - m0_size; next_state <= st_request_m1; elsif (S_DATA.DVAL = '1' and (unsigned(S_DATA.ADDR) >= conv_unsigned(m1_size+m0_size,G_ADDR_WIDTH))) then -- The received address is too big for this splitter. Something went wrong upstream in the DMM. Go into error state. next_state <= st_error; else next_state <= st_ready; end if; when st_request_m0 => next_state <= st_request_idle; when st_request_m1 => next_state <= st_request_idle; when st_request_idle => if M0_RESPONSE.DVAL = '1' then next_state <= st_response_m0; m0_response_i.DATA <= M0_RESPONSE.DATA; m0_response_i.DVAL <= M0_RESPONSE.DVAL; elsif M1_RESPONSE.DVAL = '1' then next_state <= st_response_m1; m1_response_i.DATA <= M1_RESPONSE.DATA; m1_response_i.DVAL <= M1_RESPONSE.DVAL; else next_state <= st_request_idle; end if; when st_response_m0 => next_state <= st_ready; when st_response_m1 => next_state <= st_ready; when st_error => next_state <= st_ready; when others => next_state <= st_ready; end case; end process; end RTL; From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y13g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Is this state machine written correctly? Date: Wed, 18 Mar 2009 05:48:39 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <4160a6ab-d1ed-4462-962c-6ac58351a103@y13g2000yqn.googlegroups.com> References: <33c11865-718a-4bbd-b349-ff0a0baeab52@r3g2000vbp.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237380519 2179 127.0.0.1 (18 Mar 2009 12:48:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 12:48:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y13g2000yqn.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:676 On Mar 18, 7:36=A0am, Jaco Naude wrote: > Hi there > > I've been struggling with a design containing 3 state machines (Moore) > working together to form a dynamic memory map. In behavioral > simulation the simulation works perfectly but in structural simulation > the design does not work. Peruse your synthesis report for some form of message that talks about an incomplete sensitivity list. Quick perusal shows that the "OUTPUT_DECODE" process is missing several signals, "NEXT_STATE_DECODE" is missing at least one and maybe a few more (not sure if 'S_DATA.ADDR' is a signal or constant since it's not defined in your posted code). Consider not using unclocked processes for exactly this reason, it leads to difference between simulation and synthesis. Far better to have all synchronous processes like your "SYNC_PROC" coupled with concurrent statements for things that must be unclocked. If you really prefer the form of "if...then" and "case" statements that you get to use inside a process but are not available as concurrent statements, then consider using functions or procedures instead. Functions and procedures will allow you to use 'if..then', 'case', etc. statements but you won't be able to have the equivalent of an incomplete sensitivity list since this would imply use of some signal that is not defined as an interface to the function/procedure which the compiler will immediately flag as an error. That way you won't get stuck perusing synthesis reports for incomplete sensitivity lists to catch this design error. Also, check your testbench to see if the stimulus is being generated at an acceptable time relative to the clock. In order to use the post route simulation model you must make sure that the inputs to the device meet the setup and hold time requirements that the timing report says is acceptable. If not, then you will get differences between pre- and post-route simulation models. Consider using "if rising_edge(CLK)..." rather than "if (CLK'event and CLK =3D '1')...", it's more descriptive. Has nothing to do with your current problem though. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!c11g2000yqj.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Wed, 18 Mar 2009 07:16:23 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> NNTP-Posting-Host: 217.171.129.70 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237385783 19547 127.0.0.1 (18 Mar 2009 14:16:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 14:16:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c11g2000yqj.googlegroups.com; posting-host=217.171.129.70; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:677 On 16 Mar, 23:19, Jonathan Bromley wrote: > On Mon, 16 Mar 2009 15:50:35 -0700 (PDT), Jacko wrote: > > [incomplete sensitivity list] > > >implies simulation will be differnt from produced logic, > > Indeed. =A0That fits my understanding of Bloody Stupid > pretty well. Just because simulation is lazy by not actually simulating the netlist, you assume much. > > but not necessarily create a different functioning. > > Could you kindly translate that for me? =A0I have no > idea what you mean. =A0Either synthesis and simulation > match, or they don't. =A0You seem to be saying that > there is some third alternative. Yes simulation tool support alternative of simulating netlist, so not forgetting to alter some logic levels, or synthesis creates latches which prevent unnecessay transistions, saving power, and the simulator agrees with lazy evaluation. You will find a critical subset of sensitivity which will always cause evaluation correctly, i.e. if a signal is used later in a process, and assigned earlier in a process, then it need not be in the list. For correct logic simulation, only true dependant signals need to cause logic re-evaluation, i.e. the process is performed correctly to the sensitivities supplied. > >All reasonable sythesis > >tools produce logic as though they had been included in the > >sensitivity list, > > All tools I know do so, and produce a warning message > precisely because it is not "reasonable". No, because it may not be what is expected. It may be reasonable. > > it's just easier. > > Easy and wrong doesn't work for me. Easier to list them all.... > >It main effect is to produce wrong transition counts for simulation, > >and possibly make power estimation density wrong. It does offer the > >possible implicit optimizations of not performing function stste > >changes if a signal changes which is not on the sensitivity list, as > >per simulation. > > I can imagine asynchronous design techniques (latches) in which > asynch processes could be given incomplete sensitivity lists > to imply lack of state change on some signal transitions. > In a sense that's precisely what the standard clocked > process template does (in VHDL it is functionally unaffected > if you include all inputs in the senstivity list). =A0But > given the present state of the synthesis art, I'm not > keen to try that kind of asynchronous trick. And the tool will refuse to do it, warn, and then give you the output as though all were in the list. > >p.s. I can hear the screams at BloodyStupid(tm) head office. The > >typing , oooh the long names, the list growing, oooh no, not the list > >arrrrgh!! > > Which is why we all want wildcard sensitivity lists for the > (few) occasions when we need combinational processes. > Respect to SystemVerilog for getting it right with > always_comb. =A0Boo-hiss to VHDL for holding out for > so many years against the obviously sensible > =A0 =A0process(all) > so that now it's probably too late and no-one will > take any notice of it. tis sensible. it beats always() with the extra reserved word needed. From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Wed, 18 Mar 2009 15:05:54 +0000 Organization: TRW Conekt Lines: 63 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net 7NaBJ1s0hgOZW3kG6wSpvwF9Nv9s7fQu03VXuL7HgRNXBGTa8= Cancel-Lock: sha1:Qdf254XUS7M4E1drXRft72+6AYg= sha1:E2WD22kmpN+Y1Lhu/53iufpwFys= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:678 Jacko writes: > On 16 Mar, 23:19, Jonathan Bromley > wrote: >> On Mon, 16 Mar 2009 15:50:35 -0700 (PDT), Jacko wrote: >> >> [incomplete sensitivity list] >> >> >implies simulation will be differnt from produced logic, >> >> Indeed.  That fits my understanding of Bloody Stupid >> pretty well. > > Just because simulation is lazy by not actually simulating the > netlist, you assume much. Isn't that backwards? VHDL is a simulation language. You simulate your code until it works. Then you run a synthesiser over the same code and it produces you a netlist which (in theory) matches your code that you so carefully wrote and verified. (Clearly the word "you" in the above should be replaced by "other engineers", or indeed "I" :) If the synth doesn't translate that code into a functionally equivalent netlist, how is that the simulator's fault? Of course we just have to work with the fact that synth tools do what they do, which leads me to avoid non-clocked processes wherever possible, but I don't have to like it, or try and make out it's the way things "should" work. There are always going to be things that simulate that the synth can't turn into a netlist, but is it valid for it just to go "well, here's something a bit like it" flag a quick warning (in amongst a morass of other warnings) and call "job done". And the example under discussion isn't even one where the synth-tool *can't* do the job conforming to the language spec, it just chooses not to! It's like a C-compiler changing 'i++' to '++i' "because that's usually what people want to happen when they write that". (snip) > >> >All reasonable sythesis >> >tools produce logic as though they had been included in the >> >sensitivity list, >> >> All tools I know do so, and produce a warning message >> precisely because it is not "reasonable". > > No, because it may not be what is expected. It may be reasonable. > Why is it reasonable to not work as the language spec defines it? (snip) Cheers, Martin From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e18g2000yqo.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Wed, 18 Mar 2009 10:47:28 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> NNTP-Posting-Host: 81.86.54.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237398448 28687 127.0.0.1 (18 Mar 2009 17:47:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 17:47:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e18g2000yqo.googlegroups.com; posting-host=81.86.54.230; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.14) Gecko/20080404 Firefox/2.0.0.14,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:679 On 18 Mar, 15:05, Martin Thompson wrote: > Jacko writes: > > On 16 Mar, 23:19, Jonathan Bromley > > wrote: > >> On Mon, 16 Mar 2009 15:50:35 -0700 (PDT), Jacko wrote: > > >> [incomplete sensitivity list] > > >> >implies simulation will be differnt from produced logic, > > >> Indeed. That fits my understanding of Bloody Stupid > >> pretty well. > > > Just because simulation is lazy by not actually simulating the > > netlist, you assume much. > > Isn't that backwards? VHDL is a simulation language. You simulate > your code until it works. In this case you will be suprised about the number of possible logic transitions on any signal, when the do not propergate to change the state of another signal. Most sythesizers will generate the logic which has the extra state changes of signals (as it is easier). > Then you run a synthesiser over the same code and it produces you a > netlist which (in theory) matches your code that you so carefully > wrote and verified. It will match your code in boolean logic function of registered values if all critical sensitivities are included. It may not match your code if you miss one, hence the warning. All non critical ones may produce a warning, but would not change the functioning of the code. So there are 3 types of referred to signal. process(clk) fart <= smelly; nose <= fn(fart); end process; in this instance having fart in the sensitivity list is pointless but still makes a warning. with process(clk,smelly) everything will simulate correctly but still cause a warning. with process(clk,fart) changes in smelly would not be relevant, and could be register delayed through clk. > (Clearly the word "you" in the above should be replaced by "other > engineers", or indeed "I" :) > > If the synth doesn't translate that code into a functionally > equivalent netlist, how is that the simulator's fault? Of course we > just have to work with the fact that synth tools do what they do, > which leads me to avoid non-clocked processes wherever possible, but I > don't have to like it, or try and make out it's the way things > "should" work. > > There are always going to be things that simulate that the synth can't > turn into a netlist, but is it valid for it just to go "well, here's > something a bit like it" flag a quick warning (in amongst a morass of > other warnings) and call "job done". > > > And the example under discussion isn't even one where the synth-tool > *can't* do the job conforming to the language spec, it just chooses > not to! It's like a C-compiler changing 'i++' to '++i' "because > that's usually what people want to happen when they write that". > umm. > >> >All reasonable sythesis > >> >tools produce logic as though they had been included in the > >> >sensitivity list, > > >> All tools I know do so, and produce a warning message > >> precisely because it is not "reasonable". > > > No, because it may not be what is expected. It may be reasonable. > > Why is it reasonable to not work as the language spec defines it? No. "why is it reasonable? *reasonable??* well you write the b**tard thing then!!" :-) It may be reasonable to want such registration of values to prevent such signal oscillation for power saving reasons, hence REASONable. cheer jacko From newsfish@newsfish Wed Aug 19 13:23:48 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news-1.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Wed, 18 Mar 2009 11:10:54 -0700 Lines: 14 Message-ID: <49C1392E.3080406@gmail.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net H15GPUiisdG11cCkcEW69QCucnKO4JuGIyGtymKzAQkQLbjrI6 Cancel-Lock: sha1:tYlNdUdBB5X0sk3amCD3gsppj0w= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:680 Jacko wrote: > In this case you will be suprised about the number of possible logic > transitions on any signal, when the do not propergate to change the > state of another signal. Most sythesizers will generate the logic > which has the extra state changes of signals (as it is easier). Every synthesizer I have used has generated a well minimized netlist that matches my simulation. It is up to me, of course, to follow a reasonable synchronous template. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u18g2000pro.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Error --unconstrained record or array type is not supported Date: Wed, 18 Mar 2009 11:29:41 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <5dbbf3fe-24fd-4a29-a49b-7a0c89c26a3d@u18g2000pro.googlegroups.com> References: <1e8bf031-0dcc-4997-b3bc-4345ddc68505@41g2000yqf.googlegroups.com> NNTP-Posting-Host: 67.169.206.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237400981 25015 127.0.0.1 (18 Mar 2009 18:29:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 18:29:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u18g2000pro.googlegroups.com; posting-host=67.169.206.73; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:681 > Zheyu....@googlemail.com wrote: > > I was trying to compile the VHDL code with generic (Width:positive:=3D > > 8); > > > In Quartus, I got the following error. > > Error (10427): VHDL aggregate error at GCD.vhd(49): OTHERS choice used > > in aggregate for unconstrained record or array type is not supported > > > > > ----------------------------------------------------------------- > > library IEEE; > > use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; > > entity GCD is > > generic (Width:positive:=3D 8); ---I have also tried natural and > > integer, but all failed. > > port (Clock,Reset,Load: in std_logic; > > =A0 =A0A,B: =A0 in unsigned(Width-1 downto 0); > > =A0 =A0Done: =A0out std_logic; > > =A0 =A0Y: =A0 =A0 out unsigned(Width-1 downto 0)); > > end entity GCD; > > architecture RTL of GCD is > > =A0 =A0signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0); > > =A0 =A0signal A_lessthan_B: std_logic; > > begin > > > > > =A0 =A0if (B_Hold =3D (others =3D> '0')) then =A0-- here is the error B= _Hold =3D > > (others =3D> '0') > > -----------------------------------------------------------------------= -------- > > I also googled some topic about it, is it true that when using > > generics, B_Hold =3D (others =3D> '0') OTHERS choice used in aggregate = for > > unconstrained record or array type is not supported? > Since B_hold is unsigned, you can take advantage of the overloading and compare to an integer: if B_hold =3D 0 then Cheers, Jim SynthWorks VHDL Training http://www.synthworks.com From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!c9g2000yqm.googlegroups.com!not-for-mail From: Seph Newsgroups: comp.lang.vhdl Subject: Looking for a VHDL simple description for RS-232 Date: Wed, 18 Mar 2009 14:09:42 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: NNTP-Posting-Host: 200.169.63.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237410585 3431 127.0.0.1 (18 Mar 2009 21:09:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 21:09:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c9g2000yqm.googlegroups.com; posting-host=200.169.63.222; posting-account=RUbakQoAAAAUkucHMktelQcsmAF9Mnor User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pt-BR; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxy.univali.br (squid) Xref: news.eternal-september.org comp.lang.vhdl:682 Im new to VHDL and after study a book, im going(at least i want) to implement a rs-232 protocol communication. I made some search on this group but links for the codes were broken, those posts are really old, so if theres any source of VHDL code for rs-232 with an "OK" link, i would really apreciate... More simple is better for me.. Im a new member in this group between ... Thx in any advance... From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.supernews.com!news.supernews.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 18 Mar 2009 16:52:43 -0500 From: "Pete Fraser" Newsgroups: comp.lang.vhdl References: Subject: Re: Looking for a VHDL simple description for RS-232 Date: Wed, 18 Mar 2009 14:52:37 -0700 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: Lines: 18 X-Trace: sv3-fAPwMhx/nGNR9oiVySOk1L7cPueFfJZ77t74PZMCRDJkeS7BWwQ0pUARX2VW2R894mWwuWISnzxkAsp!m7YrzwdciTY3031nLJOHuqptJckn1E4fJQzdnBCYNUzMIJZneHY4Tn3EbQSGQcMA2eBiq1VdcQRT!Ny5GTFb2+oM= X-Complaints-To: www.supernews.com/docs/abuse.html X-DMCA-Complaints-To: www.supernews.com/docs/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:683 "Seph" wrote in message news:f0a68cfb-f69a-4e7b-b48e-15ffbed77b24@c9g2000yqm.googlegroups.com... > Im new to VHDL and after study a book, im going(at least i want) to > implement a rs-232 protocol communication. > > > I made some search on this group but links for the codes were broken, > those posts are really old, so if theres any source of VHDL code for > rs-232 with an "OK" link, i would really apreciate... You're in luck. Mike Treseler is a frequent and valuable contributor here. He has a uart example: http://mysite.verizon.net/miketreseler/uart.vhd From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!h20g2000yqn.googlegroups.com!not-for-mail From: Seph Newsgroups: comp.lang.vhdl Subject: Re: Looking for a VHDL simple description for RS-232 Date: Wed, 18 Mar 2009 15:04:30 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <003f5e6a-e1f3-4b71-8d93-cfd192c63812@h20g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 200.169.63.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237413871 14117 127.0.0.1 (18 Mar 2009 22:04:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Mar 2009 22:04:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h20g2000yqn.googlegroups.com; posting-host=200.169.63.222; posting-account=RUbakQoAAAAUkucHMktelQcsmAF9Mnor User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pt-BR; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxy.univali.br (squid) Xref: news.eternal-september.org comp.lang.vhdl:684 Wow... Fast response... Thx for the advance.... From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp20-2.free.fr!not-for-mail Date: Thu, 19 Mar 2009 06:49:42 +0100 Return-Path: deboutv@free.fr From: Vince Subject: Re: Looking for a VHDL simple description for RS-232 Message-ID: <25f587fd7f5222bfdc11596768c23d84@news.free.fr> X-Priority: 3 User-Agent: NewsReader Newsgroups: comp.lang.vhdl References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="ISO-8859-15" Lines: 14 Organization: Guest of ProXad - France NNTP-Posting-Date: 19 Mar 2009 06:49:42 MET NNTP-Posting-Host: 88.177.126.42 X-Trace: 1237441782 news-2.free.fr 13336 88.177.126.42:33376 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:685 Seph a écrit: > Im new to VHDL and after study a book, im going(at least i want) to > implement a rs-232 protocol communication. > > > I made some search on this group but links for the codes were broken, > those posts are really old, so if theres any source of VHDL code for > rs-232 with an "OK" link, i would really apreciate... Take a look at http://www.opencores.org/ -- Vince From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!publishnet.news-service.com!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Looking for a VHDL simple description for RS-232 References: Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: <2cc3e$49c202f4$54f63171$13808@publishnet.news-service.com> X-Complaints-To: abuse@news-service.com Organization: Publishnet Date: Thu, 19 Mar 2009 09:31:48 +0100 Lines: 28 NNTP-Posting-Host: 84.246.49.113 (84.246.49.113) NNTP-Posting-Date: Thu, 19 Mar 2009 09:31:48 +0100 X-Trace: 2cc3e49c202f4f15394d413808 Xref: news.eternal-september.org comp.lang.vhdl:686 In comp.lang.vhdl, Seph wrote: > Im new to VHDL and after study a book, im going(at least i want) to > implement a rs-232 protocol communication. > > > I made some search on this group but links for the codes were broken, > those posts are really old, so if theres any source of VHDL code for > rs-232 with an "OK" link, i would really apreciate... You cannot implement RS232 in VHDL as the RS232 defines the voltage levels used for communication. I assume you want to be able to transmit/receive the required bit patterns. That job is done bij a UART, and googling for that will give you a lot of working examples. http://www.google.com/search?l&q=vhdl+uart (But even googling for vhdl+rs232 gives a lot of usefull results, including a comlete example by Jonathan Bromley in this newsgroup :-) ) First link (asic-world) is a simple, working example, but check out some more. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Fantasies are free." "NO!! NO!! It's the thought police!!!!" From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 19 Mar 2009 04:08:17 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Looking for a VHDL simple description for RS-232 Date: Thu, 19 Mar 2009 09:06:33 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <7k24s4pjji1ve4okcmg2q6epsvc0nh9i8k@4ax.com> References: <2cc3e$49c202f4$54f63171$13808@publishnet.news-service.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-tM5kSL64+tZQAs1TB9Y92lQuY+3l5ZEFfxHjAxEK7Vx87W00CdwAKylhZ+kFr8yJeLClkOqlCsFv+uV!A0Lyay+OfSw6ulCOLhCFf5nGfiWyQz4M5FkUV7K92KeVCKHGiaKhL2CLZf5Ku3xMWltcJCqz5+GR!RWlT X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:687 On Thu, 19 Mar 2009 09:31:48 +0100, Stef wrote: >(But even googling for vhdl+rs232 gives a lot of usefull results, >including a comlete example by Jonathan Bromley in this newsgroup :-) ) Really??? I don't remember it... though I have a few tucked away in my goodie-bag, just in case anyone should say to me at a smart dinner party "hey, Jonathan, I was just wondering if you had a UART design in VHDL handy"... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.germany.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Thu, 19 Mar 2009 09:32:19 +0000 Organization: TRW Conekt Lines: 72 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net WweGgMwtaPApXiCOOUBZ3QOglm/wkCXq5+AKrztK72Vc+jnGM= Cancel-Lock: sha1:3t0el9/uhju3EaloZ5APuj2Q1NM= sha1:VIG87QgbGgWtT3jCwdh0rhbN2JM= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:688 Jacko writes: > On 18 Mar, 15:05, Martin Thompson wrote: >> VHDL is a simulation language. You simulate >> your code until it works. > > In this case you will be suprised about the number of possible logic > transitions on any signal, when the do not propergate to change the > state of another signal. Most sythesizers will generate the logic > which has the extra state changes of signals (as it is easier). > I was talking about simulators, you're seem to continue to talk about synthesisers... >> Then you run a synthesiser over the same code and it produces you a >> netlist which (in theory) matches your code that you so carefully >> wrote and verified. > > It will match your code in boolean logic function of registered values > if all critical sensitivities are included. That's what happens - I'm saying what I (and many others?) want to happen. > It may not match your code if you miss one, hence the warning. All > non critical ones may produce a warning, but would not change the > functioning of the code. > Sorry - I know how VHDL works. There's even a specification for it - if only all the tools followed it ;) I put a lot of effort into verifiying my code in a simulator. I don't want downstream tools to change how it works. What if I explicitly don't want my circuit to respond to changes on one of those input signals for some reason? > >> >> >All reasonable sythesis >> >> >tools produce logic as though they had been included in the >> >> >sensitivity list, >> >> >> All tools I know do so, and produce a warning message >> >> precisely because it is not "reasonable". >> >> > No, because it may not be what is expected. It may be reasonable. >> >> Why is it reasonable to not work as the language spec defines it? > > No. "why is it reasonable? *reasonable??* well you write the b**tard > thing then!!" :-) > > It may be reasonable to want such registration of values to prevent > such signal oscillation for power saving reasons, hence REASONable. > Are you saying that there are things which couldn't be accomplished if the synthesier and the simulator worked in the same way? What can't you do (that you can do now) if the synthesiser actually used the sensitivity list in the same way as the simulator. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:23:49 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!feeder.news-service.com!feeder.news-service.com!publishnet.news-service.com!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Looking for a VHDL simple description for RS-232 References: <2cc3e$49c202f4$54f63171$13808@publishnet.news-service.com> <7k24s4pjji1ve4okcmg2q6epsvc0nh9i8k@4ax.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: <81fc9$49c217c4$54f63171$25664@publishnet.news-service.com> X-Complaints-To: abuse@news-service.com Organization: Publishnet Date: Thu, 19 Mar 2009 11:00:36 +0100 Lines: 25 NNTP-Posting-Host: 84.246.49.113 (84.246.49.113) NNTP-Posting-Date: Thu, 19 Mar 2009 11:00:36 +0100 X-Trace: 81fc949c217c4f15394d425664 Xref: news.eternal-september.org comp.lang.vhdl:689 In comp.lang.vhdl, Jonathan Bromley wrote: > On Thu, 19 Mar 2009 09:31:48 +0100, Stef wrote: > >>(But even googling for vhdl+rs232 gives a lot of usefull results, >>including a comlete example by Jonathan Bromley in this newsgroup :-) ) > > Really??? I don't remember it... though I have a few > tucked away in my goodie-bag, just in case anyone should > say to me at a smart dinner party "hey, Jonathan, I was > just wondering if you had a UART design in VHDL handy"... In a week the post is 4 years old: http://www.velocityreviews.com/forums/t23492-vhdl-model-of-a-rs-232-transmitter.html They have made it to look like a web forum and obfuscated the origins somewhat. Click on "> VHDL" near the top and you will see current posts. (This and cross-posting is why I include the newsgroup in my attributions, at least I can see where I posted it originally) -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Kids always brighten up a house; mostly by leaving the lights on. From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!c9g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Array of strings? Date: Thu, 19 Mar 2009 04:19:57 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237461597 5837 127.0.0.1 (19 Mar 2009 11:19:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 11:19:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c9g2000yqm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:690 Im trying to bring in a load of file paths into a testbench via generics (I use generics an an area for stuff other users are allowed to modify). I really need an array of strings for the file paths because I need to match the length to another generic that is an array, otherwise the TB should fail. Now I know I could easily do this with VHDL 2008 like: type str_array_t is array(natural range <>) of string; but lets assume for the moment that we cannot use VHDL 2008. am I stuck, going to have to use a separate generic for each file path, which makes the TB far more verbose because I wont be able to do a loop to read in all of the files. I thought about using an array of lines, but the problem with pointers is that they have to be variables, and I would have to set the paths up in a process. Ideally Id like to read the files before time starts. Im guessing Im stuck, and this is exactly why they brought unconstrained array elements into the language. From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 19 Mar 2009 06:38:30 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Array of strings? Date: Thu, 19 Mar 2009 11:36:46 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ujofb+wU2+UYH5+15ho9JZxk/MUcjWS9bYSGeLBZRiXR/aGHW3voin6uLWGDnZp5l+CyZ5JOkaZbMlH!paEXuS5oqN4r6aFFg1f6A1AaC7EaqytieGHKseNnU/iKK38k74FeBMWUUQbX1YMtJW+j1zYe1cYa!3UvB X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:691 On Thu, 19 Mar 2009 04:19:57 -0700 (PDT), Tricky wrote: >Im trying to bring in a load of file paths into a testbench via >generics (I use generics an an area for stuff other users are allowed >to modify). I really need an array of strings for the file paths >because I need to match the length to another generic that is an >array, otherwise the TB should fail. How about one great big string, with all the file paths separated by some convenient separator character such as horizontal-tab? You could then parse these out into a bunch of LINE variables, or (maybe better) keep them in the original string and save the (start, end) character position of each filename in an array of pairs of integer. Yes, the second technique would be better because you could do it all in functions at elaboration time; no nasty pointers anywhere. The same scanning function could tie up your set of filenames with the other array, and throw an assert failure if the lengths don't match. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!l38g2000vba.googlegroups.com!not-for-mail From: Jaco Naude Newsgroups: comp.lang.vhdl Subject: Re: Is this state machine written correctly? Date: Thu, 19 Mar 2009 06:15:54 -0700 (PDT) Organization: http://groups.google.com Lines: 198 Message-ID: <396ed4d6-a145-442a-8566-10f14069bae6@l38g2000vba.googlegroups.com> References: <33c11865-718a-4bbd-b349-ff0a0baeab52@r3g2000vbp.googlegroups.com> <4160a6ab-d1ed-4462-962c-6ac58351a103@y13g2000yqn.googlegroups.com> NNTP-Posting-Host: 146.64.81.8 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237468554 28537 127.0.0.1 (19 Mar 2009 13:15:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 13:15:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l38g2000vba.googlegroups.com; posting-host=146.64.81.8; posting-account=zQcqRgoAAACFp7R5zvQcoCr_PPDlo1qs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 hermes.csir.co.za:3128 (squid/2.5.STABLE12) Xref: news.eternal-september.org comp.lang.vhdl:692 On Mar 18, 2:48=A0pm, KJ wrote: > On Mar 18, 7:36=A0am, Jaco Naude wrote: > > > Hi there > > > I've been struggling with a design containing 3 state machines (Moore) > > working together to form a dynamic memory map. In behavioral > > simulation the simulation works perfectly but in structural simulation > > the design does not work. > > Peruse your synthesis report for some form of message that talks about > an incomplete sensitivity list. =A0Quick perusal shows that the > "OUTPUT_DECODE" process is missing several signals, > "NEXT_STATE_DECODE" is missing at least one and maybe a few more (not > sure if 'S_DATA.ADDR' is a signal or constant since it's not defined > in your posted code). > > Consider not using unclocked processes for exactly this reason, it > leads to difference between simulation and synthesis. =A0Far better to > have all synchronous processes like your "SYNC_PROC" coupled with > concurrent statements for things that must be unclocked. > > If you really prefer the form of "if...then" and "case" statements > that you get to use inside a process but are not available as > concurrent statements, then consider using functions or procedures > instead. =A0Functions and procedures will allow you to use 'if..then', > 'case', etc. statements but you won't be able to have the equivalent > of an incomplete sensitivity list since this would imply use of some > signal that is not defined as an interface to the function/procedure > which the compiler will immediately flag as an error. That way you > won't get stuck perusing synthesis reports for incomplete sensitivity > lists to catch this design error. > > Also, check your testbench to see if the stimulus is being generated > at an acceptable time relative to the clock. =A0In order to use the post > route simulation model you must make sure that the inputs to the > device meet the setup and hold time requirements that the timing > report says is acceptable. =A0If not, then you will get differences > between pre- and post-route simulation models. > > Consider using "if rising_edge(CLK)..." rather than "if (CLK'event and > CLK =3D '1')...", it's more descriptive. =A0Has nothing to do with your > current problem though. > > Kevin Jennings Thanks for the reply Kevin. After taking some of your ideas into consideration I've got a working version now: - ENTITY DMM_SPLITTER IS GENERIC( G_DATA_WIDTH : natural :=3D 32; G_ADDR_WIDTH : natural :=3D 24 ); PORT( S_DATA : IN transmit_bus; --! Data received from a splitter or interface feeding this splitter. S_RESPONSE : OUT response_bus; --! Data sent to a splitter or interface feeding this splitter. M0_DATA : OUT transmit_bus; --! Data sent from a leaf node which is fed by this splitter. M0_RESPONSE : IN response_bus; --! Data received from a leaf node which is fed by this splitter. M1_DATA : OUT transmit_bus; --! Data sent from a leaf node which is fed by this splitter. M1_RESPONSE : IN response_bus; --! Data received from a leaf node which is fed by this splitter. CLK : IN std_logic; --! Clock input. RESET_N : IN std_logic --! Active-low reset input. ); -- Declarations END DMM_SPLITTER ; -- hds interface_end -- hds interface_end --! @brief Architure definition DDM_SPLITTER --! @details This architecture definition should work on any device from any vendor. architecture RTL of DMM_SPLITTER is type state_type is (st_startup, st_init, st_init_m0, st_init_m1, st_ready, st_request_m0, st_request_m1, st_request_idle); signal state : state_type; signal m0_size : integer :=3D 0; signal m1_size : integer :=3D 0; begin SYNC_PROC: process (CLK, RESET_N) begin if (CLK'event and CLK =3D '1') then if (RESET_N =3D '0') then state <=3D st_startup; S_RESPONSE <=3D ((others =3D> '0'),'0'); M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); M1_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); else -- This will generate a valid pulse for new states. case (state) is when st_startup =3D> if RESET_N =3D '1' then state <=3D st_init; else state <=3D st_startup; end if; when st_init =3D> if S_DATA.DVAL =3D '1' then state <=3D st_init_m0; M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '1', '0'); end if; when st_init_m0 =3D> if M0_RESPONSE.DVAL =3D '1' then m0_size <=3D conv_integer(unsigned(M0_RESPONSE.DATA (15 downto 0))); M1_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '1', '0'); state <=3D st_init_m1; else M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); end if; when st_init_m1 =3D> if M1_RESPONSE.DVAL =3D '1' then m1_size <=3D conv_integer(unsigned(M1_RESPONSE.DATA (15 downto 0))); S_RESPONSE <=3D (std_logic_vector(conv_unsigned (m0_size + conv_integer(unsigned(M1_RESPONSE.DATA(15 downto 0))), G_DATA_WIDTH)), '1'); state <=3D st_ready; else M1_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); end if; when st_ready =3D> S_RESPONSE <=3D ((others =3D> '0'), '0'); M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0'= , '0'); M1_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0'= , '0'); if (S_DATA.DVAL =3D '1' and (unsigned(S_DATA.ADDR) < conv_unsigned(m0_size,G_ADDR_WIDTH))) then M0_DATA <=3D S_DATA; state <=3D st_request_m0; elsif (S_DATA.DVAL =3D '1' and (unsigned (S_DATA.ADDR) >=3D conv_unsigned(m0_size,G_ADDR_WIDTH)) and (unsigned (S_DATA.ADDR) < conv_unsigned(m1_size+m0_size,G_ADDR_WIDTH))) then M1_DATA <=3D S_DATA; M1_DATA.ADDR <=3D std_logic_vector(conv_unsigned (conv_integer(unsigned(S_DATA.ADDR)) - m0_size,G_ADDR_WIDTH)); state <=3D st_request_m1; elsif (S_DATA.DVAL =3D '1' and (unsigned (S_DATA.ADDR) >=3D conv_unsigned(m1_size+m0_size,G_ADDR_WIDTH))) then -- The received address is too big for this splitter. Something went wrong upstream in the DMM. Go into error state. S_RESPONSE <=3D (error_code, '1'); end if; when st_request_m0 =3D> if M0_RESPONSE.DVAL =3D '1' then S_RESPONSE <=3D M0_RESPONSE; state <=3D st_ready; else M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); state <=3D st_request_m0; end if; when st_request_m1 =3D> if M1_RESPONSE.DVAL =3D '1' then S_RESPONSE <=3D M1_RESPONSE; state <=3D st_ready; else M0_DATA <=3D ((others =3D> '0'), (others =3D> '0'), '0', '0'); state <=3D st_request_m1; end if; when others =3D> state <=3D st_ready; end case; end if; end if; end process; end RTL; Thanks again, Jaco From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!o11g2000yql.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Thu, 19 Mar 2009 08:03:52 -0700 (PDT) Organization: http://groups.google.com Lines: 87 Message-ID: <16f6e99a-7abe-45a0-810e-fc00f7be913b@o11g2000yql.googlegroups.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237475033 2890 127.0.0.1 (19 Mar 2009 15:03:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 15:03:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yql.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:693 On 19 Mar, 09:32, Martin Thompson wrote: > Jacko writes: > > On 18 Mar, 15:05, Martin Thompson wrote: > >> VHDL is a simulation language. =A0You simulate > >> your code until it works. > > > In this case you will be suprised about the number of possible logic > > transitions on any signal, when the do not propergate to change the > > state of another signal. Most sythesizers will generate the logic > > which has the extra state changes of signals (as it is easier). > > I was talking about simulators, you're seem to continue to talk about > synthesisers... > > >> Then you run a synthesiser over the same code and it produces you a > >> netlist which (in theory) matches your code that you so carefully > >> wrote and verified. > > > It will match your code in boolean logic function of registered values > > if all critical sensitivities are included. > > That's what happens - I'm saying what I (and many others?) want to happen= . > > > It may not match your code if you miss one, hence the warning. All > > non critical ones may produce a warning, but would not change the > > functioning of the code. > > > > Sorry - I know how VHDL works. =A0There's even a specification for it - > if only all the tools followed it ;) > > I put a lot of effort into verifiying my code in a simulator. =A0I don't > want downstream tools to change how it works. =A0What if I explicitly > don't want my circuit to respond to changes on one of those input > signals for some reason? > > > > > > > > > > >> >> >All reasonable sythesis > >> >> >tools produce logic as though they had been included in the > >> >> >sensitivity list, > > >> >> All tools I know do so, and produce a warning message > >> >> precisely because it is not "reasonable". > > >> > No, because it may not be what is expected. It may be reasonable. > > >> Why is it reasonable to not work as the language spec defines it? > > > No. "why is it reasonable? *reasonable??* well you write the b**tard > > thing then!!" :-) > > > It may be reasonable to want such registration of values to prevent > > such signal oscillation for power saving reasons, hence REASONable. > > Are you saying that there are things which couldn't be accomplished if > the synthesier and the simulator worked in the same way? > > What can't you do (that you can do now) if the synthesiser actually > used the sensitivity list in the same way as the simulator. > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html- Hide quoted text - > > - Show quoted text - Nothing!! nibzB.vhd not yet available will have the seperate D_I and D_O and correct sensitivity to them. From my minimum state change prospective. cheers jacko http://nibz.googlecode.com From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!talisker.lacave.net!lacave.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!w34g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Variable Input on procedure - pass by value or pass by reference? Date: Thu, 19 Mar 2009 08:58:06 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237478286 13320 127.0.0.1 (19 Mar 2009 15:58:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 15:58:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w34g2000yqm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:694 I have the following in my code: type img_2d_ptr is access image_grey_2D_t; type image_array_t is array(natural range <>) of img_2d_ptr; shared variable PIP_IMAGES : image_array_t(PIP_REGISTERS'range) := read_PIP_images; procedure destroy_images( variable x : in image_array_t ) is begin for i in x'range loop DEALLOCATE( x(i) ); end loop; end procedure destroy_images; The pass by reference/value is quite important here, because I need to actually make sure the images are actually deallocated, and it doesnt deallocate just a copy of them. Would it just be safer to ignore the input on the procedure and just deallocate the PIP_IMAGES shared variable directly? From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!talisker.lacave.net!lacave.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!s20g2000yqh.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Variable Input on procedure - pass by value or pass by reference? Date: Thu, 19 Mar 2009 08:59:11 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: fbd684ad-302d-46c8-9d3f-39684f387e4d@w34g2000yqm.googlegroups.com NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237478351 13662 127.0.0.1 (19 Mar 2009 15:59:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 15:59:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000yqh.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:695 On 19 Mar, 15:58, Tricky wrote: > I have the following in my code: > > type img_2d_ptr is access image_grey_2D_t; > type image_array_t is array(natural range <>) of img_2d_ptr; > shared variable PIP_IMAGES =A0: image_array_t(PIP_REGISTERS'range) :=3D > read_PIP_images; > > procedure destroy_images( variable x : in image_array_t ) is > begin > =A0 for i in x'range loop > =A0 =A0 DEALLOCATE( x(i) ); > =A0 end loop; > end procedure destroy_images; > > The pass by reference/value is quite important here, because I need to > actually make sure the images are actually deallocated, and it doesnt > deallocate just a copy of them. > > Would it just be safer to ignore the input on the procedure and just > deallocate the PIP_IMAGES shared variable directly? Having just read that to myself, it must be pass by reference, else the DEALLOCATE procedure itself wouldnt work! From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!talisker.lacave.net!lacave.net!de-l.enfer-du-nord.net!news.glorb.com!postnews.google.com!e38g2000yqa.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Thu, 19 Mar 2009 09:15:47 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237479347 31632 127.0.0.1 (19 Mar 2009 16:15:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 16:15:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e38g2000yqa.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:696 On Mar 18, 1:47=A0pm, Jacko wrote: > > It will match your code in boolean logic function of registered values > if all critical sensitivities are included. It may not match your code > if you miss one, hence the warning. All non critical ones may produce > a warning, but would not change the functioning of the code. > > So there are 3 types of referred to signal. > > process(clk) > =A0 fart <=3D smelly; > =A0 nose <=3D fn(fart); > end process; > > in this instance having fart in the sensitivity list is pointless but > still makes a warning. > > with process(clk,smelly) everything will simulate correctly but still > cause a warning. > > with process(clk,fart) changes in smelly would not be relevant, and > could be register delayed through clk. Correct me if I'm wrong here, but if 'fart' were not in the sensitivity list, wouldn't it be that 'nose' wouldn't get the correct value? Since 'fart' is not updated until a delta cycle later, the process would need to fire again for 'nose' to get the results of the function for the new 'fart'. But without 'fart' in the list, the process won't fire upon 'fart' changing, and 'nose' represents the value from the old 'fart'. Dave From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newshub.sdsu.edu!news-xxxfer.readnews.com!news-out.readnews.com!transit4.readnews.com!postnews.google.com!c11g2000yqj.googlegroups.com!not-for-mail From: Reuven Newsgroups: comp.lang.vhdl Subject: Re: Variable Input on procedure - pass by value or pass by reference? Date: Thu, 19 Mar 2009 12:21:38 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: fbd684ad-302d-46c8-9d3f-39684f387e4d@w34g2000yqm.googlegroups.com NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237490498 3350 127.0.0.1 (19 Mar 2009 19:21:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 19:21:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c11g2000yqj.googlegroups.com; posting-host=132.228.195.207; posting-account=96toEwoAAAAj_H6Uvl-DoCJyQg6KZtGq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:697 On Mar 19, 8:59=A0am, Tricky wrote: > On 19 Mar, 15:58, Tricky wrote: > > > > > > > I have the following in my code: > > > type img_2d_ptr is access image_grey_2D_t; > > type image_array_t is array(natural range <>) of img_2d_ptr; > > shared variable PIP_IMAGES =A0: image_array_t(PIP_REGISTERS'range) :=3D > > read_PIP_images; > > > procedure destroy_images( variable x : in image_array_t ) is > > begin > > =A0 for i in x'range loop > > =A0 =A0 DEALLOCATE( x(i) ); > > =A0 end loop; > > end procedure destroy_images; > > > The pass by reference/value is quite important here, because I need to > > actually make sure the images are actually deallocated, and it doesnt > > deallocate just a copy of them. > > > Would it just be safer to ignore the input on the procedure and just > > deallocate the PIP_IMAGES shared variable directly? > > Having just read that to myself, it must be pass by reference, else > the DEALLOCATE procedure itself wouldnt work!- Hide quoted text - > > - Show quoted text - Shouldn't the parameter be an "inout" and not just "in" ? From newsfish@newsfish Wed Aug 19 13:23:50 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!c36g2000yqn.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Thu, 19 Mar 2009 12:28:51 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: <71eea028-4aaf-46fe-a3c9-01286a00b0d0@c36g2000yqn.googlegroups.com> References: c4d20bf3-46e9-4891-83d6-6e257444f47b@e38g2000yqa.googlegroups.com NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237490932 4711 127.0.0.1 (19 Mar 2009 19:28:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 19:28:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c36g2000yqn.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:698 On 19 Mar, 16:15, Dave wrote: > On Mar 18, 1:47=A0pm, Jacko wrote: > > > > > > > > > It will match your code in boolean logic function of registered values > > if all critical sensitivities are included. It may not match your code > > if you miss one, hence the warning. All non critical ones may produce > > a warning, but would not change the functioning of the code. > > > So there are 3 types of referred to signal. > > > process(clk) > > =A0 fart <=3D smelly; > > =A0 nose <=3D fn(fart); > > end process; > > > in this instance having fart in the sensitivity list is pointless but > > still makes a warning. > > > with process(clk,smelly) everything will simulate correctly but still > > cause a warning. > > > with process(clk,fart) changes in smelly would not be relevant, and > > could be register delayed through clk. > > Correct me if I'm wrong here, but if 'fart' were not in the > sensitivity list, wouldn't it be that 'nose' wouldn't get the correct > value? Since 'fart' is not updated until a delta cycle later, the > process would need to fire again for 'nose' to get the results of the > function for the new 'fart'. But without 'fart' in the list, the > process won't fire upon 'fart' changing, and 'nose' represents the > value from the old 'fart'. "What are tou doing Dave?" - ....... But seriously that is wahat I would expect, hence power transitions on smelly or indirectly on nose would be avoided as the sim would suggest, but sythesis may emit a warning and still make a circuit which consumes said power. cheers jacko From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!p11g2000yqe.googlegroups.com!not-for-mail From: Seph Newsgroups: comp.lang.vhdl Subject: Re: Looking for a VHDL simple description for RS-232 Date: Thu, 19 Mar 2009 13:01:52 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: <640a33fb-dae6-458a-b8ad-3a2cce03ab2d@p11g2000yqe.googlegroups.com> References: <2cc3e$49c202f4$54f63171$13808@publishnet.news-service.com> <7k24s4pjji1ve4okcmg2q6epsvc0nh9i8k@4ax.com> <81fc9$49c217c4$54f63171$25664@publishnet.news-service.com> NNTP-Posting-Host: 200.169.63.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237492912 11346 127.0.0.1 (19 Mar 2009 20:01:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Mar 2009 20:01:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000yqe.googlegroups.com; posting-host=200.169.63.222; posting-account=RUbakQoAAAAUkucHMktelQcsmAF9Mnor User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pt-BR; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxy.univali.br (squid) Xref: news.eternal-september.org comp.lang.vhdl:699 Thx for all the help... Before posting i made a search at the old posts about rs-232, but it didn't helped that much... From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!t3g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Why do shared variables HAVE to be a protected type? Date: Fri, 20 Mar 2009 09:40:05 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237567205 6469 127.0.0.1 (20 Mar 2009 16:40:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Mar 2009 16:40:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t3g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:700 I asked this because Im just writing a function that has memory of certain variables, so subsequent calls use the previous data (dont worry, its for testbenching only) and to do this, I obviously have to use shared variables. Now, I ask the question above, because this function will sit in a package, and the shared variables will only sit in the package body, so nothing external to the package has access to the shared variables. Whats wrong with using unprotected shared variables here? I know modelsim only throws a warning, and my doulos golden reference guide also tells me I "must" use a protected type for a shared variable, so why doesnt modelsim throw an Error instead of a warning? sims and unprotected shared variables work fine together - I assume this is something to do with different versions of the language spec, VHDL 2000 and 2002? From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 20 Mar 2009 11:47:26 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Why do shared variables HAVE to be a protected type? Date: Fri, 20 Mar 2009 16:45:40 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 51 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-fpGYSCx3sazNvBS8ojwLCTz6trkaDINMdMYrjkVvRtmTH6MbxtPpRIkEZJVNUacrcmr7suvsq3mhQ1l!esgx7zpKY4+TwdlGqF/OMFISykkKJG6wBdGJYehdNefCF92xsF9JDc2lnkJpNKQktlFMTVmX6K34!O03N X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:701 On Fri, 20 Mar 2009 09:40:05 -0700 (PDT), Tricky wrote: >I asked this because Im just writing a function that has memory of >certain variables, so subsequent calls use the previous data (dont >worry, its for testbenching only) and to do this, I obviously have to >use shared variables. > >Now, I ask the question above, because this function will sit in a >package, and the shared variables will only sit in the package body, >so nothing external to the package has access to the shared variables. >Whats wrong with using unprotected shared variables here? Any process can access the shared variables. To get coherent behaviour you need the mutex that shared variables provide. >I know modelsim only throws a warning, and my doulos golden reference >guide also tells me I "must" use a protected type for a shared >variable, so why doesnt modelsim throw an Error instead of a warning? >sims and unprotected shared variables work fine together - I assume >this is something to do with different versions of the language spec, >VHDL 2000 and 2002? Actually VHDL-93 vs. VHDL >= 2000. VHDL-93 shared variables were unprotected, and known to be unsafe. Like sharp knives, guns and WMDs, unsafe things can be extremely useful when deployed with care by the right people :-) Unfortunately, not all VHDL simulators implement protected types. So it's probably wise for ModelSim to issue only a warning, else it would fail to run code that runs "correctly" on other tools. In practice, of course, it is rather unlikely to get incoherent behaviour from old-fashioned shared variables and most people get away with using them just fine. However, there is many a promising career that has been ruined by the tiny difference between "unlikely" and "impossible".... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why do shared variables HAVE to be a protected type? Date: Fri, 20 Mar 2009 09:55:24 -0700 Lines: 29 Message-ID: <49C3CA7C.5010007@gmail.com> References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 8YZqCxFHsFGX319k4XuyqwLPsTSNWu6nMsncIZ35t8Xl8M7Hqu Cancel-Lock: sha1:GNAcDHuML0aDgdBZfgbBwNm9jAU= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:702 Tricky wrote: > Why do shared variables HAVE to be a protected type? > I asked this because Im just writing a function that has memory of > certain variables, so subsequent calls use the previous data (dont > worry, its for testbenching only) and to do this, I obviously have to > use shared variables. I sometimes "share" regular variables across testbench procedures by declaring them all in the same test process. > Now, I ask the question above, because this function will sit in a > package, and the shared variables will only sit in the package body, > so nothing external to the package has access to the shared variables. > Whats wrong with using unprotected shared variables here? Multiple processes can use the same package. > I know modelsim only throws a warning, and my doulos golden reference > guide also tells me I "must" use a protected type for a shared > variable, so why doesnt modelsim throw an Error instead of a warning? vhdl93 style shared variables are given a pass by modelsim so that I don't have to rewrite all of my old sims at once ;) -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!j38g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Why do shared variables HAVE to be a protected type? Date: Fri, 20 Mar 2009 10:22:57 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <704bd2ba-2a66-4c10-8cae-5fec18b75519@j38g2000yqa.googlegroups.com> References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237569777 430 127.0.0.1 (20 Mar 2009 17:22:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Mar 2009 17:22:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j38g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:703 On 20 Mar, 16:45, Jonathan Bromley wrote: > On Fri, 20 Mar 2009 09:40:05 -0700 (PDT), Tricky wrote: > >I asked this because Im just writing a function that has memory of > >certain variables, so subsequent calls use the previous data (dont > >worry, its for testbenching only) and to do this, I obviously have to > >use shared variables. > > >Now, I ask the question above, because this function will sit in a > >package, and the shared variables will only sit in the package body, > >so nothing external to the package has access to the shared variables. > >Whats wrong with using unprotected shared variables here? > > Any process can access the shared variables. =A0To get > coherent behaviour you need the mutex that shared > variables provide. > But that was the point, Im only declaring them inside the package body, not the package header. So only the functions inside the package body can see them - no processes should have access to them, unless you can put processes in packages now? From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why do shared variables HAVE to be a protected type? Date: Fri, 20 Mar 2009 10:51:16 -0700 Lines: 13 Message-ID: <72i3clFq0rihU1@mid.individual.net> References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> <704bd2ba-2a66-4c10-8cae-5fec18b75519@j38g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 8UURMtTHpLiG2vzYvaTz2wHDxr+DVthAhDlKEwCpsZbKLpDlBG Cancel-Lock: sha1:l1N5ns/rkkpao2VJ6Li7dmJV1a4= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <704bd2ba-2a66-4c10-8cae-5fec18b75519@j38g2000yqa.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:704 Tricky wrote: > But that was the point, Im only declaring them inside the package > body, not the package header. So only the functions inside the package > body can see them - no processes should have access to them, unless > you can put processes in packages now? Whether the shared variable is changed directly or indirectly by a testbench process, the problem is the same. If no process can affect the variable, then it is useless. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!h20g2000yqj.googlegroups.com!not-for-mail From: edick@hotmail.com Newsgroups: comp.lang.vhdl Subject: can I specify a time-varying clock? Date: Sat, 21 Mar 2009 09:41:06 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: NNTP-Posting-Host: 216.98.199.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237653666 22575 127.0.0.1 (21 Mar 2009 16:41:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Mar 2009 16:41:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h20g2000yqj.googlegroups.com; posting-host=216.98.199.111; posting-account=BtPTKQoAAAD8Sok7ug4JB1TbSNjpgMpx User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:705 I need to simulate a circuit that uses a clock that varies over time, e.g. starts out nominal at, say 80 MHz, and then, gradually slows down to 2% below that center frequency, then gradually increases in frequency to 2% above that frequency, then comes back to the nominal 80 MHz rate in a period of, say, 1/60 second. Imagine using a sweep signal generator to produce such a cycle. Is there a cool way to specify such a thing in VHDL? Thanks! From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sat, 21 Mar 2009 16:32:36 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: can I specify a time-varying clock? Date: Sat, 21 Mar 2009 21:30:50 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <5pmas4ha4ndgv8900o1vm51o959frsubt3@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 47 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-oGEaz4oYJLsp6P+2uiXmzYR9Bf3bU6BEuxM4chEwxcN1wO1iHAkhmoYIghzSKC3I0Ghz4ioJqdQAnPr!bh7PMvCRdcP5cWkJRM6TnE5w80rM+KpfLUuW9WRdFREizUyNFUZix1aJnLm0uDxLBRobFmw5CZWn!ygrP X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:706 On Sat, 21 Mar 2009 09:41:06 -0700 (PDT), edick@hotmail.com wrote: >I need to simulate a circuit that uses a clock that varies over time, >e.g. starts out nominal at, say 80 MHz, and then, gradually slows down >to 2% below that center frequency, then gradually increases in >frequency to 2% above that frequency, then comes back to the nominal >80 MHz rate in a period of, say, 1/60 second. > >Imagine using a sweep signal generator to produce such a cycle. > >Is there a cool way to specify such a thing in VHDL? Use a signal of type TIME to represent the period, or a signal of type REAL to represent the frequency error (percentage). A standard clock-generator process can then respond to that value and generate the right cycle timing: signal frequency_error: real := 0.0; ... clock_gen: process variable period: time; constant nominal_Hz: real := 80.0e6; begin -- Compute the period period := 1 sec / (nominal_Hz * (1.0 + frequency_error)); -- Generate one cycle at the appropriate period clock <= '0', '1' after period/2; wait for period; -- And then loop back. end process; Now you can write another process that updates "frequency_error" in any way you choose as a function of time. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:51 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 21 Mar 2009 21:40:09 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: Reed Solomon Encoder Date: Sat, 21 Mar 2009 19:37:43 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 41.153.217.251 Lines: 14 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-lX3ML3Fr5C/kjTWISjWE2/H9PWf/Rce5FMidQyvTGGsdouttpDm2c+4pI7rPdxkm4d8LEStdD7P31KQ!JqKAdzM+LqujpUJH7QDcnLPsdkQP19drRrEx1IgHZgXshbiFvGlHJg4xpCfHTg== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:707 hi all , I need a reed solomon encoder/decoder implementation on vhdl ? or golay , any type of the cyclic codes. any help will be appreciated. Thank you -- afo123124 ------------------------------------------------------------------------ afo123124's Profile: http://www.fpgacentral.com/group/member.php?userid=41 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88775 From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j9g2000prh.googlegroups.com!not-for-mail From: Homuncilus Newsgroups: comp.lang.vhdl Subject: Re: Reed Solomon Encoder Date: Sun, 22 Mar 2009 05:29:29 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <5f86943c-5346-408d-ad00-c54e1dd5192b@j9g2000prh.googlegroups.com> References: NNTP-Posting-Host: 58.24.87.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237724969 21914 127.0.0.1 (22 Mar 2009 12:29:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 22 Mar 2009 12:29:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prh.googlegroups.com; posting-host=58.24.87.15; posting-account=EgaNewoAAAD5QMWXgkAgxZrTU0g1qXJn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9b5) Gecko/2008052519 CentOS/3.0b5-0.beta5.6.el5.centos Firefox/3.0b5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:708 On Mar 22, 10:37=A0am, 'use_real_email' wrote: > hi all , > I need a reed solomon encoder/decoder implementation on vhdl ? or golay > , any type of the cyclic codes. > > any help will be appreciated. > Thank you > > -- > afo123124 > ------------------------------------------------------------------------ > afo123124's Profile:http://www.fpgacentral.com/group/member.php?userid=3D= 41 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D8877= 5 you can refer to the ieee paper "high speed architectures for reed- solomon decoders" From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!gnilink.net!nx02.iad.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 23 Mar 2009 04:28:34 -0500 Date: Mon, 23 Mar 2009 09:28:26 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why do shared variables HAVE to be a protected type? References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> In-Reply-To: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 73 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-l24s/oykHeaWForoUgbX9laFKFehpIGG9KqBTL4MB3KwSBnkViqMFg8Fp1fQHiNrg3jI106JjYAZwLe!MImZawyci5YEpylpXzoRyZrmSP7sCys/Bk5V1isF03G9gc8SxPdNmwdc04P5YQ/cEYC9dvQPUFcz!C3vzjKalqbw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:709 Tricky wrote: > I asked this because Im just writing a function that has memory of > certain variables, so subsequent calls use the previous data (dont > worry, its for testbenching only) and to do this, I obviously have to > use shared variables. > > Now, I ask the question above, because this function will sit in a > package, and the shared variables will only sit in the package body, > so nothing external to the package has access to the shared variables. > Whats wrong with using unprotected shared variables here? > Hi Tricky, you can put a shared variable in a package declaration - it's certainly a good approach to share it :-) I had a play with shared variable and used a structure like this: -- compile this into lib1 say package p1 is type sT is protected impure f; end protected; end; package body p1 is type sT is protected body impure f is begin end; end protected body; end package body; -- compile this anywhere library lib1; use lib1.p1.all; package p2 is shared variable s : sT; end package; then use p2 whereever you need your shared variable. In principle you could put that all in one package, but I was trying to achieve a high degree of encapsulation hence the rather contorted structure. It was quite disappointing to discover that certain tools didn's support protected mode types :-( regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: "Symon" Newsgroups: comp.lang.vhdl Subject: Re: Reed Solomon Encoder Date: Mon, 23 Mar 2009 10:14:06 -0000 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: <5f86943c-5346-408d-ad00-c54e1dd5192b@j9g2000prh.googlegroups.com> X-Trace: news.eternal-september.org U2FsdGVkX1/rMJy8A1nTjSt3FhdwPKwer/immOvDMRlvLtEK0F0IgN//Taf5F/8JwkUmXcZW5B8Q38d6dW8Pi2b2DRdrRjAn126smadWGiI6AO7L7qUlwwn7HehTvwIbJqf8OzDT04M= X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Mon, 23 Mar 2009 10:14:12 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX19L4S/dwbMrFs2f5xM+h9qzuuQHwNKQ94k= Cancel-Lock: sha1:WxQeXqhBRzjrYzuyXzmaFH27Teo= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:710 http://sourceforge.net/projects/rstk/ From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feed.cnntp.org!news.cnntp.org!87.106.131.165.MISMATCH!newsfeed.datemas.de!news.germany.com!postnews.google.com!37g2000yqp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 23 Mar 2009 10:17:02 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237828622 29338 127.0.0.1 (23 Mar 2009 17:17:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Mar 2009 17:17:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000yqp.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:711 On Mar 19, 11:15=A0am, Dave wrote: > Correct me if I'm wrong here, but if 'fart' were not in the > sensitivity list, wouldn't it be that 'nose' wouldn't get the correct > value? Since 'fart' is not updated until a delta cycle later, the > process would need to fire again for 'nose' to get the results of the > function for the new 'fart'. But without 'fart' in the list, the > process won't fire upon 'fart' changing, and 'nose' represents the > value from the old 'fart'. > > Dave You are correct. Fart will not propagate from smelly to nose until a clock cycle later (or as written, a half clock cycle, since the process will fire on both rising and falling edges of the clock). This may be one of the most common misunderstandings in all of vhdl, but if it were not for this "feature" then race conditions would abound throughout VHDL. Simple variables, since they are not shared between processes, can safely update immediately without hazarding a race condition. Andy From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!j38g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 23 Mar 2009 10:47:12 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <4f15b66e-4287-4ca5-91ab-9084e4c552cf@j38g2000yqa.googlegroups.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> <16f6e99a-7abe-45a0-810e-fc00f7be913b@o11g2000yql.googlegroups.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237830432 2762 127.0.0.1 (23 Mar 2009 17:47:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Mar 2009 17:47:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j38g2000yqa.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:712 On Mar 19, 10:03 am, Jacko wrote: > > Nothing!! nibzB.vhd not yet available will have the seperate D_I and > D_O and correct sensitivity to them. From my minimum state change > prospective. > > cheers jacko > > http://nibz.googlecode.com If you simulated nibzA.vhd, you would see what the difference between simulation and synthesis is WRT the following simplification of your example: process(smelly) is begin fart <= smelly; nose <= fn(fart); end process; The combinatorial processes in nibzA.vhd exhibit this mistake a few times too. Andy From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w35g2000yqm.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 23 Mar 2009 12:37:48 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> <16f6e99a-7abe-45a0-810e-fc00f7be913b@o11g2000yql.googlegroups.com> <4f15b66e-4287-4ca5-91ab-9084e4c552cf@j38g2000yqa.googlegroups.com> NNTP-Posting-Host: 217.171.129.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237837068 19555 127.0.0.1 (23 Mar 2009 19:37:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Mar 2009 19:37:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000yqm.googlegroups.com; posting-host=217.171.129.73; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:713 On 23 Mar, 17:47, Andy wrote: > On Mar 19, 10:03 am, Jacko wrote: > > > > > Nothing!! nibzB.vhd not yet available will have the seperate D_I and > > D_O and correct sensitivity to them. From my minimum state change > > prospective. > > > cheers jacko > > >http://nibz.googlecode.com > > If you simulated nibzA.vhd, you would see what the difference between > simulation and synthesis is WRT the following simplification of your > example: > > process(smelly) is > begin > =A0 fart <=3D smelly; > =A0 nose <=3D fn(fart); > end process; > > The combinatorial processes in nibzA.vhd exhibit this mistake a few > times too. > > Andy Yes, I have not ignored the warnings, they are still there. The fact that sythesis in Quartus II 8.0 seems to not use the simulation understanding is of small education on such a design. On a large design, the power density limits of a material semiconductor may be exceeded by such differing 'easy' sythesis vs. 'lazy' simulation outcomes. So process(all) should be augmented with process(enough) or some such suitable enumeration generic ting. or maybe just process() which would appear to be a useless process template. cheers jacko a.k.a. doc sith (dark side pesant revolutionary front :-) From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: How do variables get synthesized in this case? Date: Mon, 23 Mar 2009 12:47:45 -0700 Lines: 11 Message-ID: <49C7E761.4000105@gmail.com> References: <5bgtr49j2b1b5iukl95d27gt1jje04jdkt@4ax.com> <3ae49ec1-31b3-4f4e-9154-4e1c92b18d4c@c11g2000yqj.googlegroups.com> <16f6e99a-7abe-45a0-810e-fc00f7be913b@o11g2000yql.googlegroups.com> <4f15b66e-4287-4ca5-91ab-9084e4c552cf@j38g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 2r+TLctnzRklIzxsz6LqMQgv7uCDOHP71NB33jd5B2PSIOqifF Cancel-Lock: sha1:Z8mQJH8bxOacpQ5sQaUonJnp4pM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:714 Jacko wrote: > or maybe just process() which would appear to be a useless process > template. My favorite is process(reset, clock) -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!news.astraweb.com!border5.newsrouter.astraweb.com!eweka.nl!hq-usenetpeers.eweka.nl!proxad.net!feeder2-2.proxad.net!newsfeed.arcor.de!newsspool3.arcor-online.net!news.arcor.de.POSTED!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.lang.vhdl Subject: Re: can I specify a time-varying clock? Date: Tue, 24 Mar 2009 11:32:36 +0100 Message-ID: <1pbhs4lecq2832moevflu82n3kt7ijt226@4ax.com> References: X-Newsreader: Forte Agent 4.2/32.1118 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 206 Organization: Arcor NNTP-Posting-Date: 24 Mar 2009 11:32:45 CET NNTP-Posting-Host: 0c64e1ff.newsspool4.arcor-online.net X-Trace: DXC=FGhID:b`7XAFJ3]dH>I?oE4IUKI need to simulate a circuit that uses a clock that varies over time, >e.g. starts out nominal at, say 80 MHz, and then, gradually slows down >to 2% below that center frequency, then gradually increases in >frequency to 2% above that frequency, then comes back to the nominal >80 MHz rate in a period of, say, 1/60 second. > >Imagine using a sweep signal generator to produce such a cycle. > >Is there a cool way to specify such a thing in VHDL? Manipulating the real value "frequency" is left as an exercise to you :-) clk_and_rst.vhd: =========================================================================== -- -- entity clk_and_reset.vhd -- (c) jul 2007 Gerhard Hoffmann, ghf at hoffmann - hochfrequenz . de -- open source under BSD conditions -- -- canonic location: /lib/vhdl/tb/clk_and_rst/clk_and_rst.vhdl -- -- Solution to an everyday problem. -- This module produces a clock for a simulation with selectable frequency -- and a reset signal with selectable width. -- The clock duty cycle is 1:1. -- The reset is active from the beginning and removed synchronously shortly -- after a rising clock edge. -- -- setting verbose to true gives some diagnostics. -- -- Make sure that your simulator has a time resolution of at least 1 ps. -- For modelsim, this is set up by the various modelsim.ini files -- and/or the project file (foobar.mpf) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity clk_and_rst is generic ( verbose: boolean := false ); port ( clock_frequency: in real := 100.0e6; min_resetwidth: in time := 12 ns; -- minimum resetwidth, is synchronized to clk clk: out std_logic; rst: out std_logic ); end entity clk_and_rst; -- architecture rtl of clk_and_rst is signal iclk: std_logic := '0'; -- entity-internal clk and rst signal irst: std_logic := '1'; signal halfcycle: time := 0 ps; -- The clock frequency is given in Hz in floating point format. -- compute the equivalent half cycle time. function frequency2halfcycle(f: real; verbose: boolean) return time is variable picoseconds: real; variable retval: time; begin assert f > 1.0e-10 report "clk_and_rst.vhd: requested clock frequency is unreasonably low or even negative - danger of 1/0.0" severity error; picoseconds := (0.5 / f ) / 1.0e-12; retval := integer(picoseconds) * 1 ps; if verbose then report "function frequency2halfcycle in clk_and_rst.vhd: picoseconds = " & real'image(picoseconds); report "halfcycle = " & time'image(retval); end if; assert retval > 0 ps report "frequency2halfcycle: length of halfcycle truncated to 0 ps. " & "Set simulator resolution to 1 ps or smaller in modelsim.ini or foobar.mpf" severity error; return retval; end; ---------------------------------------------------------------------------------------------------- begin -- generate the internal system clock u_determine_halfcycle: process (clock_frequency) is begin halfcycle <= frequency2halfcycle(clock_frequency, verbose); end process u_determine_halfcycle; u_sysclock: process is begin wait for halfcycle; iclk <= '1'; wait for halfcycle; iclk <= '0'; end process u_sysclock; clk <= iclk; -- -- generate internal reset u_rst: process is begin irst <= '1'; wait for min_resetwidth; wait until rising_edge(iclk); irst <= '0'; wait; -- forever end process u_rst; rst <= irst; end architecture rtl; =========================================================================== clk_and_rst_tb.vhd: =========================================================================== -- -- testbed for entity clk_and_reset.vhd -- (c) jul 2007 Gerhard Hoffmann, ghf at hoffmann - hochfrequenz . de -- open source under BSD conditions -- slightly modified 2009-mar-23 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; entity clk_and_rst_tb is end entity clk_and_rst_tb; -- architecture rtl of clk_and_rst_tb is component clk_and_rst is generic ( verbose: boolean := false ); port ( clock_frequency: in real := 100.0e6; min_resetwidth: in time := 12 ns; -- minimum resetwidth, is synchronized to clk clk: out std_logic; rst: out std_logic ); end component; signal clk: std_logic; signal rst: std_logic; signal frequency: real; begin frequency <= 100.0e6, 50.0e6 after 200 ns, 10.0e6 after 400 ns; uut: clk_and_rst generic map( verbose => true ) port map( clock_frequency => frequency, min_resetwidth => 153 ns, clk => clk, rst => rst ); end architecture rtl; =========================================================================== and the result: http://www.bilder-hochladen.net/files/9hqp-3-gif.html regards, Gerhard From newsfish@newsfish Wed Aug 19 13:23:52 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!t-online.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.190.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Assigning arrays of different types Date: Tue, 24 Mar 2009 06:48:05 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <22c179f9-706a-4ce1-96ea-3ebdeb8fb84e@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237902485 7045 127.0.0.1 (24 Mar 2009 13:48:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Mar 2009 13:48:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:716 Hi, I am trying the following: library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture rtl of test is subtype stype_2b is std_logic_vector(1 downto 0); type type_ch_array is array (natural range <>) of stype_2b; type type_ch is array (natural range <>) of stype_2b; signal ls_array : type_ch_array(15 downto 0); signal ls_subarray : type_ch(3 downto 0); begin ls_array(3 downto 0) <= ls_subarray; end rtl; Can someone explain why the compiler complains about that assignment ? Rgds From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Tue, 24 Mar 2009 09:21:39 -0500 Date: Tue, 24 Mar 2009 14:21:36 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Assigning arrays of different types References: <22c179f9-706a-4ce1-96ea-3ebdeb8fb84e@k2g2000yql.googlegroups.com> In-Reply-To: <22c179f9-706a-4ce1-96ea-3ebdeb8fb84e@k2g2000yql.googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 77 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Oc3cDt8ZNnXFUdZONb7wSdVGVtR39hAg/9S4Ln5ufqtGI6yOMcuwRfAPvw36JE8sFYczuUpryBSDVPV!/79hyWwIwgAgWGM1e5NW9rWFq8pzkzNr+5h7WxK8qOqXCEX76VtNNu9fw8aHcpd7vJOOTanWN8q5!u6LZu9Bqi8Y= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:717 ALuPin@web.de wrote: > Hi, > > I am trying the following: > > > library ieee; > use ieee.std_logic_1164.all; > > entity test is > end test; > > architecture rtl of test is > > subtype stype_2b is std_logic_vector(1 downto 0); > type type_ch_array is array (natural range <>) of stype_2b; > type type_ch is array (natural range <>) of stype_2b; > > > signal ls_array : type_ch_array(15 downto 0); > > signal ls_subarray : type_ch(3 downto 0); > > begin > > ls_array(3 downto 0) <= ls_subarray; > > end rtl; > > Can someone explain why the compiler complains about > that assignment ? > > Rgds Yes, because you are trying to assign objects of two different types to each other, ahd VHDL is a strongly typed language. ls_array is of type type_chr_array ls_subarray is of type type_ch However they are "closely related types" because they are both arrays with the same number of dimensions, the same element types, and the same index type. So ls_array(3 downto 0) <= type_ch_array(ls_subarray); should work. The situation is exactly analogous to signed/unsigned/std_logic_vector. regards Alan P.S. If you really want to blow your mind try declaring a new integer type :-) -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!z15g2000yqm.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: Assigning arrays of different types Date: Tue, 24 Mar 2009 07:48:58 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <74b9baa6-7fad-459e-bed4-4dd53f6c44b6@z15g2000yqm.googlegroups.com> References: <22c179f9-706a-4ce1-96ea-3ebdeb8fb84e@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237906138 18905 127.0.0.1 (24 Mar 2009 14:48:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Mar 2009 14:48:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z15g2000yqm.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:718 Thank you, the explanation is very clear. Best regards From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j38g2000yqa.googlegroups.com!not-for-mail From: heilig.brian@gmail.com Newsgroups: comp.lang.vhdl Subject: Synthesis of Concurrent Statements for FIR Filter Date: Tue, 24 Mar 2009 08:46:27 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: NNTP-Posting-Host: 173.15.144.193 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237909587 30241 127.0.0.1 (24 Mar 2009 15:46:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Mar 2009 15:46:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j38g2000yqa.googlegroups.com; posting-host=173.15.144.193; posting-account=S2_qiQkAAAAZwWA6tvR91vdgATmaxVS5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:719 Dear List, I am trying to implement a 16-tap FIR Low-Pass Filter and have written the convolution in VHDL (of which I am a beginner). The input sequence 'x' is a 1-bit sequence of 1's and 0's. This is to be converted to 1's and -1's and convolved with the impulse sequence 'h'. My goal is for the convolution portion of the filter to be completely asynchronous and parallel. That is with each clock cycle 16 bits of the input sequence are convolved with the impulse response providing a single 12- bit output. Each element of the impulse response 'h' is a 10 bit signed integer. The input sequence 'x' is a known sequence and I am sure the output sequence 'y' will always fit into 12 bits. Here is the code: -- 16-tap FIR Low-Pass Filter Convolution Function -- -- -- When convolved with the code it will produce a maximum value that will fit into 12-bits library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity fir_lpf_conv is port ( x: in std_logic_vector(15 downto 0); y: out std_logic_vector(11 downto 0) ); end fir_lpf_conv; architecture fir_lpf_conv_arch of fir_lpf_conv is type coef_type is array(0 to 15) of integer range -511 to 511; constant h: coef_type := (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); signal mult: coef_type; signal sum: integer range -2047 to 2047; begin blabla: for i in x'range generate mult(i) <= h(i) when x(i)='1' else -h(i); end generate; sum <= mult(0) + mult(1) + mult(2) + mult(3) + mult(4) + mult(5) + mult(6) + mult(7) + mult(8) + mult(9) + mult(10) + mult(11) + mult(12) + mult(13) + mult(14) + mult(15); y <= std_logic_vector(to_signed(sum,12)); end fir_lpf_arch; I haven't simulated it yet, but I have a sneaky feeling it will not do what I expect. Even if it does do what I want it to then I'd like to understand why. The code should multiply each h element by the corresponding x element (with zeros converted to -1s) in parallel, AND THEN sum the result into sum AND THEN put the 'sum' result into 'y'. My use of AND THEN in that statement makes me think I need sequential code, that is the multiply should be done in parallel, and the sum should be done in parallel, but the sum should use the results of the multiply. However when I look at sequential code it is always clock or event driven and I don't think that's what I need. All this should be done in less than 1/2 clock cycle. I could see the compiler synthesizing the above code in two different ways: 1. Multiply in parallel AND THEN add the results in parallel. (this would be good) 2. Multiply in parallel and add in parallel. The parallel sum will use the previous values stored in 'mult', and possibly some updated values in 'mult' depending on the exact timing. (this would be bad) So my question is: if the code is correct, then what is the rule for synthesis? How does the compiler know that I want 'AND THEN' behavior? If the code is incorrect, what do I write to get 'AND THEN' behavior that is not clock driven? I also have a couple less important questions: Is there a better way to write my sum using a for loop? I couldn't get it to compile. I really don't need the intermediate signal 'sum'. I'd like to just sum into 'y' but I get a type error because the synthesizer doesn't know if the stuff on the right is signed or unsigned. Thank You! Brian From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z1g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Date: Tue, 24 Mar 2009 09:16:24 -0700 (PDT) Organization: http://groups.google.com Lines: 167 Message-ID: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237911384 1300 127.0.0.1 (24 Mar 2009 16:16:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Mar 2009 16:16:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z1g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:720 On 24 Mar, 15:46, heilig.br...@gmail.com wrote: > Dear List, > > I am trying to implement a 16-tap FIR Low-Pass Filter and have written > the convolution in VHDL (of which I am a beginner). The input sequence > 'x' is a 1-bit sequence of 1's and 0's. This is to be converted to 1's > and -1's and convolved with the impulse sequence 'h'. My goal is for > the convolution portion of the filter to be completely asynchronous > and parallel. That is with each clock cycle 16 bits of the input > sequence are convolved with the impulse response providing a single 12- > bit output. Each element of the impulse response 'h' is a 10 bit > signed integer. The input sequence 'x' is a known sequence and I am > sure the output sequence 'y' will always fit into 12 bits. > > Here is the code: > -- 16-tap FIR Low-Pass Filter Convolution Function > -- > -- > -- When convolved with the code it will produce a maximum value that > will fit into 12-bits > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.numeric_std.all; > > entity fir_lpf_conv is > =A0 =A0 =A0 =A0 port ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x: in std_logic_vector(15 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 y: out std_logic_vector(11 downto 0) > =A0 =A0 =A0 =A0 ); > end fir_lpf_conv; > > architecture fir_lpf_conv_arch of fir_lpf_conv is > =A0 =A0 =A0 =A0 type coef_type is array(0 to 15) of integer range -511 to= 511; > =A0 =A0 =A0 =A0 constant h: coef_type :=3D > (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); > =A0 =A0 =A0 =A0 signal mult: coef_type; > =A0 =A0 =A0 =A0 signal sum: integer range -2047 to 2047; > begin > =A0 =A0 =A0 =A0 blabla: for i in x'range generate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mult(i) <=3D h(i) when x(i)=3D'1' else -h= (i); > =A0 =A0 =A0 =A0 end generate; > =A0 =A0 =A0 =A0 sum <=3D mult(0) + mult(1) + mult(2) + mult(3) + mult(4) = + mult(5) + > mult(6) + mult(7) > =A0 =A0 =A0 =A0 =A0 =A0 =A0+ mult(8) + mult(9) + mult(10) + mult(11) + mu= lt(12) + mult(13) > + mult(14) + mult(15); > =A0 =A0 =A0 =A0 y <=3D std_logic_vector(to_signed(sum,12)); > end fir_lpf_arch; > > I haven't simulated it yet, but I have a sneaky feeling it will not do > what I expect. Even if it does do what I want it to then I'd like to > understand why. > > The code should multiply each h element by the corresponding x element > (with zeros converted to -1s) in parallel, AND THEN sum the result > into sum AND THEN put the 'sum' result into 'y'. My use of AND THEN in > that statement makes me think I need sequential code, that is the > multiply should be done in parallel, and the sum should be done in > parallel, but the sum should use the results of the multiply. However > when I look at sequential code it is always clock or event driven and > I don't think that's what I need. All this should be done in less than > 1/2 clock cycle. > > I could see the compiler synthesizing the above code in two different > ways: > > 1. Multiply in parallel AND THEN add the results in parallel. (this > would be good) > 2. Multiply in parallel and add in parallel. The parallel sum will use > the previous values stored in 'mult', and possibly some updated values > in 'mult' depending on the exact timing. (this would be bad) > > So my question is: if the code is correct, then what is the rule for > synthesis? How does the compiler know that I want 'AND THEN' behavior? > If the code is incorrect, what do I write to get 'AND THEN' behavior > that is not clock driven? > > I also have a couple less important questions: > Is there a better way to write my sum using a for loop? I couldn't get > it to compile. > I really don't need the intermediate signal 'sum'. I'd like to just > sum into 'y' but I get a type error because the synthesizer doesn't > know if the stuff on the right is signed or unsigned. > > Thank You! > Brian What you have written contains 0 multipliers, 15 x 2-1 muxes, no registers and a very long adder chain. It is very very unlikely that this will work. you will HAVE to break up the adder chain and pipeline it - 16 adds just isnt going to work without pipelining. You normally only want to add 2-3 numbers in a single clock cycle. You also say "x" is a 1 bit sequence? is it coming in serially? or is it really coming in as a bus like you've written. As it stands, it expects all the X bits to be there at the same time. I suggest you read up on digital design. this code is no way synthesisable. Here is a hint (Im going to assume that X is a synchronous input and not asynchronous like you said): It should give you a latency of 4 clock cycles: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fir_lpf_conv is port ( clk : in std_logic; x: in std_logic_vector(15 downto 0); y: out std_logic_vector(11 downto 0) ); end fir_lpf_conv; architecture fir_lpf_conv_arch of fir_lpf_conv is type coef_type is array(0 to 15) of integer range -511 to 511; constant h: coef_type :=3D (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); signal mult: coef_type; subtype sum_range_t is integer range -2047 to 2047; signal sum: sum_range_t; signal sum01 : sum_range_t; signal sum23 : sum_range_t; .....etc begin blabla: for i in x'range generate mult(i) <=3D h(i) when x(i)=3D'1' else -h(i); end generate; sum_proc : process(clk) variable sum_total : integer; begin if rising_edge(clk) then sum01 <=3D mult(0) + mult(1); sum23 <=3D mult(2) + mult(3); ........etc sum0123 <=3D sum01 + sum23; .......etc sum_total :=3D sum0to7 + sum8to15; y <=3D std_logic_vector( to_signed( sum_total, 12) ); end if; end process; end fir_lpf_arch; Also - delete std_logic_arith from the code. It clashes with numeric_std. always use the numeric_std package (which you have). From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e38g2000yqa.googlegroups.com!not-for-mail From: heilig.brian@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Date: Tue, 24 Mar 2009 09:53:51 -0700 (PDT) Organization: http://groups.google.com Lines: 108 Message-ID: <7e51f2f0-31cb-4eac-950d-e64a58ef5bfb@e38g2000yqa.googlegroups.com> References: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> NNTP-Posting-Host: 173.15.144.193 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237913631 8524 127.0.0.1 (24 Mar 2009 16:53:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Mar 2009 16:53:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e38g2000yqa.googlegroups.com; posting-host=173.15.144.193; posting-account=S2_qiQkAAAAZwWA6tvR91vdgATmaxVS5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:721 > What you have written contains 0 multipliers, The following line... mult(i) <=3D h(i) when x(i)=3D'1' else -h(i); ...is a 1 bit multiplier where a 1 means 'multiply by 1' and a 0 means 'multiply by -1'. When x(i)=3D'1' then mult(i) <=3D h(i) * 1, else mult(i) <=3D h(i) * -1. > 15 x 2-1 muxes, no > registers and a very long adder chain. It is very very unlikely that > this will work. you will HAVE to break up the adder chain and pipeline > it - 16 adds just isnt going to work without pipelining. You normally > only want to add 2-3 numbers in a single clock cycle. Because of the propagation delay? The Quartus II software I'm using has a parallel_add megafunction (if you're not familiar with Quartus II a megafunction is like a parameterized logical element) that can add up to 128 32-bit integers in parallel! Well, at least that's what it says. > You also say "x" is a 1 bit sequence? is it coming in serially? or is > it really coming in as a bus like you've written. As it stands, it > expects all the X bits to be there at the same time. It is a 1-bit sequence that is initially serial but through a series of external d flip flops I am converting it to 16 bits in parallel. However each of these bits represents one element of the x sequence. It is not converted to a 16 bit word. > I suggest you read up on digital design. this code is no way > synthesisable. Ouch. Well you caught me. I bought "Circuit Design with VHDL" a few days ago and it is on its way. I thought, "How hard can this be?" > Here is a hint (Im going to assume that X is a > synchronous input and not asynchronous like you said): X is a synchronous input. The problem is I could draw a working logic diagram that would perform the 16 1-bit multiplies in parallel and then sum all the results in parallel. In fact I started off this way but then figured it's a good time to learn VHDL. So if I know that it can be represented as a bunch of logic gates then the problem is to write VHDL code that will synthesize those gates for me. > It should give you a latency of 4 clock cycles: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity fir_lpf_conv is > =A0 =A0 =A0 =A0 port ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk : in std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x: in std_logic_vector(15 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 y: out std_logic_vector(11 downto 0) > =A0 =A0 =A0 =A0 ); > end fir_lpf_conv; > > architecture fir_lpf_conv_arch of fir_lpf_conv is > =A0 =A0 =A0 =A0 type coef_type is array(0 to 15) of integer range -511 to= 511; > =A0 =A0 =A0 =A0 constant h: coef_type :=3D > (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); > =A0 =A0 =A0 =A0 signal mult: coef_type; > > =A0 =A0 =A0 =A0 subtype sum_range_t is integer range -2047 to 2047; > > =A0 =A0 =A0 =A0 signal sum: sum_range_t; > > =A0 =A0 =A0 =A0 signal sum01 : sum_range_t; > =A0 =A0 =A0 =A0 signal sum23 : sum_range_t; > =A0 =A0 =A0 =A0 .....etc > begin > =A0 =A0 =A0 =A0 blabla: for i in x'range generate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mult(i) <=3D h(i) when x(i)=3D'1' else -h= (i); > =A0 =A0 =A0 =A0 end generate; > > =A0 =A0 =A0 =A0 sum_proc : process(clk) > =A0 =A0 =A0 =A0 =A0 variable sum_total : integer; > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 if rising_edge(clk) then > > =A0 =A0 =A0 =A0 =A0 =A0 sum01 =A0 <=3D mult(0) + mult(1); > =A0 =A0 =A0 =A0 =A0 =A0 sum23 =A0 <=3D mult(2) + mult(3); > =A0 =A0 =A0 =A0 =A0 =A0 ........etc > > =A0 =A0 =A0 =A0 =A0 =A0 sum0123 <=3D sum01 + sum23; > =A0 =A0 =A0 =A0 =A0 =A0 .......etc > > =A0 =A0 =A0 =A0 =A0 =A0 sum_total :=3D sum0to7 + sum8to15; > =A0 =A0 =A0 =A0 =A0 =A0 y =A0 =A0 =A0 =A0 <=3D std_logic_vector( to_signe= d( sum_total, > 12) ); > > =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > end fir_lpf_arch; > > Also - delete std_logic_arith from the code. It clashes with > numeric_std. always use the numeric_std package (which you have). Ok. Thanks for the help. From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!d19g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Date: Wed, 25 Mar 2009 02:43:46 -0700 (PDT) Organization: http://groups.google.com Lines: 124 Message-ID: References: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> <7e51f2f0-31cb-4eac-950d-e64a58ef5bfb@e38g2000yqa.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237974226 10782 127.0.0.1 (25 Mar 2009 09:43:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 09:43:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:722 On 24 Mar, 16:53, heilig.br...@gmail.com wrote: > > What you have written contains 0 multipliers, > > The following line... > > mult(i) <= h(i) when x(i)='1' else -h(i); > > ...is a 1 bit multiplier where a 1 means 'multiply by 1' and a 0 means > 'multiply by -1'. When x(i)='1' then mult(i) <= h(i) * 1, else mult(i) > <= h(i) * -1. Thats probably the way you intend it, but in reality you've just written a mux with 2 constant inputs that are selected via the appropriate bit on X. on looking at the RTL viewer, that constants you have chosen make it even less complicated, making each input input just a function of X. You could completly change the constants, and you will never get a hardware multiply, you will always get a mux. > > > 15 x 2-1 muxes, no > > registers and a very long adder chain. It is very very unlikely that > > this will work. you will HAVE to break up the adder chain and pipeline > > it - 16 adds just isnt going to work without pipelining. You normally > > only want to add 2-3 numbers in a single clock cycle. > > Because of the propagation delay? The Quartus II software I'm using > has a parallel_add megafunction (if you're not familiar with Quartus > II a megafunction is like a parameterized logical element) that can > add up to 128 32-bit integers in parallel! Well, at least that's what > it says. Whats wrong with a propgation delay? FPGAs are great for massive parrallel processing, but there is normally a latency involved. Pipelining still means you can get 1 result/clock cycle, but you have to wait n clock cycles of latency before the first result arrives. n is ALWAYS fixed, so you know when the output is valid, and from then on every clock cycle yields a valid result. I fear if latency is your bigest worry, you're coming at FPGA design from the wrong angle. Yes altera do provide a parallel_add megafunction, but it looks horrible to use (the data input is based on their own 2d-array of std_logic for a start, not the best way to encourage use!). But I could do a parallel add without their mega function, and add 256x64 bit numbers in parallel if I want, just using the "+" sign. Doesnt mean it'll make good hardware/firmware though. You'll also add that there is a "Pipeline" parameter on the parallel add megafunction. ok, Ive compiled some stuff, and heres the results: As a quick reference, I ran your initial massive add through timequest, on a stratix 2 (putting registers in at the mux stage and the output, so timequest could actually work) - FMax = 94Mhz Doing the massive add with a parallel add component, 0 latency FMax = 200MHz parallel adder, pipeline length of 4, FMax = 320Mhz Pipelining it the way I did in previous post : FMax = 360MHz. remember this has been done on a large device with no additional logic, so FMax reports may be artificially high. But I know which method Id rather use!. to get hold of the parallel add, you have to actually instatiate it. Converting the data input into the write format is a bit of an arse: signal data : altera_mf_logic_2D(15 downto 0, 9 downto 0); begin i_gen : for i in data'range(1) generate j_gen :for j in data'range(2) generate data(i, j) <= std_logic_vector( to_signed(mult(i), 10) )(j); end generate j_gen; end generate i_gen; par_add : parallel_add generic map ( width => 10, size => 16, widthr => 12, pipeline => 0, representation => "SIGNED" ) port map ( data => data, result => result ); > > > You also say "x" is a 1 bit sequence? is it coming in serially? or is > > it really coming in as a bus like you've written. As it stands, it > > expects all the X bits to be there at the same time. > > It is a 1-bit sequence that is initially serial but through a series > of external d flip flops I am converting it to 16 bits in parallel. > However each of these bits represents one element of the x sequence. > It is not converted to a 16 bit word. Well, you have x coming in as a 16 bit bus. And you have 16 "multiplies" in parallel. Another question - how fast is the serial bus? 16x the main clock speed? if it isnt, how do you know when any of the X bit are valid? > > Here is a hint (Im going to assume that X is a > > synchronous input and not asynchronous like you said): > > X is a synchronous input. The problem is I could draw a working logic > diagram that would perform the 16 1-bit multiplies in parallel and > then sum all the results in parallel. In fact I started off this way > but then figured it's a good time to learn VHDL. So if I know that it > can be represented as a bunch of logic gates then the problem is to > write VHDL code that will synthesize those gates for me. But Id recommend you do it that way, especially as a VHDL beginner. VHDL is a description language, not a programming language. It is meant for describing digital hardware. You can write whatever you want in VHDL (to a point), and it may simulate how you intend giving the results you wanted in the way you specified, but that doesnt mean its any good as a hardware description. From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: heilig.brian@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Date: Wed, 25 Mar 2009 04:47:44 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: <7bbefa01-5797-44d3-8b13-4a158044418f@k2g2000yql.googlegroups.com> References: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> <7e51f2f0-31cb-4eac-950d-e64a58ef5bfb@e38g2000yqa.googlegroups.com> NNTP-Posting-Host: 98.110.65.205 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237981664 2497 127.0.0.1 (25 Mar 2009 11:47:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 11:47:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=98.110.65.205; posting-account=S2_qiQkAAAAZwWA6tvR91vdgATmaxVS5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:723 > Thats probably the way you intend it, but in reality you've just > written a mux with 2 constant inputs that are selected via the > appropriate bit on X. on looking at the RTL viewer, that constants you > have chosen make it even less complicated, making each input input > just a function of X. You could completly change the constants, and > you will never get a hardware multiply, you will always get a mux. I think this is good. It is equivalent to a multiply by 1 or -1, right? > Whats wrong with a propgation delay? FPGAs are great for massive > parrallel processing, but there is normally a latency involved. > Pipelining still means you can get 1 result/clock cycle, but you have > to wait n clock cycles of latency before the first result arrives. n > is ALWAYS fixed, so you know when the output is valid, and from then > on every clock cycle yields a valid result. I fear if latency is your > bigest worry, you're coming at FPGA design from the wrong angle. You are right. Latency is hardly a concern. I guess my line of thinking was that I could imagine the logic diagram, now if I could just write the VHDL to make that logic diagram a reality. But I wasn't asking about throughput delay, which I think is (or I'll define as) the time through the entire device. Rather I was asking about the delay between when the x elements are available on the rising edge of the clock, to when the next y outputs are available to be sampled. If this time is greater than half a clock cycle then I will get garbage out. I think you summarized this in your discussion below determining FMax. > ok, Ive compiled some stuff, and heres the results: Again, thank you for your help. > As a quick reference, I ran your initial massive add through > timequest, on a stratix 2 (putting registers in at the mux stage and > the output, so timequest could actually work) - FMax = 94Mhz > Doing the massive add with a parallel add component, 0 latency FMax = > 200MHz > parallel adder, pipeline length of 4, FMax = 320Mhz > Pipelining it the way I did in previous post : FMax = 360MHz. I see. My sample clock is 20 MHz so that's ok. But I see your point and will add pipelining. > Well, you have x coming in as a 16 bit bus. And you have 16 > "multiplies" in parallel. > Another question - how fast is the serial bus? 16x the main clock > speed? if it isnt, how do you know when any of the X bit are valid? The serial bus is 20 MHz as is the sample clock. Every time a new x bit is shifted in I process the entire 16-bit sequence again. So bits 0-14 in the last interval become bits 1-15 in this one. > But Id recommend you do it that way, especially as a VHDL beginner. > VHDL is a description language, not a programming language. It is > meant for describing digital hardware. You can write whatever you want > in VHDL (to a point), and it may simulate how you intend giving the > results you wanted in the way you specified, but that doesnt mean its > any good as a hardware description. You caught me again. I am a programmer with some hardware experience. This small exercise is only the beginning, I'll soon need to know VHDL well. So I guess I'll start reading! Thanks, Brian From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o11g2000yql.googlegroups.com!not-for-mail From: cristian_ciressan@yahoo.com Newsgroups: comp.lang.vhdl Subject: Re: can I specify a time-varying clock? Date: Wed, 25 Mar 2009 06:47:36 -0700 (PDT) Organization: http://groups.google.com Lines: 105 Message-ID: References: <1pbhs4lecq2832moevflu82n3kt7ijt226@4ax.com> NNTP-Posting-Host: 83.173.237.218 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237988856 25581 127.0.0.1 (25 Mar 2009 13:47:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 13:47:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yql.googlegroups.com; posting-host=83.173.237.218; posting-account=xrAy7AoAAAAUbaIuIKKy7IV_wOmLI0nj User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:724 On 24 mar, 11:32, Gerhard Hoffmann wrote: > On Sat, 21 Mar 2009 09:41:06 -0700 (PDT), ed...@hotmail.com wrote: > >I need to simulate a circuit that uses a clock that varies over time, > >e.g. starts out nominal at, say 80 MHz, and then, gradually slows down > >to 2% below that center frequency, then gradually increases in > >frequency to 2% above that frequency, then comes back to the nominal > >80 MHz rate in a period of, say, 1/60 second. > You probably need this feature for a spread-spectrum clocking simulation. Here is another example of clock you may consider using: use generics to provide the values for: SSC_ENABLE : boolean := FALSE; SSC_PERIOD : real := 33333000.0; -- expressed in [ps] (this would be 1/60 expressed in [ps] in your case) use the following procedure to compute the and parameters: procedure ComputeIterationsAndDelta(variable Iterations: out integer; variable Delta: out real) is variable T_start : real; -- start period variable T_stop : real; -- stop period variable Iterations_real : real; begin -- replace values of T_start and T_stop as required by you freq. modulation specifications ... -- T_start = 4000 ps; (12500 ps in your case) -- T_stop = T_start + Iterations*Delta = 4020 ps; because it is modulated 0.5% (2% in your case 12750 ps) -- where is to be determined and is also to be determined -- at this point we know = 20 ps! (250 ps for you) -- we also know that : -- T_start + (T_start + Delta) + ((T_start + 2*Delta) + .... + ((T_start + Iterations*Delta) = SSC_PERIOD/2 -- or: 2*(Iterations + 1)*T_start + Iterations*(Iterations + 1)*Delta = SSC_PERIOD -- or: 8020[ps]*(Iterations + 1) = SSC_PERIOD -- !!!!! You should change accordingly the values below) Iterations_real := (SSC_PERIOD - 8020.0) / (8020.0); Delta := 20.0e-12 / Iterations_real; Iterations := integer(Iterations_real); end procedure; and the code to have either a SSC modulation or a normal clock. The code is very simple. SSC_GENERATE: if (SSC_ENABLE = TRUE) generate -- Generate SSC Reference Clock input (250MHz) process variable Iterations : integer; variable Delta : real; variable it : integer; variable sign : integer; variable my_time : time; begin ComputeIterationsAndDelta(Iterations, Delta); it := 0; sign := +1; loop my_time := REFCLK_PERIOD + (real(it) * Delta)*1 sec; refclk_n_r <= '1'; wait for my_time/2; refclk_n_r <= '0'; wait for my_time/2; if (it = Iterations) then sign := -1; elsif (it = 0) then sign := +1; end if; it := it + sign*1; end loop; end process; end generate SSC_GENERATE; NO_SSC_GENERATE: if (SSC_ENABLE = FALSE) generate -- Generate Reference Clock input (250MHz) process begin refclk_n_r <= '1'; wait for REFCLK_PERIOD/2; refclk_n_r <= '0'; wait for REFCLK_PERIOD/2; end process; end generate; refclk_p_r <= not refclk_n_r; Good luck! Cristian From newsfish@newsfish Wed Aug 19 13:23:53 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s38g2000prg.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Wait statement error Date: Wed, 25 Mar 2009 08:06:40 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237993601 9342 127.0.0.1 (25 Mar 2009 15:06:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 15:06:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s38g2000prg.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:725 I'm starting to use ModelSim (the version included with Quartus II) for my simulations. I've been a long time user of the waveform simulator in Quartus but I thought I should stop using stone-knives and bear-skins. One problem I've hit early on: I have the following process in my testbench: DACclock : PROCESS BEGIN wait for 4 ns; DAC_clk <= not DAC_clk; end PROCESS DACclock; Seems pretty straightforward eh? ModelSim likes it and produces the clock waveform that I would expect. Quartus however complains: Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72): Wait Statement must contain condition clause with UNTIL keyword Huh? Shannon From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z1g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 08:26:10 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <9183fe0d-786d-45b8-9a7f-4579bb68eef1@z1g2000yqn.googlegroups.com> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237994771 12294 127.0.0.1 (25 Mar 2009 15:26:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 15:26:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z1g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:726 On 25 Mar, 15:06, Shannon wrote: > I'm starting to use ModelSim (the version included with Quartus II) > for my simulations. =A0I've been a long time user of the waveform > simulator in Quartus but I thought I should stop using stone-knives > and bear-skins. > > One problem I've hit early on: I have the following process in my > testbench: > > DACclock : PROCESS > BEGIN > =A0 =A0wait for 4 ns; DAC_clk =A0<=3D not DAC_clk; > end PROCESS DACclock; > > Seems pretty straightforward eh? =A0ModelSim likes it and produces the > clock waveform that I would expect. =A0Quartus however complains: > > Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72): > Wait Statement must contain condition clause with UNTIL keyword > > Huh? > > Shannon Id raise it as an Issue with Altera, but given that they include Modelsim AE, they'll probably just tell you to use that instead. From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i28g2000prd.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 08:33:26 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> NNTP-Posting-Host: 67.169.206.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1237995206 13773 127.0.0.1 (25 Mar 2009 15:33:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 15:33:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000prd.googlegroups.com; posting-host=67.169.206.73; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:727 Shannon Is this from the Quartus synthesis tool? You only need to tell the synthesis tool about your design. There may be a place to mark the file as a testbench file - make sure to do this as synthesis tools don't like many things that are part of the testbench. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!209.197.12.246.MISMATCH!nx02.iad.newshosting.com!newshosting.com!198.186.194.250.MISMATCH!news-xxxfer.readnews.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!d19g2000prh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 09:38:08 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1237999088 26289 127.0.0.1 (25 Mar 2009 16:38:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 16:38:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000prh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:728 On Mar 25, 8:33=A0am, JimLewis wrote: > Shannon > Is this from the Quartus synthesis tool? =A0You only need to > tell the synthesis tool about your design. =A0There may be a > place to mark the file as a testbench file - make sure to > do this as synthesis tools don't like many things that are > part of the testbench. > > Cheers, > Jim > SynthWorks VHDL Training It was from the "Analysis & Elaboration" tool. But I think I get the picture now. When I tried to archive the whole project it said that it had to do "Analysis & Elaboration" first. I just clicked on "yes". I don't think it understands that it is a testbench project and Elaboration is silly. (At least I think that is what is going on.) From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 10:00:11 -0700 Lines: 14 Message-ID: <72v68tFs95taU1@mid.individual.net> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net F8VP7p5cvyF1phJ0EIxSWAXLcT1bc6gRrx8bv/wUDobFkvn6Jz Cancel-Lock: sha1:wIUu0AOV69jyNu3EZ+K8QTv1b44= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:729 Shannon wrote: > It was from the "Analysis & Elaboration" tool. But I think I get the > picture now. When I tried to archive the whole project it said that > it had to do "Analysis & Elaboration" first. I just clicked on > "yes". I don't think it understands that it is a testbench project > and Elaboration is silly. (At least I think that is what is going on.) Quartus only knows about vhdl for *synthesis*. Quartus cannot use vhdl code for simulation. The quartus sim tool only knows about altera netlists and waveforms. For a vhdl testbench, use modelsim. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!news.glorb.com!news2.glorb.com!postnews.google.com!y6g2000prf.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 10:40:02 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <0134de2c-0538-44b0-8cc4-5441d2d4a1e4@y6g2000prf.googlegroups.com> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> <72v68tFs95taU1@mid.individual.net> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238002868 7355 127.0.0.1 (25 Mar 2009 17:41:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 17:41:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y6g2000prf.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:730 On Mar 25, 10:00=A0am, Mike Treseler wrote: > Shannon wrote: > > It was from the "Analysis & Elaboration" tool. =A0But I think I get the > > picture now. =A0When I tried to archive the whole project it said that > > it had to do "Analysis & Elaboration" first. =A0I just clicked on > > "yes". =A0I don't think it understands that it is a testbench project > > and Elaboration is silly. =A0(At least I think that is what is going on= .) > > Quartus only knows about vhdl for *synthesis*. > Quartus cannot use vhdl code for simulation. > The quartus sim tool only knows about altera netlists and waveforms. > For a vhdl testbench, use modelsim. > > =A0 =A0 =A0-- Mike Treseler Agreed. Next step is get get ModelSim to understand my memory initialization file. Shannon From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.z74.net!news.z74.net!news.glorb.com!news2.glorb.com!postnews.google.com!n7g2000prc.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 10:41:55 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <18f3d268-85c1-4ce6-a44a-5534f9ebefd1@n7g2000prc.googlegroups.com> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> <72v68tFs95taU1@mid.individual.net> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238002915 7486 127.0.0.1 (25 Mar 2009 17:41:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Mar 2009 17:41:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000prc.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:731 On Mar 25, 10:00=A0am, Mike Treseler wrote: > Shannon wrote: > > It was from the "Analysis & Elaboration" tool. =A0But I think I get the > > picture now. =A0When I tried to archive the whole project it said that > > it had to do "Analysis & Elaboration" first. =A0I just clicked on > > "yes". =A0I don't think it understands that it is a testbench project > > and Elaboration is silly. =A0(At least I think that is what is going on= .) > > Quartus only knows about vhdl for *synthesis*. > Quartus cannot use vhdl code for simulation. > The quartus sim tool only knows about altera netlists and waveforms. > For a vhdl testbench, use modelsim. > > =A0 =A0 =A0-- Mike Treseler Agreed. Next step is get get ModelSim to understand my memory initialization file. Shannon From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Wait statement error Date: Wed, 25 Mar 2009 11:07:39 -0700 Lines: 8 Message-ID: <72va7cFsc8fjU1@mid.individual.net> References: <68c661cc-cbb9-4562-8440-f67c5d537971@s38g2000prg.googlegroups.com> <8243c15a-2e78-4864-81e2-566d7671056a@d19g2000prh.googlegroups.com> <72v68tFs95taU1@mid.individual.net> <18f3d268-85c1-4ce6-a44a-5534f9ebefd1@n7g2000prc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 8+RlcSaqNFAXMZWqnGjmAQ68ApU2tNcdm1v1oAKn06NhEenykp Cancel-Lock: sha1:xZsDgqTtuyJJoLOSj0r7NH4zr4o= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <18f3d268-85c1-4ce6-a44a-5534f9ebefd1@n7g2000prc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:732 Shannon wrote: > Next step is get get ModelSim to understand my memory initialization > file. I would make that a vhdl constant array. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Examples of issues with std_logic_arith Date: Thu, 26 Mar 2009 11:17:20 +0100 Lines: 28 Message-ID: <73131gFslqtrU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net OkGnTauPNg/0VsBmNuj7XwO4dIXmI5zksLWurGNhwKE16i9D+z Cancel-Lock: sha1:T2WUSynT092yzVcxgTM1bKbFdxY= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) Xref: news.eternal-september.org comp.lang.vhdl:733 Hi *, I know the whole numeric_std vs. std_logic_arith issue has been covered several times before here, but please bear with me for a second :) Does anyone of you have any concrete examples of problems that came up because std_logic_arith was used? Code examples that behave differently in different simulators/synthesis tools maybe? When I look at the discussions about this issue in the past, it's always "std_logic_arith should not be used, because it's not a standard and might be implemented differently in different tools". But I've never seen actual examples or heard of a problems arising from use of std_logic_arith. I personally have always used numeric_std, because that's the way I learned it. But when I talk about this with colleagues, the "use it because it's a standard"-argument never beats the "I've been using std_logic_arith forever, never had the slightest problems and don't see why I should ever change anything"-argument. So I'd be glad if maybe someone could share some "war stories" or something. :) cu, Sean -- Replace MONTH with the three-letter-abbreviation for the current month. Simple, eh? From newsfish@newsfish Wed Aug 19 13:23:54 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 26 Mar 2009 08:44:51 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Thu, 26 Mar 2009 13:43:01 +0000 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <73131gFslqtrU1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 63 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-qUoR2e1QyTEhdyG6GWVXAYYZITp84YYaToru3RXSCNGEwErwLwsNJBDE4A69N/bzo46aYFzcBxTkY2E!wQYlm+g8OVi2BkgL1XJ5z0FM4PKPGJJafTsGG+CuFOARgHJcpjzyRX0/lGHyaHCzOHBJdFbZha9c!T6lW X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3776 Xref: news.eternal-september.org comp.lang.vhdl:734 On Thu, 26 Mar 2009 11:17:20 +0100, Sean Durkin wrote: >I know the whole numeric_std vs. std_logic_arith issue has been covered >several times before here, but please bear with me for a second :) > >Does anyone of you have any concrete examples of problems that came up >because std_logic_arith was used? Code examples that behave differently >in different simulators/synthesis tools maybe? I don't have any specific examples; I have better things to do with my time than to hunt bugs in a package that I never intend to use. But here are the things that matter to me: 1) *If* there are any errors in either package, then at least with numeric_std there is formal agreement about what the right behaviour should be, so the presence or absence of a bug is unambiguous. 2) std_logic_arith is fairly incomplete, although I'm sure some tools have filled in the gaps. numeric_std has a complete repertoire of operators that I can trust. 3) The function names in std_logic_arith are unhelpful. How am I supposed to remember whether CONV_INTEGER converts FROM or TO integer? Similar gripe with SXT. There is almost no cost to changing over; any legitimate design using std_logic_arith can be ported to numeric_std merely by allowing your compiler to find the missing function names, and appropriately patching any calls to CONV_* and SXT (there shouldn't be very many of those, in well-written code). >I personally have always used numeric_std, because that's the way I >learned it. But when I talk about this with colleagues, the "use it >because it's a standard"-argument never beats the "I've been using >std_logic_arith forever, never had the slightest problems and don't see >why I should ever change anything"-argument. So, yes, they can coexist if you're willing for YOUR PROJECT and YOUR PRODUCT to carry the risk of using a non-standard, potentially unsupported package. Are you OK with that? How about your project manager? The argument from inertia is the same one that left some folk coding unproductively in assembler when smart people were using high-level languages. >So I'd be glad if maybe someone could share some "war stories" or >something. :) Sorry I can't help, but life's too short :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:55 2009 Date: Fri, 27 Mar 2009 11:03:16 +1100 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith References: <73131gFslqtrU1@mid.individual.net> In-Reply-To: <73131gFslqtrU1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 123.243.86.135 X-Original-NNTP-Posting-Host: 123.243.86.135 Message-ID: <49cc1752$1@dnews.tpgi.com.au> X-Trace: dnews.tpgi.com.au!tpg.com.au 1238112082 123.243.86.135 (27 Mar 2009 11:01:22 +1100) Lines: 28 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!newsfeed.yul.equant.net!news-peer1.sprintlink.net!news-syd!dnews.tpgi.com.au!tpg.com.au!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:735 Sean Durkin wrote: > But I've never seen actual examples or > heard of a problems arising from use of std_logic_arith. IIUC, it's the same argument one can use for or against _any_ standard programming library. Using any non-ratified standard library, you run the risk of everything you mentioned. The bottom line - it's less portable. And whilst I can envisage plenty of future maintainers of your code converting from a non-standard library to a standard library, I can't imagine many (worth their salt) converting the other way around (even if they personally prefer the non-standard library, they should get their bum well and truly kicked for actually changing already-compliant code). Having said that, the commercial reality (IMHO) is that your code will be used in a handful (if not just one) of projects, same vendor, same tools, and if it works for you now, it'll probably continue to do so long after your legacy is completely forgotten. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Wed Aug 19 13:23:55 2009 Date: Fri, 27 Mar 2009 11:16:14 +1100 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith References: <73131gFslqtrU1@mid.individual.net> <49cc1752$1@dnews.tpgi.com.au> In-Reply-To: <49cc1752$1@dnews.tpgi.com.au> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 123.243.86.135 X-Original-NNTP-Posting-Host: 123.243.86.135 Message-ID: <49cc1a5d$1@dnews.tpgi.com.au> X-Trace: dnews.tpgi.com.au!tpg.com.au 1238112861 123.243.86.135 (27 Mar 2009 11:14:21 +1100) Lines: 33 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad.newshosting.com!newshosting.com!novia!newsfeed.yul.equant.net!news-peer1.sprintlink.net!news-syd!dnews.tpgi.com.au!tpg.com.au!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:736 Mark McDougall wrote: > (even if they personally > prefer the non-standard library, they should get their bum well and truly > kicked for actually changing already-compliant code). Further on this note... I come from a software engineering background, and have worked on a whole host of systems ranging from embedded micro through PC platform up to even mainframe. One thing I've learned "when in Rome..." There was a contract I worked on a while back where I was provided with a copy of the company's "C coding standards". Trouble was, I was adapting existing code (from Microsoft IIRC) for their purpose, and attempting to adhere to their standards would've made an absolute mess of the source code. I advised them that I was happy to follow their standards for any "external code", but any modifications/additions to the Microsoft code were going to be consistent with the Microsoft coding style. They agreed to that much at least. I admit that traditionally I've been using std_logic_arith myself - only because I cut my teeth on it before I "knew any better". Lately I've made a more concerted effort, and am slowly converting my code base to use numeric_std whenever I need to make modifications to a file. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 11:19:17 +0000 Organization: TRW Conekt Lines: 32 Message-ID: References: <73131gFslqtrU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 3Puo4kXo9xsE0J8DPlvo7QUl/AlVUFqvEyR6hLlnuhH/vr0Do= Cancel-Lock: sha1:jarGPDB86vIkSVN1pfGX+PDG0/k= sha1:agC6ZOJf1Qo7JQd2wC4gH1vrIbo= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:737 Sean Durkin writes: > Hi *, > > I know the whole numeric_std vs. std_logic_arith issue has been covered > several times before here, but please bear with me for a second :) > > Does anyone of you have any concrete examples of problems that came up > because std_logic_arith was used? Code examples that behave differently > in different simulators/synthesis tools maybe? When I look at the > discussions about this issue in the past, it's always "std_logic_arith > should not be used, because it's not a standard and might be implemented > differently in different tools". But I've never seen actual examples or > heard of a problems arising from use of std_logic_arith. IIRC (and it was a long time ago), I spoke to someone who got weird results from comparisons of different length vectors. Instead of them being sign or zero extended (depending on type) the shorter vector was always treated as less than the longer one (eg 0111 < 000001). Or something like that, I don't recall the details. IIRC the code worked fine once he changed to numeric_std. Sorry, that's a bit of a "third-hand" story, but it's where I first got told "use numeric_std"! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e18g2000yqo.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 05:10:47 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <73131gFslqtrU1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238155847 17491 127.0.0.1 (27 Mar 2009 12:10:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 12:10:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e18g2000yqo.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:738 Heres an interesting point. consider this: architecture sim of play_tb is constant ZERO_8 : std_logic_vector := x"00"; constant ZERO_9 : std_logic_vector := b"0_0000_0000"; begin process begin echo(boolean'image(ZERO_8 = ZERO_9) & LF); wait; end process; end architecture sim; if std_logic_unsigned is not included, this returns false (unmatched array lengths) if it is included, it returns true. Using numeric std (and not the synopsys packages) would allow this to always be false (as it possibly should). Basically the arith/unsigned/ signed packages give meaning to std_logic_vectors, when they really shouldnt. From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: mightycatniyander@gmail.com Newsgroups: comp.lang.vhdl Subject: Correct VHDL? Date: Fri, 27 Mar 2009 06:12:24 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: NNTP-Posting-Host: 59.95.118.128 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238159544 29529 127.0.0.1 (27 Mar 2009 13:12:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 13:12:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=59.95.118.128; posting-account=W-Z0OQoAAABTlmAqUoVxZybmc-jZmCQr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:739 Hello, I want to implement the following C++ code in VHDL double t1 = u1 * ip1[i1] - u2 * op1[i1]; double t2 = u1 * op1[i1] + u2 * ip1[i1]; ip1[i1] = ip3[i] - t1; op1[i1] = ip4[i] - t2; ip3[i] += t1; ip4[i] += t2; i am not sure if this is correct but i have tried and came up with the following VHDL entity test is port( clk : in std_logic; ip1 : in std_logic_vector(7 downto 0); op1 : in std_logic_vector(7 downto 0); ip3 : in std_logic_vector(7 downto 0); ip4 : in std_logic_vector(7 downto 0); U1 : in std_logic_vector(7 downto 0); U2 : in std_logic_vector(7 downto 0); ip1o : out std_logic_vector(15 downto 0); op1o : out std_logic_vector(15 downto 0); ip3o : out std_logic_vector(15 downto 0); ip4o : out std_logic_vector(15 downto 0)); end test; architecture Behavioral of test is signal T1 : std_logic_vector(15 downto 0); signal T2 : std_logic_vector(15 downto 0); begin process(clk) begin T1 <= (U1 * ip1) - (U2 * op1); T2 <= (U1 * op1) + (U2 * ip1); ip1o <= ip3 - T1; op1o <= ip4 - T2; ip3o <= ip3 + T1; ip4o <= ip4 + T2; end process; end Behavioral; i would really appreciate if some one can tell me is it correct, if not how can it be implemented correctly in VHDL? further i want to implement this code in a sort of variable loop, i.e. depending on the values of the output the length of the loop will change. For example consider the following c++ code for (int a=0; a<=100; a++) { i1 = i2; i2 *= 2; for (int i=i1; i<=k; i++) { //some code here; } } could this be implemented in VHDL? Thanks From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 07:45:59 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> References: <73131gFslqtrU1@mid.individual.net> NNTP-Posting-Host: 217.171.129.69 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238165160 8525 127.0.0.1 (27 Mar 2009 14:46:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 14:46:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=217.171.129.69; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:740 On 26 Mar, 10:17, Sean Durkin wrote: > Hi *, > > I know the whole numeric_std vs. std_logic_arith issue has been covered > several times before here, but please bear with me for a second :) The critical point to get is that std_logic_vector is a string type! so expect it to behave as such sometimes, including having a greater than 32 bit length. numeric standard_does a string->number->string with number being limited to 32 bits. std_logic_artih does not do this conversion, an all things remain as strings with a limited character subset. If you go for more than addition and subtraction, then things get less supported in logic arith. If you understand your logic, then this is no problem to write your own boole multiplier etc. With numeric std, full arithmetic is generally supported to 32 bit resolution with reduction of stuck at 1 or 0 inputs. You can't easily write a 64 bit cpu in numeric std. cheers jacko From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!f37g2000vbf.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 08:01:06 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238166067 11511 127.0.0.1 (27 Mar 2009 15:01:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 15:01:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f37g2000vbf.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: news.eternal-september.org comp.lang.vhdl:741 On Mar 27, 10:45=A0am, Jacko wrote: > > With numeric std, full arithmetic is generally supported to 32 bit > resolution with reduction of stuck at 1 or 0 inputs. You can't easily > write a 64 bit cpu in numeric std. > > cheers jacko I just looked at the source for numeric_std and how it implements addition, subtraction, multiplication, and division. As far as my quick perusal reveals, everything is coded at the bit level and has no constraints other than the LENGTH of the unsigned/signed numbers have to be integers, so it looks like it could support (roughly) numbers up to 2^31 bits in length. Can you give a more precise description of where you ran into this issue - I'm curious to know if I mis-read the code? - Kenn From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.k-dsl.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 27 Mar 2009 10:09:04 -0500 Date: Fri, 27 Mar 2009 15:09:12 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> In-Reply-To: <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 48 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-YHFzig3qzc2qHqxhwR64Ph/vSBFBY8ODxNGXXGNNfeaxRfn8SNCuO8wMheC09J8MseTzS44pJ1BUHYG!cYxbGV2vyDvVT95IpuDiDsO36RWuG9JKQ7hFhy2YvNAzWIU8+9LFBup0/bhc3HGxSNtUK5C3S1aN!pGOnYSkDTaE= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:742 Jacko wrote: > On 26 Mar, 10:17, Sean Durkin wrote: >> Hi *, >> >> I know the whole numeric_std vs. std_logic_arith issue has been covered >> several times before here, but please bear with me for a second :) > > The critical point to get is that std_logic_vector is a string type! > so expect it to behave as such sometimes, including having a greater > than 32 bit length. > > numeric standard_does a string->number->string with number being > limited to 32 bits. std_logic_artih does not do this conversion, an > all things remain as strings with a limited character subset. > > If you go for more than addition and subtraction, then things get less > supported in logic arith. If you understand your logic, then this is > no problem to write your own boole multiplier etc. > > With numeric std, full arithmetic is generally supported to 32 bit > resolution with reduction of stuck at 1 or 0 inputs. You can't easily > write a 64 bit cpu in numeric std. > > cheers jacko That's almost completely wrong in every respect. regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:55 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!l10g2000vba.googlegroups.com!not-for-mail From: heilig.brian@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Date: Fri, 27 Mar 2009 08:13:35 -0700 (PDT) Organization: http://groups.google.com Lines: 76 Message-ID: <03decc4e-263f-421d-9db6-be59c0e73554@l10g2000vba.googlegroups.com> References: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> <7e51f2f0-31cb-4eac-950d-e64a58ef5bfb@e38g2000yqa.googlegroups.com> <7bbefa01-5797-44d3-8b13-4a158044418f@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 173.15.144.193 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238166815 13709 127.0.0.1 (27 Mar 2009 15:13:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 15:13:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l10g2000vba.googlegroups.com; posting-host=173.15.144.193; posting-account=S2_qiQkAAAAZwWA6tvR91vdgATmaxVS5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:743 This is the code I finally settled on: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity code_filter is port ( x0: in std_logic; y: out std_logic_vector(11 downto 0); clk: in std_logic ); end code_filter; architecture code_filter_arch of code_filter is type coef_type is array(0 to 15) of integer range -511 to 511; constant h: coef_type := (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); signal mult: coef_type; signal x: std_logic_vector(15 downto 0); signal sum0_1, sum2_3, sum4_5, sum6_7: integer range -1023 to 1023; signal sum8_9, sum10_11, sum12_13, sum14_15: integer range -1023 to 1023; signal sum0_3, sum4_7, sum8_11, sum12_15: integer range -2047 to 2047; signal sum0_7, sum8_15: integer range -4095 to 4095; signal sum_total: integer range -8191 to 8191; begin process (clk) begin if rising_edge(clk) then x(x'high downto 1) <= x((x'high-1) downto 0); x(0) <= x0; end if; end process; one_bit_multiply: for i in x'range generate mult(i) <= h(i) when x(i)='1' else -h(i); end generate; sum0_1 <= mult(0) + mult(1); sum2_3 <= mult(2) + mult(3); sum4_5 <= mult(4) + mult(5); sum6_7 <= mult(6) + mult(7); sum8_9 <= mult(8) + mult(9); sum10_11 <= mult(10) + mult(11); sum12_13 <= mult(12) + mult(13); sum14_15 <= mult(14) + mult(15); sum0_3 <= sum0_1 + sum2_3; sum4_7 <= sum4_5 + sum6_7; sum8_11 <= sum8_9 + sum10_11; sum12_15 <= sum12_13 + sum14_15; sum0_7 <= sum0_3 + sum4_7; sum8_15 <= sum8_11 + sum12_15; sum_total <= sum0_7 + sum8_15; y <= std_logic_vector(to_signed(sum_total,12)); end code_filter_arch; The entire filter is now contained in this code, including the shift registers (which used to be in another file). It has been simulated and it works great. The major difference between this version and what I had before is the processing of the add. The lesson I learned here is that VHDL produces a result that closely matches the code, unlike C which will perform aggressive optimizations. My previous version resulted in 15 adders in one long chain (exactly as the code was written) whereas the current version resulted in 15 adders in a hierarchical structure (again exactly as it is written). This resulted in a reduction of the propagation delay by a factor of log2(16). Anyway it's good to know my initial design actually did work, even though it wasn't optimal. After your first scathing response I felt like I should turn in my degree and restart a career in some liberal arts field. But your reply is greatly appreciated as I understand what is going on much better. Brian From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!feeder2-2.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!q9g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 08:13:50 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <6c5d041b-3a48-4e4d-a5fc-04ac6fe0edd4@q9g2000yqc.googlegroups.com> References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238166830 13867 127.0.0.1 (27 Mar 2009 15:13:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Mar 2009 15:13:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q9g2000yqc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:744 > > numeric standard_does a string->number->string with number being > limited to 32 bits. std_logic_artih does not do this conversion, an > all things remain as strings with a limited character subset. > Tell that to my 36 bit unsigned mutliplier results! From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news-1.dfn.de!news.informatik.hu-berlin.de!tfh-berlin.DE!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 16:19:12 +0100 Lines: 11 Message-ID: <73493hFs5h60U1@mid.individual.net> References: <73131gFslqtrU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net nIpiT5nvFNNSj/RayP8anwuJHQVY7+Uu0qR+7TL7d0n+i9v1zA Cancel-Lock: sha1:YbTix7J9adw1T9t24A0lBIUJdwg= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <73131gFslqtrU1@mid.individual.net> Xref: news.eternal-september.org comp.lang.vhdl:745 Hi *, just wanted to say thanks to everyone who took the time to respond, I really appreciate it. Now I have some more convincing arguments :) cu, Sean -- Replace MONTH with the three-letter-abbreviation for the current month. Simple, eh? From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 27 Mar 2009 10:34:48 -0500 Date: Fri, 27 Mar 2009 15:34:46 +0000 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 76 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-TcymadQ0dNELNl2K0Ya7c1aHfLTWg1hWQkdVmc7oG6vlI5zefU8HfXSNDmqZ9ZyWavMyBCxF51FTTY/!iHSRz9+ctMQ9oycXtePOVZddGtf82QtrAgQc5WR38/CkOM2mXOv/y/yCijWeBvOhabBUvYr4QUpT!VRQ0Aa/6u8I= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:746 Alan Fitch wrote: > Jacko wrote: >> On 26 Mar, 10:17, Sean Durkin wrote: >>> Hi *, >>> >>> I know the whole numeric_std vs. std_logic_arith issue has been covered >>> several times before here, but please bear with me for a second :) >> >> The critical point to get is that std_logic_vector is a string type! >> so expect it to behave as such sometimes, including having a greater >> than 32 bit length. >> >> numeric standard_does a string->number->string with number being >> limited to 32 bits. std_logic_artih does not do this conversion, an >> all things remain as strings with a limited character subset. >> >> If you go for more than addition and subtraction, then things get less >> supported in logic arith. If you understand your logic, then this is >> no problem to write your own boole multiplier etc. >> >> With numeric std, full arithmetic is generally supported to 32 bit >> resolution with reduction of stuck at 1 or 0 inputs. You can't easily >> write a 64 bit cpu in numeric std. >> >> cheers jacko > > That's almost completely wrong in every respect. > > regards > Alan > > Sorry I was a bit quick there - perhaps I should be more specific 1. std_logic_vector is not "a string type" it is an unconstrained array of std_logic 2. numeric std uses types signed and unsigned which are also unconstrained arrays of std_logic 3. numeric std does *not* do a "string -> number -> string" conversion. All functions and operators (except to_integer, to_signed, to_unsigned) are written to work on signed and unsigned (which are arbitrary width up to the range of NATURAL) The exceptions are the conversions to and from integer which must produce a result limited to the range of integer - but then so is conv_integer in std_logic_arith 4. I agree that the coverage of arithmetic operations is not as good in std_logic_arith as it is in numeric_std. 5. Numeric std *can* easily write a 64 bit cpu, regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!news2.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 27 Mar 2009 11:40:28 -0500 Date: Fri, 27 Mar 2009 09:40:27 -0700 From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Concurrent Statements for FIR Filter Message-ID: <20090327094027.00004e6b@unknown> References: <59328898-fc87-4205-b5c1-8ede3fa96355@z1g2000yqn.googlegroups.com> <7e51f2f0-31cb-4eac-950d-e64a58ef5bfb@e38g2000yqa.googlegroups.com> <7bbefa01-5797-44d3-8b13-4a158044418f@k2g2000yql.googlegroups.com> <03decc4e-263f-421d-9db6-be59c0e73554@l10g2000vba.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 102 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-TJqLl0HXtJptqDhteLfPI0uyNCHnXSLveWbZdgC+RfRntxVOzAOqtkY1jUKIpp7HGzr1uenl6WcgEaU!yZ71hu9B0qpvIRait1ZSK0cUkDjExp4q5p1pdu4B2F5uTQluXjgeXjOCWf4PKVWWwQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 5516 Xref: news.eternal-september.org comp.lang.vhdl:747 On Fri, 27 Mar 2009 08:13:35 -0700 (PDT) heilig.brian@gmail.com wrote: > This is the code I finally settled on: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity code_filter is > port ( > x0: in std_logic; > y: out std_logic_vector(11 downto 0); > clk: in std_logic > ); > end code_filter; > > architecture code_filter_arch of code_filter is > type coef_type is array(0 to 15) of integer range -511 to 511; > constant h: coef_type := > (4,-2,-28,-53,-17,128,345,511,511,345,128,-17,-53,-28,-2,4); > signal mult: coef_type; > signal x: std_logic_vector(15 downto 0); > signal sum0_1, sum2_3, sum4_5, sum6_7: integer range -1023 to > 1023; signal sum8_9, sum10_11, sum12_13, sum14_15: integer range > -1023 to 1023; > signal sum0_3, sum4_7, sum8_11, sum12_15: integer range -2047 > to 2047; > signal sum0_7, sum8_15: integer range -4095 to 4095; > signal sum_total: integer range -8191 to 8191; > begin > process (clk) > begin > if rising_edge(clk) then > x(x'high downto 1) <= x((x'high-1) downto 0); > x(0) <= x0; > end if; > end process; > > one_bit_multiply: for i in x'range generate > mult(i) <= h(i) when x(i)='1' else -h(i); > end generate; > > sum0_1 <= mult(0) + mult(1); > sum2_3 <= mult(2) + mult(3); > sum4_5 <= mult(4) + mult(5); > sum6_7 <= mult(6) + mult(7); > sum8_9 <= mult(8) + mult(9); > sum10_11 <= mult(10) + mult(11); > sum12_13 <= mult(12) + mult(13); > sum14_15 <= mult(14) + mult(15); > sum0_3 <= sum0_1 + sum2_3; > sum4_7 <= sum4_5 + sum6_7; > sum8_11 <= sum8_9 + sum10_11; > sum12_15 <= sum12_13 + sum14_15; > sum0_7 <= sum0_3 + sum4_7; > sum8_15 <= sum8_11 + sum12_15; > sum_total <= sum0_7 + sum8_15; > y <= std_logic_vector(to_signed(sum_total,12)); > end code_filter_arch; > > The entire filter is now contained in this code, including the shift > registers (which used to be in another file). It has been simulated > and it works great. The major difference between this version and what > I had before is the processing of the add. The lesson I learned here > is that VHDL produces a result that closely matches the code, unlike C > which will perform aggressive optimizations. My previous version > resulted in 15 adders in one long chain (exactly as the code was > written) whereas the current version resulted in 15 adders in a > hierarchical structure (again exactly as it is written). This resulted > in a reduction of the propagation delay by a factor of log2(16). > > Anyway it's good to know my initial design actually did work, even > though it wasn't optimal. After your first scathing response I felt > like I should turn in my degree and restart a career in some liberal > arts field. But your reply is greatly appreciated as I understand what > is going on much better. > > Brian Don't confuse simulation with synthesis. It matters not a lick whether the simulation tool thinks your adder should be implemented as chain or as a tree. It's what the synthesizer is going to do with it which is highly a) synth tool dependant, b) architecture dependant, c) setting dependant. The problem with trying to do the whole shebang every clock tick isn't that the sim cares; it doesn't. It's how grotesquely far down it's going to push your maximum clock frequency when you try to render honest to god hardware out of it. Now, some synth tools are smart enough to let you just hang a few delay line registers on the far end, and it'll distribute them "optimally". Some aren't. Some, like the latest version of XST, are smart enough except when they aren't. But the takeaway should be that VHDL is in fact _EXACTLY_ like C in that fundamentally, all you're producing is a description of the operations. The tools have the option to implement that description however they please, so long as they stay within the rules. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news.enother.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 27 Mar 2009 11:53:27 -0500 Date: Fri, 27 Mar 2009 09:53:26 -0700 From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Correct VHDL? Message-ID: <20090327095326.00001aea@unknown> References: Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 86 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-uv8Y5obP1r1NRcotJQ1fUmkYkqNYzIItEzi1Pc8XkRqUkLwBmFQwkclaodrmpKVW8d9XMg7aMaz0G/F!gVo7WLh9rVrTRlf6e0pWbcpyqkcO8i3tuDS+KhzekJOWnfGFEsUkgvJzed28KZu+9w== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:748 On Fri, 27 Mar 2009 06:12:24 -0700 (PDT) mightycatniyander@gmail.com wrote: > Hello, > I want to implement the following C++ code in VHDL > > double t1 = u1 * ip1[i1] - u2 * op1[i1]; > double t2 = u1 * op1[i1] + u2 * ip1[i1]; > ip1[i1] = ip3[i] - t1; > op1[i1] = ip4[i] - t2; > ip3[i] += t1; > ip4[i] += t2; > > i am not sure if this is correct but i have tried and came up with the > following VHDL > > entity test is > port( clk : in std_logic; > ip1 : in std_logic_vector(7 downto 0); > op1 : in std_logic_vector(7 downto 0); > ip3 : in std_logic_vector(7 downto 0); > ip4 : in std_logic_vector(7 downto 0); > U1 : in std_logic_vector(7 downto 0); > U2 : in std_logic_vector(7 downto 0); > ip1o : out std_logic_vector(15 downto 0); > op1o : out std_logic_vector(15 downto 0); > ip3o : out std_logic_vector(15 downto 0); > ip4o : out std_logic_vector(15 downto 0)); > end test; > > architecture Behavioral of test is > signal T1 : std_logic_vector(15 downto 0); > signal T2 : std_logic_vector(15 downto 0); > begin > > process(clk) > begin > T1 <= (U1 * ip1) - (U2 * op1); > T2 <= (U1 * op1) + (U2 * ip1); > ip1o <= ip3 - T1; > op1o <= ip4 - T2; > ip3o <= ip3 + T1; > ip4o <= ip4 + T2; > end process; > > end Behavioral; > > i would really appreciate if some one can tell me is it correct, if > not how can it be implemented correctly in VHDL? > No, it's not correct. First of all, you're trying to perform arithmatic on std_logic_vectors, with no libraries linked in. The std_logic_arith library will allow you to do that, but shouldn't, as it completely throws away any concept of typing. The numeric_std library lets you do things properly, but you'll need to explicitly cast your std_logic_vectors to signed or unsigned accordingly. Secondly you've missed the concept of signal assignments in a clocked process, which is that all signal assignment happens all at once, on the clock edge. In the code you've written, T1 is modified on one clock edge, and then ip1o is updated with the current value of ip3, but the previously calculated value of T1. If you really want to define intermediate values that are updated immediately, you want to use variables instead. Also, of course, is the issue that your C defines T1 and T2 as doubles, implying floating point math. While floating point is possible in hardware, generally the belief that you need it is an indication that you don't understand your problem. God only knows what types you think the intermediate values are. Stop thinking of this as code. It's not. It's a hardware description language, it describes hardware. Get a quad pad, or preferably D size vellum. Draw out the hardware schematic. Be SPECIFIC as to what each piece of hardware is, and how it would be implemented on the target fabric. Then start writing the HDL to appropriately describe what's supposed to happen. Writing higher level, more abstract code, is a time-saving convenience that should be reserved for people who fully and completely understand the lower level situation. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Correct VHDL? Date: Fri, 27 Mar 2009 14:15:36 -0700 Lines: 21 Message-ID: <734tvqFt70j1U1@mid.individual.net> References: <20090327095326.00001aea@unknown> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 22dRfMGTNbqAn5rhHt47vgudtqsAGdTG2932U9Ek43uhutJI09 Cancel-Lock: sha1:DkI3+/lD1MW+THORWdYTYXROG1M= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <20090327095326.00001aea@unknown> Xref: news.eternal-september.org comp.lang.vhdl:749 Rob Gaddi wrote: > No, it's not correct. > > you're trying to perform arithmetic on std_logic_vectors, > with no libraries linked in. The std_logic_arith library will allow > you to do that, but shouldn't, as it completely throws away any concept > of typing. Actually it's the the synopsys std_logic_unsigned and std_logic_signed packages that attempt math on std_logic_vectors. These packages do not play nice with each other or with the standard comparison operators. The std_logic_arith package causes less havoc because it requires the use signed and unsigned types. Users of the synopsys "verilog subset" rarely employ these. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.tanoz.com!news.albasani.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 14:42:07 -0700 Lines: 20 Message-ID: <49CD482F.8040307@gmail.com> References: <73131gFslqtrU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net DgaJIArW51m7U+dfI9+59AqcWV2324sNMr93vOpNo9yfrKx4AT Cancel-Lock: sha1:GSGksZR9Ax8pPTmh5Wrn6R0wlII= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <73131gFslqtrU1@mid.individual.net> Xref: news.eternal-september.org comp.lang.vhdl:750 Sean Durkin wrote: > I personally have always used numeric_std, because that's the way I > learned it. But when I talk about this with colleagues, the "use it > because it's a standard"-argument never beats the "I've been using > std_logic_arith forever, never had the slightest problems and don't see > why I should ever change anything"-argument. There probably is no example that will win this argument. That's the way *they* learned it. If you prosper, you could buy the company and lay down the law. Short of that, it may be best to lead by example. I code in my own style and then provide a wrapper interface entity to anyone allergic to my vector types. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!talisker.lacave.net!lacave.net!news.ecp.fr!news.glorb.com!postnews.google.com!c11g2000yqj.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Fri, 27 Mar 2009 18:30:45 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 217.171.129.69 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238203845 11599 127.0.0.1 (28 Mar 2009 01:30:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 28 Mar 2009 01:30:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c11g2000yqj.googlegroups.com; posting-host=217.171.129.69; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:751 On 27 Mar, 15:01, kennheinr...@sympatico.ca wrote: > On Mar 27, 10:45=A0am, Jacko wrote: > > > > > With numeric std, full arithmetic is generally supported to 32 bit > > resolution with reduction of stuck at 1 or 0 inputs. You can't easily > > write a 64 bit cpu in numeric std. > > > cheers jacko > > I just looked at the source for numeric_std and how it implements > addition, subtraction, multiplication, and division. As far as my > quick perusal reveals, everything is coded at the bit level and has no > constraints other than the LENGTH of the unsigned/signed numbers have > to be integers, so it looks like it could support (roughly) numbers up > to 2^31 bits in length. =A0Can you give a more precise description of > where you ran into this issue - I'm curious to know if I mis-read the > code? > > =A0- Kenn I didn't run into an issue, I've used std_logic_arith always, I have never needed the higher coverage of division ops, or needed to convert between integers and std_logic. I only use + and - and I always make sure that the result size is assigned to a correctly sized std_logic_vector. I think the limits come by using type integer to store calculation results, which I never do. I never use any library feature to perform sign extension, and prefer a more explicit '&' concat style of coding. The reason for my preference for std_logic_arith is that I constrains me to not get too flashy with large sythesis designs. Case in point '/' can expand to a large amount of logic etc. signal1 <=3D unsigned(signal2)+1 -- is about as complex as my use is of the libraries. as a synchronous counter. The adder in the ALU of http://nibz.googlecode.com is implemented in descrete logic to reduce produced area. i.e. the whole CPU fits in less space than the multiplexed 4 way standard library version of the ALU processor. Granted it is faster in the 4 way multiplexed library version, but this is due to non optimal use of fast carry routing. (technology specific). I find I can not rely on library code reducing to minimal area. cheers jacko From newsfish@newsfish Wed Aug 19 13:23:56 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news.netfront.net!not-for-mail From: Cross Newsgroups: comp.lang.vhdl Subject: vhdl compiler Date: Sat, 28 Mar 2009 20:29:33 +0530 Organization: Netfront http://www.netfront.net Lines: 6 Message-ID: NNTP-Posting-Host: 122.50.132.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: adenine.netfront.net 1238252376 64592 122.50.132.239 (28 Mar 2009 14:59:36 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Sat, 28 Mar 2009 14:59:36 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090310) Xref: news.eternal-september.org comp.lang.vhdl:752 Hello which compiler is preferrable for vhdl in linux environment? Regards, Cross From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: vhdl compiler Date: Sat, 28 Mar 2009 11:07:56 -0700 Lines: 12 Message-ID: <49CE677C.5060907@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net gWNR/hDMguHxZGIrNce98A5B52kIHqeMugvxJ+iLda9ImGv6gh Cancel-Lock: sha1:TcP04jv6P9CwpK/fsfM6f28VN10= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:753 Cross wrote: > which compiler is preferrable for vhdl in linux environment? If your vhdl code is already written and simulated, synthesis is agnostic. For design I prefer Modelsim because I am used to it and I don't pay for the license. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!aioe.org!not-for-mail From: russ Newsgroups: comp.lang.vhdl Subject: Re: vhdl compiler Date: Sat, 28 Mar 2009 22:43:35 -0400 Organization: Aioe.org NNTP Server Lines: 8 Message-ID: References: NNTP-Posting-Host: ifU8IoVoMn1V+nTqUN2HDw.user.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org NNTP-Posting-Date: Sun, 29 Mar 2009 02:42:57 +0000 (UTC) X-Notice: Filtered by postfilter v. 0.7.7 Cancel-Lock: sha1:8FgCHgNFBaESDEEXKSgPrRxVyRQ= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) Xref: news.eternal-september.org comp.lang.vhdl:754 Cross wrote: > Hello > > which compiler is preferrable for vhdl in linux environment? > > Regards, > Cross ghdl with gtkwave works pretty well. From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!aioe.org!not-for-mail From: russ Newsgroups: comp.lang.vhdl Subject: Re: vhdl compiler Date: Sat, 28 Mar 2009 22:44:21 -0400 Organization: Aioe.org NNTP Server Lines: 8 Message-ID: References: NNTP-Posting-Host: ifU8IoVoMn1V+nTqUN2HDw.user.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org NNTP-Posting-Date: Sun, 29 Mar 2009 02:43:43 +0000 (UTC) X-Notice: Filtered by postfilter v. 0.7.7 Cancel-Lock: sha1:3emwOJM/i1veBIb4+bkaibyJNTw= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) Xref: news.eternal-september.org comp.lang.vhdl:755 Cross wrote: > Hello > > which compiler is preferrable for vhdl in linux environment? > > Regards, > Cross ghdl with gtkwave works pretty well. From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: "comp.lang.vhdl" Newsgroups: comp.lang.vhdl Subject: FIR Filter Date: Sun, 29 Mar 2009 02:16:07 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> NNTP-Posting-Host: 59.95.209.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238318167 20966 127.0.0.1 (29 Mar 2009 09:16:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 29 Mar 2009 09:16:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=59.95.209.111; posting-account=5G73hQoAAABF6IceBtE0mBmq6UPBHS-S User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.48 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:756 Can anybody tel about the application of FIR Filter. I know some of them. Low Pass Filter,High Pass Filter are its application. But don't know how to implement in VHDL. Please help me out. From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: FIR Filter Date: Sun, 29 Mar 2009 11:57:13 -0700 Lines: 9 Message-ID: <49CFC489.2080403@gmail.com> References: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net YMyKRWGlkP03fLHyYLC/rAoN7CDahDH2+8RD4Y4PIxmy6+NbDE Cancel-Lock: sha1:6Ct2FDeVApniZKpaCscaWzLma1U= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:757 comp.lang.vhdl wrote: > Can anybody tel about the application of FIR Filter. I know some of > them. Low Pass Filter,High Pass Filter are its application. But don't > know how to implement in VHDL. Please help me out. sum := d + sum; ave := sum / 16; -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!d19g2000yqb.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: FIR Filter Date: Sun, 29 Mar 2009 20:35:17 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <59e800d7-e68f-428a-a518-ee2aec6c6fb7@d19g2000yqb.googlegroups.com> References: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> NNTP-Posting-Host: 74.12.60.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238384117 5627 127.0.0.1 (30 Mar 2009 03:35:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 03:35:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000yqb.googlegroups.com; posting-host=74.12.60.239; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.6) Gecko/2009020409 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:758 On Mar 29, 5:16=A0am, "comp.lang.vhdl" wrote: > Can anybody tel about the application of FIR Filter. I know some of > them. Low Pass Filter,High Pass Filter are its application. But don't > know how to implement in VHDL. Please help me out. Do you have the internet where you live? From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!r37g2000yqn.googlegroups.com!not-for-mail From: specman baby Newsgroups: comp.lang.vhdl Subject: Code coverage Date: Mon, 30 Mar 2009 00:25:42 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: NNTP-Posting-Host: 192.163.20.232 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238397942 2482 127.0.0.1 (30 Mar 2009 07:25:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 07:25:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r37g2000yqn.googlegroups.com; posting-host=192.163.20.232; posting-account=9UZQOAoAAAA8e5Bl3zjzIrXAz9EqoR_L User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxyin13 (NetCache NetApp/6.0.5), 1.1 proxyin11 (NetCache NetApp/6.0.5), 1.1 proxyqh02 (NetCache NetApp/6.0.5) Xref: news.eternal-september.org comp.lang.vhdl:759 Hi, Can anyone provide some link which has good info on code coverage like what is UDP, FEC, etc Thanx Specman Baby From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!e21g2000yqb.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Generic range Date: Mon, 30 Mar 2009 01:50:20 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238403020 18514 127.0.0.1 (30 Mar 2009 08:50:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 08:50:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000yqb.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:760 Hi, I am trying to do the following: signal ls_test : unsigned(7 downto 0); process(ls_test) begin if ls_test(7 downto 1) = "0000000" then ... end if; end process; Now I want to have something like: signal ls_test : unsigned(gWidth-1 downto 0); process(ls_test) begin if ls_test = (ls_test'high downto ls_test'low +1 => '0') then ... end if; end process; When compiling I get the following error: "Operator "=" is not defined for such operands. Can somebody share some light on it ? Thank you. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:23:57 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp7-1.free.fr!not-for-mail Subject: Re: Generic range From: Bert_Paris References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 30 Mar 2009 11:37:08 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 50 Message-ID: <49d092c4$0$21825$426a74cc@news.free.fr> NNTP-Posting-Date: 30 Mar 2009 11:37:08 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1238405828 news-1.free.fr 21825 82.66.120.181:2975 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:761 ALuPin@web.de a formulé la demande : > Hi, > > I am trying to do the following: > > signal ls_test : unsigned(7 downto 0); > > > process(ls_test) > begin > if ls_test(7 downto 1) = "0000000" then > ... > end if; > end process; > > > Now I want to have something like: > > signal ls_test : unsigned(gWidth-1 downto 0); > > process(ls_test) > begin > if ls_test = (ls_test'high downto ls_test'low +1 => '0') then > ... > end if; > end process; > > When compiling I get the following error: > "Operator "=" is not defined for such operands. > > Can somebody share some light on it ? > > Thank you. > Rgds, ALuPin Is this what you're trying to write ? constant gWidth : positive := 8; signal ls_test : unsigned(gWidth-1 downto 0); Begin process (ls_test) begin if ls_test (ls_test'high downto ls_test'low +1) = 0 then report "done !"; end if; end process; Bert Cuzeau From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed4-a.proxad.net!nnrp20-1.free.fr!not-for-mail Subject: RS232, UART and Igloo nano Kit From: Bert_Paris Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 30 Mar 2009 11:38:11 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 23 Message-ID: <49d09304$0$11790$426a74cc@news.free.fr> NNTP-Posting-Date: 30 Mar 2009 11:38:12 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1238405892 news-1.free.fr 11790 82.66.120.181:2980 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:762 Hello, I have built an Application Note for newbies (& students !) who want to understand and implement RS232 (UART) in an FPGA. Especially when it's an assignement, they should follow this document instead of asking for the UART code (which I give away only in the context of larger educational projects). I have also built a nice (I think) Tutorial to implement and test a simple UART in the new Igloo nano Kit (49 $!), complete with all steps from installing the (free) development software to building the design, programming the kit and testing the RS232 on a PC. These are available at : http://www.alse-fr.com/UART/ALSE_RS232.pdf http://www.alse-fr.com/Actel/ALSE_Igloo_nano.exe As I state in this document, do not expect tech support for free stuff, though I welcome useful remarks and suggestions. Hope it helps (and will reduce the amount of requests for the UART), Bert Cuzeau CTO ALSE (can be reached at info@ the website in the links above) From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!v38g2000yqb.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Mon, 30 Mar 2009 03:31:57 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <958f6e61-a34e-4661-97b9-3e4651ba1d0e@v38g2000yqb.googlegroups.com> References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> <49d092c4$0$21825$426a74cc@news.free.fr> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238409117 5423 127.0.0.1 (30 Mar 2009 10:31:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 10:31:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v38g2000yqb.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:763 Hi Bert, not exactly. Your solution works for >if ls_test = (ls_test'high downto ls_test'low +1 => '0') then but not for >if ls_test = (ls_test'high downto ls_test'low +1 => '1') then that is all the vector bits are '1'. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp7-1.free.fr!not-for-mail Subject: Re: Generic range From: Bert_Paris References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> <49d092c4$0$21825$426a74cc@news.free.fr> <958f6e61-a34e-4661-97b9-3e4651ba1d0e@v38g2000yqb.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 30 Mar 2009 12:50:39 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 31 Message-ID: <49d0a3ff$0$21827$426a74cc@news.free.fr> NNTP-Posting-Date: 30 Mar 2009 12:50:39 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1238410239 news-1.free.fr 21827 82.66.120.181:3279 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:764 ALuPin@web.de avait soumis l'idée : > Hi Bert, > > not exactly. > > Your solution works for > >> if ls_test = (ls_test'high downto ls_test'low +1 => '0') then > > but not for > >> if ls_test = (ls_test'high downto ls_test'low +1 => '1') then > > that is all the vector bits are '1'. > > Rgds, > ALuPin Then : constant gWidth : positive :=8; signal ls_test : signed(gWidth-1 downto 0) := (0=>'0', others=>'1'); Begin process (ls_test) begin if ls_test (ls_test'high downto ls_test'low +1) = -1 then report "all ones, LSB ignored !"; end if; end process; From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 30 Mar 2009 10:02:43 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Mon, 30 Mar 2009 16:04:06 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 58 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-bUEeXuwUaUxx2NB8mHqx/dud51v5iZklsQazBH08wvPwuBkMA9mHjKuMtMv8608AnvH2GlR6qIXIoC7!H4HWXaydV+ylx7Qd+EHdwKUnyUox5Qr1MgRfU3++DX2Y2ApAf5x4FPWGQVqXv7bfV7wN7532LLyO!fwoG X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:765 On Mon, 30 Mar 2009 01:50:20 -0700 (PDT), "ALuPin@web.de" wrote: >Hi, >Now I want to have something like: > >signal ls_test : unsigned(gWidth-1 downto 0); > >process(ls_test) >begin > if ls_test = (ls_test'high downto ls_test'low +1 => '0') then > ... > end if; >end process; > >When compiling I get the following error: >"Operator "=" is not defined for such operands. > >Can somebody share some light on it ? The RHS expression could match any number of visible types, from string to std_logic_vector to signed to .... and "=" could be overloaded to handle any or all of them. The compiler can't possibly tell which of them you are aiming for. Unlike some other languages, rather than silently landing you with the language designer's arbitrary choice(*), VHDL reports and lets (i.e. makes) YOU decide. Either of unsigned'(ls_test'high downto ls_test'low +1 => '0') -- treat ambiguous type as unsigned or unsigned(ls_test'high downto ls_test'low +1 => '0') -- convert from (presumably SLV) to unsigned should do what you want. If it's too ugly or you are doing it more than once, wrap it in a function. If you need it in different places, that's what packages are for. (*) This may sound pedantic and a bit harsh. And for function "=" (a:unsigned,b:string) return boolean is ... function "=" (a:unsigned,b:unsigned) return boolean is ... most languages may actually give you the expected results, at least, as long as you take care that the arguments are the same length. But consider for a moment function "<" (a:unsigned,b:[some type, maybe string]) return boolean is ... Have ever been plagued by a list sorted as 1,10,11,12,13,2,3,4,5,6,7,8,9 ? I know I have. And I know which approach I prefer. - Brian From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!de-l.enfer-du-nord.net!feeder.erje.net!news-1.dfn.de!news.informatik.hu-berlin.de!tfh-berlin.DE!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Ralf Hildebrandt Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Mon, 30 Mar 2009 17:18:25 +0200 Lines: 14 Message-ID: <73c667Fu57ohU1@mid.individual.net> References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net wjMHgDhcRLAthX7au22RRwxpGRemwLi5j+OU9T/B2B/35BgQ== Cancel-Lock: sha1:CWyovY8G6XKMWtd5aF5N0U0yM8I= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:766 ALuPin@web.de schrieb: > if ls_test(7 downto 1) = "0000000" then With IEEE.numeric_std.all you can write if ls_test(7 downto 1) = 0 then because ls_test is defined as unsigned vector. Unsigned can be compared to integer and so you do this independently from the range. Ralf From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 30 Mar 2009 11:28:30 -0500 Date: Mon, 30 Mar 2009 09:28:33 -0700 From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Code coverage Message-ID: <20090330092833.00001d2b@unknown> References: Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 17 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-AWDMrEKs8oIDzALQZ9ofQqoVDX/ERFCbI7NeKnfVnz+2ofCOW80uoHpGVINqszDORBduu01N0vwiv2E!9PVjuckmVg/d35DiGYF2VT32TXEVSCCWPCfnk5h0P19xOQP3Vpnoi7/kxhZ+MMR18w== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:767 On Mon, 30 Mar 2009 00:25:42 -0700 (PDT) specman baby wrote: > Hi, > > Can anyone provide some link which has good info on code coverage like > what is UDP, FEC, etc > > Thanx > Specman Baby www.google.com www.wikipedia.com -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!l13g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Mon, 30 Mar 2009 09:47:25 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <1c4c72ad-f4be-4204-9e23-3de1c22fcee6@l13g2000vba.googlegroups.com> References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> <49d092c4$0$21825$426a74cc@news.free.fr> <958f6e61-a34e-4661-97b9-3e4651ba1d0e@v38g2000yqb.googlegroups.com> <49d0a3ff$0$21827$426a74cc@news.free.fr> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238431645 29350 127.0.0.1 (30 Mar 2009 16:47:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 16:47:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l13g2000vba.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:768 On Mar 30, 5:50=A0am, Bert_Paris wrote: > > Then : > > constant gWidth : positive :=3D8; > signal ls_test : signed(gWidth-1 downto 0) :=3D (0=3D>'0', others=3D>'1')= ; > Begin > process (ls_test) > begin > =A0 =A0 =A0if ls_test (ls_test'high downto ls_test'low +1) =3D -1 then > =A0 =A0 =A0 =A0report "all ones, LSB ignored !"; > =A0 =A0 end if; > end process;- Hide quoted text - > > - Show quoted text - There are also easier ways to strip off the lsb of an unsigned/signed vector. constant gWidth : positive :=3D 8; signal ls_test : unsigned(gWidth-1 downto 0); ... if lstest / 2 =3D 0 then... or: if signed(lstest) / 2 =3D -1 then... Andy From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!l22g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Mon, 30 Mar 2009 10:21:03 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238433663 19603 127.0.0.1 (30 Mar 2009 17:21:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Mar 2009 17:21:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l22g2000vba.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:769 On Mar 27, 10:34=A0am, Alan Fitch wrote: > Alan Fitch wrote: > > Jacko wrote: > >> On 26 Mar, 10:17, Sean Durkin wrote: > >>> Hi *, > > >>> I know the whole numeric_std vs. std_logic_arith issue has been cover= ed > >>> several times before here, but please bear with me for a second :) > > >> The critical point to get is that std_logic_vector is a string type! > >> so expect it to behave as such sometimes, including having a greater > >> than 32 bit length. > > >> numeric standard_does a string->number->string with number being > >> limited to 32 bits. std_logic_artih does not do this conversion, an > >> all things remain as strings with a limited character subset. > > >> If you go for more than addition and subtraction, then things get less > >> supported in logic arith. If you understand your logic, then this is > >> no problem to write your own boole multiplier etc. > > >> With numeric std, full arithmetic is generally supported to 32 bit > >> resolution with reduction of stuck at 1 or 0 inputs. You can't easily > >> write a 64 bit cpu in numeric std. > > >> cheers jacko > > > That's almost completely wrong in every respect. > > > regards > > Alan > > Sorry I was a bit quick there - perhaps I should be more specific > > 1. std_logic_vector is not "a string type" it is an unconstrained array > of std_logic > > 2. numeric std uses types signed and unsigned which are also > unconstrained arrays of std_logic > > 3. numeric std does *not* do a "string -> number -> string" conversion. > All functions and operators (except to_integer, to_signed, to_unsigned) > are written to work on signed and unsigned (which are arbitrary width up > to the range of NATURAL) > > The exceptions are the conversions to and from integer which must > produce a result limited to the range of integer - but then so is > conv_integer in std_logic_arith > > 4. I agree that the coverage of arithmetic operations is not as good in > std_logic_arith as it is in numeric_std. > > 5. Numeric std *can* easily write a 64 bit cpu, > > regards > Alan > > -- > Alan Fitch > Senior Consultant > > Doulos =96 Developing Design Know-how > VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project > Services > > Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: =A0+ 44 (0)1425 471223 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Email: alan.fi...= @doulos.com > Fax: =A0+44 (0)1425 471573 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0http://www.doul= os.com > > ------------------------------------------------------------------------ > > This message may contain personal views which are not the views of > Doulos, unless specifically stated.- Hide quoted text - > > - Show quoted text - I'm not that familiar with std_logic_arith. I've avoided it whenever possible, and never seen any code that got beyond the basics with it. What arithmetic operations does SLA/SLS/SLU support that numeric_std does not? I am aware that many moons ago, Synopsys did not support numeric_std.signed/unsigned and div/mod by integral powers of 2 for synthesis, but they would simulate it. Andy From newsfish@newsfish Wed Aug 19 13:23:58 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Mon, 30 Mar 2009 11:15:49 -0700 Lines: 17 Message-ID: <49D10C55.7050704@gmail.com> References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net 57GJOvSaLpEJoyiH2BNYhwJROw+tPNe+A/Ov/6CPExzNuW0yCB Cancel-Lock: sha1:eFy/iGIjfJ2yyVYpHkkD8F5VjsA= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:770 Andy wrote: > I'm not that familiar with std_logic_arith. I've avoided it whenever > possible, and never seen any code that got beyond the basics with it. Save here. The package is often declared, but rarely used. Commenting the unused USE clause can eliminate some sim warnings. > What arithmetic operations does SLA/SLS/SLU support that numeric_std > does not? None. That is the old Mentor version by the way. Synopsys has different names for those operators. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Examples of issues with std_logic_arith Date: Mon, 30 Mar 2009 11:21:10 -0700 Lines: 15 Message-ID: <49D10D96.9000503@gmail.com> References: <73131gFslqtrU1@mid.individual.net> <8ae26c18-1e41-4d81-a338-ddc207e0cf56@z9g2000yqi.googlegroups.com> <49D10C55.7050704@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net +KkZJTCpGgqOyx2fbIiy6wEjCb4jQcBdhqFYJnMPRajtxE+k7E Cancel-Lock: sha1:5T87e0UM9vvEC0O0GVU1HSJzg4Q= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <49D10C55.7050704@gmail.com> Xref: news.eternal-september.org comp.lang.vhdl:771 Mike Treseler wrote: > Save here. Same > The package is often declared, but rarely used. > Commenting the unused USE clause can eliminate some sim warnings. > >> What arithmetic operations does SLA/SLS/SLU support that numeric_std >> does not? > > None. > That is the old Mentor version by the way. > Synopsys has different names for those operators. > > -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi149.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> Subject: Re: FIR Filter Lines: 11 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi149.ffdc.sbc.com 1238469273 ST000 99.184.242.197 (Mon, 30 Mar 2009 23:14:33 EDT) NNTP-Posting-Date: Mon, 30 Mar 2009 23:14:33 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[R_PJSCTS@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WHAQFW[ML\THRCKV^GGZKJMGV^^_JSCFFUA_QXFGVSCYRPILH]TRVKC^LSN@DX_HCAFX__@J\DAJBVMY\ZWZCZLPA^MVH_P@\\EOMW\YSXHG__IJQY_@M[A[[AXQ_XDSTAR]\PG]NVAQUVM Date: Mon, 30 Mar 2009 23:08:18 -0400 Xref: news.eternal-september.org comp.lang.vhdl:772 "comp.lang.vhdl" wrote in message news:460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com... > Can anybody tel about the application of FIR Filter. I know some of > them. Low Pass Filter,High Pass Filter are its application. But don't > know how to implement in VHDL. Please help me out. Here is a helpful link http://lmgtfy.com/?q=fir+filter+design From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!proxad.net!feeder1-1.proxad.net!cleanfeed2-b.proxad.net!nnrp11-2.free.fr!not-for-mail Subject: Re: Looking for a VHDL simple description for RS-232 From: Bert_Paris References: Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 31 Mar 2009 08:59:59 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 37 Message-ID: <49d1bf6f$0$29078$426a74cc@news.free.fr> NNTP-Posting-Date: 31 Mar 2009 08:59:59 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1238482799 news-1.free.fr 29078 82.66.120.181:1674 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:773 Seph a exposé le 18/03/2009 : > Im new to VHDL and after study a book, im going(at least i want) to > implement a rs-232 protocol communication. > > > I made some search on this group but links for the codes were broken, > those posts are really old, so if theres any source of VHDL code for > rs-232 with an "OK" link, i would really apreciate... > > More simple is better for me.. > > Im a new member in this group between ... > > Thx in any advance... I have built an Application Note for newbies (& students !) who want to understand and implement RS232 (UART) in an FPGA. Especially when it's an assignement, they should follow this document instead of asking for the UART code (which I give away only in the context of larger educational projects). I have also built a nice (I think) Tutorial to implement and test a simple UART in the new Igloo nano Kit (49 $!), complete with all steps from installing the (free) development software to building the design, programming the kit and testing the RS232 on a PC. These are available at : http://www.alse-fr.com/UART/ALSE_RS232.pdf http://www.alse-fr.com/Actel/ALSE_Igloo_nano.exe As I state in this document, do not expect tech support for free stuff, though I welcome useful remarks and suggestions. Hope it helps (and will reduce the amount of requests for the UART), Bert Cuzeau CTO ALSE (can be reached at info@ the website in the links above) From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.germany.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: florinfr@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Tue, 31 Mar 2009 00:48:38 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> NNTP-Posting-Host: 85.186.179.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238485718 24456 127.0.0.1 (31 Mar 2009 07:48:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 07:48:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=85.186.179.188; posting-account=woUPTwoAAAD_WvdVTeT13eJxDKfXMu_y User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:774 On Mar 30, 11:50=A0am, "ALu...@web.de" wrote: > Hi, > > I am trying to do the following: > > signal ls_test : unsigned(7 downto 0); > > process(ls_test) > begin > =A0 =A0 =A0if ls_test(7 downto 1) =3D "0000000" then > =A0 =A0 =A0 =A0... > =A0 =A0 end if; > end process; > > Now I want to have something like: > > signal ls_test : unsigned(gWidth-1 downto 0); > > process(ls_test) > begin > =A0 =A0 =A0if ls_test =3D (ls_test'high downto ls_test'low +1 =3D> '0') t= hen > =A0 =A0 =A0 =A0... > =A0 =A0 end if; > end process; > > When compiling I get the following error: > "Operator "=3D" is not defined for such operands. > > Can somebody share some light on it ? > > Thank you. > Rgds, ALuPin You can try something like this: signal ls_test : unsigned(gWidth-1 downto 0); process(ls_test) begin if ls_test =3D conv_std_logic_vector(0,gWidth) then ... end if; end process; You can replace 0 with any unsigned integer constant. Florin From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!t-online.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!v28g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Tue, 31 Mar 2009 06:41:29 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> <49d092c4$0$21825$426a74cc@news.free.fr> <958f6e61-a34e-4661-97b9-3e4651ba1d0e@v38g2000yqb.googlegroups.com> <49d0a3ff$0$21827$426a74cc@news.free.fr> <1c4c72ad-f4be-4204-9e23-3de1c22fcee6@l13g2000vba.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238506889 27118 127.0.0.1 (31 Mar 2009 13:41:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 13:41:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v28g2000vbb.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:775 On Mar 30, 11:47=A0am, Andy wrote: > > if signed(lstest) / 2 =3D -1 then... > > Andy oops, that won't work! how about: if (not (lstest / 2)) =3D 0 then... Andy From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!z14g2000yqa.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: Generic range Date: Tue, 31 Mar 2009 07:11:47 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <9dc57de5-0354-4709-95c4-1c6150f95d96@z14g2000yqa.googlegroups.com> References: <5e5e92ff-f4bb-4ae3-bfe6-2109cd0ae71b@e21g2000yqb.googlegroups.com> <49d092c4$0$21825$426a74cc@news.free.fr> <958f6e61-a34e-4661-97b9-3e4651ba1d0e@v38g2000yqb.googlegroups.com> <49d0a3ff$0$21827$426a74cc@news.free.fr> <1c4c72ad-f4be-4204-9e23-3de1c22fcee6@l13g2000vba.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238508707 583 127.0.0.1 (31 Mar 2009 14:11:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 14:11:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqa.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:776 Hi, thank you for your inputs. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!o6g2000yql.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Generic-default : simulation vs. synthesis Date: Tue, 31 Mar 2009 07:14:06 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238508846 19914 127.0.0.1 (31 Mar 2009 14:14:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 14:14:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o6g2000yql.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:777 Hi, I am trying to do the following: In a package (pkg_generic.vhd) I declare the following types and constants: type type_range is array(1 downto 0) of integer range 0 to 3; type type_lookup is array (natural range <>) of type_range; constant cLookup : type_lookup(1 downto 0) := ( 1 => (2,4), 0 => (0,3) ); Now I have a component with the following declaration: entity test is generic( gLookup : type_lookup(0 downto 0) := cLookup(0); ); port( ...); end test; When compiling in Modelsim I get the following error: "Cannot resolve indexed name as type work.pkg_generic.type_lookup" For simulation I do not need the default (cLookup(0)) because it is asserted in the generic map of that component. But when trying to synthesize it I get the error: "gLookup has no actual or default value" How can I marry both, synthesis and simulation ? Thank you. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u8g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Generic-default : simulation vs. synthesis Date: Tue, 31 Mar 2009 08:21:29 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <5542b662-00c9-45a5-8290-1b0b967d0151@u8g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238512889 884 127.0.0.1 (31 Mar 2009 15:21:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 15:21:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u8g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:778 On 31 Mar, 15:14, "ALu...@web.de" wrote: > Hi, > > I am trying to do the following: > > In a package (pkg_generic.vhd) I declare the following types and > constants: > > type type_range is array(1 downto 0) of integer range 0 to 3; > type type_lookup is array (natural range <>) of type_range; > > constant cLookup : type_lookup(1 downto 0) :=3D ( 1 =3D> (2,4), 0 =3D> > (0,3) ); > > Now I have a component with the following declaration: > > entity test is > generic( gLookup : type_lookup(0 downto 0) :=3D cLookup(0); > =A0 =A0 =A0 =A0); > port( ...); > end test; > > When compiling in Modelsim I get the following error: > "Cannot resolve indexed name as type work.pkg_generic.type_lookup" > > For simulation =A0I do not need the default (cLookup(0)) > because it is asserted in the generic map of that component. > > But when trying to synthesize it I get the error: > "gLookup has no actual or default value" > > How can I marry both, synthesis and simulation ? > > Thank you. > > Rgds, > ALuPin cLookup(0) is not a type_lookup, its a type_range, so you're trying to assign incompatible types. try this instead: generic( gLookup : type_lookup(0 downto 0) :=3D (0 =3D> cLookup(0) ); ); From newsfish@newsfish Wed Aug 19 13:23:59 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v6g2000vbb.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: Generic-default : simulation vs. synthesis Date: Tue, 31 Mar 2009 08:23:21 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: References: NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238513001 14547 127.0.0.1 (31 Mar 2009 15:23:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 15:23:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v6g2000vbb.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.7) Gecko/2009021910 Firefox/3.0.7,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: news.eternal-september.org comp.lang.vhdl:779 On Mar 31, 10:14=A0am, "ALu...@web.de" wrote: > Hi, > > I am trying to do the following: > > In a package (pkg_generic.vhd) I declare the following types and > constants: > > type type_range is array(1 downto 0) of integer range 0 to 3; > type type_lookup is array (natural range <>) of type_range; > > constant cLookup : type_lookup(1 downto 0) :=3D ( 1 =3D> (2,4), 0 =3D> > (0,3) ); > > Now I have a component with the following declaration: > > entity test is > generic( gLookup : type_lookup(0 downto 0) :=3D cLookup(0); > =A0 =A0 =A0 =A0); > port( ...); > end test; > > When compiling in Modelsim I get the following error: > "Cannot resolve indexed name as type work.pkg_generic.type_lookup" > > For simulation =A0I do not need the default (cLookup(0)) > because it is asserted in the generic map of that component. > > But when trying to synthesize it I get the error: > "gLookup has no actual or default value" > > How can I marry both, synthesis and simulation ? > > Thank you. > > Rgds, > ALuPin I got several other errors (4 is out of range; an extra semicolon... just typos I suspect) but I think your problem is that, as written, you're assigning a value to a slice instead of a slice to a slice. The code below compiles under Modelsim. - Kenn package pkg_generic is type type_range is array(1 downto 0) of integer range 0 to 3; type type_lookup is array (natural range <>) of type_range; constant cLookup : type_lookup(1 downto 0) :=3D ( 1 =3D> (1,3), 0 =3D> (0,3) ); end pkg_generic; use work.pkg_generic.all; entity test is generic( gLookup : type_lookup(0 downto 0) :=3D cLookup(0 downto 0) ); end test; From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: "Symon" Newsgroups: comp.lang.vhdl Subject: Re: FIR Filter Date: Tue, 31 Mar 2009 16:30:29 +0100 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <460105a1-b03a-4e26-a712-ec5a75e9a9ea@b6g2000pre.googlegroups.com> X-Trace: news.eternal-september.org U2FsdGVkX1+YvH5s0z8Fas0b5AZyQ4v0cfezASu2DS/oAjvRP5MihPzFIt/ygkh0VQZMleZra6wmyriMvPi67rkPJXEV7JZEeZwyCvMXBYJg1Wh7YFaCCYNpuANY4shpMEo2qAiZxWA= X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Tue, 31 Mar 2009 15:31:14 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1/BcM5VXAEA/h9H/1uhP12UxmqsZkZzues= Cancel-Lock: sha1:QDhylNHWUWNFhYN9AqOze3a6fbU= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:780 "KJ" wrote in message news:tUfAl.13806$pr6.6273@flpi149.ffdc.sbc.com... > > Here is a helpful link > http://lmgtfy.com/?q=fir+filter+design > Cute! :-) From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!p11g2000yqe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: More synthesis myths? Date: Tue, 31 Mar 2009 08:34:59 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238513699 3581 127.0.0.1 (31 Mar 2009 15:34:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 15:34:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000yqe.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:781 I just overheard the following (or thereabouts) using the following template: process(clk, en) begin if en = '1' then if rising_edge(clk) then d <= b; end if; end if; end process; is better than the "normal" way process(clk) begin if rising_edge(clk) then if en = '1' then c <= a; end if; end if; end process; because the 2nd can produce latches where the clock is gated with enable? has this ever been the case? running either through quartus produces the same (expected) thing - a d-type with enable. Are there some other legends out there that still influence design today? were they really a problem, have they actually been fixed? From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d38g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Tue, 31 Mar 2009 08:46:25 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> NNTP-Posting-Host: 98.246.140.247 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238514386 19201 127.0.0.1 (31 Mar 2009 15:46:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 15:46:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d38g2000prn.googlegroups.com; posting-host=98.246.140.247; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:782 The normal way is the only way I code. > process(clk) > begin > if rising_edge(clk) then > if en = '1' then > c <= a; > end if; > end if; > end process; Historically some ASIC tools have/had a switch that would allow the enable (en) to be transformed into a clock gate - to be used for low power applications. Has anyone seen a synthesis tool that will do this transformation without a setting? I would consider this to be an error. WRT to the other coding template. That coding style was not in the 1076.6-1999 RTL coding styles, but is in the 1076.6-2004 RTL coding styles. I would still be concerned that there may be some tools (such as ASIC synthesis tools) that do not support it. Furthermore, since the code is logically the same, I would be concerned that any misbehaving with the "normal" coding template would also occur with this coding template. Cheers, Jim SynthWorks From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!f32g2000vbf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Tue, 31 Mar 2009 09:16:26 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <72ad71e3-496b-46da-b939-8ce5b9965aa9@f32g2000vbf.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238516188 25227 127.0.0.1 (31 Mar 2009 16:16:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Mar 2009 16:16:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f32g2000vbf.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:783 A third style is: process (clk) is begin if rising_edge(clk) and en = '1' then c <= a; end if; end process; Which produces a clock enable and is the behavioral equivalent of either style. The inclusion of en in the sensitivity list accomplishes absolutely nothing, since nothing happens unless there was rising edge event on clk. I sure hope we don't get back into the old days when the order of nested if-then statements indicated priority from an implementation/timing POV. Note it does not say "rising_edge(clk and en)", if that were even pemissible with rising_edge(), which would directly imply a gated clock. There are some FPGA synthesis tools that will convert clock enables into gated clocks, but only on devices that have "enabled clock buffers" that are "safe". But you still have to set an option for it to do that. The "other" form with clock and enable in the sensitivity list could also be drain on simulation performance with large systems, since such processes cannot be merged with others that are either not clock- enabled, enabled in another way, and/or enabled by other signals. Andy From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!j18g2000prm.googlegroups.com!not-for-mail From: AnandA Newsgroups: comp.lang.vhdl Subject: Configuration for VHDL entity instantiated under Verilog module Date: Tue, 31 Mar 2009 17:53:06 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <08ceb1fe-26a9-4c7b-91c1-c9caace03259@j18g2000prm.googlegroups.com> NNTP-Posting-Host: 199.106.103.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238547186 15538 127.0.0.1 (1 Apr 2009 00:53:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Apr 2009 00:53:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prm.googlegroups.com; posting-host=199.106.103.254; posting-account=6Kx63AoAAACkFE--mLoZ7ndlx2za5jpX User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:784 I have following hierarchy: TB(VHDL) - DUT(VHDL) - Block(Verilog) - Sub-block(VHDL). the sub-block(vhdl) has a dummy architecture that I want to use. How can I write my VHDL configuration from the TB in order to use the dummy architecture of the sub-block? Thanks, Anand. From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!o11g2000yql.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: Generic-default : simulation vs. synthesis Date: Wed, 1 Apr 2009 00:24:26 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <2648eea3-8b8d-42ba-b5d1-5ea328382eea@o11g2000yql.googlegroups.com> References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238570667 5668 127.0.0.1 (1 Apr 2009 07:24:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Apr 2009 07:24:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yql.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:785 Hi, your solutions BOTH work for me, thank you. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!news.astraweb.com!border5.newsrouter.astraweb.com!border2.nntp.ams.giganews.com!nntp.giganews.com!pe2.news.blueyonder.co.uk!blueyonder!pe1.news.blueyonder.co.uk!blueyonder!text.news.virginmedia.com!53ab2750!not-for-mail From: Dave Farrance Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Organization: Farry's Pad Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 Date: Wed, 01 Apr 2009 08:21:22 GMT NNTP-Posting-Host: 92.233.41.32 X-Complaints-To: http://netreport.virginmedia.com X-Trace: text.news.virginmedia.com 1238574082 92.233.41.32 (Wed, 01 Apr 2009 09:21:22 BST) NNTP-Posting-Date: Wed, 01 Apr 2009 09:21:22 BST Xref: news.eternal-september.org comp.lang.vhdl:786 Tricky wrote: >I just overheard the following (or thereabouts) > >using the following template: >process(clk, en) > begin > if en = '1' then > if rising_edge(clk) then > d <= b; > end if; > end if; > end process; > >is better than the "normal" way > >process(clk) > begin > if rising_edge(clk) then > if en = '1' then > c <= a; > end if; > end if; > end process; > >because the 2nd can produce latches where the clock is gated with Looking at that, I'd guess that you meant 1st not 2nd. From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!v1g2000prd.googlegroups.com!not-for-mail From: thvignesh@gmail.com Newsgroups: comp.lang.vhdl Subject: sexy actress movies &videos free download Date: Wed, 1 Apr 2009 02:19:26 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: NNTP-Posting-Host: 59.99.72.46 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238577567 16446 127.0.0.1 (1 Apr 2009 09:19:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Apr 2009 09:19:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v1g2000prd.googlegroups.com; posting-host=59.99.72.46; posting-account=f-TPYwoAAAA4CKziRhFHX501oUgiOxUZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:787 sexy actress movies &videos free download http://vigneshshann.blogspot.com http://vigneshshann.blogspot.com From newsfish@newsfish Wed Aug 19 13:24:00 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!a7g2000yqk.googlegroups.com!not-for-mail From: K Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Wed, 1 Apr 2009 07:17:33 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <882c76f9-2648-407c-93da-ff358b6c2cb2@a7g2000yqk.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.237.142.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238595453 9571 127.0.0.1 (1 Apr 2009 14:17:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Apr 2009 14:17:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a7g2000yqk.googlegroups.com; posting-host=194.237.142.6; posting-account=tYtuQQoAAAAw1sZqB08z1PUqtMe8owie User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.0; sv-SE; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:788 On Mar 31, 5:34=A0pm, Tricky wrote: > I just overheard the following (or thereabouts) > > using the following template: > process(clk, en) > =A0 begin > =A0 =A0 if en =3D '1' then > =A0 =A0 =A0 if rising_edge(clk) then > =A0 =A0 =A0 =A0 d <=3D b; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > is better than the "normal" way > > process(clk) > =A0 begin > =A0 =A0 if rising_edge(clk) then > =A0 =A0 =A0 if en =3D '1' then > =A0 =A0 =A0 =A0 c <=3D a; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > because the 2nd can produce latches where the clock is gated with > enable? has this ever been the case? running either through quartus > produces the same (expected) thing - a d-type with enable. > > Are there some other legends out there that still influence design > today? were they really a problem, have they actually been fixed? The second example is the way to write it if you want a regular DFF without asynchronous reset and with a clock enable. Usually the clock enable is synthesised with a feedback mux. However, today most tools have the possibility to do this with a clock gate latch instead (ie the clock to the DFF is gated when en =3D '0' and the old value is kept). I know that some tools do this by default (the FPGA tool we use does this, and we usually turn it off to improve timing). However for ASIC synthesis the automatic clockgating is disabled by default. We work in a low-power process, then automatic clock gating is a simple and safe way to save power (for a minor penalty in timing) so we use it. The first version you gave I'm less certain about, it doesn't match any of the default DFF or DLAT patterns i've seen. But I guess since the en signal is in the sensitivity list and is before the clock it can be considered an asynchronous signal, so synthesis tools would not try to do clock gate insertion on this since the clock gating has to be synchonous with the clock. From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.buerger.net!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> From: Paul Subject: Re: More synthesis myths? Newsgroups: comp.lang.vhdl Date: Wed, 01 Apr 2009 22:05:28 +0200 References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> User-Agent: KNode/0.10.9 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 35 NNTP-Posting-Host: 82.95.144.6 X-Trace: 1238616328 dreader26.news.xs4all.nl 3580 [::ffff:82.95.144.6]:65487 Xref: news.eternal-september.org comp.lang.vhdl:789 Tricky wrote: > I just overheard the following (or thereabouts) > > using the following template: > process(clk, en) > begin > if en = '1' then > if rising_edge(clk) then > d <= b; > end if; > end if; > end process; > > is better than the "normal" way > > process(clk) > begin > if rising_edge(clk) then > if en = '1' then > c <= a; > end if; > end if; > end process; > > because the 2nd can produce latches where the clock is gated with > enable? has this ever been the case? running either through quartus > produces the same (expected) thing - a d-type with enable. Why should 'en' be included in the sensitivity list in the first template? It just does not make sense to me. Or does this fall under the "or thereabouts"? -- Paul From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <49d3e234$0$3561$e4fe514c@dreader32.news.xs4all.nl> From: Paul Subject: Re: Why do shared variables HAVE to be a protected type? Newsgroups: comp.lang.vhdl Date: Wed, 01 Apr 2009 23:52:52 +0200 References: <7699939d-dd15-4161-80fe-8634f161c0a4@t3g2000yqa.googlegroups.com> User-Agent: KNode/0.10.9 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 50 NNTP-Posting-Host: 82.95.144.6 X-Trace: 1238622772 dreader32.news.xs4all.nl 3561 [::ffff:82.95.144.6]:49995 Xref: news.eternal-september.org comp.lang.vhdl:790 Jonathan Bromley wrote: > Actually VHDL-93 vs. VHDL >= 2000. VHDL-93 shared variables > were unprotected, and known to be unsafe. Like sharp knives, > guns and WMDs, unsafe things can be extremely useful when > deployed with care by the right people :-) Even protected shared variables are unsafe. Let's assume 'count' is a shared protected variable and has some accessors like inc, set and get. Then write something along these lines: p1: process is begin count.set(1); wait; end process p1; p2: process is begin count.set(2); wait; end process p2; p3: process is variable v1, v2: natural; begin v1 := count.get; wait for 1 ns; v2 := count.get; wait; end process p3; After 1 ns, what are the values of v1 and v2? v1 can either be 0 (asuming that is the initial value of count), 1 or 2. v2 can either be 1 or 2. There are of course good uses to shared (protected) variables. But undeterminism can be introduced all too easy. The way in which protected types are save is that their accessor subprograms are executed atomically. Its flow of execution cannot be interrupted by the execution of another process that also accesses the same shared variable. At least, that is what I remember. Correct me if I'm wrong. -- Paul From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!f19g2000yqo.googlegroups.com!not-for-mail From: knight Newsgroups: comp.lang.vhdl Subject: Maximum Frequency Date: Thu, 2 Apr 2009 02:35:26 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <9e46d517-579e-4034-9f8c-531f344153fc@f19g2000yqo.googlegroups.com> NNTP-Posting-Host: 59.92.153.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238664926 16300 127.0.0.1 (2 Apr 2009 09:35:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 09:35:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f19g2000yqo.googlegroups.com; posting-host=59.92.153.163; posting-account=Du942woAAAB-YUaZ4ycYC_1tgUkVDBDH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.18) Gecko/20081029 Firefox/2.0.0.18,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxy.deeopl.com:2005 (squid/2.5.STABLE3) Xref: news.eternal-september.org comp.lang.vhdl:791 Hi all, Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum frequency of more than 400 Mhz. But when i combine everything iam getting only 121Mhz. Can you tell me the reason...??? Does this mean i cannot use a clock more than 121 Mhz in my design(iam using and found it working well..) How can i increase my timing for high frequencies..?? Iam providing the synthesis report here. Can you tell me what is the Maximum frequency mentioned here..? Timing Summary: --------------- Speed Grade: -1 Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) Minimum input arrival time before clock: 3.043ns Maximum output required time after clock: 3.281ns Maximum combinational path delay: 2.072ns I want to acheive minimum 400Mhz for my entire design.... Is it possible...? That is my target.... Do comment... From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e10g2000vbe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Maximum Frequency Date: Thu, 2 Apr 2009 05:35:14 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <8dc37faa-fa02-41ff-a3e9-e22892989f7e@e10g2000vbe.googlegroups.com> References: <9e46d517-579e-4034-9f8c-531f344153fc@f19g2000yqo.googlegroups.com> NNTP-Posting-Host: 82.31.160.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238675714 18237 127.0.0.1 (2 Apr 2009 12:35:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 12:35:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e10g2000vbe.googlegroups.com; posting-host=82.31.160.216; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:792 On Apr 2, 10:35=A0am, knight wrote: > Hi all, > > Iam using Xilinx XST for synthesis. > Iam using almost 20 modules in my design. > each if i synthesize seperately iam getting a maximum frequency of > more than 400 Mhz. But when i combine everything iam getting > only 121Mhz. > > Can you tell me the reason...??? > Does this mean i cannot use a clock more than 121 Mhz in my design(iam > using and found it working well..) > How can i increase my timing for high frequencies..?? > Iam providing the synthesis report here. > Can you tell me what is the Maximum frequency mentioned here..? > > Timing Summary: > --------------- > Speed Grade: -1 > > =A0 =A0Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) > =A0 =A0Minimum input arrival time before clock: 3.043ns > =A0 =A0Maximum output required time after clock: 3.281ns > =A0 =A0Maximum combinational path delay: 2.072ns > > I want to acheive minimum 400Mhz for my entire design.... Is it > possible...? That is my target.... > Do comment... When you only have 1 module in the design the syntheisiser has the entire chip to put a single module in. When you put 20 together, there is obviously more of the chip used, and depending on the connections, the slowest time between 2 registers is 121Mhz. The timing analyser gives you the worst case speed, ie. the largest delay over the entire design. It may work at a higher frequency for verious reasons, but it is best to try and obay the timing analyser. To make it clock faster, you will have to go through and identify the slowest path, and minimise the logic between registers. From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!f37g2000vbf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Maximum Frequency Date: Thu, 2 Apr 2009 06:47:12 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: <25f222e4-7d06-4d81-953e-0b8575f3360a@f37g2000vbf.googlegroups.com> References: <9e46d517-579e-4034-9f8c-531f344153fc@f19g2000yqo.googlegroups.com> <8dc37faa-fa02-41ff-a3e9-e22892989f7e@e10g2000vbe.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238680032 32165 127.0.0.1 (2 Apr 2009 13:47:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 13:47:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f37g2000vbf.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:793 On Apr 2, 7:35=A0am, Tricky wrote: > On Apr 2, 10:35=A0am, knight wrote: > > > > > > > Hi all, > > > Iam using Xilinx XST for synthesis. > > Iam using almost 20 modules in my design. > > each if i synthesize seperately iam getting a maximum frequency of > > more than 400 Mhz. But when i combine everything iam getting > > only 121Mhz. > > > Can you tell me the reason...??? > > Does this mean i cannot use a clock more than 121 Mhz in my design(iam > > using and found it working well..) > > How can i increase my timing for high frequencies..?? > > Iam providing the synthesis report here. > > Can you tell me what is the Maximum frequency mentioned here..? > > > Timing Summary: > > --------------- > > Speed Grade: -1 > > > =A0 =A0Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) > > =A0 =A0Minimum input arrival time before clock: 3.043ns > > =A0 =A0Maximum output required time after clock: 3.281ns > > =A0 =A0Maximum combinational path delay: 2.072ns > > > I want to acheive minimum 400Mhz for my entire design.... Is it > > possible...? That is my target.... > > Do comment... > > When you only have 1 module in the design the syntheisiser has the > entire chip to put a single module in. When you put 20 together, there > is obviously more of the chip used, and depending on the connections, > the slowest time between 2 registers is 121Mhz. The timing analyser > gives you the worst case speed, ie. the largest delay over the entire > design. It may work at a higher frequency for verious reasons, but it > is best to try and obay the timing analyser. To make it clock faster, > you will have to go through and identify the slowest path, and > minimise the logic between registers.- Hide quoted text - > > - Show quoted text - Another potential reason for the difference is if your individual blocks have combinatorial input and/or output paths (i.e. gates before the first input register, or after the last output register) that may not be timing constrained, because they don't fall under the nominal clock-clock constraint when the module is synthesized by itself (different tools handle this differently). Put that module in a larger design, where the combinatorial output paths get tied to registered (or worse, combinatorial) input paths on another module, and suddenly those paths are now constrained, and start driving the overall max clock rate. If you have a module that has combinatorial input and/or output paths, it is best to put it in a wrapper that inserts registers on all inputs and outputs for performance evaluation. Note that this does not help if your design feeds a combinatorial output from one module into a combinatorial input on another. The propagation delays add together. Most folks tend to avoid combinatorial outputs on modules, to avoid instances where input and output delays sum together between modules. Andy From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!v6g2000vbb.googlegroups.com!not-for-mail From: Massi Newsgroups: comp.lang.vhdl Subject: Store register instantiation Date: Thu, 2 Apr 2009 07:12:42 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <5ff79e80-240f-4584-83d6-d983b8be9d83@v6g2000vbb.googlegroups.com> NNTP-Posting-Host: 150.145.1.64 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238681562 29206 127.0.0.1 (2 Apr 2009 14:12:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 14:12:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v6g2000vbb.googlegroups.com; posting-host=150.145.1.64; posting-account=WWUlQQoAAAA7X1fJ_0M7jreoB5ymf0dg User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:794 Hi everyone, I'm really new to the vhdl world, so I apologize if my question is trivial. I'm working on xilinx Virtex 5 FPGA with ISE 10.1. My module receives a 16 bit input data and I would like to store it into a register, without using any RAM block. Which is the simplest way to instantiate such a simple store register? Is there any primitive? Thanks in advance. From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.82.MISMATCH!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-ID: <49D4D5E6.20600@xs4all.nl> Date: Thu, 02 Apr 2009 17:12:38 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Massi Subject: Re: Store register instantiation References: <5ff79e80-240f-4584-83d6-d983b8be9d83@v6g2000vbb.googlegroups.com> In-Reply-To: <5ff79e80-240f-4584-83d6-d983b8be9d83@v6g2000vbb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 39 NNTP-Posting-Host: 80.127.156.245 X-Trace: 1238685158 news.xs4all.nl 184 [::ffff:80.127.156.245]:54264 X-Complaints-To: abuse@xs4all.nl Xref: news.eternal-september.org comp.lang.vhdl:795 Massi wrote: > Hi everyone, I'm really new to the vhdl world, so I apologize if my > question is trivial. I'm working on xilinx Virtex 5 FPGA with ISE > 10.1. My module receives a 16 bit input data and I would like to store > it into a register, without using any RAM block. Which is the simplest > way to instantiate such a simple store register? Is there any > primitive? > Thanks in advance. A simple FF should do the trick: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY example IS PORT ( clk : std_logic; data_in : std_logic_vector(15 DOWNTO 0) ); END ENTITY example; ARCHITECTURE rtl OF example IS SIGNAL data_in_i : std_logic_vector(15 DOWNTO 0); BEGIN input_reg: PROCESS IS BEGIN WAIT UNTIL clk = '1'; data_in_i <= data_in; END PROCESS input_reg; END ARCHITECTURE rtl; Kind regards, Pieter Hulshoff From newsfish@newsfish Wed Aug 19 13:24:01 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!r28g2000vbp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Store register instantiation Date: Thu, 2 Apr 2009 08:55:57 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: References: <5ff79e80-240f-4584-83d6-d983b8be9d83@v6g2000vbb.googlegroups.com> <49D4D5E6.20600@xs4all.nl> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238687757 24948 127.0.0.1 (2 Apr 2009 15:55:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 15:55:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r28g2000vbp.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:796 On Apr 2, 10:12=A0am, Pieter Hulshoff wrote: > =A0 input_reg: PROCESS IS > =A0 BEGIN > =A0 =A0 WAIT UNTIL clk =3D '1'; > =A0 =A0 data_in_i <=3D data_in; > =A0 END PROCESS input_reg; I stronly agree with inferring a register, rather than instantiating one. Instantiated primitive names are often not portable across differen devices. There are lots of ways to infer a register; the simplest is probably: data_in_i <=3D data_in when rising_edge(clk); -- concurrent statement, no process needed Where data_in_i is the output of the inferred register. However, I believe a more standard (and more appropriate for new users) process template for inferring one or more registers is as follows: input_reg: process (clk) is begin if rising_edge(clk) then data_in_i <=3D data_in; end if; end process; The rising_edge() function specifically avoids simulation problems from strange transitions on the clock signal. Pieter's template could be improved in this regard by using "wait until rising_edge(clk);" The wait statement template is more difficult to add an asynchronous reset input. For an asynchronously reset register: input_reg: process (clk, rst) is begin if rst =3D '1' then -- active high reset data_in_i <=3D (others -> '0'); elsif rising_edge(clk) then data_in_i <=3D data_in; end if; end process; Or, in the concurrent template: data_in_i <=3D (others =3D> '0') when rst =3D '1' else data_in when rising_edge(clk); All of these are roughly equivalent if all you need to do is insert a register between two other entities, etc. If you are also specifying the logic that is in between the registers, the process templates are much better suited, since you can describe the logic and the registers in the same process, at the same time. Andy From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!l1g2000yqk.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Synchronization Date: Thu, 2 Apr 2009 10:06:50 -0700 (PDT) Organization: http://groups.google.com Lines: 633 Message-ID: NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238692010 6431 127.0.0.1 (2 Apr 2009 17:06:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Apr 2009 17:06:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l1g2000yqk.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:797 Hello, Clock (clk1x) is a 100MHz clock and the VHDL program is using it to read the SDRAM. I need to load the SDRAM with the data and then send it to the Digital to Analog converter. The DAC works with 1MHz clock, 49 bits of data and a Tag signal which tells the DAC that a new 49 bit data is available. I tried to divide the 100MHz clock to 1MHz and send the data to the clock. But I am unable to see the DAC working. I hooked up the logic analyzer and looked at the signals. The Tag who should repeats itself after every 49 bits is not stable at all. it repeats multiple times during the data stream and resets the DAC. My code is given below. I am having clock synchronization problems. Please advice. John library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package mem is component memTest generic( PIPE_EN : boolean := false; -- enable pipelined operations DATA_WIDTH : natural := 16; -- memory data width ADDR_WIDTH : natural := 23; -- memory address width BEG_TEST_1 : natural := 16#00_0000#; -- beginning test range address BEG_TEST_2 : natural := 16#00_0002#; BEG_TEST_3 : natural := 16#00_0004#; BEG_TEST_4 : natural := 16#00_0006#; BEG_TEST_5 : natural := 16#00_0008#; BEG_TEST_6 : natural := 16#00_0009#; END_TEST_1 : natural := 16#3F_FFFF#; END_TEST_2 : natural := 16#3F_FFFF#; END_TEST_3 : natural := 16#3F_FFFF#; END_TEST_4 : natural := 16#3F_FFFF#; END_TEST_5 : natural := 16#3F_FFFF#; END_TEST_6 : natural := 16#7F_FFFF# -- ending test range address ); port( clk : in std_logic; -- master clock input rst : in std_logic; -- reset doAgain : in std_logic; -- re-do memory test begun : in std_logic; -- memory operation begun indicator done : in std_logic; -- memory operation done indicator dIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from memory rdPending: in std_logic; -- read operations in progress indicator rd : out std_logic; -- memory read control signal wr : out std_logic; -- memory write control signal addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); -- address to memory dOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to memory progress : out std_logic_vector(1 downto 0); -- memory test progress indicator err : out std_logic; -- memory error flag Logic_port: out std_logic_vector(DATA_WIDTH-1 downto 0); Trigger : out std_logic; -- lock_in : in std_logic; clk1x : in std_logic; clk_out : out std_logic; ser_out : out std_logic; done_1 : out std_logic; done_2 : out std_logic; done_3 : out std_logic; -- Signals for Six more Phil's Chips -- ser_out_1 : out std_logic; sclk_1 : out std_logic; Dclk_1 : out std_logic; Tag_1 : out std_logic; ser_out_2 : out std_logic; sclk_2 : out std_logic; Dclk_2 : out std_logic; Tag_2 : out std_logic; ser_out_3 : out std_logic; sclk_3 : out std_logic; Dclk_3 : out std_logic; Tag_3 : out std_logic; ser_out_4 : out std_logic; sclk_4 : out std_logic; Dclk_4 : out std_logic; Tag_4 : out std_logic; ser_out_5 : out std_logic; sclk_5 : out std_logic; Dclk_5 : out std_logic; Tag_5 : out std_logic ); end component; end package mem; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; use WORK.common.all; use WORK.rand.all; entity memTest is generic( PIPE_EN : boolean := false; -- enable pipelined operations DATA_WIDTH : natural := 16; -- memory data width ADDR_WIDTH : natural := 23; -- memory address width BEG_TEST_1 : natural := 16#00_0000#; -- beginning test range address BEG_TEST_2 : natural := 16#00_0002#; BEG_TEST_3 : natural := 16#00_0004#; BEG_TEST_4 : natural := 16#00_0006#; BEG_TEST_5 : natural := 16#00_0008#; BEG_TEST_6 : natural := 16#00_0009#; END_TEST_1 : natural := 16#3F_FFFF#; END_TEST_2 : natural := 16#3F_FFFF#; END_TEST_3 : natural := 16#3F_FFFF#; END_TEST_4 : natural := 16#3F_FFFF#; END_TEST_5 : natural := 16#3F_FFFF#; END_TEST_6 : natural := 16#7F_FFFF# -- ending test range address ); port( clk : in std_logic; -- master clock input rst : in std_logic; -- reset doAgain : in std_logic; -- re-do memory test begun : in std_logic; -- memory operation begun indicator done : in std_logic; -- memory operation done indicator dIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from memory rdPending : in std_logic; -- read operations in progress indicator rd : out std_logic; -- memory read control signal wr : out std_logic; -- memory write control signal addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); -- address to memory dOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to memory progress : out std_logic_vector(1 downto 0); -- memory test progress indicator err : out std_logic; -- memory error flag Logic_port : out std_logic_vector(DATA_WIDTH-1 downto 0); Trigger : out std_logic; clk1x : in std_logic; clk_out : out std_logic; ser_out : out std_logic; done_1 : out std_logic; done_2 : out std_logic; done_3 : out std_logic; -- Signals for Six more Phil's Chip -- ser_out_1 : out std_logic; sclk_1 : out std_logic; Dclk_1 : out std_logic; Tag_1 : out std_logic; ser_out_2 : out std_logic; sclk_2 : out std_logic; Dclk_2 : out std_logic; Tag_2 : out std_logic; ser_out_3 : out std_logic; sclk_3 : out std_logic; Dclk_3 : out std_logic; Tag_3 : out std_logic; ser_out_4 : out std_logic; sclk_4 : out std_logic; Dclk_4 : out std_logic; Tag_4 : out std_logic; ser_out_5 : out std_logic; sclk_5 : out std_logic; Dclk_5 : out std_logic; Tag_5 : out std_logic ); end memTest; architecture arch of memTest is type matrix is array ( 47 downto 0) of bit; --states of the memory tester state machine type testState is ( INIT, Ser_buff_LOAD_1, Ser_buff_LOAD_2, Ser_buff_LOAD_3, Ser_buff_LOAD_4, EMPTY_PIPE, STOP, ser_out_state, extra_state, First_byte, Second_byte, Third_byte, Reset_state, Tag_state, extra_Tag_state ); signal state_r, state_x : testState; -- state register and next state --registers signal addr_r, addr_x : unsigned(addr'range); signal err_r,err_x :std_logic; --Internal signals signal ld : std_logic; signal cke: std_logic; signal rand :std_logic_vector (dOut'range); signal seed :std_logic_vector (dIn'range); signal ser_buff : std_logic_vector (47 downto 0); signal p2s_counter : unsigned (5 downto 0); signal count_begin :std_logic; signal count_load : std_logic; signal d1,d2,d3 : std_logic; -- Signals to load the data buffers signal Reset_counter : std_logic; signal p2s: std_logic_vector (5 downto 0); signal co : std_logic_vector (5 downto 0); signal xser_out : std_logic; signal Tag : std_logic; signal clk_divider : std_logic_vector ( 10 downto 0); signal clk_a, a,b,c,clk_b : std_logic; signal Tag_fall,dummy_clk,clk_out_1, Tag2, t2, Tag3, t3,D_2clk,Q_2clk : std_logic; signal D,Q,d_1 : std_logic; signal slow_clk : std_logic; signal count : std_logic_vector ( 6 downto 0); signal Tag_sig : std_logic; signal ser_out_sig_1: std_logic; signal ser_out_sig_2: std_logic; signal clk_delay : std_logic; signal Tag_out_2, Tag_out_1,Tag_out_0 : std_logic; signal Reset_counter_0, Reset_counter_1,final_reset,clk_synch,synch_reset,synch_reset_2 : std_logic; signal Reset_synch_0,Reset_synch_1,Reset_synch_2,Reset_synch_3 : std_logic; ---Second State Machine -- Type Pulse_state is ( seek, find); Signal status : PULSE_STATE; Signal Pulse_out : std_logic; Signal Pulse_out_1 : std_logic; Signal Pulse_out_2 : std_logic; Begin seed <= (others => '1');-- random number seed is 111...111 u0 : randGen generic map( DATA_WIDTH => seed'length ) port map( clk => clk, -- input clock cke => cke, -- clock-enable to control when new random num is computed ld => ld, -- load seed control signal seed => seed, -- random number seed rand => rand -- random number output from generator ); ------------------------------------------------------------------------------------ addr <= std_logic_vector(addr_r); -- linear memory addressing clk_b <= clk_divider(6); done_1 <= synch_reset ;-- Tag done_3 <= clk_synch when synch_reset ='0' else '0'; -- DCLK clk_out <= clk_divider(5); -- SCLK ----------------------------------------------------------------------------------- -- memory test controller state machine operations combinatorial : process(err_r, addr_r, dIn, rand, begun, done, rdPending, doAgain ) begin -- default operations (do nothing unless explicitly stated in the following case statement) rd <= NO; -- no memory write wr <= NO; -- no memory read ld <= NO; -- don't load the random number generator cke <= NO; -- don't generate a new random number addr_x <= addr_r; -- next address is the same as current address err_x <= err_r; -- error flag is unchanged state_x <= state_r; -- no change in memory tester state -- **** compute the next state and operations **** case state_r is ------------------------------------------------------ -- initialize the memory test controller ------------------------------------------------------ when INIT => ld <= YES; -- load random number seed cke <= YES; -- enable clocking of rand num gen so seed gets loaded addr_x <= TO_UNSIGNED(BEG_TEST_1, addr_x'length); -- load starting mem address err_x <= NO; -- clear memory error flag state_x <= Ser_buff_LOAD_1; -- next go to LOAD state and write pattern to memory progress <= "00"; -- indicate the current controller state Reset_counter <= '1'; count_begin <= '0'; when Ser_buff_LOAD_1 => -- re-run the generator and compare it to memory contents Reset_counter <= '1'; if PIPE_EN then rd <= YES; if begun = YES then addr_x <= addr_r + 1; -- increment address to check next memory location end if; if addr_r = END_TEST_1 then state_x <= EMPTY_PIPE; end if; if done = YES then cke <= YES; end if; else if done = NO then -- current read operation is not complete rd <= YES; -- keep read signal active since memory read is not done count_begin <='0'; else rd <= NO; d1 <='1'; -- Loaded first set of buffer d2 <='0'; d3 <='0'; count_begin <='0'; state_x <= Ser_buff_LOAD_2; if addr_r= END_TEST_1 then state_x <= STOP; -- go to STOP state once entire range has been checked end if; addr_x <= addr_r + 1; -- increment address to check next memory location cke <= YES; End if; End if; ------------------------------------ When Ser_buff_LOAD_2 => Reset_counter <='1'; if PIPE_EN then rd <= YES; if begun = YES then addr_x <= addr_r + 1; -- increment address to check next memory location end if; if addr_r = END_TEST_1 then state_x <= EMPTY_PIPE; end if; if done = YES then cke <= YES; end if; else if done = NO then -- current read operation is not complete rd <= YES; -- keep read signal active since memory read is not done count_begin <='0'; else rd <= NO; d1 <='0'; d2 <='1'; -- Loaded Second set of buffer d3 <='0'; count_begin <='0'; state_x <= Ser_buff_LOAD_3; if addr_r= END_TEST_1 then state_x <= STOP; -- go to STOP state once entire range has been checked end if; addr_x <= addr_r + 1; -- increment address to check next memory location cke <= YES; End if; End if; --------------------------------------------- When Ser_buff_LOAD_3 => if PIPE_EN then rd <= YES; if begun = YES then addr_x <= addr_r + 1; -- increment address to check next memory location end if; if addr_r = END_TEST_1 then state_x <= EMPTY_PIPE; end if; if done = YES then cke <= YES; end if; else if done = NO then -- current read operation is not complete rd <= YES; -- keep read signal active since memory read is not done count_begin <='0'; else rd <= NO; d1 <='0'; d2 <='0'; d3 <='1'; -- Loaded Third set of buffer count_begin <='0'; state_x <= Reset_state; if addr_r= END_TEST_1 then state_x <= STOP; -- go to STOP state once entire range has been checked end if; addr_x <= addr_r + 1; -- increment address to check next memory location cke <= YES; End if; End if; ---------------------------------------------- when Reset_state => progress <= "10"; -- indicate the current controller state d1<='0'; d2<='0'; d3<='0'; Reset_counter <='1'; rd<=NO; count_begin<='0'; state_x<= Tag_state; -------------------------------------------- when Tag_state => -- Is this an extra state d1 <= '0'; d2 <= '0'; d3 <= '0'; Reset_counter <='0'; rd<=NO; count_begin <= '0'; state_x <= ser_out_state; ---------------------------------------- when ser_out_state => Reset_counter <='0'; if ( p2s_counter /= "110001") then rd <= NO; count_begin <= '1'; Reset_counter <='0'; state_x <= ser_out_state; else state_x <= Ser_buff_LOAD_1; end if; --------------------------------------- When EMPTY_PIPE => Reset_counter <='1'; if done = YES then cke <= YES; end if; if rdPending = NO then state_x <= STOP; end if; ------------------------------------ When others => if doAgain = YES then Reset_counter <='1'; ld <= YES; cke <= YES; addr_x <= TO_UNSIGNED (BEG_TEST_1, addr_x'length); count_begin <='0'; state_x <= INIT; end if; end case; end process; ------------------------------------ -- clk1x is the main clock generated by xess's program update: process (clk1x) begin if clk1x'event and clk1x = '1' then if rst = YES then -- main reset from xess's program state_r <= INIT; else addr_r <= addr_x; state_r <= state_x; end if; end if; end process; ------------------------------------ -- Filling the Buffers with memory data trig: process ( clk1x) begin if clk1x'event and clk1x = '1' then if ( done = YES ) then if ( d1 = '1') then ser_buff ( 15 downto 0) <= dIn ( 15 downto 0); --ser_buff ( 15 downto 0) <= "1010101010101010"; a <='1'; b <='0'; c <= '0'; elsif ( d2 = '1' ) then ser_buff ( 31 downto 16 ) <= dIn ( 15 downto 0); --ser_buff ( 31 downto 16 ) <= "1010101010101010"; a <= '0'; b <= '1'; c <= '0'; elsif ( d3 = '1') then ser_buff ( 47 downto 32 ) <= dIn ( 15 downto 0); --ser_buff ( 47 downto 32 ) <= "1010101010101010"; a <= '0'; b <= '0'; c <= '0'; else a <='0'; b <='0'; c <='0'; end if; end if; end if; end process; -------------------------------------- -- Synchronizing the Reset counter of the state machine.. Reset_synch: process ( clk1x,rst) Begin if (rst= '1') then clk_synch <= '0'; elsif rising_edge (clk1x) then clk_synch <= clk_b; end if; end process; ------------------------------------- serial_count : process (synch_reset , clk_synch) begin if ( synch_reset = '1') Then p2s_counter <= ( others =>'0'); elsif falling_edge (clk_synch) then p2s_counter <= p2s_counter + 1; --ser_out<=ser_buff ( to_integer ( p2s_counter ) ); else end if; end process; ------------------------------------ -- Synchronizing the state machine "Reset counter" with the DCLK-- process(clk_synch, Reset_counter) begin If (Reset_counter = '1') Then synch_reset_2 <='1'; elsif rising_edge (clk_synch) then synch_reset_2 <= Reset_counter; end if; end process; ------------------------------------ process(clk_synch, synch_reset_2) begin If ( synch_reset_2 = '1') Then synch_reset <='1'; elsif rising_edge (clk_synch) then synch_reset <= synch_reset_2; end if; end process; ----------------------------------- div : process ( rst,clk1x) begin If ( rst = '1') Then clk_divider <= "00000000000"; elsIf rising_edge (clk1x) then clk_divider <= clk_divider + 1; end if; end process; --------------------------------- End arch; From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: "Symon" Newsgroups: comp.lang.vhdl Subject: Re: Synchronization Date: Fri, 3 Apr 2009 15:04:25 +0100 Organization: A noiseless patient Spider Lines: 5 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX18PSlFQpIQn9h+LRVzMVHZ9ubJPc8btTfQVtR1XGDoCicYuyi8i+zc5ceI2J+9pyan51ne+KPHyXiKdptyaHqrhSisckETdEKPTNGJRpydL6ux+ZyEhoLSK+uKtSaQeKuc= X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Fri, 3 Apr 2009 14:04:38 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX19j6gsuwRxuHRajfWe09eNkTzGD0OKwgLs= Cancel-Lock: sha1:F3/Zzh5vX9zRhbwcHgtRJkxxVrU= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:798 Hi John, Use a simulator. HTH., Syms. From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Synchronization Date: Fri, 03 Apr 2009 09:12:00 -0700 Lines: 14 Message-ID: <49D63550.9020305@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net WbUHodtDG5JHm9Eyp15IwAMBFUduf0azjGdg8xtHu/bfetsrga Cancel-Lock: sha1:QVc+G0VRQEpHnd2he9EU//S+gB4= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:799 john wrote: > Clock (clk1x) is a 100MHz clock and the VHDL program is using it to > read the SDRAM. I need to load the SDRAM with the data and then send > it to the Digital to Analog converter. The DAC works with 1MHz clock, > 49 bits of data and a Tag signal which tells the DAC that a new 49 bit > data is available. I tried to divide the 100MHz clock to 1MHz and send > the data to the clock. But I am unable to see the DAC working. A 100MHz process running on the fpga ought to be fast enough to handshake synchronously with a 1 MHz dac. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc02.gnilink.net.POSTED!3e6d510d!not-for-mail From: Marc Guardiani Reply-To: news.guardiani@gmail.com User-Agent: Thunderbird 2.0.0.17 (X11/20090201) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> In-Reply-To: <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 36 Message-ID: Date: Fri, 03 Apr 2009 23:57:25 GMT NNTP-Posting-Host: 173.75.43.206 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1238803045 173.75.43.206 (Fri, 03 Apr 2009 19:57:25 EDT) NNTP-Posting-Date: Fri, 03 Apr 2009 19:57:25 EDT Xref: news.eternal-september.org comp.lang.vhdl:800 Paul wrote: > Tricky wrote: > >> I just overheard the following (or thereabouts) >> >> using the following template: >> process(clk, en) >> begin >> if en = '1' then >> if rising_edge(clk) then >> d <= b; >> end if; >> end if; >> end process; >> >> is better than the "normal" way >> >> process(clk) >> begin >> if rising_edge(clk) then >> if en = '1' then >> c <= a; >> end if; >> end if; >> end process; >> >> because the 2nd can produce latches where the clock is gated with >> enable? has this ever been the case? running either through quartus >> produces the same (expected) thing - a d-type with enable. > > Why should 'en' be included in the sensitivity list in the first > template? It just does not make sense to me. Or does this fall under > the "or thereabouts"? As I understand processes, 'en' is in the sensitivity list because you want the process to "run", so to speak, whenever it changes. From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!nlpi057.nbdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi068.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> Subject: Re: More synthesis myths? Lines: 20 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi068.nbdc.sbc.com 1238806171 ST000 99.184.242.197 (Fri, 03 Apr 2009 20:49:31 EDT) NNTP-Posting-Date: Fri, 03 Apr 2009 20:49:31 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[OER[ODPRUORRPXIZOD]_\@VR]^@B@MCPWZKB]MPXHBTWICYFWUQBKZQLYJX\_ITFD_KFVLUN[DOM_A_NSYNWPFWNS[XV\I]PZ@BQ[@CDQDPCL^FKCBIPC@KLGEZEFNMDYMKHRL_YYYGDSSODXYN@[\BK[LVTWI@AXGQCOA_SAH@TPD^\AL\RLGRFWEARBM Date: Fri, 3 Apr 2009 20:49:28 -0400 Xref: news.eternal-september.org comp.lang.vhdl:801 >> Why should 'en' be included in the sensitivity list in the first >> template? It just does not make sense to me. Or does this fall under >> the "or thereabouts"? > > As I understand processes, 'en' is in the sensitivity list because you > want the process to "run", so to speak, whenever it changes. Since the very next statement is "if rising_edge(clk) then..." the process certainly won't be running too far... >From a synthesis perspective including (or not including) 'en' makes no difference. From a simulation perspective, including 'en' in the sensitivity list will make that process chew up some miniscule extra bit of processor time, but everything will simulate exactly the same. Kevin From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!y6g2000prf.googlegroups.com!not-for-mail From: mightycatniyander@gmail.com Newsgroups: comp.lang.vhdl Subject: how to write SD ram Date: Sun, 5 Apr 2009 00:30:53 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: <870cb907-22be-41b4-8f6e-326e27a82f6d@y6g2000prf.googlegroups.com> NNTP-Posting-Host: 59.95.111.55 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1238916653 16376 127.0.0.1 (5 Apr 2009 07:30:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Apr 2009 07:30:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y6g2000prf.googlegroups.com; posting-host=59.95.111.55; posting-account=W-Z0OQoAAABTlmAqUoVxZybmc-jZmCQr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:802 hi this is the top level design of the SDRAM controller, can some one point me out how to read data, process it (for ex: addition, subtraction, etc) and write it back to memory. I know it can be done with the sData signal, but how i don't know. library IEEE; use IEEE.std_logic_1164.all; use WORK.test_board_core_pckg.all; entity test_board is port( ce_n : out std_logic; -- Flash RAM chip-enable sw2 : in std_logic; -- active-low pushbutton input clk : in std_logic; -- main clock input from external clock source sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays sclk : out std_logic; -- clock to SDRAM cke : out std_logic; -- SDRAM clock-enable cs_n : out std_logic; -- SDRAM chip-select ras_n : out std_logic; -- SDRAM RAS cas_n : out std_logic; -- SDRAM CAS we_n : out std_logic; -- SDRAM write-enable ba : out std_logic_vector( 1 downto 0); -- SDRAM bank- address sAddr : out std_logic_vector(12 downto 0); -- SDRAM address bus sData : inout std_logic_vector(15 downto 0); -- data bus to/from SDRAM dqmh : out std_logic; -- SDRAM DQMH dqml : out std_logic; -- SDRAM DQML s : out std_logic_vector(6 downto 0); -- 7-segment LED pps : out std_logic_vector(6 downto 3) -- outputs to parallel port status bits ); end entity; architecture arch of test_board is begin ce_n <= '1'; -- disable Flash RAM u0 : test_board_core generic map( FREQ => 100_000, PIPE_EN => true, DATA_WIDTH => sData'length, SADDR_WIDTH => sAddr'length, NROWS => 8192, NCOLS => 512, BEG_ADDR => 16#00_0000#, END_ADDR => 16#FF_FFFF#, BEG_TEST => 16#00_0000#, END_TEST => 16#FF_FFFF# ) port map( button_n => sw2, clk => clk, sclkfb => sclkfb, sclk => sclk, cke => cke, cs_n => cs_n, ras_n => ras_n, cas_n => cas_n, we_n => we_n, ba => ba, sAddr => sAddr, sData => sData, dqmh => dqmh, dqml => dqml, led => s, heartBeat => pps(6) ); end arch; thanks From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!zen.net.uk!dedekind.zen.co.uk!news.glorb.com!postnews.google.com!r33g2000yqn.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: how to write SD ram Date: Sun, 5 Apr 2009 05:20:27 -0700 (PDT) Organization: http://groups.google.com Lines: 106 Message-ID: <3bc29fc0-a5f7-490b-bdd7-93b60f86c246@r33g2000yqn.googlegroups.com> References: <870cb907-22be-41b4-8f6e-326e27a82f6d@y6g2000prf.googlegroups.com> NNTP-Posting-Host: 74.12.60.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1238934027 6987 127.0.0.1 (5 Apr 2009 12:20:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Apr 2009 12:20:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r33g2000yqn.googlegroups.com; posting-host=74.12.60.239; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009032803 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:803 On Apr 5, 3:30=A0am, mightycatniyan...@gmail.com wrote: > hi > > this is the top level design of the SDRAM controller, can some one > point me out how to read data, process it (for ex: addition, > subtraction, etc) and write it back to memory. I know it can be done > with the sData signal, but how i don't know. > > library IEEE; > use IEEE.std_logic_1164.all; > use WORK.test_board_core_pckg.all; > > entity test_board is > =A0 port( > =A0 =A0 ce_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- Flash RAM ch= ip-enable > =A0 =A0 sw2 =A0 =A0: in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- active-l= ow pushbutton input > =A0 =A0 clk =A0 =A0: in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- main clo= ck input from > external clock source > =A0 =A0 sclkfb : in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- feedback SDR= AM clock with > PCB delays > =A0 =A0 sclk =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- clock to SDR= AM > =A0 =A0 cke =A0 =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM cloc= k-enable > =A0 =A0 cs_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM chip-s= elect > =A0 =A0 ras_n =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM RAS > =A0 =A0 cas_n =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM CAS > =A0 =A0 we_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM write-= enable > =A0 =A0 ba =A0 =A0 : out =A0 std_logic_vector( 1 downto 0); =A0-- SDRAM b= ank- > address > =A0 =A0 sAddr =A0: out =A0 std_logic_vector(12 downto 0); =A0-- SDRAM add= ress > bus > =A0 =A0 sData =A0: inout std_logic_vector(15 downto 0); =A0-- data bus to= /from > SDRAM > =A0 =A0 dqmh =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM DQMH > =A0 =A0 dqml =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM DQML > =A0 =A0 s =A0 =A0 =A0: out =A0 std_logic_vector(6 downto 0); =A0-- 7-segm= ent LED > =A0 =A0 pps =A0 =A0: out =A0 std_logic_vector(6 downto 3) =A0-- outputs t= o > parallel port status bits > =A0 =A0 ); > end entity; > > architecture arch of test_board is > begin > > =A0 ce_n <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- = disable Flash RAM > > =A0 u0 : test_board_core > =A0 =A0 generic map( > =A0 =A0 =A0 FREQ =A0 =A0 =A0 =A0=3D> 100_000, > =A0 =A0 =A0 PIPE_EN =A0 =A0 =3D> true, > =A0 =A0 =A0 DATA_WIDTH =A0=3D> sData'length, > =A0 =A0 =A0 SADDR_WIDTH =3D> sAddr'length, > =A0 =A0 =A0 NROWS =A0 =A0 =A0 =3D> 8192, > =A0 =A0 =A0 NCOLS =A0 =A0 =A0 =3D> 512, > =A0 =A0 =A0 BEG_ADDR =A0 =A0=3D> 16#00_0000#, > =A0 =A0 =A0 END_ADDR =A0 =A0=3D> 16#FF_FFFF#, > =A0 =A0 =A0 BEG_TEST =A0 =A0=3D> 16#00_0000#, > =A0 =A0 =A0 END_TEST =A0 =A0=3D> 16#FF_FFFF# > =A0 =A0 =A0 ) > =A0 =A0 port map( > =A0 =A0 =A0 button_n =A0 =A0=3D> sw2, > =A0 =A0 =A0 clk =A0 =A0 =A0 =A0 =3D> clk, > =A0 =A0 =A0 sclkfb =A0 =A0 =A0=3D> sclkfb, > =A0 =A0 =A0 sclk =A0 =A0 =A0 =A0=3D> sclk, > =A0 =A0 =A0 cke =A0 =A0 =A0 =A0 =3D> cke, > =A0 =A0 =A0 cs_n =A0 =A0 =A0 =A0=3D> cs_n, > =A0 =A0 =A0 ras_n =A0 =A0 =A0 =3D> ras_n, > =A0 =A0 =A0 cas_n =A0 =A0 =A0 =3D> cas_n, > =A0 =A0 =A0 we_n =A0 =A0 =A0 =A0=3D> we_n, > =A0 =A0 =A0 ba =A0 =A0 =A0 =A0 =A0=3D> ba, > =A0 =A0 =A0 sAddr =A0 =A0 =A0 =3D> sAddr, > =A0 =A0 =A0 sData =A0 =A0 =A0 =3D> sData, > =A0 =A0 =A0 dqmh =A0 =A0 =A0 =A0=3D> dqmh, > =A0 =A0 =A0 dqml =A0 =A0 =A0 =A0=3D> dqml, > =A0 =A0 =A0 led =A0 =A0 =A0 =A0 =3D> s, > =A0 =A0 =A0 heartBeat =A0 =3D> pps(6) > =A0 =A0 =A0 ); > > end arch; > > thanks You need two things for sure: a schematic for the board, and a datasheet for the SDRAM device in particular that you're talking to. The ports you list suggest that this is the top level interface to an SDRAM, not to a controller. You either need to find source code for a controller for your chip, or write your own (which is a good educational experience but consider it an "advanced" topic not ideally suitable for a newbie). The datasheet will tell you what you have to do with the SDRAM pins you list in order to make the memory accesses happen. - Kenn From newsfish@newsfish Wed Aug 19 13:24:02 2009 Message-ID: <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> From: Paul Subject: Re: More synthesis myths? Newsgroups: comp.lang.vhdl Date: Sun, 05 Apr 2009 22:47:22 +0200 References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> User-Agent: KNode/0.10.9 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 60 NNTP-Posting-Host: 82.95.144.6 X-Trace: 1238964443 dreader20.news.xs4all.nl 3491 [::ffff:82.95.144.6]:61651 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!x-privat.org!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!news2.euro.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:804 Marc Guardiani wrote: > Paul wrote: >> Tricky wrote: >> >>> I just overheard the following (or thereabouts) >>> >>> using the following template: >>> process(clk, en) >>> begin >>> if en = '1' then >>> if rising_edge(clk) then >>> d <= b; >>> end if; >>> end if; >>> end process; >>> >>> is better than the "normal" way >>> >>> process(clk) >>> begin >>> if rising_edge(clk) then >>> if en = '1' then >>> c <= a; >>> end if; >>> end if; >>> end process; >>> >>> because the 2nd can produce latches where the clock is gated with >>> enable? has this ever been the case? running either through >>> quartus produces the same (expected) thing - a d-type with enable. >> >> Why should 'en' be included in the sensitivity list in the first >> template? It just does not make sense to me. Or does this fall >> under the "or thereabouts"? > > As I understand processes, 'en' is in the sensitivity list because > you want the process to "run", so to speak, whenever it changes. Yes, that's correct. But why on earth would you like to run the process when 'en' changes? Functionally it just adds nothing (as KJ rightfully explained). The only thing that is added is obfuscation. For a pure synchronous process, my favorite template is: process is begin wait until clk = '1'; -- or: wait until rising_edge(clk); if en = '1' then q <= d; end if; end process; Major advantage (IMHO): at the first glance you see this is a synchronous process. Now doubt possible. Also no long winded if/end-if needed, with an additional indentation level. -- Paul Uiterlinden From newsfish@newsfish Wed Aug 19 13:24:02 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!y9g2000yqg.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Reverse function - unconstrained types Date: Mon, 6 Apr 2009 06:45:11 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239025511 9579 127.0.0.1 (6 Apr 2009 13:45:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Apr 2009 13:45:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y9g2000yqg.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:805 Hi, one possible solution to reverse an unconstrained std_logic_vector is to use the following function: function reverse(p: std_logic_vector) return std_logic_vector is variable result: std_logic_vector(p'reverse_range); begin for i in p'range loop result(i) := p(i); end loop; return result; end; Now I have the following type and signal declaration: subtype stype_data is std_logic_vector(7 downto 0); type type_array is array (natural range <>) of stype_data; signal ls_test_data : type_array(3 downto 0); How would a function have to look like to be capable of reverse the order of the array elements ? Is it legal to use the following unconstrained function to achieve that reversing ? function reverse2(p: type_array) return type_array is variable result: type_array(p'reverse_range); begin for i in p'range loop result(i) := p(i); end loop; return result; end; Thank you for your opinion. Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.k-dsl.de!news.glorb.com!news2.glorb.com!postnews.google.com!k15g2000vbl.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Mon, 6 Apr 2009 06:52:19 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239025939 29073 127.0.0.1 (6 Apr 2009 13:52:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Apr 2009 13:52:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k15g2000vbl.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:806 On Apr 5, 3:47=A0pm, Paul wrote: > For a pure synchronous process, my favorite template is: > > =A0 process is > =A0 begin > =A0 =A0 wait until clk =3D '1'; -- or: wait until rising_edge(clk); > > =A0 =A0 if en =3D '1' then > =A0 =A0 =A0 q <=3D d; > =A0 =A0 end if; > =A0 end process; > > Major advantage (IMHO): at the first glance you see this is a > synchronous process. Now doubt possible. Also no long winded > if/end-if needed, with an additional indentation level. Just to add more options to the mix (If you don't like additional levels of if-then statements or indentation): (I've not tried this, so I don't know if any synthesis tools will "get it right" or not) process is begin wait until rising_edge(clk) and en =3D '1'; q <=3D d; end process; Or it's concurrent behavioral equivalent: q <=3D d when rising_edge(clk) and en =3D '1'; About the sensitivity list issue: some simulators use an optimization whereby multiple processes that share the same sensitivity list are merged into one process in order to save setup/teardown overhead associated with multiple processes. Adding an enable to the sensitivity list would defeat this optimization in most cases. The same is true for the concurrent statement's implied sensitivity list. There is also a process template that uses variables for storage, with assignments to signals after the end of the clocked if-then statement to infer combinatorial logic outputs (no combo in->out paths). It may not be recognized by all synthesis tools, but at least Quartus, Synplify and Precision handle it. An example would be (ignoring reset): process (clk) is variable count: natural range 0 to 2**n-1; begin if rising_edge(clk) then count :=3D (count - 1) mod 2**n; end if; output <=3D count =3D 2; -- combinatorial decode end if; I'm not sure how you would/could do this with a wait statement. Andy From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!l13g2000vba.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: Reverse function - unconstrained types Date: Mon, 6 Apr 2009 07:22:29 -0700 (PDT) Organization: http://groups.google.com Lines: 69 Message-ID: References: NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239027749 16947 127.0.0.1 (6 Apr 2009 14:22:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Apr 2009 14:22:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l13g2000vba.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: news.eternal-september.org comp.lang.vhdl:807 On Apr 6, 9:45=A0am, "ALu...@web.de" wrote: > Hi, > > one possible solution to reverse an unconstrained std_logic_vector is > to use > the following function: > > function reverse(p: std_logic_vector) return std_logic_vector is > =A0variable result: std_logic_vector(p'reverse_range); > =A0begin > =A0 =A0 for i in p'range loop > =A0 =A0 =A0 result(i) :=3D p(i); > =A0 =A0 end loop; > =A0 =A0 return result; > end; > > Now I have the following type and signal declaration: > > subtype stype_data =A0is std_logic_vector(7 downto 0); > type type_array is array (natural range <>) of stype_data; > > signal ls_test_data : type_array(3 downto 0); > > How would a function have to look like to be capable of > reverse the order of the array elements ? Is it legal to use > the following unconstrained function to achieve that reversing ? > > function reverse2(p: type_array) return type_array is > =A0variable result: type_array(p'reverse_range); > =A0begin > =A0 =A0 for i in p'range loop > =A0 =A0 =A0 result(i) :=3D p(i); > =A0 =A0 end loop; > =A0 =A0 return result; > end; > > Thank you for your opinion. > > Rgds, > ALuPin Your std_logic_vector is itself an unconstrained array. Your two questions are therefore equivalent :-) As a note on "style" (purely a personal thing, nothing to do with correctness), your functions could be confusing to some, as they rely on a logical remapping of the vector indices (through the use of reverse_range) coupled with the language-defined assignment (when you actually call the function) that maps left-to-left and right-to-right indices, thereby undoing the remap. This clever "double negative" could be made explicit (and also avoid any bizarre user surprises, such as when passing the result to a function that checks the index and range of its argument, such as ieee_fixed package functions). I'd suggest that the following would make the output signature match the input signature. function reverse(p: std_logic_vector) return std_logic_vector is variable result: std_logic_vector(p'reverse_range); variable equivalent_result: std_logic_vector(p'range); begin for i in p'range loop result(i) :=3D p(i); end loop; equivalent_result :=3D result; return equivalent_result; end; - Kenn From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!gegeweb.org!de-l.enfer-du-nord.net!border1.nntp.ams.giganews.com!nntp.giganews.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-ID: <49DA1589.7010805@xs4all.nl> Date: Mon, 06 Apr 2009 16:45:29 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Andy Subject: Re: More synthesis myths? References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 21 NNTP-Posting-Host: 80.127.156.245 X-Trace: 1239029129 news.xs4all.nl 200 [::ffff:80.127.156.245]:39334 X-Complaints-To: abuse@xs4all.nl Xref: news.eternal-september.org comp.lang.vhdl:808 Andy wrote: > process (clk) is > variable count: natural range 0 to 2**n-1; > begin > if rising_edge(clk) then > count := (count - 1) mod 2**n; > end if; > output <= count = 2; -- combinatorial decode > end if; Personally I would avoid these constructions: 1. You generate FFs from variables, which are often hard to find due to name changing during synthesis. 2. Your logic path consists of FF, - operator, comparator; from a timing perspective it's better to use the comparator directly on the FF output, and adjust the expected value accordingly. 3. Your output is not a FF, which may also create timing problems. Kind regards, Pieter Hulshoff From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z1g2000yqn.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: Reverse function - unconstrained types Date: Mon, 6 Apr 2009 07:45:58 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <63c2ae1c-9e2a-4190-8f5d-474b46bf73b6@z1g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239029158 7016 127.0.0.1 (6 Apr 2009 14:45:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Apr 2009 14:45:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z1g2000yqn.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:809 Hi Kenn, thank you for your answer. Yes, the point concerning matching between input and output signature is an important one! Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Mon, 06 Apr 2009 08:46:42 -0700 Lines: 26 Message-ID: <73umf4F11418hU1@mid.individual.net> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 3rHi+xPB0qdOFWNsZkGg6w/SdsMTXccEqgap1nQ8qsG/U9cip4 Cancel-Lock: sha1:MGIK6QSzdm4nnL5/r8c938uQfnw= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <49DA1589.7010805@xs4all.nl> Xref: news.eternal-september.org comp.lang.vhdl:810 Pieter Hulshoff wrote: > Personally I would avoid these constructions: > 1. You generate FFs from variables, which are often hard to find due to name > changing during synthesis. In modelsim, I use an 'add wave' command for each process to make the variables visible. Quartus uses the variable names directly, when they represent flops rather than wires. > 2. Your logic path consists of FF, - operator, comparator; from a timing > perspective it's better to use the comparator directly on the FF output, and > adjust the expected value accordingly. In a simple example like this, you have a point. In my processes, I may have 30 variables, and these are mostly internal registers. > 3. Your output is not a FF, which may also create timing problems. The output is indeed a flip flop. The signal assignment represents the wire from Q to the output port. Try it and see. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!xlned.com!feeder1.xlned.com!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!r31g2000prh.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Synchronization Date: Mon, 6 Apr 2009 11:09:20 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239041360 14101 127.0.0.1 (6 Apr 2009 18:09:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Apr 2009 18:09:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r31g2000prh.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:811 On Apr 2, 10:06=A0am, john wrote: > Hello, > > Clock (clk1x) is a 100MHz clock and the VHDL program is using it to > read the SDRAM. I need to load the SDRAM with the data and then send > it to the Digital to Analog converter. The DAC works with 1MHz clock, > 49 bits of data and a Tag signal which tells the DAC that a new 49 bit > data is available. I tried to divide the 100MHz clock to 1MHz and send > the data to the clock. =A0But I am unable to see the DAC working. I > hooked up the logic analyzer and looked at the signals. The Tag who > should repeats itself after every 49 bits is not stable at all. it > repeats multiple times during the data stream and resets the DAC. My > code is given below. I am having clock synchronization problems. > Please advice. John Wow, more two-process state machine lossage. And you've declared both numeric_std and std_logic_arith. -a From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.ecp.fr!news2.arglkargh.de!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Mon, 06 Apr 2009 12:59:43 -0700 Lines: 16 Message-ID: <49DA5F2F.2090105@gmail.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net DrZRePe9nMA4/F9FAacXFAqywccpzye/Iqi2aZLMuYHm/BqDGe Cancel-Lock: sha1:3+I/ECeM6HUZSAyXaJNXH6HMmmg= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <49DA1589.7010805@xs4all.nl> Xref: news.eternal-september.org comp.lang.vhdl:812 > Andy wrote: >> output <= count = 2; -- combinatorial decode Pieter Hulshoff wrote: > 3. Your output is not a FF, which may also create timing problems. Sorry, I read what I expected, "output <= count;" not what he wrote. I agree with you, that with rare exceptions, process outputs should be registers. -- Mike From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Apr 2009 17:51:48 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Reading memory images into a VHDL testbench Date: Mon, 06 Apr 2009 23:49:50 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Uxb9HaMKxJGg45KXps4e5W3t2kWCEGTmYtxm92x9G8MCioKVnwWr3Tqdk3/drG1L0VHDdasjAs5jG4i!1G1Vyj0W8n7oExQnBIj0lyy3iKEHkEaVZGP4zKs7ZQeiagkYzqmF2z2Ndx/9IZ/rJNqAHmCW4ntH!2yJb X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2626 Xref: news.eternal-september.org comp.lang.vhdl:813 Back in August '08 there was an inconclusive thread here asking whether you could find a VHDL lookalike for the very convenient Verilog readmemb/readmemh system tasks. It's something I have often wanted for myself, to support testbenches written in a mixture of VHDL and Verilog - or when translating from one to another. I don't want to have to rewrite all my memory image files into some VHDL-friendly format. I've now done a reasonably complete implementation of readmemb/readmemh in VHDL, and will make it available after a bit more testing. However, it seems likely that the ability to read .COE and .MIF would also be handy (nice to use the same memory image files for behavioural models and synthesis); and perhaps Intel HEX or S-record as well. Which of these do folk think is most important? I don't have time to do a thorough job on all of them. It's easy and quick to do something that's *almost* right but, like most things in life, doing it properly costs real work. Alternatively, has anyone stumbled across any existing implementations of file-readers for those formats in VHDL? I couldn't find anything after a brief Google session. TIA -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:03 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench Date: Mon, 06 Apr 2009 17:33:19 -0700 Lines: 46 Message-ID: <49DA9F4F.7030608@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 9A7dijr46pmNZTb9lL/Rngxa0GyZMZgOS9Hk8EsxhSBI6vL9DI Cancel-Lock: sha1:g4yovT9W87AZWCuGTl/p5qttb74= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:814 Jonathan Bromley wrote: > I've now done a reasonably complete implementation of > readmemb/readmemh in VHDL, and will make it available > after a bit more testing. Good work. Does that mean I can writememh from verilog and readmemh from vhdl, but not vice-versa? > However, it seems likely > that the ability to read .COE and .MIF would also be > handy (nice to use the same memory image files for > behavioural models and synthesis); That would be the top two, but I really shouldn't vote, since I am partial to vhdl constant arrays and letting synthesis make those files for me. > and perhaps > Intel HEX or S-record as well. Less important, but probably the next two. > Which of these do > folk think is most important? I don't have time > to do a thorough job on all of them. It's easy > and quick to do something that's *almost* right > but, like most things in life, doing it properly > costs real work. Just do one of them as an example. I'm sure you will clarify and virtualise the process with vhdl functions, so the others should be an trivial exercise ;) > Alternatively, has anyone stumbled across any > existing implementations of file-readers for those > formats in VHDL? I couldn't find anything after > a brief Google session. Nothing in vhdl. Just a perl parser example for the verilog format: http://search.cpan.org/~gsullivan/Verilog-Readmem-0.04/lib/Verilog/Readmem.pm -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:04 2009 Date: Tue, 07 Apr 2009 10:44:25 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 123.243.86.135 X-Original-NNTP-Posting-Host: 123.243.86.135 Message-ID: <49daa1ec$1@dnews.tpgi.com.au> X-Trace: dnews.tpgi.com.au!tpg.com.au 1239065068 123.243.86.135 (7 Apr 2009 10:44:28 +1100) Lines: 25 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder8.cambrium.nl!feed.tweaknews.nl!195.14.215.230.MISMATCH!news.netcologne.de!newsfeed-hp2.netcologne.de!usenet.hanse.com!nntp.gblx.net!nntp3.phx1!dnews.tpgi.com.au!tpg.com.au!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:815 Jonathan Bromley wrote: > However, it seems likely > that the ability to read .COE and .MIF would also be > handy (nice to use the same memory image files for > behavioural models and synthesis); and perhaps > Intel HEX or S-record as well. Which of these do > folk think is most important? In stark contrast to Mike, I'm going to vote for Intel HEX and S-record. Not trying to be difficult, but they are the two formats I use myself. I really dislike MIF in a big way, though concede it's perhaps better for sparsely populated _big_ arrays - not that I've had much of a use for them myself. I always use Intel Hex for on-chip memories - it allows me to use the same image for simulation and synthesis. My $0.02 worth... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!gnilink.net!nx02.iad01.newshosting.com!newshosting.com!novia!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Apr 2009 20:12:49 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench Date: Tue, 07 Apr 2009 02:10:51 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <2q9lt4lb2ja0a97k22l5klfh5lfdmb6cbc@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 25 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-l9Kr0JSz+Ag0vVAhNLoAjVr/dycz1wRb60uuzqWxn/qlWs4w2DQkVx5qeN6C5lrIHi3mbsi0Mr2/QJo!/05JAiuFNeNxR9N7HnOdz7T2lSxTW5JHzMtx+BGjkl6eZKL/gfy8jvQifiKWf3wS3C47F/DS9opZ!rIL5 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:816 On Mon, 06 Apr 2009 23:49:50 +0100, Jonathan Bromley wrote: >I've now done a reasonably complete implementation of >readmemb/readmemh in VHDL, and will make it available >after a bit more testing. Only a little bit. Testing and bug reports welcomed. VHDL, a readme file and a silly demo example at http://www.oxfordbromley.plus.com/files/readmem/readmem.zip If the laughter isn't too loud, I'll do one of the other formats some time soon. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Apr 2009 20:17:09 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench Date: Tue, 07 Apr 2009 02:15:12 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <11alt49rgnicn6j7qsqvvo3f5o3q3dnsrt@4ax.com> References: <49DA9F4F.7030608@gmail.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 35 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wYsBfa2ASXLL8kSIpsmZfk+Kkr8amKnYeM+bWIwc8XjzBEsYUtbyzac2JzDazU+8Uo+d+drpqhtseu9!tVcQeJcSd179t/eplGc44Q+nTCNfvOVCavP4iJgHnVyJim5GmsJreYJGg2OwXRFb9c7PumUhW6Xu!MkO4 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2383 Xref: news.eternal-september.org comp.lang.vhdl:817 On Mon, 06 Apr 2009 17:33:19 -0700, Mike Treseler wrote: >Does that mean I can writememh from verilog >and readmemh from vhdl, but not vice-versa? It's intended to be read-only for both. The idea is that the text file is created by some external tool, or by hand, and read into your sim to initialise some values. I know you like to do it with VHDL source, but sometimes you don't get the choice... Writing the files is considerably easier than reading them, because you don't need to worry about error conditions. There's no built-in writer in Verilog, but it's trivial to do; I'll add the VHDL equivalent too. >Just a perl parser example for the verilog format: >http://search.cpan.org/~gsullivan/Verilog-Readmem-0.04/lib/Verilog/Readmem.pm Thanks, I'll look - but I don't know Perl well, so probably won't learn much :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!news2.euro.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-ID: <49DB1909.5060607@xs4all.nl> Date: Tue, 07 Apr 2009 11:12:41 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Mike Treseler Subject: Re: More synthesis myths? References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> In-Reply-To: <73umf4F11418hU1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 43 NNTP-Posting-Host: 80.127.156.245 X-Trace: 1239095561 news.xs4all.nl 183 [::ffff:80.127.156.245]:48154 X-Complaints-To: abuse@xs4all.nl Xref: news.eternal-september.org comp.lang.vhdl:818 Mike, >> 2. Your logic path consists of FF, - operator, comparator; from a timing >> perspective it's better to use the comparator directly on the FF >> output, and >> adjust the expected value accordingly. > > In a simple example like this, you have a point. > In my processes, I may have 30 variables, and > these are mostly internal registers. This second point had more to do with the logic generated by the compiler than with the use of variables. Take for example: WAIT UNTIL clk = '1'; counter := counter + 1; IF counter = 5 THEN counter := 0; END IF; vs WAIT UNTIL clk = '1'; IF counter = 4 THEN counter := 0; END IF; counter := counter + 1; or WAIT UNTIL clk = '1'; counter <= counter + 1; IF counter = 4 THEN counter <= 0; END IF; The last 2 examples will usually synthesize into faster logic than the 1st, since the first assumes a + followed by a compare while the last two do the compare directly on the FF output. Kind regards, Pieter Hulshoff From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Tue, 07 Apr 2009 06:38:56 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench Date: Tue, 07 Apr 2009 12:36:58 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <2q9lt4lb2ja0a97k22l5klfh5lfdmb6cbc@4ax.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-L2OPJLOr1cW/7Cd8O04ZrAiVzy2u55w3Q9AT005yKX++mv95rzcgr1U2wrF2PBql8D79xi6d9DM0BOH!jjQYM2XQggziu6VUCcw93P+ep2iD/lu7UY7bh3s9GjNc5bcfUbwp0UxvKZIum1WsoGp+2L7VWa3j!oe8Q X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 1975 Xref: news.eternal-september.org comp.lang.vhdl:819 On Tue, 07 Apr 2009 02:10:51 +0100, Jonathan Bromley wrote: > Testing and bug reports welcomed. Hmm, better fix those stupidities double-quick before Alan Fitch gets to see it and spots all my silly errors! http://www.oxfordbromley.plus.com/files/readmem/readmem_0.1.zip fixes... - forgot to close the input file when done; - function "get_mem" does not need to be IMPURE. The original idea was Alan's anyway... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!v6g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Tue, 7 Apr 2009 07:38:23 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: <7558118a-bd80-49ea-9855-cd983a856ef8@v6g2000vbb.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239115103 8491 127.0.0.1 (7 Apr 2009 14:38:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Apr 2009 14:38:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v6g2000vbb.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:820 On Apr 6, 9:45=A0am, Pieter Hulshoff wrote: > Andy wrote: > > process (clk) is > > variable count: natural range 0 to 2**n-1; > > begin > > =A0 if rising_edge(clk) then > > =A0 =A0 count :=3D (count - 1) mod 2**n; > > =A0 end if; > > =A0 output <=3D count =3D 2; -- combinatorial decode > > end if; > > Personally I would avoid these constructions: > 1. You generate FFs from variables, which are often hard to find due to n= ame > changing during synthesis. > 2. Your logic path consists of FF, - operator, comparator; from a timing > perspective it's better to use the comparator directly on the FF output, = and > adjust the expected value accordingly. > 3. Your output is not a FF, which may also create timing problems. > > Kind regards, > > Pieter Hulshoff #1: I've never had problems finding variable-inferred register names. The hierarchical naming works the same for signals or variables, there's just an additional level of hierarchy for the process with variables. Use descriptive process names and you won't have any problems. #2: I think you misunderstood what happens with signal assignments from variables. For instance, the initical example I gave, and this one, are cycle-accurately identical to each other WRT the output signal: process (clk) is variable count: natural range 0 to 2**n-1; begin if rising_edge(clk) then count :=3D (count - 1) mod 2**n; output <=3D count =3D 2; -- registered decode of combo count end if; end if; The difference is where the register is implemented. In the initial example, the register is after the decrement, splitting the decrement and comparison. In this example, the register is after both the decrement and the comparison, and is a separate register. The cycle based timing for output in both is identical. Depending on where the output is needed, the advantage generally lies with the former. Naturally this is a trivial example which could easily be re-coded behaviorally to compensate for an additional clock delay from a registered outputs, but that is not the point. Re-coding for such compensation often obfuscates the overall behavior that is intended. When I specify two output signals, using the same expression, but one within and one after the clocked clause, Synplify will recognize they are functionally identical, and optimize the combinatorial output version away. However, I've never seen it convert the combinatorial output to a registered output unless such duplication was being adressed, or register retiming was invoked. Both simulate the same (WRT cycle-based timing on output), both behave the same after synthesis. #3: These examples are not intended as a verdict on the appropriateness for all applications of combinatorial outputs from synchronous processes, but rather an example of how to generate one without introducing an additional process (implied or explicit). I use signals only for inter-process communication. My processes tend to be large and complex to minimize both the number of processes and the signal-based communication between them, both of which contribute to simulation efficiency. All intra-process communication uses variables, whether the behavior implies a register or not. I prefer not to focus on the explicit location of registers, but on the cyclic behavior of the process, which is easier to read and debug from a truly sequential description of variables than a pseudo-sequential description of signals. Register re-timing optimizations change the register/logic locations anyway, and usually do it better than I can afford to. Just make sure you disable such optimizations (as well as register replication, etc.) around synchronization boundaries (and don't ask me how I know that!). Andy From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!t-online.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Mathworks Simulink Date: Tue, 7 Apr 2009 07:42:04 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239115324 24420 127.0.0.1 (7 Apr 2009 14:42:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Apr 2009 14:42:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:821 Does anyone have much experience with this and Auto-VHDL generation of algorithms? It seems some people have the idea that once they have the algorithm specified in sumulink, they can just press the "to VHDL" button and out pops some working code that will go straight into our hardware, solving all of our problems (these are not hardware engineers, who have so far been a little sceptical to say the least). Am I going to be out of a job writing algorithm based VHDL in the next 5 years? From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Tue, 07 Apr 2009 10:11:39 -0700 Lines: 20 Message-ID: <49DB894B.70303@gmail.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4d0h45UB4ocHuWLq54KHswaQPzDdcCqB9i5xBnOSNV7ahSxJZH Cancel-Lock: sha1:r8u7exIncTYV0SyiQhnqQaL2ZDE= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <49DB1909.5060607@xs4all.nl> Xref: news.eternal-september.org comp.lang.vhdl:822 Pieter Hulshoff wrote: > The last 2 examples will usually synthesize into faster logic than the 1st, > since the first assumes a + followed by a compare while the last two do the > compare directly on the FF output. I can't benchmark synthesis until there is an entity and port assignments. A real design also needs a reset strategy. Synthesis sometimes creates duplicate registers at the front end that are taken out during mapping. Because of these complications, I stick with well-tested "known good" synchronous template for my designs. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:04 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Tue, 07 Apr 2009 10:29:52 -0700 Lines: 28 Message-ID: <49DB8D90.1050809@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 2CzWg/exijV8VjHj/G4RwQr/J4kKlaPkVrQ/TZhF/5K+LOjNhc Cancel-Lock: sha1:9HPVPra6Yc9aTUC2d94ZDwTfUeA= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:823 Tricky wrote: > Does anyone have much experience with this and Auto-VHDL generation of > algorithms? It seems some people have the idea that once they have the > algorithm specified in simulink, they can just press the "to VHDL" > button and out pops some working code that will go straight into our > hardware, solving all of our problems (these are not hardware > engineers, who have so far been a little skeptical to say the least). Simulink is a good tutorial on how to code dsp modules, and can generate usable rtl code, but everything else is better covered directly by vhdl or verilog. All code generators make ugly code. Once I understand what the generator is doing, I will capture and parametrize the functions, and take the odd tool out of the design loop. > Am I going to be out of a job writing algorithm based VHDL in the next > 5 years? Not because of code generators. The pressure on FPGA designers comes from cheap servers and open source software. Luckily servers are big and noisy so far. Also note that algorithms work in any environment. -- Mike From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!q9g2000yqc.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Tue, 7 Apr 2009 10:42:25 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: References: <49DB8D90.1050809@gmail.com> NNTP-Posting-Host: 66.38.210.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239126145 27220 127.0.0.1 (7 Apr 2009 17:42:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Apr 2009 17:42:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q9g2000yqc.googlegroups.com; posting-host=66.38.210.253; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; fr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:824 > > The pressure on FPGA designers comes from > cheap servers and open source software. > Luckily servers are big and noisy so far. > Also note that algorithms work in any environment. > > =A0 =A0 =A0 =A0 -- Mike Care to elaborate? I'm interested in your views. Best regards From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Tue, 07 Apr 2009 22:54:16 +0200 Lines: 53 Message-ID: <741sroF117dc1U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net yLH4iWE4GW2O2+YbaD9vNwOSq7QR6BIe72f12h5wZi6Sfn/4+T Cancel-Lock: sha1:9ocgcW0YdnJmNO+xRtCRB5yQRUY= User-Agent: Thunderbird 2.0.0.21 (X11/20090318) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:825 Tricky wrote: > Does anyone have much experience with this and Auto-VHDL generation of > algorithms? It seems some people have the idea that once they have the > algorithm specified in sumulink, they can just press the "to VHDL" > button and out pops some working code that will go straight into our > hardware, solving all of our problems (these are not hardware > engineers, who have so far been a little sceptical to say the least). > > Am I going to be out of a job writing algorithm based VHDL in the next > 5 years? I doubt it. A while back, we evaluated several tools that claim to save gazillions of man months when porting algorithms to FPGAs, but then decided to stick to hand-coding for the time being. 1. Matlab -> RTL (the solution offered by mathworks): The downside is that the blocks that are supported are very limited in number and function. They have things like adders, subtractors, delay elements and the like, all stuff that you can basically just write on-the-fly in VHDL anyway. At that time, no really interesting things were available, like FFTs or ready-to-use filters or so. To me it seemed like you would then just use Simulink as a kind of "schematic editor" to connect very simple primitives and have it spit out a HDL description. This could save you some time and you get free "documentation" (meaning the block diagram) as well, but to me it seemed it's not really worth the money (the license is quite expensive). Besides, the algorithm people still have to adapt to the limitations, i.e. the Matlab designer has to know exactly which functions he can use and how the functions map to hardware when writing the algorithm, or the HDL designer needs to adapt it afterwards. So, in the end, I didn't really see how this would be a big time-saver, except maybe for people new to HDL design. 2. Mentor Catapult C: To me this seemed the most "advanced", judging by what it claims to be able to do, like loop unrolling and taking care of BRAM at the input or outputs of your algorithm module. But it crashed twice during one 2-hour presentation, running the examples supplied with the program, and the price for a single license is higher than many a project's entire budget, so this was out of the race quite fast. Besides, it needs C code for the algorithm, whereas our people do their stuff with Matlab. Plus, it also needs Precision Synthesis to work, so that makes it even more expensive. 3. Xilinx AccelDSP: very cheap, works well, lots of available cores (sometimes they require additional licenses), but only for Xilinx devices. You can always try that out with a free 30-day test license. We didn't get very far in testing this, since it was then decided not to use a tool that only works with one manufacturer's devices. So, in the end we decided not to follow this any further, at least for the meantime. cu, Sean From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!h28g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Wed, 8 Apr 2009 00:55:21 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: <741sroF117dc1U1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239177321 16551 127.0.0.1 (8 Apr 2009 07:55:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Apr 2009 07:55:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h28g2000yqd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:826 > > 1. Matlab -> RTL (the solution offered by mathworks): The downside is > that the blocks that are supported are very limited in number and > function. They have things like adders, subtractors, delay elements and > the like, all stuff that you can basically just write on-the-fly in VHDL > anyway. At that time, no really interesting things were available, like > FFTs or ready-to-use filters or so. To me it seemed like you would then > just use Simulink as a kind of "schematic editor" to connect very simple > primitives and have it spit out a HDL description. This could save you > some time and you get free "documentation" (meaning the block diagram) > as well, but to me it seemed it's not really worth the money (the > license is quite expensive). Besides, the algorithm people still have to > adapt to the limitations, i.e. the Matlab designer has to know exactly > which functions he can use and how the functions map to hardware when > writing the algorithm, or the HDL designer needs to adapt it afterwards. > So, in the end, I didn't really see how this would be a big time-saver, > except maybe for people new to HDL design. >From what Ive seen recently, they do now have things like "filter wizards" where you can modify the parameters and taps and whatever, and it will allow you to output RTL. Plus there is the altera DSP Builder which I think adds altera versions of FFT and other interesting image processing and DSP elements. (I think there is a Xilinx Equivalent) But, of course it will never cope with the specifics of boards - memory controllers, UARTS etc. Or if they do, it will never be as effecient as a hand crafted job. I see it like making something like a Vase out of lego. Yes it can be done, but making it out of clay would be much better. My worry is the management get sucked into the mathworks presentation - see that anyone can now generate firmware (from the coughed up RTL code) and then all I get to do is the memory controllers and UARTs, and stitch it together with the terrible auto-generated VHDL. What I do like about simulink though is the way it help encapsulate specs and tie a project together. Now if only they would leave the firmware generation out of it.. From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: Novlednes Newsgroups: comp.lang.vhdl Subject: Pipelining a multi-dimensional array. Date: Wed, 8 Apr 2009 07:07:24 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 62.58.98.250 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239199644 24229 127.0.0.1 (8 Apr 2009 14:07:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Apr 2009 14:07:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=62.58.98.250; posting-account=wsoP4woAAACuYnm6s12SJWCMEc8GbEqo User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:827 Hi, I'm trying to pipeline the multi-dimensional array T in the following code snippet. The pipelining is done in process p_Pipe. However, there is a driver on T(0) in process p_Sim. No problem you would think, since the for loop in p_Pipe only addresses elements T(1), T(2) and T (3). For some reason, my simulator (Modelsim) appears to translate the for loop in a driver on T(0) as well, leading to all Xs on T(0). But when unfolding the for loop in individual assignments (see the inline comments) for T(1), T(2) and T(3), there is no problem anymore: the pipeline behaves as expected. What I cannot put my finger on, is why the individual assignments behave differently than the for loop? Does anyone have some insights on that? library IEEE; use IEEE.std_logic_1164.all; entity tb_MultiDimArray is end tb_MultiDimArray; architecture Simulation of tb_MultiDimArray is subtype t_Word is std_logic_vector(31 downto 0); type t_T is array(0 to 3) of t_Word; signal Clk : std_logic := '1'; signal T : t_T := (others => (others => '1')); begin p_Clock : process begin loop Clk <= not Clk; -- do not forget to initialize the clock ! wait for 5 ns; end loop; end process p_Clock; p_Pipe : process(Clk) begin if rising_edge(Clk) then -- T(1) <= T(0); -- T(2) <= T(1); -- T(3) <= T(2); for i in 0 to 2 loop T(i+1) <= T(i); end loop; end if; -- rising_edge end process p_Pipe; p_Sim: process begin wait until falling_edge(Clk); T(0) <= (others => '0'); wait; -- Will wait forever. end process p_Sim; end Simulation; From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b16g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Wed, 8 Apr 2009 07:47:54 -0700 (PDT) Organization: http://groups.google.com Lines: 100 Message-ID: <4456c1b6-49fa-46aa-87a7-4533c4bd1a68@b16g2000yqb.googlegroups.com> References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239202074 32133 127.0.0.1 (8 Apr 2009 14:47:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Apr 2009 14:47:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b16g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:828 On 8 Apr, 15:07, Novlednes wrote: > Hi, > > I'm trying to pipeline the multi-dimensional array T in the following > code snippet. The pipelining is done in process p_Pipe. However, there > is a driver on T(0) in process p_Sim. No problem you would think, > since the for loop in p_Pipe only addresses elements T(1), T(2) and T > (3). For some reason, my simulator (Modelsim) appears to translate the > for loop in a driver on T(0) as well, leading to all Xs on T(0). But > when unfolding the for loop in individual assignments (see the inline > comments) for T(1), T(2) and T(3), there is no problem anymore: the > pipeline behaves as expected. > > What I cannot put my finger on, is why the individual assignments > behave differently than the for loop? Does anyone have some insights > on that? > > library IEEE; > use IEEE.std_logic_1164.all; > > entity tb_MultiDimArray is > end tb_MultiDimArray; > > architecture Simulation of tb_MultiDimArray is > > =A0 =A0subtype t_Word =A0 =A0is std_logic_vector(31 downto 0); > =A0 =A0type t_T =A0 =A0 =A0 =A0 =A0is array(0 to 3) of t_Word; > > =A0 =A0signal Clk =A0 =A0 : std_logic :=3D '1'; > =A0 =A0signal T =A0 =A0 =A0 : t_T :=3D (others =3D> (others =3D> '1')); > > begin > > =A0 =A0p_Clock : process > =A0 =A0begin > =A0 =A0 =A0 loop > =A0 =A0 =A0 =A0 =A0Clk <=3D not Clk; =A0-- do not forget to initialize th= e clock ! > =A0 =A0 =A0 =A0 wait for 5 ns; > =A0 =A0 =A0 =A0 end loop; > =A0 =A0end process p_Clock; > > =A0 =A0p_Pipe : process(Clk) > =A0 =A0begin > =A0 =A0 =A0 if rising_edge(Clk) then > =A0 =A0 =A0 =A0 =A0-- T(1) <=3D T(0); > =A0 =A0 =A0 =A0 =A0-- T(2) <=3D T(1); > =A0 =A0 =A0 =A0 =A0-- T(3) <=3D T(2); > > =A0 =A0 =A0 =A0 =A0for i in 0 to 2 loop > =A0 =A0 =A0 =A0 =A0 =A0 T(i+1) <=3D T(i); > =A0 =A0 =A0 =A0 =A0end loop; > > =A0 =A0 =A0 end if; -- rising_edge > =A0 =A0end process p_Pipe; > > =A0 =A0p_Sim: process > =A0 =A0begin > =A0 =A0 =A0 wait until falling_edge(Clk); > =A0 =A0 =A0 T(0) <=3D (others =3D> '0'); > =A0 =A0 =A0 wait; -- Will wait forever. > =A0 =A0end process p_Sim; > > end Simulation; It's because you have got the same signal, T, spread out in 2 processes. T(0) and T(1-3) are all part of the same signal, and so therefore it you have multiple drivers on the same signal. To fix it, you'll either have to put T in the same process like this: p_Pipe : process(Clk) variable first : boolean :=3D true; begin if falling_edge(clk) then if first then T(0) <=3D (others =3D> '0'); first :=3D false; end if; elsif rising_edge(Clk) then T(1) <=3D T(0); T(2) <=3D T(1); T(3) <=3D T(2); for i in 0 to 2 loop T(i+1) <=3D T(i); end loop; end if; -- rising_edge end process p_Pipe; or do something like this for the shift register: if rising_edge(clk) then T <=3D some_other_signal & T(0 to T'high-1); end if; Some other signal can then be modified inside another process. From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!news.motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Wed, 08 Apr 2009 10:35:36 -0700 Lines: 22 Message-ID: <49DCE068.2020403@gmail.com> References: <741sroF117dc1U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net BonILD0g+V/ebOHwEJEX6AxxPGveiIJFPmE87sHTQeZV9n8tao Cancel-Lock: sha1:UVRTRR6GK3MvlzJsPTBmy3g9yC0= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:829 Tricky wrote: > My worry is the management get sucked into the mathworks presentation > - see that anyone can now generate firmware (from the coughed up RTL > code) and then all I get to do is the memory controllers and UARTs, > and stitch it together with the terrible auto-generated VHDL. Managers of the Profit/Loss/Schedule type, spend about as much time thinking about engineering tools as janitorial supplies. It's hardware engineers, looking at covering DSP functions in a hurry who evaluate such tools. > What I do like about simulink though is the way it help encapsulate > specs and tie a project together. It's a passable system level simulator, but I don't think it will replace any fpga designers. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Wed, 08 Apr 2009 11:05:19 -0700 Lines: 15 Message-ID: <49DCE75F.3080409@gmail.com> References: <49DB8D90.1050809@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net jKQICUlnt6DQPTZg5xSSbwYK3CiK/PrA05JZhlm52qWyz+ZAMc Cancel-Lock: sha1:PYQq+6A9orTq2BoP0+I2xGsv0YI= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:830 Benjamin Couillard wrote: > Care to elaborate? I'm interested in your views. The cost of a generic multi-core rack-mount server is nearing the price of a high-end fpga on a circuit board in a custom box. If the project uses standard interfaces, and requires web access, with heavy math or database functions, the server solution is becoming competitive for some applications. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Wed, 08 Apr 2009 17:44:33 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Wed, 08 Apr 2009 23:42:33 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 52 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-SiHB+JbFQOXJU2fCZGvnkmvsO4ctxO/TDzi853Pa+9DBJVyMlxmXc2/nCX2k5bSc0oPvTm2SCozkNdJ!Q7P7nmPm3APmiJCdPcEf5MubBFCQkTWfeaK7QvwZn/JfBp1tl8Tfk0UyQy3lEIG5+jqRbP2r87Sw!S/2h X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2789 Xref: news.eternal-september.org comp.lang.vhdl:831 On Wed, 8 Apr 2009 07:07:24 -0700 (PDT), Novlednes wrote: > there >is a driver on T(0) in process p_Sim. No problem you would think, >since the for loop in p_Pipe only addresses elements T(1), T(2) and T >(3). For some reason, my simulator (Modelsim) appears to translate the >for loop in a driver on T(0) as well That is correct. It's a well-known VHDL "gotcha". FOR-loops are dynamically elaborated; in other words, even if the loop bounds are constant, the simulator does not know that at compile time. Consequently, in the following example.... architecture Foo of Bar is signal S: std_logic_vector(3 downto 0); begin P: process begin for i in 2 to 3 loop S(i) <= '1'; end loop; end process; end; ...the process P drives ALL FOUR elements of S, even though you and I can easily see that the FOR-loop can only iterate over elements 2 and 3. Sometimes you can work around that using a GENERATE-loop, which is elaborated statically. And it is always possible to work around it using additional intermediate signals. If you really want a fun-filled day, you may care to scan the VHDL LRM for mentions of "longest static prefix", where you will find all the gory details. Good luck. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:05 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 08 Apr 2009 19:21:52 -0500 Date: Wed, 08 Apr 2009 20:21:21 -0400 From: David Bishop User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink References: <741sroF117dc1U1@mid.individual.net> In-Reply-To: <741sroF117dc1U1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 10 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-cBvqYPV0sYpxaXxAx0Aan8XPZf+0NeR0cEhT1QiVJ7pjglvJwHowjul/ZMmigh05zn9kjVicKT3H1ze!1KMmGu72tI97IzV4dS1RyhmDNQfyPGSBil3zGYSl+ZlVqqmRHevuVOBiM4HGLf8= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:832 Sean Durkin wrote: .... > A while back, we evaluated several tools that claim to save > gazillions of man months when porting algorithms to FPGAs, but then > decided to stick to hand-coding for the time being. I didn't evaluate all of these, but I came basically to the same conclusion. That's why I put the fixed and floating point packages together. David Bishop. From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!216.40.30.110.MISMATCH!novia!novia!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc01.gnilink.net.POSTED!5a11a07f!not-for-mail From: "Marty Ryba" Newsgroups: comp.lang.vhdl References: <49DB8D90.1050809@gmail.com> <49DCE75F.3080409@gmail.com> Subject: Re: Mathworks Simulink Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: Date: Thu, 09 Apr 2009 03:09:02 GMT NNTP-Posting-Host: 72.72.65.183 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1239246542 72.72.65.183 (Wed, 08 Apr 2009 23:09:02 EDT) NNTP-Posting-Date: Wed, 08 Apr 2009 23:09:02 EDT Xref: news.eternal-september.org comp.lang.vhdl:833 "Mike Treseler" wrote in message news:49DCE75F.3080409@gmail.com... > The cost of a generic multi-core rack-mount server > is nearing the price of a high-end fpga > on a circuit board in a custom box. > > If the project uses standard interfaces, > and requires web access, > with heavy math or database functions, > the server solution is becoming competitive > for some applications. Actually, for DSP-intensive applications, the current rage is GPUs- the NVIDIA chips ganged together several to a board, with several of these boards installed into rackmount servers. Our company is using these in several applications on both R&D and "real" projects. Our technology managers recently ran a little "summit" to compare notes on these efforts scattered across the company. I've looked at some of their results and it's pretty impressive how many FLOPS/Watt they can get. As far as FLOPS/$, the GPUs may be pretty competitive as well. Of course these beasts have their own learning curve if you want to do something real. My DSP processing is straightforward enough that I can (and have) done it in VHDL already so there is less incentive to port it to something else now, plus I need realtime behaviors that are hard to get in standard computers, and my project has to eventually target a single custom ASIC so it's better to work in FPGAs now. -Marty Ryba From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g19g2000yql.googlegroups.com!not-for-mail From: "tringuyen858@gmail.com" Newsgroups: comp.lang.vhdl Subject: counter in state machine Date: Wed, 8 Apr 2009 20:16:14 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: NNTP-Posting-Host: 76.88.4.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239246974 15404 127.0.0.1 (9 Apr 2009 03:16:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 03:16:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000yql.googlegroups.com; posting-host=76.88.4.1; posting-account=iuzo3goAAABSkSILXzW4rVFsFrCtTAQe User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:834 Hi all, I am trying to simulate a state machine that has a counter. Below is the code. When I run the simulation, it gets stuck at BEGIN_COUNT and start_flag_counter is X"01" throughout the whole simulation. I can't figure out what is wrong. May be it is something obvious that I can't see. thank you for your input. SYNC_PROC: process (clk_100, SYS_RST_N) begin if (SYS_RST_N='0') then state_count <= INIT; clk_100_locked_reg <= '0'; lock_reg_int_reg <= '0'; elsif rising_edge(clk_100) then state_count <= next_state; clk_100_locked_reg <= clk_100_locked; lock_reg_int_reg <= lock_reg_int; end if; end process; start_sig: process(state_count, clk_100_locked_reg, lock_reg_int_reg) begin case state_count is when INIT => start_reg <= '0'; start_flag_counter <= X"00"; if clk_100_locked_reg = '1' and lock_reg_int_reg = '1' then next_state <= BEGIN_COUNT; else next_state <= INIT; end if; when BEGIN_COUNT => start_flag_counter <= start_flag_counter + 1; start_reg <= '0'; if start_flag_counter = X"64" then next_state <= START_FLAG; else next_state <= BEGIN_COUNT; end if; when START_FLAG => start_flag_counter <= start_flag_counter + 1; start_reg <= '1'; if start_flag_counter = X"6A" then next_state <= STOP_COUNT; else next_state <= START_FLAG; end if; when STOP_COUNT => start_flag_counter <= X"00"; start_reg <= '0'; next_state <= STOP_COUNT; end case; end process; From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b16g2000yqb.googlegroups.com!not-for-mail From: Novlednes Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Thu, 9 Apr 2009 00:11:32 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <28813907-9fbb-45f5-a9fa-7014ea5361ed@b16g2000yqb.googlegroups.com> References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 62.58.98.250 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239261092 7477 127.0.0.1 (9 Apr 2009 07:11:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 07:11:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b16g2000yqb.googlegroups.com; posting-host=62.58.98.250; posting-account=wsoP4woAAACuYnm6s12SJWCMEc8GbEqo User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:835 Thank you both for your answers, Tricky and Jonathan. The dynamic elaboration of for-loops was not so well-known to me yet. Good to know though. I'll keep the LRM lookup for some other day ;-) Regards From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z1g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Mathworks Simulink Date: Thu, 9 Apr 2009 00:32:19 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <815d51f6-8e28-4b97-bf69-edd3576f7ec3@z1g2000yqn.googlegroups.com> References: <49DB8D90.1050809@gmail.com> <49DCE75F.3080409@gmail.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239262339 32356 127.0.0.1 (9 Apr 2009 07:32:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 07:32:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z1g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:836 On 8 Apr, 19:05, Mike Treseler wrote: > Benjamin Couillard wrote: > > Care to elaborate? I'm interested in your views. > > The cost of a generic multi-core rack-mount server > is nearing the price of a high-end fpga > on a circuit board in a custom box. > > If the project uses standard interfaces, > and requires web access, > with heavy math or database functions, > the server solution is becoming competitive > for some applications. > > =A0 =A0 =A0 =A0 -- Mike Treseler Unfortunately, This wont fit in a PC104 standard and run somewhere around 25-50W, so I guess Im safe for a while. From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y13g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: counter in state machine Date: Thu, 9 Apr 2009 00:49:36 -0700 (PDT) Organization: http://groups.google.com Lines: 88 Message-ID: <2659ba7e-f6f6-4fca-ab47-7af3cb714b44@y13g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239263376 14574 127.0.0.1 (9 Apr 2009 07:49:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 07:49:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y13g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:837 On 9 Apr, 04:16, "tringuyen...@gmail.com" wrote: > Hi all, > > I am trying to simulate a state machine that has a counter. =A0Below is > the code. =A0When I run the simulation, it gets stuck at BEGIN_COUNT and > start_flag_counter is X"01" throughout the whole simulation. =A0I can't > figure out what is wrong. =A0May be it is something obvious that I can't > see. =A0thank you for your input. > > =A0 =A0SYNC_PROC: process (clk_100, SYS_RST_N) > =A0 =A0begin > =A0 =A0 =A0 if (SYS_RST_N=3D'0') then > =A0 =A0 =A0 =A0 =A0state_count <=3D INIT; > =A0 =A0 =A0 =A0 =A0clk_100_locked_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0lock_reg_int_reg <=3D '0'; > =A0 =A0 =A0 elsif rising_edge(clk_100) then > =A0 =A0 =A0 =A0 =A0state_count <=3D next_state; > =A0 =A0 =A0 =A0 =A0clk_100_locked_reg <=3D clk_100_locked; > =A0 =A0 =A0 =A0 =A0lock_reg_int_reg <=3D lock_reg_int; > =A0 =A0 =A0 end if; > =A0 =A0end process; > > =A0 =A0start_sig: process(state_count, clk_100_locked_reg, > lock_reg_int_reg) > =A0 =A0begin > =A0 =A0 =A0 case state_count is > =A0 =A0 =A0 =A0 =A0when INIT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D X"00"; > =A0 =A0 =A0 =A0 =A0 =A0 if clk_100_locked_reg =3D '1' and lock_reg_int_re= g =3D '1' > then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D BEGIN_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D INIT; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when BEGIN_COUNT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D start_flag_counter + 1; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 if start_flag_counter =3D X"64" then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D START_FLAG; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D BEGIN_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when START_FLAG =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D start_flag_counter + 1; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 if start_flag_counter =3D X"6A" then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D STOP_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D START_FLAG; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when STOP_COUNT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D X"00"; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 next_state <=3D STOP_COUNT; > =A0 =A0 =A0 end case; > =A0 =A0end process; You need to put the counter in it's own clocked process. At the moment, when it gets into the "BEGIN_COUNT" state, nothing is changing that causes the sensitivity list to fire and cause the counter to increment. instead of putting the counter inside the state, put an enable instead: when BEGIN_COUNT =3D> start_flag_count_en <=3D '1'; ....... count_proc : process(clk_100, SYS_RST_N) begin if SYS_RST_N =3D '0' then start_flag_counter <=3D x"00"; elsif rising_edge(clk_100) then if start_flag_count_en =3D '1' then --add sync reset conditions first start_flag_counter <=3D start_flag_counter + 1; end if; end if; end process; Of course, moving the whole state machine into a single process would eliminate this problem because it would be clocked anyway. From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!37g2000yqp.googlegroups.com!not-for-mail From: bknpk@hotmail.com Newsgroups: comp.lang.vhdl Subject: system C versus VHDL|verilog|specman .... Date: Thu, 9 Apr 2009 01:50:44 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: NNTP-Posting-Host: 79.177.66.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239267044 14630 127.0.0.1 (9 Apr 2009 08:50:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 08:50:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000yqp.googlegroups.com; posting-host=79.177.66.75; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; he; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:838 I would like to know if system C is used in the high tech industry as main tool for sign-off during development of RTL and verification. For me system C is a great, free and high performance hardware simulator with the C++ as a verification engine. As a pilot, I took a little design from a customer and converted its RTL to system C. Since this DUT uses buses of greater than 64 bits, free verilog to system C tools, did not deliver. I did the conversion manually. The results as well as the verification code and its description is available free at: http://bknpk.no-ip.biz/First_SCV/aisTB.html From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp5-2.free.fr!not-for-mail Subject: Re: counter in state machine From: Bert_Paris References: Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Thu, 09 Apr 2009 11:41:32 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 12 Message-ID: <49ddc2ce$0$16237$426a74cc@news.free.fr> NNTP-Posting-Date: 09 Apr 2009 11:41:34 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1239270094 news-3.free.fr 16237 82.66.120.181:1949 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:839 tringuyen858@gmail.com a exposé le 09/04/2009 : > start_flag_counter <= start_flag_counter + 1; In a combinational process ????? Bad, bad, bad.... You probably wouldn't have goofed if you had your FSM in a single process. Bert From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r37g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: counter in state machine Date: Thu, 9 Apr 2009 09:18:40 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <01a60a49-db28-4fe7-955a-e14f6be04c4d@r37g2000yqn.googlegroups.com> References: <2659ba7e-f6f6-4fca-ab47-7af3cb714b44@y13g2000yqn.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239293921 15770 127.0.0.1 (9 Apr 2009 16:18:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 16:18:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r37g2000yqn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:840 On Apr 9, 2:49=A0am, Tricky wrote:> > Of course, moving the whole state machine into a single process would > eliminate this problem because it would be clocked anyway. Agreed. Two-process (separate clocked and combinatorial processes) descriptions are prone to latches (what you got), require twice the signal declarations, twice the process executions per clock cycle, cumbersome sensitivity lists, and a host of other bad side effects. Andy From newsfish@newsfish Wed Aug 19 13:24:06 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!talisker.lacave.net!lacave.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!v15g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Thu, 9 Apr 2009 09:08:48 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239293328 13821 127.0.0.1 (9 Apr 2009 16:08:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Apr 2009 16:08:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v15g2000yqn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:841 Jonathan is correct; from the language/simulation point of view, at compilation time, the for loop's index values are not known. However, for synthesis, the notion of "static" is a little different (and "static" may not even be the correct term). The impact of this is that for synthesis, for-loops are unrolled, and references to the index are implemented the same way constants are. Unlike simulation, the bounds of the for-loop index must be static for synthesis (so that the loop can be unrolled). You can have an exit statement to exit a loop early based on dynamic conditions, but the loop index itself must be statically bound (again, for synthesis only!). A quick example: for i in 0 to 3 loop if i = addr then reg(i) := data_a; reg(i+4) := data_b; end if; end loop; is likely to be implemented differently than: for i in 0 to 3 loop if i = addr then reg(addr) := data_a; reg(addr+4) := data_b; end if; end loop; The behavior is the same, but the hardware may not be optimized the same, because (i+4) is static in synthesis, whereas (addr+4) is not. Andy From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Thu, 09 Apr 2009 10:37:09 -0700 Lines: 16 Message-ID: <746q26F11tsctU1@mid.individual.net> References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net cH9H6M5Zk8/o57hUpqUeDwC/PxAoxchT7rrP2F6d8K52pcMkl9 Cancel-Lock: sha1:MDscLjFrdQXQH4zQleom8wlPoUA= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:842 Jonathan Bromley wrote: > ...the process P drives ALL FOUR elements of S, > even though you and I can easily see that the FOR-loop > can only iterate over elements 2 and 3. > > Sometimes you can work around that using a > GENERATE-loop, which is elaborated statically. > And it is always possible to work around it using > additional intermediate signals. Or I can use variables in a single process entity for internal regs, and reserve the signal assignments for ports only. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!c9g2000yqm.googlegroups.com!not-for-mail From: sdguy Newsgroups: comp.lang.vhdl Subject: Re: counter in state machine Date: Thu, 9 Apr 2009 22:06:51 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <568b46a0-d98a-442e-842b-666151c44cd4@c9g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 76.88.4.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239340011 1792 127.0.0.1 (10 Apr 2009 05:06:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Apr 2009 05:06:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c9g2000yqm.googlegroups.com; posting-host=76.88.4.1; posting-account=iuzo3goAAABSkSILXzW4rVFsFrCtTAQe User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:843 On Apr 8, 8:16=A0pm, "tringuyen...@gmail.com" wrote: > Hi all, > > I am trying to simulate a state machine that has a counter. =A0Below is > the code. =A0When I run the simulation, it gets stuck at BEGIN_COUNT and > start_flag_counter is X"01" throughout the whole simulation. =A0I can't > figure out what is wrong. =A0May be it is something obvious that I can't > see. =A0thank you for your input. > > =A0 =A0SYNC_PROC: process (clk_100, SYS_RST_N) > =A0 =A0begin > =A0 =A0 =A0 if (SYS_RST_N=3D'0') then > =A0 =A0 =A0 =A0 =A0state_count <=3D INIT; > =A0 =A0 =A0 =A0 =A0clk_100_locked_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0lock_reg_int_reg <=3D '0'; > =A0 =A0 =A0 elsif rising_edge(clk_100) then > =A0 =A0 =A0 =A0 =A0state_count <=3D next_state; > =A0 =A0 =A0 =A0 =A0clk_100_locked_reg <=3D clk_100_locked; > =A0 =A0 =A0 =A0 =A0lock_reg_int_reg <=3D lock_reg_int; > =A0 =A0 =A0 end if; > =A0 =A0end process; > > =A0 =A0start_sig: process(state_count, clk_100_locked_reg, > lock_reg_int_reg) > =A0 =A0begin > =A0 =A0 =A0 case state_count is > =A0 =A0 =A0 =A0 =A0when INIT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D X"00"; > =A0 =A0 =A0 =A0 =A0 =A0 if clk_100_locked_reg =3D '1' and lock_reg_int_re= g =3D '1' > then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D BEGIN_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D INIT; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when BEGIN_COUNT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D start_flag_counter + 1; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 if start_flag_counter =3D X"64" then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D START_FLAG; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D BEGIN_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when START_FLAG =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D start_flag_counter + 1; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 if start_flag_counter =3D X"6A" then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D STOP_COUNT; > =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0next_state <=3D START_FLAG; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0when STOP_COUNT =3D> > =A0 =A0 =A0 =A0 =A0 =A0 start_flag_counter <=3D X"00"; > =A0 =A0 =A0 =A0 =A0 =A0 start_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 next_state <=3D STOP_COUNT; > =A0 =A0 =A0 end case; > =A0 =A0end process; thanks for all the suggestions. It works!! From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p11g2000yqe.googlegroups.com!not-for-mail From: florinfr@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Pipelining a multi-dimensional array. Date: Fri, 10 Apr 2009 01:41:17 -0700 (PDT) Organization: http://groups.google.com Lines: 98 Message-ID: References: <35eb65fd-c6d9-4c2b-baac-04fbcd92cc58@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 213.233.93.218 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239352878 31110 127.0.0.1 (10 Apr 2009 08:41:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Apr 2009 08:41:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000yqe.googlegroups.com; posting-host=213.233.93.218; posting-account=woUPTwoAAAD_WvdVTeT13eJxDKfXMu_y User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:844 On Apr 8, 5:07=A0pm, Novlednes wrote: > Hi, > > I'm trying to pipeline the multi-dimensional array T in the following > code snippet. The pipelining is done in process p_Pipe. However, there > is a driver on T(0) in process p_Sim. No problem you would think, > since the for loop in p_Pipe only addresses elements T(1), T(2) and T > (3). For some reason, my simulator (Modelsim) appears to translate the > for loop in a driver on T(0) as well, leading to all Xs on T(0). But > when unfolding the for loop in individual assignments (see the inline > comments) for T(1), T(2) and T(3), there is no problem anymore: the > pipeline behaves as expected. > > What I cannot put my finger on, is why the individual assignments > behave differently than the for loop? Does anyone have some insights > on that? > > library IEEE; > use IEEE.std_logic_1164.all; > > entity tb_MultiDimArray is > end tb_MultiDimArray; > > architecture Simulation of tb_MultiDimArray is > > =A0 =A0subtype t_Word =A0 =A0is std_logic_vector(31 downto 0); > =A0 =A0type t_T =A0 =A0 =A0 =A0 =A0is array(0 to 3) of t_Word; > > =A0 =A0signal Clk =A0 =A0 : std_logic :=3D '1'; > =A0 =A0signal T =A0 =A0 =A0 : t_T :=3D (others =3D> (others =3D> '1')); > > begin > > =A0 =A0p_Clock : process > =A0 =A0begin > =A0 =A0 =A0 loop > =A0 =A0 =A0 =A0 =A0Clk <=3D not Clk; =A0-- do not forget to initialize th= e clock ! > =A0 =A0 =A0 =A0 wait for 5 ns; > =A0 =A0 =A0 =A0 end loop; > =A0 =A0end process p_Clock; > > =A0 =A0p_Pipe : process(Clk) > =A0 =A0begin > =A0 =A0 =A0 if rising_edge(Clk) then > =A0 =A0 =A0 =A0 =A0-- T(1) <=3D T(0); > =A0 =A0 =A0 =A0 =A0-- T(2) <=3D T(1); > =A0 =A0 =A0 =A0 =A0-- T(3) <=3D T(2); > > =A0 =A0 =A0 =A0 =A0for i in 0 to 2 loop > =A0 =A0 =A0 =A0 =A0 =A0 T(i+1) <=3D T(i); > =A0 =A0 =A0 =A0 =A0end loop; > > =A0 =A0 =A0 end if; -- rising_edge > =A0 =A0end process p_Pipe; > > =A0 =A0p_Sim: process > =A0 =A0begin > =A0 =A0 =A0 wait until falling_edge(Clk); > =A0 =A0 =A0 T(0) <=3D (others =3D> '0'); > =A0 =A0 =A0 wait; -- Will wait forever. > =A0 =A0end process p_Sim; > > end Simulation; Hi, You can try this (I hope this is what you intended in the first place): library IEEE; use IEEE.std_logic_1164.all; entity tb_MultiDimArray is end tb_MultiDimArray; architecture Simulation of tb_MultiDimArray is type t_T is array(0 to 3) of std_logic_vector(31 downto 0); signal Clk : std_logic :=3D '1'; signal T : t_T :=3D (others =3D> (others =3D> '1')); begin Clk <=3D not Clk after 5 ns; p_Pipe : process(Clk) variable vZEROS : std_logic_vector(31 downto 0) :=3D (others =3D> '0'); begin if rising_edge(Clk) then T <=3D vZEROS & T(0 to 2); end if; -- rising_edge end process p_Pipe; end Simulation; F From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!q9g2000yqc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Constrained Random Verification with VHDL Date: Fri, 10 Apr 2009 07:08:08 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <5691ef22-5497-4aee-a065-8eaefa9b1bca@q9g2000yqc.googlegroups.com> NNTP-Posting-Host: 98.246.140.247 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239372488 28920 127.0.0.1 (10 Apr 2009 14:08:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Apr 2009 14:08:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q9g2000yqc.googlegroups.com; posting-host=98.246.140.247; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:845 I have just released the packages we use for doing constrained random verification with VHDL at http://www.synthworks.com/downloads/index.htm You will also find the slides from the webiniar I did with Aldec which will give you ideas at how to apply them. The package uses VHDL-2002 protected types and work with any simulator that supports them. I have tested them with Active-HDL, Riviera, and ModelSim. There are places where the procedures need to be able to work with variable sized sets of integer values. To do this I used an unconstrained integer array input to the subprograms. Since there is a type named integer_vector that does this in VHDL-2008, I decided to leverage that. So for a short time, there will be two sets of packages - one that references package ieee_proposed.standard_additions and another that requires one to use the VHDL-2008 switch on your compiler. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsfeed.r-kom.de!news.m-online.net!not-for-mail From: Arnim Newsgroups: comp.lang.vhdl Subject: Re: Reading memory images into a VHDL testbench Date: Sat, 11 Apr 2009 09:33:37 +0200 Organization: (posted via) M-net Telekommunikations GmbH Lines: 16 Message-ID: References: NNTP-Posting-Host: ppp-82-135-88-46.dynamic.mnet-online.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: svr7.m-online.net 1239435119 16006 82.135.88.46 (11 Apr 2009 07:31:59 GMT) X-Complaints-To: abuse@m-online.net NNTP-Posting-Date: Sat, 11 Apr 2009 07:31:59 +0000 (UTC) User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: X-Enigmail-Version: 0.95.7 Xref: news.eternal-september.org comp.lang.vhdl:846 > I don't have time > to do a thorough job on all of them. It's easy > and quick to do something that's *almost* right > but, like most things in life, doing it properly > costs real work. I wouldn't bother with Intel HEX or S-record but focus on one single reader implementation. Do only one job but do it right :-) There are other tools that focus on format conversion, e.g. Srecord: http://srecord.sf.net/ Reads/writes verilog VMEM, HEX, S-record, MIF, and many others (COE's missing yet). Arnim From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 11 Apr 2009 14:10:10 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: resell d&g t-shirts polo t-shirts gucci shoes era caps lv bag kids sandals shoes Date: Sat, 11 Apr 2009 12:08:51 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 59.60.115.46 Lines: 24 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-4OKVrSNDqiw6tSvNqIVcknhsjmOpi7a61FAJHyozopwH+aDQbpEcvN7DdtG5Y2WsserKGMR5zPQnMyy!75lk5Q27eHme/ggNHRZLDvXzh4a0fYF2pnOpL/JkY+7rDptI+9WEDBqRHyQ= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 6 X-Original-Bytes: 2170 Xref: news.eternal-september.org comp.lang.vhdl:847 We are a manufacture who offer the first-class quality, reasonable prices, timely shipping and best after-sales service. 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Thanks. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!v19g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Constrained Random Verification with VHDL Date: Mon, 13 Apr 2009 06:46:42 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <8349a7ca-9268-462b-915d-d75d83b2aa95@v19g2000yqn.googlegroups.com> References: <5691ef22-5497-4aee-a065-8eaefa9b1bca@q9g2000yqc.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239630402 18396 127.0.0.1 (13 Apr 2009 13:46:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Apr 2009 13:46:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:849 Jim, Nice work! Consider support for fixed and/or floating point types? I guess a separate package of functions for those types could be defined that simply converts to arguments SLV/signed/unsigned and calls this package's functions. Ideally, I suppose there should be separate packages for each set of types (std_logic, numeric_std, numeric_bit, fixed_point, floating_point). Given that the range of valid values for the elements of RandomSeedType is constrained to much less than that of integer, why did you choose integer_vector as its base type? Seems like a custom type would be more useful (bounds checking), and less of a hassle given the current status of integer_vector. Just like we have multiple standard types of vectors of SL for different purposes, I see no reason why we should not have different types of vectors of integer, especially when there are different ranges to be enforced on the elements. Use of capitalization (instead of '_') for word separation in identifiers is not in keeping with current ieee standard packages. If this is intended for eventual inclusion in the ieee standard (I think it should be), will these identifiers require changing? Just one of my pet peeves, but I do not recommend naming conventions that use capitalization (especially mixed) in a language that ignores capitalization in identifiers. This naming convention works well in C and other languages, but not in VHDL. Regardless, I believe efforts bound for standardization should stick to the naming conventions already present in the standard packages. Andy From newsfish@newsfish Wed Aug 19 13:24:07 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.buerger.net!news.cs.univ-paris8.fr!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!x3g2000yqa.googlegroups.com!not-for-mail From: Aiken Newsgroups: comp.lang.vhdl Subject: Re: Synchronization Date: Mon, 13 Apr 2009 10:18:49 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <5ef64be8-08da-4c87-9834-8fb8c7fa9073@x3g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 199.10.150.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239643130 13011 127.0.0.1 (13 Apr 2009 17:18:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Apr 2009 17:18:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqa.googlegroups.com; posting-host=199.10.150.140; posting-account=o1NIRQoAAACD94UsAWOsHscwtNA8hiam User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:850 Did you check the DAC data sheet the SETUP and HOLD time for the DAC you may need to Hold/Set your data to the DAC at rising/falling edge in the DAC clock. On Apr 6, 2:09=A0pm, Andy Peters wrote: > On Apr 2, 10:06=A0am, john wrote: > > > Hello, > > > Clock (clk1x) is a 100MHz clock and the VHDL program is using it to > > read the SDRAM. I need to load the SDRAM with the data and then send > > it to the Digital to Analog converter. The DAC works with 1MHz clock, > > 49 bits of data and a Tag signal which tells the DAC that a new 49 bit > > data is available. I tried to divide the 100MHz clock to 1MHz and send > > the data to the clock. =A0But I am unable to see the DAC working. I > > hooked up the logic analyzer and looked at the signals. The Tag who > > should repeats itself after every 49 bits is not stable at all. it > > repeats multiple times during the data stream and resets the DAC. My > > code is given below. I am having clock synchronization problems. > > Please advice. John > > Wow, more two-process state machine lossage. > > And you've declared both numeric_std and std_logic_arith. > > -a From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!i28g2000prd.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Constrained Random Verification with VHDL Date: Mon, 13 Apr 2009 14:01:03 -0700 (PDT) Organization: http://groups.google.com Lines: 110 Message-ID: References: <5691ef22-5497-4aee-a065-8eaefa9b1bca@q9g2000yqc.googlegroups.com> <8349a7ca-9268-462b-915d-d75d83b2aa95@v19g2000yqn.googlegroups.com> NNTP-Posting-Host: 98.246.140.247 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239656463 23852 127.0.0.1 (13 Apr 2009 21:01:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Apr 2009 21:01:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000prd.googlegroups.com; posting-host=98.246.140.247; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:851 Andy, > Consider support for fixed and/or floating point types? I guess a > separate package of functions for those types could be defined that > simply converts to arguments SLV/signed/unsigned and calls this > package's functions. Ideally, I suppose there should be separate > packages for each set of types (std_logic, numeric_std, numeric_bit, > fixed_point, floating_point). I considered it. There is a road block in that each package instance creates a new type, and hence, it is not really possible for general support. I think there may also be other issues WRT larger (> 62 bits) numbers. The seeds for uniform are 62 bits. Can a 62 bit seed generate numbers that are bigger than 62 bit that cover the entire value set? Instead of trying to answer this question, I separated out RandomBasePkg to allow the seeds, the base randomization (currently uniform) and any customizations (currently FAVOR_SMALL and FAVOR_BIG) to be easily changed without having to worry about disturbing the rest of RandomPkg. Long term, I expect RandomBasePkg to evolve to address common customizations and maybe to handle an extended range of numbers (if it does not adversely effect performance). I was also thinking that RandomSeedType, RandomModeType and randomize could be passed as package generics to the package (unless generics get added to protected types/classes in the future - in which case, add them there). > Given that the range of valid values for the elements of > RandomSeedType is constrained to much less than that of integer, why > did you choose integer_vector as its base type? Seems like a custom > type would be more useful (bounds checking), and less of a hassle > given the current status of integer_vector. Just like we have multiple > standard types of vectors of SL for different purposes, I see no > reason why we should not have different types of vectors of integer, > especially when there are different ranges to be enforced on the > elements. For the seeds that makes sense. Changing it to a record with constrained subtypes of integer would be transparent since an aggregate is used to set the seeds. However, since other things use integer vector (randomizing sparse sets of numbers and exclude vectors), it does not remove the need for an integer array type. I thought that long term, using one type for this application would make it easier to keep general. > Use of capitalization (instead of '_') for word separation in > identifiers is not in keeping with current ieee standard packages. If > this is intended for eventual inclusion in the ieee standard (I think > it should be), will these identifiers require changing? =A0Just one of > my pet peeves, but I do not recommend naming conventions that use > capitalization (especially mixed) in a language that ignores > capitalization in identifiers. My pinky finger curses the person that put the '_' key in such an inconvenient place on the key board. Shift key is so much easier. In being nice to my fingers, I adopted mix cased names for signals, variables, and subprograms. > This naming convention works well in C and other languages, but > not in VHDL. I would disagree. VHDL makes things safer by allowing only one spelling of a name to be visible whether it is mixed or all lower case with '_'. Whether you use '_' or mixed case in VHDL, it is nothing more than a visual thing. Sure '_' forces one to make the subprogram calls more readable, but if this is your only mechanism to force people to write readable code you are in real trouble. > Regardless, I believe efforts bound for standardization should > stick to the naming conventions already present in the standard > packages. While I want to standardize them with IEEE, I do not think they are a practical solution. To be able to display the contents of VHDL packages in tools, either the standards WG (which has no money) or the vendors need to pony up a significant amount of money ($15K - 60K) to IEEE-SA. As the IEEE VHDL chair, I have already invested time into looking into this issue and IEEE does not seem to be flexible. I am thinking that they need to remain open source. That would allow vendors to distribute them and all to use them and see the packages and/or documentation. Perhaps then we need to form a separate organization for peer review. I have several other packages that I will also be releasing. While I not too excited about switching naming styles within a large set of packages and my pinky finger is even less excited, I may be able to be swayed. However, perhaps this is the difference between the packages developed by the different organizations. Note that I also have legacy considerations as we also have been distributing these packages to students in our training classes for several years now. Best, Jim P.S. IEEE is great for working on the base standard and I am hoping we can add more verification features to the language (such as classes and declarative class based randomization). From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.glorb.com!postnews.google.com!n7g2000prc.googlegroups.com!not-for-mail From: Vikram Newsgroups: comp.arch.fpga,comp.dsp,comp.lang.verilog,comp.lang.vhdl Subject: Find FPGA updates On Twitter Date: Mon, 13 Apr 2009 15:22:01 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <4af78531-9571-4cd3-9437-fed73274249f@n7g2000prc.googlegroups.com> NNTP-Posting-Host: 171.71.145.235 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239661321 6849 127.0.0.1 (13 Apr 2009 22:22:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Apr 2009 22:22:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000prc.googlegroups.com; posting-host=171.71.145.235; posting-account=ROblUgoAAABUCieY-adRND7iPJOdhLol User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:2639 comp.dsp:4381 comp.lang.verilog:342 comp.lang.vhdl:852 Guys, Wanted to let you know abou the FPGA Twitter at http://twitter.com/fpga , it is a great way to follow what is hapenning in the FPGA world.. -Vikram From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.supernews.com!news.supernews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 13 Apr 2009 22:49:19 -0500 From: Jack Klein Newsgroups: comp.arch.fpga,comp.dsp,comp.lang.verilog,comp.lang.vhdl Subject: Re: Find FPGA updates On Twitter Date: Mon, 13 Apr 2009 22:49:19 -0500 Message-ID: References: <4af78531-9571-4cd3-9437-fed73274249f@n7g2000prc.googlegroups.com> X-Newsreader: Forte Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 X-Trace: sv3-7JbqpV9dJfJQDfttG5dXDTDATVum3HKWnhpnnHGiNXDYifKzaOM6Zl1HrRzp+PVDtQXxh3/Ex3VYym8!Tt/WAs2BjCaMOnG3cSA4ep7MzI/TxuA6Y/r8huXIxpDaA3i1jieTXwOOFWmUWqCh8TS92XtUaGmn!hB0Q7Fk= X-Complaints-To: www.supernews.com/docs/abuse.html X-DMCA-Complaints-To: www.supernews.com/docs/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.arch.fpga:2642 comp.dsp:4385 comp.lang.verilog:343 comp.lang.vhdl:853 On Mon, 13 Apr 2009 15:22:01 -0700 (PDT), Vikram wrote in comp.dsp: > Guys, > > Wanted to let you know abou the FPGA Twitter at http://twitter.com/fpga > , it is a great way to follow what is hapenning in the FPGA world.. No, it is not. Do you think everyone is as idiotic as you are? -- Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://c-faq.com/ comp.lang.c++ http://www.parashift.com/c++-faq-lite/ alt.comp.lang.learn.c-c++ http://www.club.cc.cmu.edu/~ajo/docs/FAQ-acllc.html From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.unit0.net!newsfeed.sovam.com!mtu.ru!teleglobe.net!uunet!dca.uu.net!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: MEMORY MODELS EXPERTISE ?? Date: Tue, 14 Apr 2009 09:01:43 +0200 Organization: NetVision InterNetNews site Lines: 20 Message-ID: NNTP-Posting-Host: 85-250-237-251.bb.netvision.net.il X-Trace: localhost.localdomain 1239686996 12962 85.250.237.251 (14 Apr 2009 05:29:56 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Tue, 14 Apr 2009 05:29:56 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:854 Hi all I am new to VHDL and I am looking for an expertise direction. Lately I came to conclusion that I want to focus on memories modeling from all kinds , SRAM , ROM, FLASH etc. My question is : Is it realistic to focus on memories modeling , is there a market for such expertise. I ask this because there are many free online models of memories but in the other hand , there are many many memories and memories stacks that need to be modeled for new ASIC , MICRO and FPGA based systems. Thanks in advance EC From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.swapon.de!news.glorb.com!postnews.google.com!c36g2000yqn.googlegroups.com!not-for-mail From: serkany Newsgroups: comp.lang.vhdl Subject: A Simple Integrated Circuit Design with Factorial Calculation Date: Tue, 14 Apr 2009 07:46:15 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> NNTP-Posting-Host: 193.255.198.69 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239720376 14889 127.0.0.1 (14 Apr 2009 14:46:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Apr 2009 14:46:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c36g2000yqn.googlegroups.com; posting-host=193.255.198.69; posting-account=d_BWvQoAAACZqHJ1ZneDTNHrO9Jb7XXO User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:855 Hi, I have been studying VHDL for a couple of months through the book named as "Circuit Design with VHDL" by Volnei A. Pedroni. It is a useful book for beginners. But I may ask you a few questions to make my mind confident. 1- I learnt basic structures of VHDL. And I want to make a simple design to calculate 5! factorial in a design. I want to design a chip for this work. I wanna add memory, RAM and such units to this project... Which book you advise me to learn those things? Where can I start to use my theoretical knowledge? 2- What steps should I take to be a good VHDL programmer? 3- I am in the last year of university in electrical-electronics engineering. I want to assign myself to PLC, Scada, Automatic Control, VHDL and FGPA design. Do I have a Master of Science chance in an American university? Which of them may work for me to apply for master? Thanks in Advance, From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.unit0.net!news.glorb.com!news2.glorb.com!postnews.google.com!y6g2000prf.googlegroups.com!not-for-mail From: beckjer Newsgroups: comp.lang.vhdl Subject: Re: MEMORY MODELS EXPERTISE ?? Date: Tue, 14 Apr 2009 10:07:48 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <216ca034-009c-4173-97b7-eeba82e1a286@y6g2000prf.googlegroups.com> References: NNTP-Posting-Host: 209.237.32.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239728868 10274 127.0.0.1 (14 Apr 2009 17:07:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Apr 2009 17:07:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y6g2000prf.googlegroups.com; posting-host=209.237.32.1; posting-account=IBJIuQoAAAA2I4Rzdg-BG2Cirx4vQ-NJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:856 On Apr 13, 11:01=A0pm, "RealInfo" wrote: > Hi all > > I am new to VHDL and I am looking for an =A0expertise direction. > > Lately I came to conclusion that I want to focus on memories modeling fro= m > all kinds , SRAM , ROM, FLASH etc. > > My question is : Is it realistic to focus on memories modeling , is there= a > market for such expertise. > > I ask this because there are many free online models of memories but in t= he > other hand , there are many many memories and memories stacks > that need to be modeled for new =A0ASIC , MICRO and FPGA based systems. > > Thanks in advance > > EC Having come from the memory industry (Lexar/Micron), I can say that there are a few areas of interest - which can also be valuable outside the memory world. Memory is a commodity product, it will always be needed - but it won't be as "glamorous" as the latest AMD/Intel chip. The first is error detection/correction. It is amazing how few people actually understand this topic properly when determining how many bits it requires for complete failure. The second is interface. Memory is all about how fast can you get data without corruption (there are few applications, that require long term persistence over speed - Library of Congress being one). I put in here the decision of how large a block of memory you need to address at a time (2Kb vs 512b makes a big difference in performance when updating a FAT) These two are fairly universal in most projects, IMHO. It all boils down to what is the best way to get data? (Pick your definition of best) Memory tends to be driven by how people want to access it. The end result almost never is a perfect fit for any market, but very darn close to several high volume markets. Of course this was based on my interests, there are other specialties within the memory world. From newsfish@newsfish Wed Aug 19 13:24:08 2009 Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> Subject: Re: A Simple Integrated Circuit Design with Factorial Calculation Lines: 51 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.127.59 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe01.ams2 1239729311 86.16.127.59 (Tue, 14 Apr 2009 17:15:11 UTC) NNTP-Posting-Date: Tue, 14 Apr 2009 17:15:11 UTC Organization: virginmedia.com Date: Tue, 14 Apr 2009 18:15:06 +0100 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news4us.nl!goblin2!goblin.stu.neva.ru!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe01.ams2.POSTED!7564ea0f!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:857 "serkany" wrote in message news:5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com... > Hi, > I have been studying VHDL for a couple of months through the book > named as "Circuit Design with VHDL" by Volnei A. Pedroni. It is a > useful book for beginners. But I may ask you a few questions to make > my mind confident. > > 1- I learnt basic structures of VHDL. And I want to make a simple > design to calculate 5! factorial in a design. I want to design a chip > for this work. I wanna add memory, RAM and such units to this ^^^^^^ I would personally refrain from using contractions like wanna instead of want to. Although English is not my native language I do know that if you use constructs like this on your CV or in an email to a prospective employer they might not appreciate it and in the current climate you really have to dot your i's and cross your t's. > project... Which book you advise me to learn those things? Where can I > start to use my theoretical knowledge? Get yourself a low-cost prototype board like drigmorn1 and some free tools are start working on your factorial design. Make sure you spend enough time on properly simulating and testing your design and don't just burn and try or eyeball the waveform as a means of verification. Your future employer might ask you about this. > > 2- What steps should I take to be a good VHDL programmer? Practise, practise and practise and ignore any advice that SystemVerilog is the way forward :-) > > 3- I am in the last year of university in electrical-electronics > engineering. I want to assign myself to PLC, Scada, Automatic Control, > VHDL and FGPA design. Do I have a Master of Science chance in an > American university? Which of them may work for me to apply for > master? Contact the University and ask what their entry requirements are. Hans www.ht-lab.com > > Thanks in Advance, From newsfish@newsfish Wed Aug 19 13:24:08 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.tanoz.com!news.albasani.net!newsfeed.freenet.de!border-2.ams.xsnews.nl!feed.xsnews.nl!border-3.ams.xsnews.nl!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf02.ams.highwinds-media.com!newsfe04.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: MEMORY MODELS EXPERTISE ?? Lines: 40 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.127.59 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe04.ams2 1239730476 86.16.127.59 (Tue, 14 Apr 2009 17:34:36 UTC) NNTP-Posting-Date: Tue, 14 Apr 2009 17:34:36 UTC Organization: virginmedia.com Date: Tue, 14 Apr 2009 18:32:49 +0100 Xref: news.eternal-september.org comp.lang.vhdl:858 "RealInfo" wrote in message news:gs170k$cl2$1@localhost.localdomain... > Hi all > > I am new to VHDL and I am looking for an expertise direction. > > Lately I came to conclusion that I want to focus on memories modelling > from all kinds , SRAM , ROM, FLASH etc. I am sure the VHDL community will appreciate VHDL models of popular Micron SDRAM/DDR devices. It is such a shame Micron only cares about Verilog users . > > My question is : Is it realistic to focus on memories modeling , is there > a market for such expertise. Virtual prototyping is growing area and if you look at companies like Denali there is definitely a market for them. > > I ask this because there are many free online models of memories but in > the other hand , there are many many memories and memories stacks > that need to be modeled for new ASIC , MICRO and FPGA based systems. There are lots of models but never the one you want ;-) Hans www.ht-lab.com > > Thanks in advance > > EC > > > From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.tanoz.com!news.albasani.net!feeder.erje.net!news-1.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: A Simple Integrated Circuit Design with Factorial Calculation Date: Tue, 14 Apr 2009 12:38:06 -0700 Lines: 16 Message-ID: <49E4E61E.8050807@gmail.com> References: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Sfhgh3gGOJDlh4u3ycobEAAXWnuVmzky34IOkCBcWMyduFzmzs Cancel-Lock: sha1:lFgc2+uypCBeaCwRYM4nV2e1QRE= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:859 serkany wrote: > 1- I learnt basic structures of VHDL. And I want to make a simple > design to calculate 5! factorial in a design. That's more of a compile time constant than a design: test_output <= std_logic_vector(to_unsigned(factorial(5),8)); > 2- What steps should I take to be a good VHDL programmer? I would 1. Learn synchronous digital design techniques. 2. Learn vhdl simulation. 3. Not call myself a programmer. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.z74.net!news.z74.net!news.glorb.com!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi070.nbdc.sbc.com.POSTED!60c1a94d!not-for-mail From: "ISQED" Newsgroups: comp.lang.vhdl Subject: ASQED Final call for Papers - KL Malaysia Lines: 50 Organization: ISQED MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Windows Mail 6.0.6001.18000 X-MimeOLE: Produced By Microsoft MimeOLE V6.0.6001.18049 Message-ID: NNTP-Posting-Host: 71.131.20.98 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi070.nbdc.sbc.com 1239746990 ST000 71.131.20.98 (Tue, 14 Apr 2009 18:09:50 EDT) NNTP-Posting-Date: Tue, 14 Apr 2009 18:09:50 EDT X-UserInfo1: SCSYQN_@FS@UC]X[GJID]_\@VR]^@B@MCPWZKB]MPXHTEPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Tue, 14 Apr 2009 15:10:36 -0700 Xref: news.eternal-september.org comp.lang.vhdl:860 1st Asia Symposium on Quality Electronic Design ASQED'09 July 15-16, 2009 Kuala Lumpur, Malaysia http://www.isqed-asia.org EXTENDED SUBMISSION DEADLINE: April 17, 2009 Due to demand by many authors the paper submission deadline for the 1st Asia Symposium on Quality Electronic Design (ASQED'09) has been extended to April 17th. This is a firm deadline and will not be extended any further. ASQED09 is accepting papers and tutorial proposals in the following topics: o Circuit & System Design o Test & Verification o IC Packaging Technology o PCB and PWB Technology & Manufacturing o Semiconductor Technology & Manufacturing o Nano and Bio Electronics Innovations o Photovoltaic Technology & Manufacturing o Electronic Design Automation Methodologies ASQED'09 spans two days, Wednesday and Thursday, in three parallel tracks, planning to host over 60 technical presentations, several keynote speakers, tutorials and other informal meetings. Conference proceedings will be published by IEEE and posted in the digital library. SUBMISSION OF PAPERS Paper submission must be done on-line through the conference web site at http://www.isqed-asia.org. The guidelines for the final paper format are provided on the conference web site. Authors should submit FULL-LENGTH, original, original/unpublished papers (Minimum 4, maximum 10 pages) along with an abstract of about 200 words. To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. The complete contact author information needs to be entered separately. Please check the as-printed appearance of your paper before sending your paper. Contact info09@isqed-asia.org if you have any other questions. Please note the following important dates: o Paper Submission Deadline: April 17, 2009 o Acceptance Notifications: May 16, 2009 o Final Camera-Ready paper: June 2, 2009 From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: sdguy Newsgroups: comp.lang.vhdl Subject: triggered and oscillate a clock Date: Tue, 14 Apr 2009 16:53:41 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <87e0be15-19ee-4150-af45-ae0aeab3b465@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 198.253.49.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239753222 24167 127.0.0.1 (14 Apr 2009 23:53:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Apr 2009 23:53:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=198.253.49.6; posting-account=iuzo3goAAABSkSILXzW4rVFsFrCtTAQe User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:861 Hi all, I am implementing vernier interpolation principles and I am trying to to triggered a clock by a start signal. Input: ref_clk 100mhz Input: start Output: start_clk 95 mhz I can generate the two clocks with DCM using a virtex 4 but I don't want the start_clk to run right away when the program powered up. I want the input start when goes high, to trigger start_clk to oscillate. Someone suggested using BUFGCE with start as CE. but BUFGCE take a running clock and output when CE goes high. I want input start to actually start the oscillation when start goes high. does anyone have a suggestion? thanks From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.arch.fpga,comp.dsp,comp.lang.verilog,comp.lang.vhdl Subject: Re: Find FPGA updates On Twitter Date: Tue, 14 Apr 2009 17:28:51 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <134cf3f2-0180-4c58-afa5-b0c93680f0a8@k41g2000yqh.googlegroups.com> References: <4af78531-9571-4cd3-9437-fed73274249f@n7g2000prc.googlegroups.com> NNTP-Posting-Host: 70.30.217.184 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239755331 16682 127.0.0.1 (15 Apr 2009 00:28:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 00:28:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=70.30.217.184; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:2676 comp.dsp:4427 comp.lang.verilog:351 comp.lang.vhdl:862 On 13 avr, 18:22, Vikram wrote: > Guys, > > Wanted to let you know abou the FPGA Twitter athttp://twitter.com/fpga > , it is a great way to follow what is hapenning in the FPGA world.. > > -Vikram No it isn't. Sorry From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!d38g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: MEMORY MODELS EXPERTISE ?? Date: Tue, 14 Apr 2009 17:36:48 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: NNTP-Posting-Host: 70.7.223.69 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239755808 18329 127.0.0.1 (15 Apr 2009 00:36:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 00:36:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d38g2000prn.googlegroups.com; posting-host=70.7.223.69; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:863 Hi, > I ask this because there are many free online models of memories but in t= he > other hand , there are many many memories and memories stacks > that need to be modeled for new =A0ASIC , MICRO and FPGA based systems. If you want to add value to what is there, you might want to focus on filling in any gaps. One site I find quite useful is the GPL'ed memory models at: http://www.freemodelfoundry.com/fmf_VHDL_models.html If you are charging for the models, you would want to at least have the performance of the FMF models. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y33g2000prg.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Tue, 14 Apr 2009 23:09:23 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> NNTP-Posting-Host: 208.151.245.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239775764 31096 127.0.0.1 (15 Apr 2009 06:09:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 06:09:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y33g2000prg.googlegroups.com; posting-host=208.151.245.189; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:864 > This second point had more to do with the logic generated by the compiler= than > with the use of variables. Take for example: > > WAIT UNTIL clk =3D '1'; > counter :=3D counter + 1; > IF counter =3D 5 THEN > =A0 counter :=3D 0; > END IF; > > vs > > WAIT UNTIL clk =3D '1'; > IF counter =3D 4 THEN > =A0 counter :=3D 0; > END IF; > counter :=3D counter + 1; > > or > > WAIT UNTIL clk =3D '1'; > counter <=3D counter + 1; > IF counter =3D 4 THEN > =A0 counter <=3D 0; > END IF; > > The last 2 examples will usually synthesize into faster logic than the 1s= t, > since the first assumes a + followed by a compare while the last two do t= he > compare directly on the FF output. > Interesting example. While I agree with your conclusions above, there is another contributing factor with the last 2 examples. With an incrementer and a smart synthesis tool, the condition "counter =3D 4" is the same as (converting to unsigned for notation only) "counter(2) =3D '1'" Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi149.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> Subject: Re: More synthesis myths? Lines: 17 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi149.ffdc.sbc.com 1239794256 ST000 99.184.242.197 (Wed, 15 Apr 2009 07:17:36 EDT) NNTP-Posting-Date: Wed, 15 Apr 2009 07:17:36 EDT Organization: at&t http://my.att.net/ X-UserInfo1: OP[EB[SE[RUABQTY]BCBNWX@RJ_XPDLMN@GZ_GYO^JWTEPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Wed, 15 Apr 2009 07:11:05 -0400 Xref: news.eternal-september.org comp.lang.vhdl:865 "JimLewis" wrote in message news:7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com... > another contributing factor with the last 2 examples. With an > incrementer > and a smart synthesis tool, the condition "counter = 4" is the same > as > (converting to unsigned for notation only) "counter(2) = '1'" Which is why it is usually better to code it as "counter >= 4". Then you don't need to have as smart of a synthesis tool in order to reach the conclusion that only bit 2 of the counter is needed. KJ From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!y7g2000yqa.googlegroups.com!not-for-mail From: serkany Newsgroups: comp.lang.vhdl Subject: Re: A Simple Integrated Circuit Design with Factorial Calculation Date: Wed, 15 Apr 2009 05:52:12 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <35af5fd2-5960-49b7-a99b-b44e1a8c5409@y7g2000yqa.googlegroups.com> References: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> <49E4E61E.8050807@gmail.com> NNTP-Posting-Host: 193.255.198.83 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239799932 11409 127.0.0.1 (15 Apr 2009 12:52:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 12:52:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y7g2000yqa.googlegroups.com; posting-host=193.255.198.83; posting-account=d_BWvQoAAACZqHJ1ZneDTNHrO9Jb7XXO User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; tr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:866 @Mike Treseler > That's more of a compile time constant than a design: > test_output <= std_logic_vector(to_unsigned(factorial(5),8)); Actually, my purpose is to find 5! in each trigger CLK. I want to make 4 triggers with RUN button, so at the end we will obtain 5!. first Run trigger : 5 second one : 5*4 third one : 5*4*3 fourth one : 5*4*3*2 Where is my mistake here? Can you have a look at it, everyone? --------------------------------------------- -----------5! factorial calculation----------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; ------------------------------------------- entity factorial is port (clk : IN BIT; result : OUT INTEGER); end factorial; ------------------------------------------- architecture calculation of factorial is signal n: integer :=5; signal temp: integer :=1; begin PROCESS (clk) begin if (clk'EVENT AND clk='1') then temp <= temp * n; n <= n-1; result <= temp; end if; end PROCESS; end calculation; ------------------------------------------ ------------------------------------------ From newsfish@newsfish Wed Aug 19 13:24:09 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!w40g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: A Simple Integrated Circuit Design with Factorial Calculation Date: Wed, 15 Apr 2009 06:15:20 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> <49E4E61E.8050807@gmail.com> <35af5fd2-5960-49b7-a99b-b44e1a8c5409@y7g2000yqa.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239801350 1705 127.0.0.1 (15 Apr 2009 13:15:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 13:15:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w40g2000yqd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:867 On 15 Apr, 13:52, serkany wrote: > @Mike Treseler > > > That's more of a compile time constant than a design: > > test_output <=3D std_logic_vector(to_unsigned(factorial(5),8)); > > Actually, my purpose is to find 5! in each trigger CLK. I want to make > 4 triggers with RUN button, so at the end we will obtain 5!. > first Run trigger =A0 =A0: 5 > second one =A0 =A0 =A0 =A0 =A0 : 5*4 > third one =A0 =A0 =A0 =A0 =A0 =A0: 5*4*3 > fourth one =A0 =A0 =A0 =A0 =A0 : 5*4*3*2 > > Where is my mistake here? Can you have a look at it, everyone? > > --------------------------------------------- > -----------5! factorial calculation----------- > library ieee; > =A0 =A0 use ieee.std_logic_1164.all; > =A0 =A0 use ieee.std_logic_arith.all; > =A0 =A0 use ieee.std_logic_signed.all; > > ------------------------------------------- > entity factorial is > =A0 =A0 port (clk : IN BIT; > =A0 =A0 =A0 =A0 =A0 result : OUT INTEGER); > =A0 =A0 end factorial; > ------------------------------------------- > architecture calculation of factorial is > =A0 =A0 signal n: integer :=3D5; > =A0 =A0 signal temp: integer :=3D1; > > =A0 =A0 begin > =A0 =A0 PROCESS (clk) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 if (clk'EVENT AND clk=3D'1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp <=3D temp * n; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 n <=3D n-1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 result <=3D temp; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 end PROCESS; > =A0 =A0 end calculation; > ------------------------------------------ > ------------------------------------------ after 5 clocks you're going to end up with 0, and it will just stay there. for what you are proprosing, why not do this? type int_array_t is array(natural range<>) of integer; constant VALUES : int_array(0 to 3) :=3D (5, 5*4, 5*4*3, 5*4*3*2); signal idx : integer range 0 to 3; begin process(clk) begin if reset =3D '1' then idx <=3D 0; elsif rising_edge(clk) then if idx =3D 3 then idx <=3D 0; else idx <=3D idx + 1; end if; end if; end process; result <=3D VALUES(idx); From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: A Simple Integrated Circuit Design with Factorial Calculation Date: Wed, 15 Apr 2009 07:10:05 -0700 (PDT) Organization: http://groups.google.com Lines: 125 Message-ID: <2a46559a-4cec-4764-8bba-a22267a7df7d@r34g2000vba.googlegroups.com> References: <5b5bc3f0-f0f4-493f-a69b-26eb4d1a94c9@c36g2000yqn.googlegroups.com> <49E4E61E.8050807@gmail.com> <35af5fd2-5960-49b7-a99b-b44e1a8c5409@y7g2000yqa.googlegroups.com> NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239804605 12206 127.0.0.1 (15 Apr 2009 14:10:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 14:10:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: news.eternal-september.org comp.lang.vhdl:868 On Apr 15, 8:52=A0am, serkany wrote: > @Mike Treseler > > > That's more of a compile time constant than a design: > > test_output <=3D std_logic_vector(to_unsigned(factorial(5),8)); > > Actually, my purpose is to find 5! in each trigger CLK. I want to make > 4 triggers with RUN button, so at the end we will obtain 5!. > first Run trigger =A0 =A0: 5 > second one =A0 =A0 =A0 =A0 =A0 : 5*4 > third one =A0 =A0 =A0 =A0 =A0 =A0: 5*4*3 > fourth one =A0 =A0 =A0 =A0 =A0 : 5*4*3*2 > > Where is my mistake here? Can you have a look at it, everyone? > > --------------------------------------------- > -----------5! factorial calculation----------- > library ieee; > =A0 =A0 use ieee.std_logic_1164.all; > =A0 =A0 use ieee.std_logic_arith.all; > =A0 =A0 use ieee.std_logic_signed.all; > > ------------------------------------------- > entity factorial is > =A0 =A0 port (clk : IN BIT; > =A0 =A0 =A0 =A0 =A0 result : OUT INTEGER); > =A0 =A0 end factorial; > ------------------------------------------- > architecture calculation of factorial is > =A0 =A0 signal n: integer :=3D5; > =A0 =A0 signal temp: integer :=3D1; > > =A0 =A0 begin > =A0 =A0 PROCESS (clk) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 if (clk'EVENT AND clk=3D'1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp <=3D temp * n; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 n <=3D n-1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 result <=3D temp; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 end PROCESS; > =A0 =A0 end calculation; > ------------------------------------------ > ------------------------------------------ As Tricky mentioned, your loop doesn't have a proper termination condition (test for n=3D1) - this means that your result will only be cofrrect for one clock cycle, and whether that's the first or second or fifth clock cycle will depend on what value of n you started with. This kind of structure (where you "toss a value into the wind" and hope you can catch it when the corresponding answer comes back ) is usually a dangerous way to design a system - too many ways to mess up. I added a "done" bit you can observe in the code below. Also, while this is "neat" for a learning project, most real hardware should do something more than once (unless you're computing the number 42), so you want a "start on new input" or a "reset" input as well as an input that isn't constant - I'll leave this to you. You also have to be careful of two other more things: Your calculation outputs an INTEGER as opposed to a std_logic_vector which means that, even though your design might simulate OK on the computer, an FPGA synthesizer is not guaranteed to create the "normal" twos complement bus on the FPGA pins the way you probably want. The other thing to watch out for is that (you mention a RUN button) - on an FPGA eval board, you need to make sure that your RUN button is cleanly debounced - mechanical switches can jiggle enough to make dozens of clock events happen in a matter of milliseconds on the first button press. One way to test if your "framework" (RUN button and output pins) is correct is to change your calculation logic (the factorial) into the simplest logic you can think of: for example, a counter, or just shifting by one bit per clock, or a toggling value every clock and see if your board toggles the outputs. Using a dead-simple computation lets you check that your "other stuff" (like clocking, and initial conditions) are correct before you worry about the math. Also, use "numeric_std" instead of "std_logic_arith" - just because some tutorial written in 1992 says to do it, don't. It's 2008 now. There have been lost of flame wars about this - Google this group to learn more. If I were to take a stab, I'd write it like this (caveat: I'm just typing this on the fly, not testing or compiling): Good luck, - Kenn library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------- entity factorial is port (clk : IN BIT; result : OUT std_logic_vector(7 downto 0); done : out std_logic); end factorial; ------------------------------------------- architecture calculation of factorial is signal n: integer :=3D5; signal temp: integer :=3D1; begin PROCESS (clk) begin if (clk'EVENT AND clk=3D'1') then temp <=3D temp * n; done <=3D '1'; -- provisionally if (n > 1) then n <=3D n-1; done <=3D '0'; -- Oh, wasn't really done end if; result <=3D std_logic_vector(to_unsigned (result,result'length)); end if; end PROCESS; end calculation; ------------------------------------------ From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Wed, 15 Apr 2009 09:54:46 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <803b20f8-7890-4d5f-bea9-95593c7a9ef7@g20g2000vba.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239814486 11546 127.0.0.1 (15 Apr 2009 16:54:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 16:54:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:869 I've always felt "safer" with '>=' or '<=' comparisons rather than '=' on counters, especially when dealing with non-modulo-2^n counters. However, it should be noted that the three examples given do not behave identically. Examples 1 and 3 count from 0 to 4 and repeat. Example 2 counts from 1 to 4 and repeats! Small, fast and wrong is still just wrong. Andy From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!y34g2000prb.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Wed, 15 Apr 2009 16:49:41 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <803b20f8-7890-4d5f-bea9-95593c7a9ef7@g20g2000vba.googlegroups.com> NNTP-Posting-Host: 68.29.125.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239839381 8891 127.0.0.1 (15 Apr 2009 23:49:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Apr 2009 23:49:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y34g2000prb.googlegroups.com; posting-host=68.29.125.18; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:870 > I've always felt "safer" with '>=' or '<=' comparisons rather than '=' > on counters, especially when dealing with non-modulo-2^n counters. > > However, it should be noted that the three examples given do not > behave identically. Examples 1 and 3 count from 0 to 4 and repeat. > Example 2 counts from 1 to 4 and repeats! > > Small, fast and wrong is still just wrong. Except in special cases, I almost always load with a value (or the value from a base register) and down count to zero and detect zero by watching the carry bit. Special cases would be like incrementing to a number with a sparse number of 1's (like 4) as the only thing you need to check are the 1's. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k19g2000prh.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Wed, 15 Apr 2009 17:16:26 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> NNTP-Posting-Host: 68.29.125.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239840986 14300 127.0.0.1 (16 Apr 2009 00:16:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 00:16:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k19g2000prh.googlegroups.com; posting-host=68.29.125.18; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:871 On Apr 15, 4:11=A0am, "KJ" wrote: > "JimLewis" wrote in message > > news:7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com... > > > another contributing factor with the last 2 examples. =A0With an > > incrementer > > and a smart synthesis tool, the condition =A0"counter =3D 4" is the sam= e > > as > > (converting to unsigned for notation only) "counter(2) =3D '1'" > > Which is why it is usually better to code it as "counter >=3D 4". =A0Then= you > don't need to have as smart of a synthesis tool in order to reach the > conclusion that only bit 2 of the counter is needed. > > KJ KJ, I don't think I agree. While >=3D 4 seems to produce similar results to the bit comparison, what about >=3D 5? If I did my kmaps right - yikes this is digging back some, decoding the general sense of >=3D 5 requires: ((Count(2) and Count(0)) or (Count(2) and Count(1)) OTOH, if I count up to 5 and think "=3D" rather than ">=3D", due to properties of counters, I can decode just the bits that are 1 and the resulting logic is: (Count(2) and Count(0)) =3D'1'. For =3D5 or >=3D5 to do as good as decoding bits, you need a smart compiler. OTOH, in a LUT based design, will I notice the difference of 1 LUT pin? Probably not - unless I have alot of counters. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p11g2000yqe.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Wed, 15 Apr 2009 19:06:59 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> NNTP-Posting-Host: 70.50.190.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239847619 20815 127.0.0.1 (16 Apr 2009 02:06:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 02:06:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000yqe.googlegroups.com; posting-host=70.50.190.142; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:872 On Apr 15, 8:16=A0pm, JimLewis wrote: > On Apr 15, 4:11=A0am, "KJ" wrote: > > > "JimLewis" wrote in message > > >news:7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com..= . > > > > another contributing factor with the last 2 examples. =A0With an > > > incrementer > > > and a smart synthesis tool, the condition =A0"counter =3D 4" is the s= ame > > > as > > > (converting to unsigned for notation only) "counter(2) =3D '1'" > > > Which is why it is usually better to code it as "counter >=3D 4". =A0Th= en you > > don't need to have as smart of a synthesis tool in order to reach the > > conclusion that only bit 2 of the counter is needed. > > > KJ > > KJ, > I don't think I agree. =A0While >=3D 4 seems to produce similar results > to the bit comparison, what about >=3D 5? =A0If I did my kmaps right - > yikes this is digging back some, decoding the general sense of >=3D 5 > requires: > ((Count(2) and Count(0)) or (Count(2) and Count(1)) > > OTOH, if I count up to 5 and think "=3D" rather than ">=3D", due to > properties of counters, I can decode just the bits that are 1 > and the resulting logic is: > (Count(2) and Count(0)) =3D'1'. > > For =3D5 or >=3D5 to do as good as decoding bits, you need a smart > compiler. =A0OTOH, in a LUT based design, will I notice the > difference of 1 LUT pin? =A0Probably not - unless I have alot > of counters. > > Cheers, > Jim I think I agree with KJ, but for different reasons. In many of my designs, a counter typically indicates how long to remain in one state of a FSM, or else is used to loop through a shortened (not a full power of two) sequence, like pixel or line count in video. I've always felt that decoding (n >=3D k) instead of (n=3Dk) gives me more of a safety net to get back more quickly to the restart state or get back into the main loop in case I reach an unreachable state (defined for this purpose as n > k). This might happen because I messed up some obscure corner case in my multiple-interconnected-FSM control logic, in which I freely admit I'm at fault. But it's been my experience that getting your chassis hit with 20 kV from an ESD gun during product compliance testing can do unusual things to your flops, which you should still recover from ASAP. It seems to me that on the balance of probability, if I include a "free" check (in the source code sense of free) for unreachable states (e.g. NTSC_LINE_NUMBER >=3D 525 in preference to NTSC_LINE_NUMBER=3D525) then I have a better chance of not getting stuck forever when I go into the weeds. There are a lot of cases where writing stuff in the source (like a redundant 'when others' case in an otherwise fully covered case stmt decoding an enumerated state type) has zero semantic meaning in VHDL. In these cases, one can argue back and forth, and inconclusively, that a tool ought to or ought not to take extra steps to take the hint to cover unreachable states, but there's no clear, LRM-traceable justification for this. But comparing against a counter in a power-of- two modulus bit vector seems to give a pretty clear mandate to the synthesizer. Clearly this design style trick is nowhere near a rigorous proof of recovery (not like a proper CTL model checking run, by any means), but it helps. My next statement will probably offend the hard-core gate bangers, but here goes: I'm too old to care about optimizing the last p-term out of one comparison -- I tend to be more concerned with correctness, recoverability and reliability. I'd much rather it never locks up and recovers quickly when I fuzz test it. - Kenn From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!feeder2.news.saunalahti.fi!feeder1.news.saunalahti.fi!nntp.inet.fi!inet.fi!uunet!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: Re: MEMORY MODELS EXPERTISE ?? Date: Thu, 16 Apr 2009 07:20:21 +0200 Organization: NetVision InterNetNews site Lines: 28 Message-ID: References: NNTP-Posting-Host: 85-250-240-185.bb.netvision.net.il X-Trace: localhost.localdomain 1239853714 30622 85.250.240.185 (16 Apr 2009 03:48:34 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Thu, 16 Apr 2009 03:48:34 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:873 Do I have to use VITAL in memory modeling ? I ask this because I have seen many memory models in VHDL books that use the standard time generics of VHDL . Thanks EC "JimLewis" ??? ??????:cb138c0e-fa6b-418d-a0fc-173c39dea6a6@d38g2000prn.googlegroups.com... Hi, > I ask this because there are many free online models of memories but in > the > other hand , there are many many memories and memories stacks > that need to be modeled for new ASIC , MICRO and FPGA based systems. If you want to add value to what is there, you might want to focus on filling in any gaps. One site I find quite useful is the GPL'ed memory models at: http://www.freemodelfoundry.com/fmf_VHDL_models.html If you are charging for the models, you would want to at least have the performance of the FMF models. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!g37g2000yqn.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: triggered and oscillate a clock Date: Wed, 15 Apr 2009 23:13:30 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: References: <87e0be15-19ee-4150-af45-ae0aeab3b465@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239862410 17419 127.0.0.1 (16 Apr 2009 06:13:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 06:13:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g37g2000yqn.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.7) Gecko/2009032803 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:874 On 15 Apr., 01:53, sdguy wrote: > Hi all, > > I am implementing vernier interpolation principles and I am trying to > to triggered a clock by a start signal. > > Input: ref_clk 100mhz > Input: start > Output: start_clk 95 mhz > > I can generate the two clocks with DCM using a virtex 4 but I don't > want the start_clk to run right away when the program powered up. =A0I > want the input start when goes high, to trigger start_clk to > oscillate. =A0Someone suggested using BUFGCE with start as CE. =A0but > BUFGCE take a running clock and output when CE goes high. =A0I want > input start to actually start the oscillation when start goes high. > does anyone have a suggestion? =A0thanks Hi sdguy, first of all: you can't power up a program. Programms are lists off commands for processors (ore more generic: programmable automatons). These are build in hardware which requres power to work. So you can only power up hardware. Now to your problem. Why would you want to power up a oscillator or DCM later than the rest of your Hardware? Is it for power saving purposes? Well, ok then. But keep in mind the physics. Both circuits need some time to stabilize after power up. DCMs have the LOCKED output to tell you when the clock outputs are stable. So there will be a considerable, but hardly determinable delay between your start signal and the availability of a stable clock. Can you deal with that in your design? To me the BUFGCE idea sounds quite good, even when power saving is required. I guess that the power used by the running DCM alone (that is just driving the net to the BUFGCE-Input) is just a fraction of the power consumtion of the driven clock net when your design gets the start signal. You may make some power measurements on a test circuit to verify my assumption. So, what other reasons do you have for your strange requirement? Have a nice synthesis Eilert From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!nlpi057.nbdc.sbc.com!prodigy.net!kcnewsm01.prserv.net!prserv.net!uunet!dca.uu.net!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: VITAL needed for memories modeling ? Date: Thu, 16 Apr 2009 08:25:41 +0200 Organization: NetVision InterNetNews site Lines: 13 Message-ID: Reply-To: "RealInfo" NNTP-Posting-Host: 85-250-240-185.bb.netvision.net.il X-Trace: localhost.localdomain 1239857634 12156 85.250.240.185 (16 Apr 2009 04:53:54 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Thu, 16 Apr 2009 04:53:54 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:875 Hi all I am learning now modeling of memories of all kinds , RAM , SRAM , DRAM etc .. My question is : Do I have to use VITAL in the memories models which are behavioral , not for synthesis , or it is ok to use the standard VHDL TIME generics to describe the true timing of a memory modeled with VHDL ? Thanks EC From newsfish@newsfish Wed Aug 19 13:24:10 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!f1g2000prb.googlegroups.com!not-for-mail From: sdguy Newsgroups: comp.lang.vhdl Subject: Re: triggered and oscillate a clock Date: Wed, 15 Apr 2009 23:53:36 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: <8235be76-f455-453b-8a14-cc3467040e86@f1g2000prb.googlegroups.com> References: <87e0be15-19ee-4150-af45-ae0aeab3b465@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 76.88.4.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239864816 24975 127.0.0.1 (16 Apr 2009 06:53:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 06:53:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f1g2000prb.googlegroups.com; posting-host=76.88.4.1; posting-account=iuzo3goAAABSkSILXzW4rVFsFrCtTAQe User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:876 On Apr 15, 11:13=A0pm, goo...@twinmail.de wrote: > On 15 Apr., 01:53, sdguy wrote: > > > > > Hi all, > > > I am implementing vernier interpolation principles and I am trying to > > to triggered a clock by a start signal. > > > Input: ref_clk 100mhz > > Input: start > > Output: start_clk 95 mhz > > > I can generate the two clocks with DCM using a virtex 4 but I don't > > want the start_clk to run right away when the program powered up. =A0I > > want the input start when goes high, to trigger start_clk to > > oscillate. =A0Someone suggested using BUFGCE with start as CE. =A0but > > BUFGCE take a running clock and output when CE goes high. =A0I want > > input start to actually start the oscillation when start goes high. > > does anyone have a suggestion? =A0thanks > > Hi sdguy, > first of all: you can't power up a program. Programms are lists off > commands for processors (ore more generic: programmable automatons). > These are build in hardware which requres power to work. So you can > only power up hardware. > > Now to your problem. Why would you want to power up a oscillator or > DCM later than the rest of your Hardware? Is it for power saving > purposes? Well, ok then. But keep in mind the physics. Both circuits > need some time to stabilize after power up. DCMs have the LOCKED > output to tell you when the clock outputs are stable. So there will be > a considerable, but hardly determinable delay between your start > signal and the availability of a stable clock. Can you deal with that > in your design? > > To me the BUFGCE idea sounds quite good, even when power saving is > required. > I guess that the power used by the running DCM alone (that is just > driving the net to the BUFGCE-Input) is just a fraction of the power > consumtion of the driven clock net when your design gets the start > signal. > You may make some power measurements on a test circuit to verify my > assumption. > > So, what other reasons do you have for your strange requirement? > Have a nice synthesis > =A0 Eilert Hi Eilert, what I am trying to do is much better describe in this google book links below (synchronization of digital network). It required that start trigger a clock. It has nothing to do with power saving. books.google.com/books?isbn=3D0471615501 and go to page 326 thanks From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!v19g2000yqn.googlegroups.com!not-for-mail From: olliH Newsgroups: comp.lang.vhdl Subject: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex 4 LX 60) Date: Thu, 16 Apr 2009 01:25:10 -0700 (PDT) Organization: http://groups.google.com Lines: 128 Message-ID: NNTP-Posting-Host: 132.230.169.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239870310 28310 127.0.0.1 (16 Apr 2009 08:25:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 08:25:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqn.googlegroups.com; posting-host=132.230.169.36; posting-account=u-_8RQoAAADmnPy9yIFNjCGPIpHoXIVw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:877 Hi everybody, in my design i have a timing problem with an ADC. I have this problem since my design has become more dense: This is the ADC I'm using: AD677 (http://www.analog.com/static/ imported-files/data_sheets/AD677.pdf) My ADC-Entity has 3 inputs and 3 outputs. (see datasheet) BUSY: IN SCLK: IN SDATA: IN CAL: OUT CLK: OUT SAMPLE: OUT How do i now define the relationship between the CLK-output and the SCLK-input for example? In the datasheet are the timing- specifications. Abstract of my *.UCF file: NET ADC1_BUSY LOC = C25; NET ADC1_SCLK LOC = E24; NET ADC1_SDATA LOC = B24; NET ADC1_CAL LOC = E14; NET ADC1_CLK LOC = D11; NET "ADC1_SAMPLE" LOC = F14; I hope somebody with some experience in constraining a design can give me some hints. The only timing constraint i'm using right now is the period constraint for the 100 MHz-clock i'm using. I'm an absolute beginner in timing-constraint.... In advance thanks a lof for your help. sincerely yours Olli Here the whole UCF-File: CONFIG STEPPING = "2"; NET clk LOC = B13; NET ADC_reset LOC = G9; NET ADC1_BUSY LOC = C25; NET ADC1_CAL LOC = E14; NET ADC1_CLK LOC = D11; NET ADC1_SCLK LOC = E24; NET ADC1_SDATA LOC = B24; NET ADC2_BUSY LOC = F24; NET ADC2_CAL LOC = D13; NET ADC2_CLK LOC = D14; NET ADC2_SAMPLE LOC = C11; NET ADC2_SCLK LOC = C26; NET ADC2_SDATA LOC = E23; NET DEACTIVATE_N LOC = N25; NET MESS_DONE LOC = L26; NET MESS_ENABLE LOC = E2; NET M_RESET LOC = E1; NET DIP_STRING LOC = A4; NET DIP_TD_READMODE LOC = B6; NET DOUT LOC = C24; NET Druck_VCC LOC = F11; NET DIN LOC = A23; NET MCLK LOC = F16; NET SCLK LOC = B23; NET MITTLUNG_LED LOC = V25; NET MITTLUNG0 LOC = B4; NET MITTLUNG1 LOC = C6; NET modell_MESSUNG LOC = G10; NET SER_IN_0 LOC = U4; NET SER_IN_1 LOC = AA11; NET SER_OUT_0 LOC = V4; NET SER_OUT_1 LOC = AC11; NET "SER_OUT_2" LOC = AC15; NET "SER_IN_2" LOC = AC14; NET SHIFT_5_TO_3<7> LOC = AC12; NET SHIFT_5_TO_3<6> LOC = AA13; NET SHIFT_5_TO_3<5> LOC = AD13; NET SHIFT_5_TO_3<4> LOC = AB13; NET SHIFT_5_TO_3<3> LOC = AC13; NET SHIFT_5_TO_3<2> LOC = AA14; NET SHIFT_5_TO_3<1> LOC = AD14; NET SHIFT_5_TO_3<0> LOC = AB14; NET TASTER1 LOC = D2; NET TASTER2 LOC = D1; NET TD_out LOC = F12; NET TD_out2 LOC = F13; NET TD_VCC LOC = D16; NET TD_VCC2 LOC = D15; NET URX_LED LOC = K26; NET URX_TX_go_to LOC = C10; NET "clk" TNM_NET = clk; TIMESPEC TS_clk = PERIOD "clk" 10 ns; NET "mittlung_LED" LOC = V25; NET "ADC1_SAMPLE" LOC = F14; NET "EIN_kHZ" LOC = AA15; NET "EIN_kHz" LOC = AA15; NET "pin_x" LOC = AD25; NET "pin_y" LOC = AC19; NET "pin_z" LOC = AD19; NET "sync" LOC = AC16; NET "sendclk" LOC = AA16; From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v15g2000yqn.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: triggered and oscillate a clock Date: Thu, 16 Apr 2009 04:38:44 -0700 (PDT) Organization: http://groups.google.com Lines: 103 Message-ID: References: <87e0be15-19ee-4150-af45-ae0aeab3b465@k2g2000yql.googlegroups.com> <8235be76-f455-453b-8a14-cc3467040e86@f1g2000prb.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239881924 15389 127.0.0.1 (16 Apr 2009 11:38:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 11:38:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v15g2000yqn.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.7) Gecko/2009032803 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:878 On 16 Apr., 08:53, sdguy wrote: > On Apr 15, 11:13=A0pm, goo...@twinmail.de wrote: > > > > > On 15 Apr., 01:53, sdguy wrote: > > > > Hi all, > > > > I am implementing vernier interpolation principles and I am trying to > > > to triggered a clock by a start signal. > > > > Input: ref_clk 100mhz > > > Input: start > > > Output: start_clk 95 mhz > > > > I can generate the two clocks with DCM using a virtex 4 but I don't > > > want the start_clk to run right away when the program powered up. =A0= I > > > want the input start when goes high, to trigger start_clk to > > > oscillate. =A0Someone suggested using BUFGCE with start as CE. =A0but > > > BUFGCE take a running clock and output when CE goes high. =A0I want > > > input start to actually start the oscillation when start goes high. > > > does anyone have a suggestion? =A0thanks > > > Hi sdguy, > > first of all: you can't power up a program. Programms are lists off > > commands for processors (ore more generic: programmable automatons). > > These are build in hardware which requres power to work. So you can > > only power up hardware. > > > Now to your problem. Why would you want to power up a oscillator or > > DCM later than the rest of your Hardware? Is it for power saving > > purposes? Well, ok then. But keep in mind the physics. Both circuits > > need some time to stabilize after power up. DCMs have the LOCKED > > output to tell you when the clock outputs are stable. So there will be > > a considerable, but hardly determinable delay between your start > > signal and the availability of a stable clock. Can you deal with that > > in your design? > > > To me the BUFGCE idea sounds quite good, even when power saving is > > required. > > I guess that the power used by the running DCM alone (that is just > > driving the net to the BUFGCE-Input) is just a fraction of the power > > consumtion of the driven clock net when your design gets the start > > signal. > > You may make some power measurements on a test circuit to verify my > > assumption. > > > So, what other reasons do you have for your strange requirement? > > Have a nice synthesis > > =A0 Eilert > > Hi Eilert, > > what I am trying to do is much better describe in this google book > links below (synchronization of digital network). =A0It required that > start trigger a clock. =A0It has nothing to do with power saving. > > books.google.com/books?isbn=3D0471615501 =A0and go to page 326 > > thanks Hi sdguy, ok, you are going to create a digital nonius. Nice application. But if you are trying to create a "textbook solution", like shown in the pictures on page 326 you are about to fail. Things to consider here: The input events for start and stop of the two deviant clocks are asynchronous. There's probably no solution to synchronize a stable clock to an asynchronous event as required. But: You may synchronize your event to the deviant clock (simple 2 stage shift register) In this case you get a measurement error due to the synchronization. Find out if that error is acceptable for your application or not. The good news is: With such a simple design you don't have to hassle around with BUFGCEs and so on. The events will just trigger some FSM and/or counters running on the deviant clocks. The bad news is: You have to determine when the reference clock and the deviant clock are switching at the same time. Tricky thing, because your clocks are probably 50% duty cycle clocks, while the book works with discrete events (like delta impulses). How nice it looks in theory, but its a PITA when you want to build some real hardware. Because a delda impulse is just a theoretical construct. You can approcimate it by creating clocks with a very low duty cycle. Still you will get some measurement error due to this fact which needs to be determined and added to the synchronisation error. You need a lot of creativity to find a good solution, because you have to deal with reality. The book shows just a concept, but not the solution. Have a nice synthesis Eilert From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!postnews.google.com!g37g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Thu, 16 Apr 2009 05:29:18 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: <95893957-37aa-4d68-ae2f-693b279104c3@g37g2000yqn.googlegroups.com> References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239884958 25086 127.0.0.1 (16 Apr 2009 12:29:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 12:29:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g37g2000yqn.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:879 On Apr 15, 8:16=A0pm, JimLewis wrote: > On Apr 15, 4:11=A0am, "KJ" wrote: > > > "JimLewis" wrote in message > > >news:7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com..= . > > > > another contributing factor with the last 2 examples. =A0With an > > > incrementer > > > and a smart synthesis tool, the condition =A0"counter =3D 4" is the s= ame > > > as > > > (converting to unsigned for notation only) "counter(2) =3D '1'" > > > Which is why it is usually better to code it as "counter >=3D 4". =A0Th= en you > > don't need to have as smart of a synthesis tool in order to reach the > > conclusion that only bit 2 of the counter is needed. > > > KJ > > KJ, > I don't think I agree. =A0While >=3D 4 seems to produce similar results > to the bit comparison, what about >=3D 5? =A0If I did my kmaps right - > yikes this is digging back some, decoding the general sense of >=3D 5 > requires: > ((Count(2) and Count(0)) or (Count(2) and Count(1)) > > OTOH, if I count up to 5 and think "=3D" rather than ">=3D", due to > properties of counters, I can decode just the bits that are 1 > and the resulting logic is: > (Count(2) and Count(0)) =3D'1'. > I'm not sure that this is a fair comparison, specifically the way you're creating the logic for "=3D5" by virtue of your simply counting the one bits and "due to properties of counters" but not applying that same thinking to the ">=3D" case. The only way you can get the logic that you listed for the "=3D5" case is by 'knowing' that count=3D7 can not occur therefore count(1) is not needed in the decode. Fair enough. But to be fair on the >=3D5 case you should also acknowledge that if one 'knows' that count=3D7 is impossible, then count=3D6 is just as impossible and therefore the "or (Count(2) and Count(1))" term would not be needed and the exact same logic would be produced. A given revision of a given synthesis tool would either have the capability to detect this condition or not and I think would not generate the logic that you listed for '>=3D5' if it was capable of producing the logic that you listed for '=3D5'. > For =3D5 or >=3D5 to do as good as decoding bits, you need a smart > compiler. My point wasn't that a smart compiler wouldn't do better than a not so smart one (the rising tide will lift all boats after all). My point was that for a given compiler, I believe you'll get equivalent or better logic by using >=3D5 than by using =3D5. I'll accept that there might be some instance where this is not true, but I've seen far more instances where it is and have yet to run across the case where it is not. > OTOH, in a LUT based design, will I notice the > difference of 1 LUT pin? =A0Probably not - unless I have alot > of counters. > But that's the reason for these discussions huh? Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o11g2000yql.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Thu, 16 Apr 2009 05:42:36 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239885756 12573 127.0.0.1 (16 Apr 2009 12:42:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 12:42:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yql.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:880 On Apr 15, 10:06=A0pm, kennheinr...@sympatico.ca wrote: > On Apr 15, 8:16=A0pm, JimLewis wrote: > I tend to be more concerned with > correctness, recoverability and reliability. I'd much rather it never > locks up and recovers quickly when I fuzz test it. > I'm fully in the same camp as you on this. The primary reason for >=3D is to insure recovery of the design, a secondary benefit is potentially less logic (and most likely but I've never formally proved it...never produce more logic). From a readability/maintainability/ support perspective either method is equivalent in my opinion. KJ From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k27g2000vbb.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: clock synchronization and flip flops Date: Thu, 16 Apr 2009 12:06:04 -0700 (PDT) Organization: http://groups.google.com Lines: 165 Message-ID: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239908764 22169 127.0.0.1 (16 Apr 2009 19:06:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Apr 2009 19:06:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k27g2000vbb.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:881 Hello All, I am need for some serious advice. I am trying to synchronize the passing of the control signal "Reset_counter" between two clocks namely "clk1x" and clk_b = clk_synch. The clk_b is equal to "clk_divider (6) and generated by dividing the "clk1x" as you can see in the following code. The sequential machine is running on "clk1x" and it generates the signal called "Reset_counter" to reset the 49 bit counter "p2s_counter". This counter outputs 49 bit of serial data at the rising edge of the slower clock "clk_synch". Because "clk_synch" is slower than the "clk1x", so I tired to pass the signal "Reset_counter" through atleast three flip flops as you can see in the code clocking with the slower clock " clk_synch". Then I used the resultant output signal " synch_reset_2" to Reset the 49 bit counter. The sequential state machine " ser_out_state" checks running on "clk1x" for p2s counter to get equal to count 49. after the counter reaches its count the state machine gets into a new state. Since, "clk1x " is way faster than "clk_synch" thats why it will not miss the p2s_counter signal. I am using xess board and foundation code and have all sorts of problems simulating the code. SO thats why i am testing the code using Logic Analyzer. My questions is Am I synchronizing the clocks in the right way? I will appreciate any advice! John combinatorial : process(err_r, addr_r, dIn, rand, begun, done, rdPending, doAgain ) begin case state_r is when INIT => Reset_counter <= '1'; state_x <= Ser_buff_LOAD_1; when Ser_buff_LOAD_1 => Reset_counter <= '1'; state_x <= Ser_buff_LOAD_2; When Ser_buff_LOAD_2 => Reset_counter <='1'; state_x <= Ser_buff_LOAD_3; When Ser_buff_LOAD_3 => Reset_counter <='1'; state_x <= Reset_state; when Reset_state => Reset_counter <='1'; state_x<= Tag_state; when Tag_state => Reset_counter <='1'; state_x <= ser_out_state; ---------------------------------------- when ser_out_state => Reset_counter <='1'; if ( p2s_counter /= "110001") then Reset_counter <='0'; state_x <= ser_out_state; else Reset_counter <='1'; state_x <= Ser_buff_LOAD_1; end if; --------------------------------------- When EMPTY_PIPE => Reset_counter <='1'; if done = YES then cke <= YES; end if; if rdPending = NO then state_x <= STOP; end if; When others => end process; ------------------------------------ -- clk1x is the main clock generated by xess's program update: process (clk1x) begin if clk1x'event and clk1x = '1' then if rst = YES then -- main reset from xess's program state_r <= INIT; else addr_r <= addr_x; state_r <= state_x; end if; end if; end process; ------------------------------------ clk_synch <= clk_b; ------------------------------------- -- 49 bits, parallel to serial port conversion-- serial_count : process ( clk_synch) begin if rising_edge (clk_synch) then if ( synch_reset_2 = '0') Then p2s_counter <= p2s_counter + 1; ser_out<=ser_buff ( to_integer ( p2s_counter ) ); else p2s_counter <= ( others =>'0'); end if; end if; end process; ------------------------------------ Two_flip_flop_synch: process(clk_synch, Reset_counter) variable synch_reset_a : std_logic; variable synch_reset_b: std_logic; begin If (Reset_counter = '1') Then synch_reset_a := '1'; synch_reset_b := '1'; elsif rising_edge (clk_synch) then synch_reset_a :=synch_reset_b; synch_reset_b:= '0'; end if; synch_reset <= synch_reset_a ; end process; ----------------------------------- -- Third Synchronizing Flip Flop to sycnhronize the Reset_counter -- third_flip_flop_synch : process (clk_synch,Reset_counter ) variable synch_reset_c: std_logic; variable synch_reset_d:std_logic; Begin if ( Reset_counter ='1') then synch_reset_c:= '1'; synch_reset_d:='1'; elsif rising_edge (clk_synch) then synch_reset_c:= synch_reset; synch_reset_d:='0'; end if; done_1 <= synch_reset_c; synch_reset_2<= synch_reset_c; end process; ---------------------------------- -- Dividing the 100MHz clk1x to 1MHz clk_synch-- div : process ( rst,clk1x) begin If ( rst = '1') Then clk_divider <= "00000000000"; elsIf rising_edge (clk1x) then clk_divider <= clk_divider + 1; end if; end process; --------------------------------- End arch; -- End of the VHDL Program -- From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!f19g2000yqh.googlegroups.com!not-for-mail From: Massi Newsgroups: comp.lang.vhdl Subject: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 03:29:22 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> NNTP-Posting-Host: 150.145.1.64 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1239964162 20358 127.0.0.1 (17 Apr 2009 10:29:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Apr 2009 10:29:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f19g2000yqh.googlegroups.com; posting-host=150.145.1.64; posting-account=WWUlQQoAAAA7X1fJ_0M7jreoB5ymf0dg User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:882 Hi everyone, I'm working on a Xilinx Virtex 5 FPGA with ISE 10.1. In my design I have to instantiate 128 ram blocks, each one of them is 1024 bytes wide. The outuput of my device depends on only one ram block at a time, therefore I have to multiplex them. Which is the smartest way to implement such a huge multiplexer? Thanks a lot for you help. From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Apr 2009 05:43:46 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 11:41:37 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <1gmgu4dr81t8moaf5i2evckkevha0cg28b@4ax.com> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 68 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-UN7nslNzilDKBSiIepbMsM8bFIDCuM9Qbp3A5zSyiuIigt8Vzv8GDk+PSF1ZBkSI4kVeyzrOGyUc73w!X+3skUoNvcSfE4nb5XoUD10mtJ4feMtKWa7sEfozQdZK74v1xWf5vLqj8bb3sj1h9WOIANNME2c9!Hq0y X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3495 Xref: news.eternal-september.org comp.lang.vhdl:883 On Fri, 17 Apr 2009 03:29:22 -0700 (PDT), Massi wrote: >Hi everyone, I'm working on a Xilinx Virtex 5 FPGA with ISE 10.1. In >my design I have to instantiate 128 ram blocks, each one of them is >1024 bytes wide. The outuput of my device depends on only one ram >block at a time, therefore I have to multiplex them. Which is the >smartest way to implement such a huge multiplexer? Funny, we just answered a query from a customer about almost exactly the same topic. Do you really mean 1024 bytes WIDE? That's way scary - an 8192-bit data path :-) I guess you mean that each RAM block is in fact 1024 locations, each 8 bits wide. That's normally known as a "depth" of 1024. We've found that XST does a better job of optimizing wide MUXes if you code them as an explicit AND-OR structure. I don't know why this is, and I don't know if it will always be true; you could imagine, for example, that a synthesis tool might be able to exploit carry chains to build the big OR gates. Anyway, here's a sketch of the code: -- useful declarations subtype byte is std_logic_vector(7 downto 0); type byte_array is array(natural range <>) of byte; -- one result from each of your 128 RAM blocks signal RAM_read_data: byte_array(0 to 127); -- final output signal mux_data: byte; -- memory selector, chooses one from 128 signal which_RAM: integer range RAM_read_data'range; ... process (RAM_read_data, which_RAM) variable mux_result: byte; begin mux_result := (others => '0'); for i in RAM_read_data'range loop if i = which_RAM then mux_result := mux_result OR RAM_read_data(which_RAM); end if; end loop; mux_data <= mux_result; end process; If this trick doesn't provide the improvement you need, the next step is to consider pipelining. It won't reduce the area, but will give you better Fmax. I'm sure other folk will have more, better ideas. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.unit0.net!news.glorb.com!news2.glorb.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: Massi Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 04:10:17 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <5ad095ae-4a05-4091-8bab-277eb8e9288a@k41g2000yqh.googlegroups.com> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> <1gmgu4dr81t8moaf5i2evckkevha0cg28b@4ax.com> NNTP-Posting-Host: 150.145.1.64 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239966617 28345 127.0.0.1 (17 Apr 2009 11:10:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Apr 2009 11:10:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=150.145.1.64; posting-account=WWUlQQoAAAA7X1fJ_0M7jreoB5ymf0dg User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:884 > Do you really mean 1024 bytes WIDE? That's way scary - > an 8192-bit data path :-) I guess you mean that each > RAM block is in fact 1024 locations, each 8 bits wide. > That's normally known as a "depth" of 1024. Silly me....of course I meant depth, that's my bad english fault. > We've found that XST does a better job of optimizing > wide MUXes if you code them as an explicit AND-OR > structure. =A0I don't know why this is, and I don't > know if it will always be true; you could imagine, > for example, that a synthesis tool might be able > to exploit carry chains to build the big OR gates. > Anyway, here's a sketch of the code: > > =A0 -- useful declarations > =A0 subtype byte is std_logic_vector(7 downto 0); > =A0 type byte_array is array(natural range <>) of byte; > > =A0 -- one result from each of your 128 RAM blocks > =A0 signal RAM_read_data: byte_array(0 to 127); > > =A0 -- final output > =A0 signal mux_data: byte; > > =A0 -- memory selector, chooses one from 128 > =A0 signal which_RAM: integer range RAM_read_data'range; > > =A0 ... > =A0 process (RAM_read_data, which_RAM) > =A0 =A0 variable mux_result: byte; > =A0 begin > =A0 =A0 mux_result :=3D (others =3D> '0'); > =A0 =A0 for i in RAM_read_data'range loop > =A0 =A0 =A0 if i =3D which_RAM then > =A0 =A0 =A0 =A0 mux_result :=3D mux_result OR RAM_read_data(which_RAM); > =A0 =A0 =A0 end if; > =A0 =A0 end loop; > =A0 =A0 mux_data <=3D mux_result; > =A0 end process; > > If this trick doesn't provide the improvement you need, > the next step is to consider pipelining. =A0It won't reduce > the area, but will give you better Fmax. > > I'm sure other folk will have more, better ideas. I really appreciate your help, I'll immediatly try to integrate your code in my design...thank you! From newsfish@newsfish Wed Aug 19 13:24:11 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.buerger.net!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Apr 2009 06:20:39 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 12:18:31 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> <1gmgu4dr81t8moaf5i2evckkevha0cg28b@4ax.com> <5ad095ae-4a05-4091-8bab-277eb8e9288a@k41g2000yqh.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-OIdxdAOQQrEB8CfD3d5rgFmAq479d/sLXtcEpFX/6TalzM8nrHdpUGF8RqIzOsna8U45lLOXEp3r3UF!vxfiZPi1gMk2NTQkBInhpjnoMEyGDhvms/0SzrCnNemOt5+E3QrJC0cDRmO+Pf6CzVR7042ywGxF!3g09 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:885 On Fri, 17 Apr 2009 04:10:17 -0700 (PDT), Massi wrote: >I really appreciate your help, I'll immediatly try to integrate your >code in my design...thank you! OOOOOH, don't do that just yet... sorry.... >>         mux_result := mux_result OR RAM_read_data(which_RAM); No, don't do that. My mistake. Instead,         mux_result := mux_result OR RAM_read_data(i); The difference is that, when the loop is unrolled, you are subscripting the array with a CONSTANT (i) rather than with a variable. It can be important for optimization, even though the two are functionally identical. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!weretis.net!feeder1.news.weretis.net!takemy.news.telefonica.de!telefonica.de!kanaga.switch.ch!switch.ch!newsfeed3.funet.fi!newsfeed1.funet.fi!newsfeeds.funet.fi!nntp.inet.fi!inet.fi!uunet!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: VITAL PACKAGE Date: Fri, 17 Apr 2009 16:49:43 +0200 Organization: NetVision InterNetNews site Lines: 10 Message-ID: Reply-To: "RealInfo" NNTP-Posting-Host: 93-172-121-194.bb.netvision.net.il X-Trace: localhost.localdomain 1239970678 28801 93.172.121.194 (17 Apr 2009 12:17:58 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Fri, 17 Apr 2009 12:17:58 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 Xref: news.eternal-september.org comp.lang.vhdl:886 Hi all How can I look into the VITAL package , I want to learn the functiuons and types it offers. Can I download it some where ? Thanks EC From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: Chris Maryan Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 09:06:34 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> <1gmgu4dr81t8moaf5i2evckkevha0cg28b@4ax.com> <5ad095ae-4a05-4091-8bab-277eb8e9288a@k41g2000yqh.googlegroups.com> NNTP-Posting-Host: 204.187.63.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239984394 21611 127.0.0.1 (17 Apr 2009 16:06:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Apr 2009 16:06:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=204.187.63.106; posting-account=X7y8VwoAAABRatUHKb0_XV_h2SmGb2rK User-Agent: G2/1.0 X-HTTP-Via: 1.0 MANU X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:887 > The difference is that, when the loop is unrolled, you > are subscripting the array with a CONSTANT (i) rather > than with a variable. =A0It can be important for optimization, > even though the two are functionally identical. Yes, that's VERY important. I ran into something like this a while ago with Synplify, where the constant version properly instantiated a mux and the variable version implemented some sort of variable shift widget that was about an order of magnitude larger. Chris From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.swapon.de!newsfeed.straub-nv.de!newsfeed.kpn.net!pfeed08.wxs.nl!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe29.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: VITAL PACKAGE Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe29.ams2 1239984924 86.16.123.60 (Fri, 17 Apr 2009 16:15:24 UTC) NNTP-Posting-Date: Fri, 17 Apr 2009 16:15:24 UTC Organization: virginmedia.com Date: Fri, 17 Apr 2009 17:15:17 +0100 Xref: news.eternal-september.org comp.lang.vhdl:888 "RealInfo" wrote in message news:gs9s1m$s41$1@localhost.localdomain... > Hi all > > How can I look into the VITAL package , I want to learn the functiuons and > types it offers. > Can I download it some where ? It is most likely supplied with your simulator. If you use Modelsim then look in the vhdl_src/vital* directories, all the packages are supplied in source. This paper might help you out: www.freemodelfoundry.com/pdf/complex_models.pdf Hans www.ht-lab.com > > Thanks > EC > From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!motzarella.org!feeder.motzarella.org!news.motzarella.org!news.albasani.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!de-l.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.190.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!postnews.google.com!x3g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Fri, 17 Apr 2009 12:01:39 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <28cac38a-dd36-4183-beef-4f71803d6875@x3g2000yqa.googlegroups.com> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1239994899 23460 127.0.0.1 (17 Apr 2009 19:01:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Apr 2009 19:01:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqa.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:889 On Apr 17, 5:29=A0am, Massi wrote: > Which is the > smartest way to implement such a huge multiplexer? The smartest way is to let the synthesis tool do as much of the work as possible. Don't try to outsmart it unless you have to. If the simplest, easiest to read, understand or write description will work (i.e. meet timing, area, etc. requirements), then use that. Borrowing Jonathan's definitions: -- 128-to-1, byte wide multiplexer: mux_data <=3D RAM_read_data(which_RAM); If you don't know your requirements, then you won't know whether the implementation you used is good enough, no matter how fast/small/cool/ elegant it is. Andy From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v19g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Fri, 17 Apr 2009 18:30:00 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240018200 4348 127.0.0.1 (18 Apr 2009 01:30:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 18 Apr 2009 01:30:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:890 On Apr 16, 3:06=A0pm, john wrote: > I am using xess board and foundation code and have all sorts of > problems simulating the code. SO thats why i am testing the code using > Logic Analyzer. > You're attacking the problem backwards then. It is far easier and more productive to debug in a simulator then with a logic analyzer. With the simulator you have immediate access to every signal in the design at any time...with the analyzer you do not. > My questions is > > Am I synchronizing the clocks in the right way? > No. Unless you're doing a custom ASIC design, don't generate clocks at all, timing between clock domains will be your doom. Have everything run off of one clock signal. Rather than creating a divided down clock from a high speed clock consider this approach 1. Create a counter that counts from 0 to some maximum count and then goes back to 0. For example, if you want to create a lower speed clock that is 1/50th of the original clock signal what you would do instead is have a counter that runs from 0 to 49 and then resets back to 0. You're not using this counter as a clock, it's just a counter. 2. Create a clock enable signal from the counter by decoding one of the counter states like this "clock_enable <=3D '1' when (counter =3D 7) else '0'; Here I've arbitrarily picked a count value of 7, unless you have some specific phase relationship to maintain between the clocks for some reason the exact count value can be anything. This clock enable signal will fire for exactly one clock cycle and then sit inactive for the other values of the counter (in the above example, it would sit inactive for 49 clock cycles). 3. Wherever you would have liked to do this... process(Generated_Clock) if rising_edge(Generated_Clock) then ...Your logic here end if; end process; Do this instead... process(Clock) if rising_edge(Clock) then if (Clock_Enable =3D '1') then ...Your logic here end if; end if; end process; > I will appreciate any advice! > The best advice is to try to avoid multiple clocks until you really have an understanding of how to do it correctly. I haven't gone into how to do that here simply because it doesn't appear that you've fully mastered good synchronous design practice. > > =A0combinatorial : process(err_r, addr_r, dIn, rand, begun, done, > rdPending, doAgain ) Don't use combinatorial process. They are sources of the following types of design errors that are difficult to debug to but are completely avoidable if you simply use only clocked processes and concurrent signal assignments. - Synthesis differs from simulation because synthesis tools do not properly handle sensitivity lists per the LRM. If your sensitivity list is missing a signal, you'll get burned. - Latches are easy to create and if you do create one...again, you'll get burned. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!b7g2000pre.googlegroups.com!not-for-mail From: leena Newsgroups: comp.lang.vhdl Subject: =?UTF-8?B?4pmj4pa84pmjIOKWiOKWk+KWiCAgIDE2IHRvIDM1IEFnZSBnaXJscyBwcm9maWxlcyA=?= =?UTF-8?B?4pmj4pa84pmjIOKWiOKWk+KWiA==?= Date: Sat, 18 Apr 2009 08:47:13 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <051661a4-8af6-4d8c-ad3a-83a25568a901@b7g2000pre.googlegroups.com> NNTP-Posting-Host: 117.201.37.214 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 X-Trace: posting.google.com 1240069633 27592 127.0.0.1 (18 Apr 2009 15:47:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 18 Apr 2009 15:47:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b7g2000pre.googlegroups.com; posting-host=117.201.37.214; posting-account=wh6SrwoAAADMx3qsG7C2lZifyRXsk569 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; FunWebProducts; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30618),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:891 4pmj4pa84pmjIOKWiOKWk+KWiCAgIDE2IHRvIDM1IEFnZSBnaXJscyBwcm9maWxlcyDimaPilrzi maMg4paI4paT4paICioqKioqKioqKioqKioqKioqKioqKioqKioqCmh0dHA6Ly9lYXJuNG1vbmxp bmUuNTB3ZWJzLmNvbQpodHRwOi8vZWFybjRtb25saW5lLjUwd2Vicy5jb20KKioqKioqKioqKioq KioqKioqKioqKioqKioK From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail From: Barry Newsgroups: comp.lang.vhdl Subject: Re: VITAL PACKAGE Date: Sat, 18 Apr 2009 09:09:12 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <7594cebb-59c9-4b8c-8fb0-17fca21ec64e@k8g2000yqn.googlegroups.com> References: NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240070952 31440 127.0.0.1 (18 Apr 2009 16:09:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 18 Apr 2009 16:09:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=192.25.142.225; posting-account=4NVzAQoAAAC-7jG90dquZ3NiXsf363Dd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; Agilent Technologies IE6 SP1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:892 On Apr 17, 7:49=A0am, "RealInfo" wrote: > Hi all > > How can I look into the VITAL package , I want to learn the functiuons an= d > types it offers. > Can I download it some where ? > > Thanks > EC VITAL is normally installed with your simulator. On my computer, Modelsim installed the source files at C:\modeltech_6.4b\vhdl_src \vital2000. I found this book to be helpful in using the VITAL packages: "ASIC & FPGA Verification" by Richard Munden Barry From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news-1.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Sat, 18 Apr 2009 10:34:26 -0700 Lines: 19 Message-ID: <74uh93F14t169U1@mid.individual.net> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 8KZRz9ZHFoYdqY4pidqKwgcvXY03GaUAcuGRonMIAKj0/xII3h Cancel-Lock: sha1:9iqrXSVnOWou0L4W5ygBTJ697E0= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:893 Massi wrote: > Hi everyone, I'm working on a Xilinx Virtex 5 FPGA with ISE 10.1. In > my design I have to instantiate 128 ram blocks, each one of them is > 1024 bytes wide. The outuput of my device depends on only one ram > block at a time, therefore I have to multiplex them. Which is the > smartest way to implement such a huge multiplexer? > Thanks a lot for you help. I agree with Andy. I don't solve a synthesis problem until I have one. The cleanest mux description is an array selection. Give ISE a crack at it and have a look at the RTL viewer and static timing. I also agree with Jonathan. Declare register/port dimensions first. VHDL gives us an unfair advantage here. -- Mike From newsfish@newsfish Wed Aug 19 13:24:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!194.134.4.91.MISMATCH!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: Re: VITAL PACKAGE Date: Sun, 19 Apr 2009 05:05:12 +0200 Organization: NetVision InterNetNews site Lines: 26 Message-ID: References: <7594cebb-59c9-4b8c-8fb0-17fca21ec64e@k8g2000yqn.googlegroups.com> Reply-To: "RealInfo" NNTP-Posting-Host: 93-173-130-77.bb.netvision.net.il X-Trace: localhost.localdomain 1240101221 8888 93.173.130.77 (19 Apr 2009 00:33:41 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Sun, 19 Apr 2009 00:33:41 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:894 Many Thanks EC "Barry" ??? ??????:7594cebb-59c9-4b8c-8fb0-17fca21ec64e@k8g2000yqn.googlegroups.com... On Apr 17, 7:49 am, "RealInfo" wrote: > Hi all > > How can I look into the VITAL package , I want to learn the functiuons and > types it offers. > Can I download it some where ? > > Thanks > EC VITAL is normally installed with your simulator. On my computer, Modelsim installed the source files at C:\modeltech_6.4b\vhdl_src \vital2000. I found this book to be helpful in using the VITAL packages: "ASIC & FPGA Verification" by Richard Munden Barry From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!news.glorb.com!postnews.google.com!p6g2000pre.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Sun, 19 Apr 2009 23:30:09 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <90945e06-690c-4c20-865f-af4877a78fab@p6g2000pre.googlegroups.com> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> NNTP-Posting-Host: 203.58.241.190 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240209009 21150 127.0.0.1 (20 Apr 2009 06:30:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 06:30:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p6g2000pre.googlegroups.com; posting-host=203.58.241.190; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 haides.silverbrookresearch.com:3128 (Squid/2.4.STABLE6) Xref: news.eternal-september.org comp.lang.vhdl:895 If you only need one RAM at a time could you merge the rams into a smaller number of larger ones? This would require that you only write to one ram at a time too. Also, I have used tbufs in the past to do this, however it appears that V5's don't have these. Darrin From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!gegeweb.org!fdn.fr!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed4-a.proxad.net!nnrp11-2.free.fr!not-for-mail Subject: Igloo nano Starter Kit From: Bert_Paris Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 20 Apr 2009 09:33:57 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 11 Message-ID: <49ec2566$0$18353$426a74cc@news.free.fr> NNTP-Posting-Date: 20 Apr 2009 09:33:58 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240212838 news-2.free.fr 18353 82.66.120.181:1834 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:896 Hello, For those who just got their hands on an Igloo nano Starter Kit, and especially for beginners, I have assembled a complete Tutorial at : http://www.alse-fr.com/Actel/igloo.html Enjoy... Bert From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: T Newsgroups: comp.lang.vhdl Subject: Generating C header files? Date: Mon, 20 Apr 2009 04:59:11 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 198.51.118.71 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240228751 15377 127.0.0.1 (20 Apr 2009 11:59:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 11:59:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=198.51.118.71; posting-account=r7SVvgoAAADKvRiTuOSBDGR65BgxDVer User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:897 Greetings: We have a VHDL file with register definitions, does anyone know of a tool/script which will parse this code and be capable of generating a C header file for the software folks? Thanks in Advance! Tom From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!gegeweb.org!de-l.enfer-du-nord.net!feeder.news-service.com!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe01.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com> Subject: Re: Generating C header files? Lines: 23 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <5q_Gl.72254$ga.49804@newsfe01.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe01.ams2 1240232705 86.16.123.60 (Mon, 20 Apr 2009 13:05:05 UTC) NNTP-Posting-Date: Mon, 20 Apr 2009 13:05:05 UTC Organization: virginmedia.com Date: Mon, 20 Apr 2009 14:04:59 +0100 Xref: news.eternal-september.org comp.lang.vhdl:898 "T" wrote in message news:2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com... > Greetings: > > We have a VHDL file with register definitions, does anyone know of a > tool/script which will parse this code and be capable of generating a > C header file for the software folks? Tcl plus a bit of regular expression should do the trick. I would recommend Trev from Doulos which makes building regular expression easy as pie.... http://www.doulos.com/knowhow/tcltk/examples/trev/ Hans www.ht-lab.com > > Thanks in Advance! > Tom From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!37g2000yqp.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: "sync_fifo" with Almost flags Date: Mon, 20 Apr 2009 06:25:18 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240233918 31016 127.0.0.1 (20 Apr 2009 13:25:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 13:25:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000yqp.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:899 Hi, I have found Mike Treseler's synchronous fifo description "sync_fifo.vhd" on his homepage. Very interesting description. Has someone tried to insert Almost Empty/Full flags in that description? Rgds, ALuPin From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newspeer1.de.telia.net!newspeer4.de.telia.net!de.telia.net!nx01.iad01.newshosting.com!newshosting.com!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!s20g2000yqh.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 08:00:00 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240239600 6369 127.0.0.1 (20 Apr 2009 15:00:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 15:00:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000yqh.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:900 Hi KJ, I tried to follow the following document (Page 11) http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf I will try to follow your advice and get back to you as soon as I can. bye John From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Smart coding for big multiplexer Date: Mon, 20 Apr 2009 08:18:55 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <4b06e4a2-1499-4f50-b6aa-6b5006e2b769@z5g2000vba.googlegroups.com> References: <7fc85c3b-49a1-4a61-baf3-470839f15846@f19g2000yqh.googlegroups.com> <90945e06-690c-4c20-865f-af4877a78fab@p6g2000pre.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240240736 10141 127.0.0.1 (20 Apr 2009 15:18:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 15:18:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:901 On Apr 20, 1:30=A0am, Dal wrote: > If you only need one RAM at a time could you merge the rams into a > smaller number of larger ones? =A0This would require that you only write > to one ram at a time too. > > Also, I have used tbufs in the past to do this, however it appears > that V5's don't have these. > > Darrin Tri-state bus code is translated into equivalent multiplexer type circuits. The tristate enables are assumed to be mutually exclusive for the multiplexor implementation. This actually comes in handy in some applications where it is difficult to convince the synthesis tool that separate inputs are mutually exclusive. Andy From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!q2g2000vbr.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 09:16:26 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <5ce03520-a1a6-43ba-b3cd-42717e9661c8@q2g2000vbr.googlegroups.com> References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240244186 21441 127.0.0.1 (20 Apr 2009 16:16:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 16:16:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbr.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:902 Hi, So , I will use the counter output as clock. I need a 1MHz clock to serial output the data. Where will I get that clock? Regards, John From newsfish@newsfish Wed Aug 19 13:24:13 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: Kartik_Vashishta Newsgroups: comp.lang.vhdl,comp.lang.idl-pvwave,comp.soft-sys.matlab,sci.math.num-analysis,comp.lang.verilog Subject: Computing needs, here's free root account on Solaris10 Date: Mon, 20 Apr 2009 09:59:39 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <25fb9903-a15d-4712-bcff-772ccd8988cb@s28g2000vbp.googlegroups.com> NNTP-Posting-Host: 98.215.91.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240246780 5162 127.0.0.1 (20 Apr 2009 16:59:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 16:59:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=98.215.91.201; posting-account=d9Q1pwoAAACuUvCB6vmryO6KRmewCKLd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; (R1 1.5); .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:903 comp.lang.idl-pvwave:1656 comp.soft-sys.matlab:24090 sci.math.num-analysis:1615 comp.lang.verilog:366 For computing, a free root account, is a tool. It may not be a bad idea to avail of the free root access I provide. For inconveniencing you, I apologize. If there are issues, contact me. You may install software, etc. Soon, a system faster than the current one, will be made available. Now, to avail of free root access, first login to one system: telnet trainingzone.getmyip.com (username: unix password: no password, hit enter), then, telnet 192.168.0.108 AND/OR telnet 192.168.0.128 (username:root password: no password, hit enter). Updates about the free training, free root account, will be made available on: http://www.kartik.com/FreeUNIXaccount.html Do not hesitate to contact me. Contact me, via my web page. Comfort and Peace, I wish for you. Kartik Vashishta From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.z74.net!news.z74.net!news.glorb.com!postnews.google.com!f1g2000prb.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Mon, 20 Apr 2009 10:02:08 -0700 (PDT) Organization: http://groups.google.com Lines: 89 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240246929 30447 127.0.0.1 (20 Apr 2009 17:02:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 17:02:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f1g2000prb.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:904 KJ, > From a readability/maintainability/ > support perspective either method is equivalent in my opinion. Agreed. For me, readability and maintainability are most important. Recovery is also important. I count down. It recovers also. >From hardware optimization standpoint, counting down and detecting 0 costs one carry output - independent of the size of the counter and the value to be detected. signal CountReg : unsigned(2 downto 0) ; CountProc : process(Clk, nReset) variable vCountReg : unsigned(CountReg'length downto 0) ; -- 3 downto 0 begin if nReset = '0' then CountReg <= "101" ; elsif rising_edge(Clk) then vCountReg := ('0' & CountReg) - 1 ; if vCountReg(vCountReg'left) = '1' then vCountReg := "0101" ; end if ; CountReg <= vCountReg(CountReg'range) ; end if ; end process ; >From a readability perspective, I would throw this into a procedure. procedure Dec ( signal Count : inout unsigned ; constant ReloadVal : in unsigned ; constant IncEnable : in std_logic := '1' ) is variable vCount : unsigned(Count'length downto 0) ; begin vCount := ('0' & Count) - IncEnable ; if vCount(vCount'left) = '1' then vCount := '0' & ReloadVal ; end if ; Count <= vCount(Count'length -1 downto 0) ; end procedure ; Then the process is: CountProc : process(Clk, nReset) begin if nReset = '0' then CountReg <= "101" ; elsif rising_edge(Clk) then Dec(CountReg, "101") ; end if ; end process ; In the general implementation, you may prefer if IncEnable = '1' then vCount := ('0' & Count) - 1; end if ; instead of: vCount := ('0' & Count) - IncEnable ; I prefer the latter since it often produces smaller hardware (although not always). > The primary reason for >= > is to insure recovery of the design, a secondary benefit is > potentially less logic (and most likely but I've never formally proved > it...never produce more logic). WRT less logic, one counter example proves an assertion false. Decoding =5 results in: Count(2) and Count(1) and Count(0) Decoding >= 5 results in: ((Count(2) and Count(0)) or (Count(2) and Count(1)) Here is a case where ">=" creates more hardware than "=". So you can't prove your assertion "never produce more logic" because it isn't true. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: More synthesis myths? Date: Mon, 20 Apr 2009 10:26:04 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <1e25dc90-95b8-4f44-84bf-81057bf6d1c3@p11g2000yqe.googlegroups.com> <49d3c908$0$3580$e4fe514c@dreader26.news.xs4all.nl> <49d918db$0$3491$e4fe514c@dreader20.news.xs4all.nl> <49DA1589.7010805@xs4all.nl> <73umf4F11418hU1@mid.individual.net> <49DB1909.5060607@xs4all.nl> <7082d731-d77d-406d-b347-2774cd918d83@y33g2000prg.googlegroups.com> <2b29ef8c-79ca-481d-aa7c-0a73f1365dc1@k19g2000prh.googlegroups.com> <95893957-37aa-4d68-ae2f-693b279104c3@g37g2000yqn.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240248365 2467 127.0.0.1 (20 Apr 2009 17:26:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 17:26:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:905 KJ > > For =3D5 or >=3D5 to do as good as decoding bits, you need a smart > > compiler. > > My point wasn't that a smart compiler wouldn't do better than a not so > smart one (the rising tide will lift all boats after all). =A0My point > was that for a given compiler, I believe you'll get equivalent or > better logic by using >=3D5 than by using =3D5. =A0I'll accept that there > might be some instance where this is not true, but I've seen far more > instances where it is and have yet to run across the case where it is > not. Note that I have always hand coded the =3D5 trick since this is only more effective than counting down and detecting 0 where there are only a few bits (I only do it when there is 1 or 2 bits decoded). WRT optimizing >=3D5, you can't do both recovery and counter bit optimizations. Recovery in this case requires coverage of the terms 5, 6, and 7. So the best you will get is: ((Count(2) and Count(0)) or (Count(2) and Count(1)) |------ 5 or 7 --------| |------ 6 or 7 -------| To me though both of these are a mute point as this discussion has only reinforced my thought that counting down and detecting 0 (using the carry chain) is the better implementation (from both optimization and recovery). Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!m19g2000yqk.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 10:38:56 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: <22907090-7838-437c-a413-361208c64f4c@m19g2000yqk.googlegroups.com> References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> <5ce03520-a1a6-43ba-b3cd-42717e9661c8@q2g2000vbr.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240249136 12489 127.0.0.1 (20 Apr 2009 17:38:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 17:38:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m19g2000yqk.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:906 On Apr 20, 12:16=A0pm, john wrote: > So , I will use the counter output as clock. As the clock to what? An external device? Internal to the design? If it is internal to the design, then you didn't get my post at all so go back and re-read. If it is a signal to an external device, then it is not a 'clock' from the perspective of your design since it is not used *by your design* to sample anything. > I need a 1MHz clock to > serial output the data. Where will I get that clock? > This suggests to me that the '1MHz clock' is some output of your design and that there is some other serial output data as well...those are two separate outputs. But the '1 MHz clock' is not a clock to your design at all, it is a clock input to *the external device*. If that is what you're trying to do (I'm not sure, it's not at all clear to me) then to generate this 1 MHz output signal from say a 50 MHz clock input you would construct the counter like I mentioned previously to count from 0 to 49 (or 49 downto 0 if you'd like). Keep in mind that any particular value of the count then essentially defines something that happens at a 1 MHz rate. So.... process(Clock) begin if rising_edge(Clock) then if (Count =3D 3) then My_1MHz_Output <=3D '1'; elsif (Count =3D 28) then My_1MHz_Output <=3D '0'; end if; end if; end process; The signal 'My_1MHz_Output' then will be a 1 MHz output signal, you wouldn't use it internally within your design, it is simply the output signal that you're generating in order to interface to whatever device is using this signal. The value of '3' that I picked for switching the output to a '1' is arbitrary, any value would work. The value of '28' was chosen because people like to see 50% duty cycle clocks. If you want a different duty cycle then change the 28 to something else. Presumably your serial output data must have some specific timing relationship to the 'clock' to meet some setup or hold time requirement. Perhaps the external device samples on the data on the rising edge so you would need to make sure that the data is stable around that point (which from the above example would be around the time when Count=3D3). Based on whatever your requirement is, you might then decide that 70 ns is more than enough hold time and decide to only allow the data to change when the count =3D 10 (7 ticks of the 100 MHz clock =3D 70 ns). process(Clock) begin if rising_edge(Clock) then if (Count =3D 10) then Serial_Out_Data <=3D ... end if; end if; end process; That's the basic idea. You would probably want to define some constants so that the numbers '3', '10' and '28' (or whatever) have real definitions instead of appearing to be magic constants. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:14 2009 From: KJ Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 10:39:15 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <463982b0-e0cf-4da5-ad21-86b5fbb038f4@y7g2000yqa.googlegroups.com> References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240249156 12525 127.0.0.1 (20 Apr 2009 17:39:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 17:39:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y7g2000yqa.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news4us.nl!feeder.erje.net!news.glorb.com!postnews.google.com!y7g2000yqa.googlegroups.com!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:907 On Apr 20, 11:00=A0am, john wrote: > Hi KJ, > > I tried to follow the following document (Page 11) > > http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf > So you're doing an ASIC? KJ From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!3g2000yqk.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 10:46:05 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> <5ce03520-a1a6-43ba-b3cd-42717e9661c8@q2g2000vbr.googlegroups.com> <22907090-7838-437c-a413-361208c64f4c@m19g2000yqk.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240249565 13852 127.0.0.1 (20 Apr 2009 17:46:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 17:46:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 3g2000yqk.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:908 On Apr 20, 1:38=A0pm, KJ wrote: > then decide that 70 ns is more than enough hold time and decide to > only allow the data to change when the count =3D 10 (7 ticks of the 100 > MHz clock =3D 70 ns). Should've said 7 ticks of the 50 MHz clock...and said that maybe 140 ns is plenty of hold time KJ From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!94.232.116.15.MISMATCH!ramfeed-1.ams.xsnews.nl!feed.xsnews.nl!border-2.ams.xsnews.nl!212.27.60.7.MISMATCH!feeder1-1.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!r36g2000vbr.googlegroups.com!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Re: clock synchronization and flip flops Date: Mon, 20 Apr 2009 11:58:22 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <6ba69275-5c46-42e2-b02d-597b1db2c9fb@r36g2000vbr.googlegroups.com> References: <2c3f7bc0-228c-4ee5-854a-505df0bd2a10@k27g2000vbb.googlegroups.com> <28461d2c-b7e1-4390-8a83-11464209e21a@s20g2000yqh.googlegroups.com> <463982b0-e0cf-4da5-ad21-86b5fbb038f4@y7g2000yqa.googlegroups.com> NNTP-Posting-Host: 146.9.116.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240253903 20270 127.0.0.1 (20 Apr 2009 18:58:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Apr 2009 18:58:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbr.googlegroups.com; posting-host=146.9.116.19; posting-account=OhlgNAoAAAA5Tw7BuOexRvy_yqk5xTlw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:909 Hi, I am not doing ASIC. I think , I got the idea. I will try your adviced solution and we will see. I am trying to generate clock, data and tag signals for a DAC. The DAC needs 49 bit of data at the clock of 1MHz. The internal clock frequency is 100MHz. I think that the counter solution might work. Thanks John From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.z74.net!news.z74.net!feeder.erje.net!ecngs!feeder2.ecngs.de!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: "sync_fifo" with Almost flags Date: Mon, 20 Apr 2009 13:21:54 -0700 Lines: 13 Message-ID: <7543r3F16jq52U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net RPO+vbonT+mEtzE2y9iClQNzKUYaCEZZT7U30baHWN0T5a9pfH Cancel-Lock: sha1:NaScuw22RaxI8FbQbW9Pefk+PAw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:910 ALuPin@web.de wrote: > I have found Mike Treseler's synchronous fifo description > "sync_fifo.vhd" on his > homepage. Very interesting description. Has someone tried to insert > Almost Empty/Full > flags in that description? Just output comparisons to "full_ctr". If that is too much trouble, run the altera GUI on lpm_fifo, but that gives you a netlist rather than source code. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp18-1.free.fr!not-for-mail Subject: Factorial solution From: Bert_Paris Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 09:41:37 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 93 Message-ID: <49ed78b2$0$664$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 09:41:38 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240299698 news-2.free.fr 664 82.66.120.181:2731 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:911 -- Fact_rtl.vhd -- -------------------------------------------------- -- Factorial Example - Synthesizable & efficient ! -- -------------------------------------------------- -- Author : Bert Cuzeau. ALSE. http://www.alse-fr.com -- Tested successfully with Quartus II v9.0. -- but it should be fine with any decent synthesizer. -- -- Note : added registers in front and after to easily -- get the Tsu (Fmax) after synthesis -- Synthesis results : 10 LUTs for the Factorial, as expected ! -- Timing : speed practically unlimited since 1 Logic Level (250Mhz on Cyclone III) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- --------------------------------------- Entity Factorial is -- --------------------------------------- port ( Clk : in std_logic; Din : in std_logic_vector (2 downto 0); -- 0! .. 7! = 0 .. 944 Result : out std_logic_vector (9 downto 0) ); -- 0 .. 1023 End Entity Factorial; -- --------------------------------------- Architecture RTL of Factorial is -- yes, this is perfect for synthesis ! -- --------------------------------------- -- The usual recursive function function fact (d : natural) return natural is variable res : natural; begin if d=0 then res := 0; elsif d=1 then res := 1; else res := d * fact (d-1); end if; return res; end function fact; -- Constant table type type Table_t is array (0 to 7) of unsigned(result'range); -- Function to initialize a table with the factorial impure function Init_Table return Table_t is variable T : Table_t; begin for I in T'range loop T(I) := to_unsigned(fact(I),Result'length); end loop; return T; end function Init_Table; -- The Table itself, initialized at creation : signal Table : Table_t := Init_Table; -- note ;: this table will be smplified in a few Logic Elements signal Dinr : std_logic_vector (Din'range); ------\ begin -- Architecture ------/ Dinr <= Din when rising_edge(Clk); -- input FFs result <= std_logic_vector(Table(to_integer(unsigned(Dinr)))) when rising_edge(Clk); end RTL; ------------------------------------------ -- Test Bench. Simulate -all ------------------------------------------ -- synopsys translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity factorial_tb is end; Architecture test of factorial_tb is signal Clk : std_logic := '0'; signal Din : std_logic_vector (2 downto 0) := "000"; -- 0! .. 7! = 840 signal Result : std_logic_vector (9 downto 0); begin assert Clk='0' or now < 500 ns report "Simulation has ended (not an error)." severity failure; Clk <= not Clk after 5 ns; -- 100 MHz clock Din <= std_logic_vector (unsigned(Din)+1) after 40 ns; -- F/4 uut: entity work.factorial port map (Clk,Din,Result); end architecture TEST; -- synopsys translate_on From newsfish@newsfish Wed Aug 19 13:24:14 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!c9g2000yqm.googlegroups.com!not-for-mail From: "ALuPin@web.de" Newsgroups: comp.lang.vhdl Subject: Re: "sync_fifo" with Almost flags Date: Tue, 21 Apr 2009 00:44:58 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <107e07d9-9d13-4c7f-b4f6-b6c4edaf840a@c9g2000yqm.googlegroups.com> References: <7543r3F16jq52U1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240299898 3125 127.0.0.1 (21 Apr 2009 07:44:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Apr 2009 07:44:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c9g2000yqm.googlegroups.com; posting-host=217.91.93.34; posting-account=91e4AwkAAADRcENnvIQpJ0lcioT1Zdb_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.0.3) Gecko/2008092417 Firefox/3.0.3,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) Xref: news.eternal-september.org comp.lang.vhdl:912 Hi Mike, thank you for the hint, I will try to implement it. Best regards, ALuPin From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!novia!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Tue, 21 Apr 2009 05:57:49 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Factorial solution Date: Tue, 21 Apr 2009 11:55:38 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <49ed78b2$0$664$426a74cc@news.free.fr> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-qW5pCH/6bmvA90fMcUeMtfZ48u+lbGJ+I4oN5X7b9R5ppCyekCoVxgJM/b1h1QSQQdlxDbDq9F1OVGf!JhkETkRQiezQ8EKK+Zg9jb441TUd9Z3l7FhykCUawjHgnushHMu5IF2WibFsVHNq5i9ACI0/QCsw!XlTd X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:913 On Tue, 21 Apr 2009 09:41:37 +0200, Bert_Paris wrote: > Synthesis results : 10 LUTs for the Factorial, as expected ! Very nice :-) and I suppose the corresponding design for Ackermann's function [*] is left as an exercise for the student..... [*] For non-negative integer m,n: A(0, n) = n+1 A(m, 0) = A(m-1, 1) for m>0 A(m,n) = A(m-1, A(m, n-1)) for m,n > 0 You don't need many bits for the inputs! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp19-2.free.fr!not-for-mail Subject: Re: Factorial solution From: Bert_Paris References: <49ed78b2$0$664$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 13:26:56 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <49edad81$0$5226$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 13:26:57 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240313217 news-2.free.fr 5226 82.66.120.181:1892 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:914 Hi Jonathan :-) Some tools can reduce it to 6 LUTs, but my description without Flops and no async reset does help them too much ;-) We should stop doing the students' assignments in this forum (lol) I guess the next assignment will be the Ackermann's function (if the teachers keep an eye on this newsgroup) ? Bert > On Tue, 21 Apr 2009 09:41:37 +0200, Bert_Paris wrote: > >> Synthesis results : 10 LUTs for the Factorial, as expected ! > From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp8-1.free.fr!not-for-mail Subject: Re: Factorial solution From: Bert_Paris References: <49ed78b2$0$664$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 13:42:58 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 103 Message-ID: <49edb142$0$3504$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 13:42:59 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240314179 news-2.free.fr 3504 82.66.120.181:2971 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:915 Before anyone notices ;-) The previous version didn't handle the last value (7) correctly, which factorial is 5040 and thus requires a 13 bits output vector. Or maybe we should leave intentional errors for the teachers (lol) ? -- Fact_rtl.vhd -- -------------------------------------------------- -- Factorial Example - Synthesizable & efficient ! -- -------------------------------------------------- -- Author : Bert Cuzeau. ALSE. http://www.alse-fr.com -- Version : 2.0, handles all values 0..7 -> 0 .. 5040 -- Tested successfully with : -- * Altera Quartus II v9.0, -- * Actel Libero 8.5 (Synplify) -- * Xilinx ISE 10 -- but it should be fine with any decent synthesizer -- -- Note : added registers in front and after to easily -- get the Tsu (Fmax) after synthesis. -- Synthesis results : 8 LUTs for the Factorial ! -- Timing : speed practically unlimited since only 1 Logic Level (250Mhz on Cyclone III) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- --------------------------------------- Entity Factorial is -- --------------------------------------- port ( Clk : in std_logic; Din : in std_logic_vector (2 downto 0); -- 0! .. 7! = 0 .. 5040 Result : out std_logic_vector (12 downto 0) ); -- 0 .. 8191 End Entity Factorial; -- --------------------------------------- Architecture RTL of Factorial is -- yes, this is perfect for synthesis ! -- --------------------------------------- -- The usual recursive function function fact (d : natural) return natural is variable res : natural; begin if d=0 then res := 0; elsif d=1 then res := 1; else res := d * fact (d-1); end if; return res; end function fact; -- Constant table type type Table_t is array (0 to 7) of unsigned(result'range); -- Function to initialize a table with the factorial impure function Init_Table return Table_t is variable T : Table_t; begin for I in T'range loop T(I) := to_unsigned(fact(I),Result'length); end loop; return T; end function Init_Table; -- The Table itself, initialized at creation : signal Table : Table_t := Init_Table; -- note : this table will be simplified into a few LUTs signal Dinr : std_logic_vector (Din'range); ------\ begin -- Architecture ------/ Dinr <= Din when rising_edge(Clk); -- input FFs result <= std_logic_vector(Table(to_integer(unsigned(Dinr)))) when rising_edge(Clk); End architecture RTL; -------------------------------------------------- -- Test Bench. Simulate -all, eyeball the results -------------------------------------------------- -- synopsys translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity factorial_tb is end; Architecture TEST of factorial_tb is signal Clk : std_logic := '0'; signal Din : std_logic_vector (2 downto 0) := "000"; -- 0! .. 7! = 840 signal Result : std_logic_vector (12 downto 0); begin assert Clk='0' or now < 500 ns report "Simulation has ended (not an error)." severity failure; Clk <= not Clk after 5 ns; -- 100 MHz clock Din <= std_logic_vector (unsigned(Din)+1) after 40 ns; -- F/4 uut: entity work.factorial port map (Clk,Din,Result); end architecture TEST; -- synopsys translate_on From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Tue, 21 Apr 2009 07:11:58 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Factorial solution Date: Tue, 21 Apr 2009 13:09:46 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <49ed78b2$0$664$426a74cc@news.free.fr> <49edb142$0$3504$426a74cc@news.free.fr> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-RT8+qf2ztcdAyReIZJrEwKnuzvv9J4xPdW1LIA9AzKN/ACiPJIVkXf+W8K18rpha3koFIbFtn+bLl1A!OmSHjHXthbWFby3Q6qn/7caieZYvHJnx7raSaGMWs6GjPO5HSyFs+jJMyAnkz6EmbhYF1J3SY9IL!lWxs X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:916 On Tue, 21 Apr 2009 13:42:58 +0200, Bert_Paris wrote: >Before anyone notices ;-) >From Jonathan's Dictionary of Computing Terms: SEND BUTTON (n): Powerful design review tool intended to improve code quality by exposing authors of erroneous code to public ridicule. Unfortunately it can be proven that this tool can only work retrospectively; this is a consequence of Goedel's Incompleteness Theorem and is a property shared with related tools such as BOOK PUBLICATION and PRODUCT RELEASE. >Or maybe we should leave intentional errors for the teachers (lol) ? No, we make enough of our own :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!l5g2000vbc.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Factorial solution Date: Tue, 21 Apr 2009 07:51:09 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: References: <49ed78b2$0$664$426a74cc@news.free.fr> <49edb142$0$3504$426a74cc@news.free.fr> NNTP-Posting-Host: 66.38.210.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240325469 15423 127.0.0.1 (21 Apr 2009 14:51:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Apr 2009 14:51:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l5g2000vbc.googlegroups.com; posting-host=66.38.210.253; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; fr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:917 On 21 avr, 08:09, Jonathan Bromley wrote: > On Tue, 21 Apr 2009 13:42:58 +0200, Bert_Paris wrote: > >Before anyone notices ;-) > > From Jonathan's Dictionary of Computing Terms: > > SEND BUTTON (n): > Powerful design review tool intended to improve > code quality by exposing authors of erroneous > code to public ridicule. =A0Unfortunately it can be > proven that this tool can only work retrospectively; > this is a consequence of Goedel's Incompleteness > Theorem and is a property shared with related > tools such as BOOK PUBLICATION and PRODUCT RELEASE. > > >Or maybe we should leave intentional errors for the teachers (lol) ? > > No, we make enough of our own :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I might not be as good as you guys are in VHDL and FPGAs, but there's an error in the code 0! =3D 1 Therefore, it should be corrected (it's not a big deal) From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp9-1.free.fr!not-for-mail Subject: Re: Factorial solution From: Bert_Paris References: <49ed78b2$0$664$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 17:04:36 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 104 Message-ID: <49ede085$0$5254$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 17:04:37 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240326277 news-3.free.fr 5254 82.66.120.181:2524 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:918 Argh, I actually modified my code to implement 0!=0, but you're right : "By convention, 0! = 1". The code is now two lines shorter ;-) and I used an attribute for the Table length, so I guess the port could now use unconstrained vectors. Slick. -- Fact_rtl.vhd -- -------------------------------------------------- -- Factorial Example - Synthesizable & efficient ! -- -------------------------------------------------- -- Author : Bert Cuzeau. ALSE. http://www.alse-fr.com -- Version : 2.1, handles all values 0..7 -> 0 .. 5040 -- By convention, 0! = 1 -- Tested successfully with : -- * Altera Quartus II v9.0, -- * Actel Libero 8.5 (Synplify) -- * Xilinx ISE 10 -- but it should be fine with any decent synthesizer -- -- Note : added registers in front and after to easily -- get the Tsu (Fmax) after synthesis. -- Synthesis results : 8 LUTs for the Factorial ! -- Timing : speed practically unlimited since only 1 Logic Level (250Mhz on Cyclone III) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- --------------------------------------- Entity Factorial is -- --------------------------------------- port ( Clk : in std_logic; Din : in std_logic_vector (2 downto 0); -- 0! .. 7! = 0 .. 5040 Result : out std_logic_vector (12 downto 0) ); -- 0 .. 8191 End Entity Factorial; -- --------------------------------------- Architecture RTL of Factorial is -- yes, this is perfect for synthesis ! -- --------------------------------------- -- The usual recursive function function fact (d : natural) return natural is variable res : natural; begin if d<2 then res := 1; else res := d * fact (d-1); end if; return res; end function fact; -- Constant table type type Table_t is array (0 to 2**Din'length - 1) of unsigned(result'range); -- Function to initialize a table with the factorial impure function Init_Table return Table_t is variable T : Table_t; begin for I in T'range loop T(I) := to_unsigned(fact(I),Result'length); end loop; return T; end function Init_Table; -- The Table itself, initialized at creation : signal Table : Table_t := Init_Table; -- note : this table will be simplified into a few LUTs signal Dinr : std_logic_vector (Din'range); ------\ begin -- Architecture ------/ Dinr <= Din when rising_edge(Clk); -- input FFs result <= std_logic_vector(Table(to_integer(unsigned(Dinr)))) when rising_edge(Clk); End architecture RTL; -------------------------------------------------- -- Test Bench. Simulate -all, eyeball the results -------------------------------------------------- -- synopsys translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity factorial_tb is end; Architecture TEST of factorial_tb is signal Clk : std_logic := '0'; signal Din : std_logic_vector (2 downto 0) := "000"; -- 0! .. 7! = 840 signal Result : std_logic_vector (12 downto 0); begin assert Clk='0' or now < 500 ns report "Simulation has ended (not an error)." severity failure; Clk <= not Clk after 5 ns; -- 100 MHz clock Din <= std_logic_vector (unsigned(Din)+1) after 40 ns; -- F/4 uut: entity work.factorial port map (Clk,Din,Result); end architecture TEST; -- synopsys translate_on From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news-in.maxbaud.net!news.ecp.fr!news1.int-evry.fr!u-psud.fr!news.cs.univ-paris8.fr!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed4-a.proxad.net!nnrp13-1.free.fr!not-for-mail Subject: Factorial solution (final ?) From: Bert_Paris References: <49ed78b2$0$664$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 17:42:27 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 116 Message-ID: <49ede963$0$18750$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 17:42:27 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240328547 news-3.free.fr 18750 82.66.120.181:2555 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:919 I can't resist :-) This is the unconstrained ports version, a breeze to parameterize. And it handles integers larger than 32 bits. -- Fact_rtl.vhd -- -------------------------------------------------- -- Factorial Example - Synthesizable & efficient ! -- -------------------------------------------------- -- Author : (c) Bert Cuzeau. ALSE. http://www.alse-fr.com -- Version : 3.0, using unconstrained vectors. -- Handles numbers larger than 2**31 -- -- Synthesis results : 8 LUTs for (0! .. 7!) -- 32 LUTS for (0! .. 15! = 1307674368000) -- Tested with Quartus II v 9.0. -- Should be fine with any synthesis tool. -- -- Make sure you synthesize "Wrapper" as the top level. Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- --------------------------------------- Entity Factorial is -- --------------------------------------- port ( Clk : in std_logic; Din : in std_logic_vector; -- Yep, unconstrained ! Result : out std_logic_vector ); End Entity Factorial; -- --------------------------------------- Architecture RTL of Factorial is -- yes, this is perfect for synthesis ! -- --------------------------------------- -- The (almost) usual recursive function function fact (d : unsigned) return unsigned is variable res : unsigned (d'range); begin if d<2 then -- note that, by convention, 0! = 1 res := to_unsigned(1,res'length); else res := "*" (d,fact (d-1))(res'range); end if; return res; end function fact; -- Constant table type type Table_t is array (0 to 2**Din'length - 1) of unsigned(Result'range); -- Function to initialize a table with the factorial impure function Init_Table return Table_t is variable T : Table_t; begin for I in T'range loop T(I) := fact(to_unsigned(I,Result'length)); end loop; return T; end function Init_Table; -- The Table itself, initialized at creation : signal Table : Table_t := Init_Table; -- note : this table will be simplified into a few LUTs signal Dinr : std_logic_vector (Din'range); ------\ Begin -- Architecture ------/ Dinr <= Din when rising_edge(Clk); -- input FFs result <= std_logic_vector(Table(to_integer(unsigned(Dinr)))) when rising_edge(Clk); End architecture RTL; -------------------------------------------------------- -- Wrapper for Synthesis (4 -> 41 bits implementation) -------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; Entity Wrapper is -- For Synthesis of 4 bits -> 41 bits port ( Clk : in std_logic; Din : in std_logic_vector (3 downto 0); -- 0! .. 15! = 13077775800hex Result : out std_logic_vector (40 downto 0) ); -- 41 bits result End Entity Wrapper; architecture Wrap of Wrapper is begin Fact : entity work.Factorial port map (Clk,Din,Result); end architecture Wrap; -------------------------------------------------- -- Test Bench. Simulate -all, eyeball the results -------------------------------------------------- -- synopsys translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity factorial_tb is end; Architecture TEST of factorial_tb is signal Clk : std_logic := '0'; signal Din : std_logic_vector (3 downto 0) := (others=>'0'); -- 0! .. 15! signal Result : std_logic_vector (40 downto 0); begin assert Clk='0' or now < 800 ns report "Simulation has ended (not an error)." severity failure; Clk <= not Clk after 5 ns; -- 100 MHz clock Din <= std_logic_vector (unsigned(Din)+1) after 40 ns; -- F/4 uut: entity work.factorial port map (Clk,Din,Result); end architecture TEST; -- synopsys translate_on From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe23.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <49ed78b2$0$664$426a74cc@news.free.fr> <49ede963$0$18750$426a74cc@news.free.fr> Subject: Re: Factorial solution (final ?) Lines: 45 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe23.ams2 1240329494 86.16.123.60 (Tue, 21 Apr 2009 15:58:14 UTC) NNTP-Posting-Date: Tue, 21 Apr 2009 15:58:14 UTC Organization: virginmedia.com Date: Tue, 21 Apr 2009 16:58:07 +0100 Xref: news.eternal-september.org comp.lang.vhdl:920 "Bert_Paris" wrote in message news:49ede963$0$18750$426a74cc@news.free.fr... >I can't resist :-) > This is the unconstrained ports version, a breeze to parameterize. > And it handles integers larger than 32 bits. ..snip nearly final, add a bit VHDL2008 goodness to remove the error/failure message....:-) > -------------------------------------------------- > -- Test Bench. Simulate -all, eyeball the results > -------------------------------------------------- > -- synopsys translate_off > library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library std; use std.env.all; > Entity factorial_tb is end; > Architecture TEST of factorial_tb is > signal Clk : std_logic := '0'; > signal Din : std_logic_vector (3 downto 0) := (others=>'0'); -- 0! .. > 15! > signal Result : std_logic_vector (40 downto 0); > begin -- assert Clk='0' or now < 800 ns report "Simulation has ended (not an -- error)." severity failure; STOP(1); Hans www.ht-lab.com > Clk <= not Clk after 5 ns; -- 100 MHz clock > Din <= std_logic_vector (unsigned(Din)+1) after 40 ns; -- F/4 > uut: entity work.factorial port map (Clk,Din,Result); > end architecture TEST; > -- synopsys translate_on > > From newsfish@newsfish Wed Aug 19 13:24:15 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp17-2.free.fr!not-for-mail Subject: VHDL 2008 ? From: Bert_Paris References: <49ed78b2$0$664$426a74cc@news.free.fr> <49ede963$0$18750$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 21 Apr 2009 18:19:26 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 16 Message-ID: <49edf20f$0$21438$426a74cc@news.free.fr> NNTP-Posting-Date: 21 Apr 2009 18:19:27 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240330767 news-3.free.fr 21438 82.66.120.181:2224 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:921 HT-Lab a exprimé avec précision : > ... VHDL2008 goodness ... Isn't this an oxymoron ? ;-) For the purist who doesn't like the failure ending, it's easy to stop simulation using events starvation (stopping the clock) : Clk <= '0' when Done else not Clock after (Period / 2); Done <= true after 800 ns; I don't think your 2008 code works as is (without a process, and a wait) btw: Is anyone using or even still interested in VHDL 2008 ? I still wouldn't recommend using VHDL2008 yet, and I don't feel it's going to save the language, but maybe I'm wrong. From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!weretis.net!feeder2.news.weretis.net!news.musoftware.de!wum.musoftware.de!feeder.erje.net!lightspeed.eweka.nl!81.171.88.16.MISMATCH!eweka.nl!hq-usenetpeers.eweka.nl!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf02.ams.highwinds-media.com!newsfe21.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <49ed78b2$0$664$426a74cc@news.free.fr> <49ede963$0$18750$426a74cc@news.free.fr> <49edf20f$0$21438$426a74cc@news.free.fr> Subject: Re: VHDL 2008 ? Lines: 39 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe21.ams2 1240332339 86.16.123.60 (Tue, 21 Apr 2009 16:45:39 UTC) NNTP-Posting-Date: Tue, 21 Apr 2009 16:45:39 UTC Organization: virginmedia.com Date: Tue, 21 Apr 2009 17:45:25 +0100 Xref: news.eternal-september.org comp.lang.vhdl:922 "Bert_Paris" wrote in message news:49edf20f$0$21438$426a74cc@news.free.fr... > HT-Lab a exprimé avec précision : >> ... VHDL2008 goodness ... > Isn't this an oxymoron ? ;-) No it is a pleonasm :-) > > For the purist who doesn't like the failure ending, it's easy to stop > simulation using events starvation (stopping the clock) : > Clk <= '0' when Done else not Clock after (Period / 2); > Done <= true after 800 ns; > I don't think your 2008 code works as is (without a process, and a wait) you are correct. > > btw: Is anyone using or even still interested in VHDL 2008 ? Using, no since I am still waiting for Mentor to support it. Interested, definitely yes since it has some nice additions. > I still wouldn't recommend using VHDL2008 yet, and I don't feel it's going > to save the language, but maybe I'm wrong. Saving the language from what? For verification I agree that the ship has sailed (although you can still see it in the distance) since SV/SC are simply to far ahead but for design VHDL will be use for a long long time.....(I hope) Hans www.ht-lab.com > > From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Multiple components driving a single bus Date: Tue, 21 Apr 2009 18:27:42 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: NNTP-Posting-Host: 70.52.37.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240363662 16509 127.0.0.1 (22 Apr 2009 01:27:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 22 Apr 2009 01:27:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=70.52.37.36; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:923 Hi, I've got a question for you guys. Let's say I've got 2 blocks that can drive one bus (but there could be more). Block1 : Block generic map (Address => x"000") port map (CLK => CLK, ADDR => ADDR, BUS_STB => BUS_STB, RD_WR_N => RD_WR_N, DATA_OUT => BUS_DATA, ....); Block2 : Block generic map (Address => x"004") port map (CLK => CLK, ADDR => ADDR, BUS_STB => BUS_STB, RD_WR_N => RD_WR_N, DATA_OUT => BUS_DATA, ......); Let's say that when the address is not 0, DATA_OUT of block1 will be high-Z and when the addres is not 4 Data_out of block 2 will be high- Z. Will ISE synthesis engine be smart enough to realize there is no bus contention? Basically, will ISE infer muxes from that code? I realize that I could use a switch case, however I want a more scalable solution where I don't need to have an ugly 200-line switch case. I looked a Jonathan Bromley's solution too, it's very clever and it looks like a good solution, however I'd like to know your opinion on this method first. The reason, why I like the solution above is that the address is specified when we instantiate the block. Best regards. From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 22 Apr 2009 02:03:50 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Multiple components driving a single bus Date: Wed, 22 Apr 2009 08:05:49 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-Nj3r7/b9iiHoNIt0t0owQYsDSMfUfeDvocfStmbMPwN2C+mIWBQ9wcnvNPfCWgnRnY3wfnWkeXueICo!gwJUWouKVYo3MuwE3i/ZA+Bt/1kJMCIaJUNkJZu+GiAemjY1AAu9JSNCDKnprf1SDQT6QpycqLLh!obgE X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:924 On Tue, 21 Apr 2009 18:27:42 -0700 (PDT), Benjamin Couillard wrote: >Hi, I've got a question for you guys. > >Let's say I've got 2 blocks that can drive one bus (but there could be >more). > >Block1 : Block >generic map (Address => x"000") >port map (CLK => CLK, > ADDR => ADDR, > BUS_STB => BUS_STB, > RD_WR_N => RD_WR_N, > DATA_OUT => BUS_DATA, > ....); > > >Block2 : Block >generic map (Address => x"004") >port map (CLK => CLK, ... >Let's say that when the address is not 0, DATA_OUT of block1 will be >high-Z and when the addres is not 4 Data_out of block 2 will be high- >Z. Will ISE synthesis engine be smart enough to realize there is no >bus contention? Basically, will ISE infer muxes from that code? Look in the synthesis report for warnings that tri-states have been replaced by muxes. Any time I've tried it, it has worked - but XST will complain about it. This ssumes ADDR is internal. If ADDR goes off chip, the synth tool can't analyse the outside world. It may be smart enough to infer MUXes internally and tristates on the I/O pins but I haven't verified that. - Brian From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!a7g2000yqk.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: TextIO Tutorial Date: Wed, 22 Apr 2009 00:57:40 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 93.37.210.110 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240387060 26584 127.0.0.1 (22 Apr 2009 07:57:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 22 Apr 2009 07:57:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a7g2000yqk.googlegroups.com; posting-host=93.37.210.110; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:925 Hi everybody, I'm new to VHDL an to this group too; as an exercise I'm trying to import data from several files using package TextIO, but I haven't found yet a good manual or tutorial about it; may you suggest me some? Thanks Bye Dek From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!193.201.147.71.MISMATCH!xlned.com!feeder3.xlned.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!spool.news.uu.net!ash.uu.net!news.netvision.net.il!not-for-mail From: "RealInfo" Newsgroups: comp.lang.vhdl Subject: VITAL for behavioural models ? Date: Wed, 22 Apr 2009 16:48:36 +0200 Organization: NetVision InterNetNews site Lines: 11 Message-ID: Reply-To: "RealInfo" NNTP-Posting-Host: 93-172-169-70.bb.netvision.net.il X-Trace: localhost.localdomain 1240406147 27993 93.172.169.70 (22 Apr 2009 13:15:47 GMT) X-Complaints-To: usenet@netvision.net.il NNTP-Posting-Date: Wed, 22 Apr 2009 13:15:47 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:926 HI all Is VITAL relevant for NOT for synthesis models ? For example an existing RAM memory model to be simulated with a new dsign idea ? Thanks EC From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Wed, 22 Apr 2009 08:36:46 -0700 Lines: 10 Message-ID: <49EF398E.5090907@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net uGEeQgxU4aN7gsx6D1/9TARFkf77cg8Su75d21qq1C7aw13pTk Cancel-Lock: sha1:fPMPScHNKumoWrgJx6HOYXhEyQs= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:927 Dek wrote: > I'm new to VHDL an to this group too; as an exercise I'm trying to > import data from several files using package TextIO, but I haven't > found yet a good manual or tutorial about it; may you suggest me some? When I want to work with files and data, i use python or perl. If I want to make a hardware model, I use vhdl. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!z14g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Wed, 22 Apr 2009 09:24:16 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240417456 27260 127.0.0.1 (22 Apr 2009 16:24:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 22 Apr 2009 16:24:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:928 On 22 Apr, 08:57, Dek wrote: > Hi everybody, > > I'm new to VHDL an to this group too; as an exercise I'm trying to > import data from several files using package TextIO, but I haven't > found yet a good manual or tutorial about it; may you suggest me some? > > Thanks > > Bye > > Dek If you're only trying to read in text, then TextIO is what you need. For binary files, you dont use the TextIO package, and reading data in is a bit more contrived and apparently doesnt work the same accross different apps. (as a note, I have functions to read/write bitmap files directly from VHDL in Modelsim but thats only because I work with video and looking at an actual picture is alot quicker than trying to interpret text). But like Mike says, if its for anything other than input to a hardware model, use something else to do the work. It might be best to just ask the questions here, or go on the Doulos VHDL courses. From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!z14g2000yqa.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 01:06:29 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 93.37.211.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240473990 14438 127.0.0.1 (23 Apr 2009 08:06:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 08:06:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqa.googlegroups.com; posting-host=93.37.211.149; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:929 On 22 Apr, 18:24, Tricky wrote: > On 22 Apr, 08:57, Dek wrote: > > > Hi everybody, > > > I'm new to VHDL an to this group too; as an exercise I'm trying to > > import data from several files using package TextIO, but I haven't > > found yet a good manual or tutorial about it; may you suggest me some? > > > Thanks > > > Bye > > > Dek > > If you're only trying to read in text, then TextIO is what you need. > For binary files, you dont use the TextIO package, and reading data in > is a bit more contrived and apparently doesnt work the same accross > different apps. (as a note, I have functions to read/write bitmap > files directly from VHDL in Modelsim but thats only because I work > with video and looking at an actual picture is alot quicker than > trying to interpret text). > > But like Mike says, if its for anything other than input to a hardware > model, use something else to do the work. It might be best to just ask > the questions here, or go on the Doulos VHDL courses. Thanks for the answer, what I want to do actually is an hardware model using a .txt file for the testbench. I' m trying to read different lines from a single file, and different data from a single line, and writing the same. Where can I find Doulos VHDL courses? Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:16 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!t21g2000yqi.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 01:56:20 -0700 (PDT) Organization: http://groups.google.com Lines: 104 Message-ID: <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 93.37.211.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240476980 23976 127.0.0.1 (23 Apr 2009 08:56:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 08:56:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t21g2000yqi.googlegroups.com; posting-host=93.37.211.149; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:930 On 23 Apr, 10:06, Dek wrote: > On 22 Apr, 18:24, Tricky wrote: > > > > > > > On 22 Apr, 08:57, Dek wrote: > > > > Hi everybody, > > > > I'm new to VHDL an to this group too; as an exercise I'm trying to > > > import data from several files using package TextIO, but I haven't > > > found yet a good manual or tutorial about it; may you suggest me some? > > > > Thanks > > > > Bye > > > > Dek > > > If you're only trying to read in text, then TextIO is what you need. > > For binary files, you dont use the TextIO package, and reading data in > > is a bit more contrived and apparently doesnt work the same accross > > different apps. (as a note, I have functions to read/write bitmap > > files directly from VHDL in Modelsim but thats only because I work > > with video and looking at an actual picture is alot quicker than > > trying to interpret text). > > > But like Mike says, if its for anything other than input to a hardware > > model, use something else to do the work. It might be best to just ask > > the questions here, or go on the Doulos VHDL courses. > > Thanks for the answer, > > what I want to do actually is an hardware model using a .txt file for > the testbench. I' m trying to read different lines from a single file, > and different data from a single line, and writing the same. Where can > I find Doulos VHDL courses? > > Thanks > > Bye- Nascondi testo citato > > - Mostra testo citato - For example I wrote this code: -------------------------------------------------------------------- USE std.textio.all; ENTITY form_IO IS --empty END form_IO; ARCHITECTURE formatted OF form_IO IS BEGIN PROCESS IS FILE formout : Text ; VARIABLE int : Integer := 5 ; VARIABLE buf : Line ; VARIABLE fstatus : File_open_status ; BEGIN File_open(fstatus, formout, "C:/Users/Daniele/Desktop/Esercizi/ form_io.txt", write_mode); L1:write (buf, "This is an example of formatted I/O"); L2:writeline (formout, buf); L3:write (buf, "Integer int="); L4:write (buf, int); L5:writeline (formout, buf); L6:file_close(formout); wait; END PROCESS; END formatted; ----------------------------------------------------------------- but I got the following error message: # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24): Subprogram 'write' is ambiguous. # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24): No feasible entries for subprogram "write". # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(26): Subprogram 'write' is ambiguous. # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(26): No feasible entries for subprogram "write". # ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(33): VHDL Compiler exiting where am I wrong? Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2009 03:55:53 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Multiple components driving a single bus Date: Thu, 23 Apr 2009 09:53:39 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <4ua0v4l7cj39vrqpnk52g790pvsm8t1uei@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-s4TcFvcmY3r897a8KRPQfDvf4UI/fCdXv7qnHIOgMxh2GffTdd6HdtHSvxtYG2pYQov0VxZGNWdiwWQ!Yqvl4weKaHtCYJobSCThuXZFkjVdExl2KSY790shaFl/Eh00AXHeS7nyNW/zK2c/34CrJQqOcoEn!hEQL X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:931 On Tue, 21 Apr 2009 18:27:42 -0700 (PDT), Benjamin Couillard wrote: [...] >Let's say that when the address is not 0, DATA_OUT of block1 will be >high-Z and when the addres is not 4 Data_out of block 2 will be high- >Z. Will ISE synthesis engine be smart enough to realize there is no >bus contention? Basically, will ISE infer muxes from that code? This is the readback-decode problem that has caused me much pain in the past. There was quite an interesting related discussion here back in January, in the thread "Unassigned register decode", in which I posted a sketch of one possible way to attack it - without writing tri-states and then expecting the tool to convert them to muxes. But I agree with you and Brian that the tristate=>mux solution usually works pretty well. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.buerger.net!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2009 04:25:11 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 10:22:57 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 78 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Lc0h9UhxEnvt0A0pGs5rf/03TWXJNfSgEoidn6MpePheNtXHG6ShtEzKq43ijTJb4X2FC5nr+pHDB8z!boqWY1DlABLUE3i9TcLY9YBAEasCwWQoJEwexhbfBq/VR1W/L4z7gBE88PYp8whtFYwUYW7g4i43!hsd/ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:932 On Thu, 23 Apr 2009 01:56:20 -0700 (PDT), Dek wrote: > File_open(fstatus, formout, ".../form_io.txt", write_mode); > L1:write (buf, "This is an example of formatted I/O"); > L2:writeline (formout, buf); > L3:write (buf, "Integer int="); > L4:write (buf, int); > L5:writeline (formout, buf); > L6:file_close(formout); > >but I got the following error message: > ># ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24): >Subprogram 'write' is ambiguous. > >where am I wrong? OK, that one's easy... There are at least eight different versions of "write". The version to write a string looks, to the compiler, exactly the same as the version to write a bit-vector: write(buf, "1011"); -- String or bit-vector??? Hence the "ambiguous" error message. There are two possible fixes: 1) Type-qualify the string: write(buf, string'("My message")); 2) Create a specialised version of "write", with a different name, to deal with the very common problem of writing a string message: procedure WrStr(L: inout line; S: in string) is begin write (L, S); -- No ambiguity; S is of string type end; Now you can do simply WrStr(buf, "My message"); and all will be well. FOOTNOTE for the nitpickier members of c.l.vhdl: The simple implementation of WrStr, above, is incomplete. To provide the full facilities of "write", complete with formatting, you need this slightly more complex version: procedure WrStr ( L : inout line ; S : in string ; JUSTIFIED : in SIDE := right ; FIELD : in WIDTH := 0 ) is begin write(L, S, JUSTIFIED, FIELD); end; Of course, thanks to the default arguments you can still call it like this if you wish: WrStr(buf, "message"); -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp5-1.free.fr!not-for-mail Subject: Re: TextIO Tutorial From: Bert_Paris References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Thu, 23 Apr 2009 11:26:06 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <49f03430$0$24828$426a74cc@news.free.fr> NNTP-Posting-Date: 23 Apr 2009 11:26:08 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240478768 news-3.free.fr 24828 82.66.120.181:3796 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:933 Dek avait prétendu : > L1:write (buf, "This is an example of formatted I/O"); You need to use qualified expressions : L1:write (buf, string'("This is an example of formatted I/O")); I personnaly use often the trick to concatenate a character. "Hello" & HT becomes automatically a string (it's not ambiguous any more) We teach this in the Doulos course ;-) Bert From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!t21g2000yqi.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 02:55:42 -0700 (PDT) Organization: http://groups.google.com Lines: 82 Message-ID: <391b905b-88dd-4df7-b275-473377f9ab9e@t21g2000yqi.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> NNTP-Posting-Host: 93.37.211.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240480542 29501 127.0.0.1 (23 Apr 2009 09:55:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 09:55:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t21g2000yqi.googlegroups.com; posting-host=93.37.211.149; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:934 On 23 Apr, 11:22, Jonathan Bromley wrote: > On Thu, 23 Apr 2009 01:56:20 -0700 (PDT), Dek wrote: > > =A0 =A0 =A0 File_open(fstatus, formout, ".../form_io.txt", write_mode); > > =A0 =A0 =A0 L1:write (buf, "This is an example of formatted I/O"); > > =A0 =A0 =A0 L2:writeline (formout, buf); > > =A0 =A0 =A0 L3:write (buf, "Integer int=3D"); > > =A0 =A0 =A0 L4:write (buf, int); > > =A0 =A0 =A0 L5:writeline (formout, buf); > > =A0 =A0 =A0 L6:file_close(formout); > > >but I got the following error message: > > ># ** Error: C:/Users/Daniele/Desktop/Esercizi/Format_IO.vhd(24): > >Subprogram 'write' is ambiguous. > > >where am I wrong? > > OK, that one's easy... > > There are at least eight different versions of "write". > The version to write a string looks, to the compiler, > exactly the same as the version to write a bit-vector: > > =A0 write(buf, "1011"); -- String or bit-vector??? > > Hence the "ambiguous" error message. =A0There are two > possible fixes: > > 1) Type-qualify the string: > > =A0 write(buf, string'("My message")); > > 2) Create a specialised version of "write", with a > different name, to deal with the very common problem > of writing a string message: > > =A0 procedure WrStr(L: inout line; S: in string) is > =A0 begin > =A0 =A0 write (L, S); =A0-- No ambiguity; S is of string type > =A0 end; > > Now you can do simply > > =A0 WrStr(buf, "My message"); > > and all will be well. > > FOOTNOTE for the nitpickier members of c.l.vhdl: > The simple implementation of WrStr, above, is > incomplete. =A0To provide the full facilities of > "write", complete with formatting, you need this > slightly more complex version: > > =A0 procedure WrStr > =A0 =A0 ( L =A0 =A0 =A0 =A0 : inout line > =A0 =A0 ; S =A0 =A0 =A0 =A0 : in string > =A0 =A0 ; JUSTIFIED : in SIDE :=3D right > =A0 =A0 ; FIELD =A0 =A0 : in WIDTH :=3D 0 > =A0 =A0 ) is > =A0 begin > =A0 =A0 write(L, S, JUSTIFIED, FIELD); > =A0 end; > > Of course, thanks to the default arguments you can > still call it like this if you wish: > =A0 WrStr(buf, "message"); > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thank you very much now it works properly From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!g19g2000yql.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 02:57:24 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <7828a697-00c2-4135-a12a-b118551ba276@g19g2000yql.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> <49f03430$0$24828$426a74cc@news.free.fr> NNTP-Posting-Host: 93.37.211.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240480645 29785 127.0.0.1 (23 Apr 2009 09:57:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 09:57:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000yql.googlegroups.com; posting-host=93.37.211.149; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:935 On 23 Apr, 11:26, Bert_Paris wrote: > Dek avait pr=E9tendu : > > > =A0 =A0 =A0 =A0L1:write (buf, "This is an example of formatted I/O"); > > You need to use qualified expressions : > =A0 =A0 =A0 =A0L1:write (buf, string'("This is an example of formatted I/= O")); > > I personnaly use often the trick to concatenate a character. > "Hello" & HT becomes automatically a string (it's not ambiguous any > more) > > We teach this in the Doulos course ;-) > > Bert Thank you very much, now it works properly, but I didn't how to concatenate a character; what should I write? From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!37g2000yqp.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 02:59:37 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> <49f03430$0$24828$426a74cc@news.free.fr> NNTP-Posting-Host: 93.37.211.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240480777 30120 127.0.0.1 (23 Apr 2009 09:59:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 09:59:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000yqp.googlegroups.com; posting-host=93.37.211.149; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:936 On 23 Apr, 11:26, Bert_Paris wrote: > Dek avait pr=E9tendu : > > > =A0 =A0 =A0 =A0L1:write (buf, "This is an example of formatted I/O"); > > You need to use qualified expressions : > =A0 =A0 =A0 =A0L1:write (buf, string'("This is an example of formatted I/= O")); > > I personnaly use often the trick to concatenate a character. > "Hello" & HT becomes automatically a string (it's not ambiguous any > more) > > We teach this in the Doulos course ;-) > > Bert Thank you all, now it works properly, but I didn't get how to concatenate a character; what should I write? Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:17 2009 Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: TextIO Tutorial Lines: 29 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe16.ams2 1240481401 86.16.123.60 (Thu, 23 Apr 2009 10:10:01 UTC) NNTP-Posting-Date: Thu, 23 Apr 2009 10:10:01 UTC Organization: virginmedia.com Date: Thu, 23 Apr 2009 11:09:53 +0100 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news4us.nl!eweka.nl!hq-usenetpeers.eweka.nl!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe16.ams2.POSTED!7564ea0f!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:937 "Dek" wrote in message news:e577ffcf-1762-4bd8-9a3a-483d68cff414@a7g2000yqk.googlegroups.com... > Hi everybody, > > I'm new to VHDL an to this group too; as an exercise I'm trying to > import data from several files using package TextIO, but I haven't > found yet a good manual or tutorial about it; may you suggest me some? > > Thanks > > Bye > > Dek Hi Dek, As has been suggested a number of times on this newsgroup you might want to check out the VHDL stdio package: http://bear.ces.case.edu/VHDL/index.html if you know C than this package makes textio a lot easier (at least I think it does), Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: TextIO Tutorial From: Bert_Paris References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> <49f03430$0$24828$426a74cc@news.free.fr> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Thu, 23 Apr 2009 14:04:21 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 33 Message-ID: <49f05947$0$31211$426a74cc@news.free.fr> NNTP-Posting-Date: 23 Apr 2009 14:04:23 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240488263 news-3.free.fr 31211 82.66.120.181:1704 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:938 Dek a utilisé son clavier pour écrire : > On 23 Apr, 11:26, Bert_Paris wrote: >> Dek avait prétendu : >> >>>        L1:write (buf, "This is an example of formatted I/O"); >> >> You need to use qualified expressions : >>        L1:write (buf, string'("This is an example of formatted I/O")); >> >> I personnaly use often the trick to concatenate a character. >> "Hello" & HT becomes automatically a string (it's not ambiguous any >> more) >> >> We teach this in the Doulos course ;-) >> >> Bert > > > > > Thank you all, > > now it works properly, but I didn't get how to concatenate a > character; > what should I write? > > Thanks > > Bye "Hello" & HT From newsfish@newsfish Wed Aug 19 13:24:17 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!r33g2000yqn.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 06:53:20 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <8d4ba513-2758-45f8-8c57-5d7456b16061@r33g2000yqn.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> <49f03430$0$24828$426a74cc@news.free.fr> <49f05947$0$31211$426a74cc@news.free.fr> NNTP-Posting-Host: 93.37.193.187 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240494800 7748 127.0.0.1 (23 Apr 2009 13:53:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 13:53:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r33g2000yqn.googlegroups.com; posting-host=93.37.193.187; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:939 On 23 Apr, 14:04, Bert_Paris wrote: > Dek a utilis=E9 son clavier pour =E9crire : > > > > > > > On 23 Apr, 11:26, Bert_Paris wrote: > >> Dek avait pr=E9tendu : > > >>> =A0 =A0 =A0 =A0L1:write (buf, "This is an example of formatted I/O"); > > >> You need to use qualified expressions : > >> =A0 =A0 =A0 =A0L1:write (buf, string'("This is an example of formatted= I/O")); > > >> I personnaly use often the trick to concatenate a character. > >> "Hello" & HT becomes automatically a string (it's not ambiguous any > >> more) > > >> We teach this in the Doulos course ;-) > > >> Bert > > > Thank you all, > > > now it works properly, but I didn't get how to concatenate a > > character; > > what should I write? > > > Thanks > > > Bye > > "Hello" & HT- Nascondi testo citato > > - Mostra testo citato - Nice trick, thanks again From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!n7g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 09:04:34 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <2d3ce93e-13fb-46b5-85c1-130c5d39647d@n7g2000prc.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240502674 9428 127.0.0.1 (23 Apr 2009 16:04:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 16:04:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000prc.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:940 Hi, > 2) Create a specialised version of "write", with a > different name, to deal with the very common problem > of writing a string message: > > =A0 procedure WrStr(L: inout line; S: in string) is > ... In the VHDL-2008 language revision, the following alias was added to std.textio: alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH]; You call SWRITE just like Jonanthan's WrStr. I have been using some of the supported VHDL-2008 features in both ModelSim and Aldec. If you have the latest versions, I suspect this is in the supported list. Cheers, Jim SynthWorks VHDL Training P.S. If you are in the US, SynthWorks also covers textio and has regularly scheduled classes. http://www.synthworks.com From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2009 11:24:27 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 17:22:11 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75abe842-8b5a-47dd-af27-98af0374073f@t21g2000yqi.googlegroups.com> <2d3ce93e-13fb-46b5-85c1-130c5d39647d@n7g2000prc.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-58jVlG5MFMrelMJZJVUeRRLNzV/7hc/FMwHSWeDFx4hIcksBhlHOw5oEt3/LAJ48P9yZa0sWgXbUjef!5puNjhhnl3mW0dXFdDs3O+K+CdTsccOqtVjVTp6N7uY5RtNHuQd/wI1aM4v+SYyyR7I6YhHkkFG7!j4TY X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:941 On Thu, 23 Apr 2009 09:04:34 -0700 (PDT), JimLewis wrote: >In the VHDL-2008 language revision, the following alias >was added to std.textio: > >alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH]; And, of course, you can write the alias for yourself if you don't have it in your local version of std.textio. The alias is much cooler (and, I guess, more efficient) than my proxy procedure, but I didn't mention it for two reasons: 1) I reckon the proxy is easier to understand for newbies, 2) I'd completely forgotten about the possibility :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 23 Apr 2009 10:19:09 -0700 Lines: 18 Message-ID: <75bm8eF16r1tkU1@mid.individual.net> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net LOhPRNTEcISQiIgA2AWPqwRIdbuyI3Ewy5Ukk9CegcDMeWMUym Cancel-Lock: sha1:8Wu3jnHaL9Tzr9YBE/0v2k6tFpE= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:942 Dek wrote: > what I want to do actually is an hardware model using a .txt file for > the testbench. I' m trying to read different lines from a single file, > and different data from a single line, and writing the same. It is quite common for new vhdl testbenchers to try to write a text script and interpret it using textio rather than learning how to use vhdl types and procedures. I will decline to elaborate because I don't think this is a good idea. > Where can I find Doulos VHDL courses? http://www.doulos.com/ -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!g19g2000yql.googlegroups.com!not-for-mail From: vhdl_addicted Newsgroups: comp.lang.vhdl Subject: a simple CPU Design with some basic operations Date: Thu, 23 Apr 2009 10:59:28 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> NNTP-Posting-Host: 85.99.81.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240509568 20216 127.0.0.1 (23 Apr 2009 17:59:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 17:59:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000yql.googlegroups.com; posting-host=85.99.81.169; posting-account=d_BWvQoAAACZqHJ1ZneDTNHrO9Jb7XXO User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; tr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:943 Hi, I would like to design my own first simplest CPU with VHDL codes. I studied parts of a CPU on some books as Accumulator, Registers, Memory, Control Unit. I have some questions to get answered: ----I want to make a 16-bit simple CPU. I want to multiply 2 numbers (result= 3x5) by calling them from memory in my CPU. I will calculate the result in ALU (arightmetic logic unit) as I consider. Then I want to see the result on the CLK pulse screen in Multisim. But can you give me a hint how to start in my architecture? How can I call accumulator, multiplication, ALU and memory in my codes? -how can i store 3 and 5 in my memory? -what codes are used to call and multiply them in ALU? -how can i carry my result to screen? Thanks in advance, From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: a simple CPU Design with some basic operations Date: Thu, 23 Apr 2009 11:34:13 -0700 Lines: 13 Message-ID: <75bql5F176abpU1@mid.individual.net> References: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Pq39S1SJvuuo7qp/Zx58vA9a58EDVranORdxbObVjtKvTIAQ8q Cancel-Lock: sha1:suZ6iDpOPS6CH8BuSyWx9AR8OEM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:944 vhdl_addicted wrote: > Hi, > > I would like to design my own first simplest CPU with VHDL codes. I would consider something like this: http://www.oxfordbromley.plus.com/files/miniCPU/arch.pdf Google for examples. Every text book has one. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!goblin2!goblin.stu.neva.ru!news.acm.uiuc.edu!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Multiple components driving a single bus Date: Thu, 23 Apr 2009 11:40:23 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <176af698-a319-4343-96b1-08745bda2834@z5g2000vba.googlegroups.com> References: <4ua0v4l7cj39vrqpnk52g790pvsm8t1uei@4ax.com> NNTP-Posting-Host: 66.38.210.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240512023 7183 127.0.0.1 (23 Apr 2009 18:40:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 18:40:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=66.38.210.253; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; fr; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:945 On 23 avr, 04:53, Jonathan Bromley wrote: > On Tue, 21 Apr 2009 18:27:42 -0700 (PDT), Benjamin Couillard wrote: > > [...] > > >Let's say that when the address is not 0, DATA_OUT of block1 =A0will be > >high-Z and when the addres is not 4 Data_out of block 2 will be high- > >Z. Will ISE synthesis engine be smart enough to realize there is no > >bus contention? Basically, will ISE infer muxes from that code? > > This is the readback-decode problem that has caused me much pain > in the past. > > There was quite an interesting related discussion here back in > January, in the thread "Unassigned register decode", in which > I posted a sketch of one possible way to attack it - without > writing tri-states and then expecting the tool to convert > them to muxes. > > But I agree with you and Brian that the tristate=3D>mux solution > usually works pretty well. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I tried my method, and it doesn't seem to scale well. ISE seems to synthesize just fine even though there are address conflicts (I put those conflicts on purpose) . I think I'm gonna use your method Jonathan, it seems to scale reasonably well and it avoids the mess of having one huge process implementing all the registers (I have about 50 register so far, but the number could easily double). From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!q16g2000yqg.googlegroups.com!not-for-mail From: Aiken Newsgroups: comp.lang.vhdl Subject: any program can generate block diagrams? Date: Thu, 23 Apr 2009 14:50:41 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> NNTP-Posting-Host: 199.10.150.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240523442 30020 127.0.0.1 (23 Apr 2009 21:50:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Apr 2009 21:50:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q16g2000yqg.googlegroups.com; posting-host=199.10.150.26; posting-account=o1NIRQoAAACD94UsAWOsHscwtNA8hiam User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:946 I provide RTL code and the program will generate block diagrams with connection between blocks Is it possible? From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!news.glorb.com!news-in-01.newsfeed.easynews.com!easynews!core-easynews-01!easynews.com!en-nntp-08.dc1.easynews.com.POSTED!not-for-mail From: Aldorus Subject: Can you have multiple architecture declarations tied to the same entity? Newsgroups: comp.lang.vhdl User-Agent: pan 0.119 (Karma Hunters) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 42 Message-ID: X-Complaints-To: abuse@easynews.com Organization: EasyNews, UseNet made Easy! X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Thu, 23 Apr 2009 22:03:34 GMT Xref: news.eternal-september.org comp.lang.vhdl:947 newbie here ... I have the following circuit (that will help me learn VHDL) 4 x seven segment displays to be controlled by one cpld. each of the seven segment displays will decode a separate 3 bit register I imagine the entity description should go like this: entity ent_seven_seg_display is port ( itemstate: in bit_vector(2 downto 0); sevseg : out bit_vector(6 downto 0)); end ent_seven_seg_display; Is it possible to have 4 different architecture declarations all referencing the above entity description as in architecture display1 of ent_seven_seg_display is blah blah blah architecture display2 of ent_seven_seg_display is blah blah blah architecture display3 of ent_seven_seg_display is blah blah blah architecture display4 of ent_seven_seg_display is blah blah blah ? Again bear in mind I have 4 seven segment displays that I want to decode the state of 4 x 3 bit registers so at any given point in time each of the seven segment displays will hold a different number. I have one large CPLD with enough pins to handle this circuit ... I just want to know if I can save having to create four entity descriptions that are identical in everything BUT port names Thanks note to self: maybe I should finish reading this VHDL book before posing such questions ... From newsfish@newsfish Wed Aug 19 13:24:18 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: any program can generate block diagrams? Date: Thu, 23 Apr 2009 15:29:16 -0700 Lines: 15 Message-ID: <75c8dtF17bbaaU1@mid.individual.net> References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net sMn9pl2GHKkr5PDIrgPwbgLVeteyj0g04msQyZv8Fi7ftPgirB Cancel-Lock: sha1:trOySSJRlptwzXltjmjUbeiNVJk= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:948 Aiken wrote: > I provide RTL code and the program will generate block diagrams with > connection between blocks > > Is it possible? Yes, see: http://mysite.verizon.net/miketreseler/stack.pdf I use the quartus RTL viewer which requires a license. The ise webpack viewer is free, but not as pretty. Emacs vhdl-mode speedbar is free, but uses text. Everything else is expensive or fussy. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Can you have multiple architecture declarations tied to the same entity? Date: Thu, 23 Apr 2009 16:35:54 -0700 Lines: 19 Message-ID: <75ccarF17986gU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net kyO7O3iHFM9VZL1QR3UYrgHGDSE2BbYjjjSAjS86FsMoQgljQF Cancel-Lock: sha1:NEdXORu01dzGivwknl7lraBJY5Q= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:949 Aldorus wrote: > Is it possible to have 4 different architecture declarations all > referencing the above entity description If I were feeling structural, I could have four *instances* of the same entity/architecture pair. But I usually feel more like declaring and array of registers in a single entity. > note to self: maybe I should finish reading this VHDL book before posing > such questions ... Good idea. Another is to get a simulator and start with some working examples. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2009 19:39:14 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Multiple components driving a single bus Date: Fri, 24 Apr 2009 01:41:16 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <4ua0v4l7cj39vrqpnk52g790pvsm8t1uei@4ax.com> <176af698-a319-4343-96b1-08745bda2834@z5g2000vba.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 29 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-05CSrzlLHtb5MDcMzgSB0C7B2Lkd7fCyqYVjKI08tNQP/IqOuUf0sEHv/iTT78UqpGNyl7KXwhMSPTY!t6BGU/OIteXdexIP4RHRNpJ2roM14+z6bncsCE8VoY1Bwtu1RTfQPYSSMvbR0OmOs7QW/11fmikI!hQ== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:950 On Thu, 23 Apr 2009 11:40:23 -0700 (PDT), Benjamin Couillard wrote: >On 23 avr, 04:53, Jonathan Bromley >wrote: >> On Tue, 21 Apr 2009 18:27:42 -0700 (PDT), Benjamin Couillard wrote: >> >> [...] >> >> >Let's say that when the address is not 0, DATA_OUT of block1  will be >> >high-Z and when the addres is not 4 Data_out of block 2 will be high- >> >Z. Will ISE synthesis engine be smart enough to realize there is no >> >bus contention? Basically, will ISE infer muxes from that code? >> But I agree with you and Brian that the tristate=>mux solution >> usually works pretty well. >I tried my method, and it doesn't seem to scale well. ISE seems to >synthesize just fine even though there are address conflicts (I put >those conflicts on purpose) This is a fair comment; the muxes start to slow down given enough registers (30 maybe 50 seem no problem in V5, maybe half that in S3. My answer was simply to pipeline pages of about 16-30 registers! (A second cycle muxes between the pages) However I believe Jonathan's method will scale rather better... - Brian From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!x5g2000yqk.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: any program can generate block diagrams? Date: Thu, 23 Apr 2009 18:49:35 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240537775 25148 127.0.0.1 (24 Apr 2009 01:49:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 01:49:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x5g2000yqk.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:952 On Apr 23, 5:50=A0pm, Aiken wrote: > I provide RTL code and the program will generate block diagrams with > connection between blocks > > Is it possible? Three free utilities might help: doxygen, VHdocL, and VHDLdoc. Even though doxygen was originally made for software (C/C++/Java), it does have a VHDL mode and I'm told they've made improvements to the VHDL support. I've played a bit with VHDLdoc and VHdocL. I'm not a fan of VHDLdoc - too many restrictions on coding style for my liking. VHdocL is pretty simple and might get you something like a block diagram quickly. Hope this helps. Dave From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: Can you have multiple architecture declarations tied to the same entity? Date: Thu, 23 Apr 2009 23:07:31 -0700 (PDT) Organization: http://groups.google.com Lines: 80 Message-ID: References: NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240553251 9217 127.0.0.1 (24 Apr 2009 06:07:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 06:07:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.7) Gecko/2009032803 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:953 On 24 Apr., 00:03, Aldorus wrote: > newbie here ... > > I have the following circuit (that will help me learn VHDL) > 4 x seven segment displays to be controlled by one cpld. each of the > seven segment displays will decode a separate 3 bit register > > I imagine the entity description should go like this: > entity ent_seven_seg_display is port ( > =A0 =A0 =A0 =A0itemstate: in =A0bit_vector(2 downto 0); > =A0 =A0 =A0 =A0sevseg =A0 : out bit_vector(6 downto 0)); > end ent_seven_seg_display; > > Is it possible to have 4 different architecture declarations all > referencing the above entity description > > as in > architecture display1 of ent_seven_seg_display is > blah blah blah > > architecture display2 of ent_seven_seg_display is > blah blah blah > > architecture display3 of ent_seven_seg_display is > blah blah blah > > architecture display4 of ent_seven_seg_display is > blah blah blah > > ? > > Again bear in mind I have 4 seven segment displays that I want to decode > the state of 4 x 3 bit registers so at any given point in time each of > the seven segment displays will hold a different number. > > I have one large CPLD with enough pins to handle this circuit ... > > I just want to know if I can save having to create four entity > descriptions that are identical in everything BUT port names > > Thanks > note to self: maybe I should finish reading this VHDL book before posing > such questions ... Hi Aldorus, you are contradicting yourself in your posting. If you are using a common entity all your architectures have to use te same port names. But still you are free to write independent entities with the same port names too. Or did you mean: ...identical in everything BUT _Entity_ names... ? anyway... about VHDL: Yo can use in line instantiation like this: decoder1: entity work.decoder(arch1) port map ... decoder2: entity work.decoder(arch2) port map ... This works at least for simulation, you have to try it for synthesis. Maybe not all tools can handle it. about your design: Looks like you need four 7-segment decoders. I wonder why they should be different in any way? In VHDL you are able to instantiate the same ent-arc pair multiple times, and connect them do tifferent signals (keyword: structural design). You will need a toplevel design anyway. eg.: decoder1: entity work.decoder(behavioral) port map (itemstate =3D> stateinput1, sevseg =3D> display1); decoder2: entity work.decoder(behavioral) port map (itemstate =3D> stateinput2, sevseg =3D> display2); Have a nice synthesis Eilert From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!q16g2000yqg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Can you have multiple architecture declarations tied to the same entity? Date: Fri, 24 Apr 2009 01:12:21 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <65bf7d7f-2231-4aa1-a4b4-01fe38585cff@q16g2000yqg.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240560742 1166 127.0.0.1 (24 Apr 2009 08:12:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 08:12:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q16g2000yqg.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:954 On 23 Apr, 23:03, Aldorus wrote: > newbie here ... > > I have the following circuit (that will help me learn VHDL) > 4 x seven segment displays to be controlled by one cpld. each of the > seven segment displays will decode a separate 3 bit register > > I imagine the entity description should go like this: > entity ent_seven_seg_display is port ( > =A0 =A0 =A0 =A0itemstate: in =A0bit_vector(2 downto 0); > =A0 =A0 =A0 =A0sevseg =A0 : out bit_vector(6 downto 0)); > end ent_seven_seg_display; > > Is it possible to have 4 different architecture declarations all > referencing the above entity description > > as in > architecture display1 of ent_seven_seg_display is > blah blah blah > > architecture display2 of ent_seven_seg_display is > blah blah blah > > architecture display3 of ent_seven_seg_display is > blah blah blah > > architecture display4 of ent_seven_seg_display is > blah blah blah > > ? > > Again bear in mind I have 4 seven segment displays that I want to decode > the state of 4 x 3 bit registers so at any given point in time each of > the seven segment displays will hold a different number. > > I have one large CPLD with enough pins to handle this circuit ... > > I just want to know if I can save having to create four entity > descriptions that are identical in everything BUT port names > > Thanks > note to self: maybe I should finish reading this VHDL book before posing > such questions ... The only time I have seen multiple architectures for the same entity is when there is a different architecture for simulation and synthesis (normally to speed up simulation). For the 7-seg display normally the decode would be the same, so why cant you just instatiate the same entity 4 times connected to the 4 different registers? From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe20.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> <49f11357$0$2711$4d3efbfe@news.sover.net> Subject: Re: any program can generate block diagrams? Lines: 28 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe20.ams2 1240561703 86.16.123.60 (Fri, 24 Apr 2009 08:28:23 UTC) NNTP-Posting-Date: Fri, 24 Apr 2009 08:28:23 UTC Organization: virginmedia.com Date: Fri, 24 Apr 2009 09:28:18 +0100 Xref: news.eternal-september.org comp.lang.vhdl:955 "Jeff Cunningham" wrote in message news:49f11357$0$2711$4d3efbfe@news.sover.net... > Aiken wrote: >> I provide RTL code and the program will generate block diagrams with >> connection between blocks >> >> Is it possible? > > Mentor used to have a product called Renoir that could do this. Apparently > the name has changed and searching for it leads here: That name has changed probably close to 10 years ago :-) It is now called HDL Designer/Author and it is a great product (but as you mentioned not cheap). Hans www.ht-lab.com > > http://www.mentor.com/products/fpga/request? > > I'm guessing its not cheap. > > -Jeff From newsfish@newsfish Wed Aug 19 13:24:19 2009 From: aralimaradsir@gmail.com Newsgroups: comp.lang.vhdl Subject: error in simulation Date: Fri, 24 Apr 2009 02:05:06 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <9979595f-853a-4bdd-8f32-5a7f017dd6a5@k8g2000yqn.googlegroups.com> NNTP-Posting-Host: 210.212.197.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240563907 21576 127.0.0.1 (24 Apr 2009 09:05:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 09:05:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=210.212.197.162; posting-account=n5XdswoAAABwvo0dMWxBsOKUpPSvJHxg User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news4us.nl!news.glorb.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:956 i wrote following code in quartus II and tried to simulate but i am not getting results what could be the reason can anyone fix it thank you. package non is type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0); end non; library ieee; use ieee.std_logic_1164.all; use work.non.all; entity add_key1 is port(clk:in bit;o:out matrix); end add_key1; architecture abc of add_key1 is --type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0); constant m1:matrix:=(("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111")); constant m2:matrix:=(("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111"), ("11111111","11111111","11111111","11111111")); signal m3:matrix; begin process begin wait until clk='1'; loop1: for i in 0 to 3 loop loop2:for j in 0 to 3 loop m3(i,j)<=m1(i,j) xor m2(i,j); end loop loop2; end loop loop1; o<=m3; end process; end abc; From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!f19g2000yqh.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: error in simulation Date: Fri, 24 Apr 2009 02:30:41 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: References: <9979595f-853a-4bdd-8f32-5a7f017dd6a5@k8g2000yqn.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240565441 26135 127.0.0.1 (24 Apr 2009 09:30:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 09:30:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f19g2000yqh.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:957 On 24 Apr, 10:05, aralimarad...@gmail.com wrote: > i wrote following code in quartus II and tried to simulate but i am > not getting results what could be the reason can anyone fix it thank > you. > > package non is > > type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0); > > end non; > > library ieee; > use ieee.std_logic_1164.all; > use work.non.all; > entity add_key1 is > port(clk:in bit;o:out matrix); > end add_key1; > architecture abc of add_key1 is > --type matrix is array (0 to 3, 0 to 3)of bit_vector(7 downto 0); > constant m1:matrix:=3D(("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111")); > constant m2:matrix:=3D(("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111"), > ("11111111","11111111","11111111","11111111")); > signal m3:matrix; > begin > process > begin > wait until clk=3D'1'; > loop1: for i in 0 to 3 loop > > loop2:for j in 0 to 3 loop > =A0 m3(i,j)<=3Dm1(i,j) xor m2(i,j); > > end loop loop2; > end loop loop1; > o<=3Dm3; > end process; > > end abc; It runs fine for me - The output is exactly how I expected, all 0's. What exactly is the problem? From newsfish@newsfish Wed Aug 19 13:24:19 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed4-a.proxad.net!nnrp8-1.free.fr!not-for-mail Subject: Re: any program can generate block diagrams? From: Bert_Paris References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Fri, 24 Apr 2009 12:36:44 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 8 Message-ID: <49f1963e$0$3531$426a74cc@news.free.fr> NNTP-Posting-Date: 24 Apr 2009 12:36:46 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240569406 news-1.free.fr 3531 82.66.120.181:1744 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:958 Last time I checked (quite a while ago), ease HDL was a pretty good tool: http://www.hdlworks.com/products/ease/index.html btw: AFAIK, you don't need the subscription version to use Quartus' RTL Viewer, it's free, included in the Web Edition. Bert From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!3g2000yqk.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Fri, 24 Apr 2009 03:39:31 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240569572 29230 127.0.0.1 (24 Apr 2009 10:39:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 10:39:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 3g2000yqk.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:959 On 23 Apr, 19:19, Mike Treseler wrote: > Dek wrote: > > what I want to do actually is an hardware model using a .txt file for > > the testbench. I' m trying to read different lines from a single file, > > and different data from a single line, and writing the same. > > It is quite common for new vhdl testbenchers > to try to write a text script and interpret it using > textio rather than learning how to use > vhdl types and procedures. > I will decline to elaborate because > I don't think this is a good idea. > > > Where can I find Doulos VHDL courses? > > http://www.doulos.com/ > > =A0 =A0 =A0-- Mike Treseler I think I can't do anything better, because I have to simulate how an FPGA would work on data coming from a detector, that are already stored in many .txt files. Now the problem is that such files are thousands and it takes a lot of time to change manually their name in vhdl code. One idea is to use Generics, name all data files in a "name.do" file and use "do name.do" command. Even in this case, however, I have to name files manually one by one. Do you know if there is a way to read all files in a folder without nameing them? The same problem, unfortunately, is for writing, since for each in- file I have to write one out-file. Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!k41g2000yqh.googlegroups.com!not-for-mail From: vhdl_addicted Newsgroups: comp.lang.vhdl Subject: Re: a simple CPU Design with some basic operations Date: Fri, 24 Apr 2009 04:23:01 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> <75bql5F176abpU1@mid.individual.net> NNTP-Posting-Host: 88.229.5.198 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240572181 5281 127.0.0.1 (24 Apr 2009 11:23:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 11:23:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k41g2000yqh.googlegroups.com; posting-host=88.229.5.198; posting-account=d_BWvQoAAACZqHJ1ZneDTNHrO9Jb7XXO User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; tr; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:960 On Apr 23, 9:34=A0pm, Mike Treseler wrote: > vhdl_addicted wrote: > > Hi, > > > I would like to design my own first simplest CPU with VHDL codes. > > I would consider something like this:http://www.oxfordbromley.plus.com/fi= les/miniCPU/arch.pdf > > Google for examples. > Every text book has one. > > =A0 =A0 =A0 =A0-- Mike Treseler I needed a document about VHDL and cpu design with a good explanation. I guess it will help me out. Thanks a lot for your help. The only problem is how to design the datapath between Accumulator, control unit, Arithmetic logic unit and so on... I dont know how to drop them into VHDL codes. It might take time, but it will be worthy. From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 24 Apr 2009 06:31:49 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: a simple CPU Design with some basic operations Date: Fri, 24 Apr 2009 12:29:38 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> <75bql5F176abpU1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-4r5xC5fdYwJHfv57XAZVsDUkywsKQsVMB6uNSOThL3ODCy/eGlYh6/PJS4/yLC/j7S+u55Hq/8z3gI7!Qgu60YqtK/BdOpYZ2xiYdtAbx3AQ2NpoPtIlWjSqQ0ehCJA4IDt1IVQxvNDBaNvCIupJLvSkjyY/!9mDX X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:961 On Fri, 24 Apr 2009 04:23:01 -0700 (PDT), vhdl_addicted wrote: >problem is how to design the datapath between Accumulator, control >unit, Arithmetic logic unit and so on... I dont know how to drop them >into VHDL codes. It might take time, but it will be worthy. Have a look around on opencores.org; there are plenty of CPU designs there. But I fear you will not find a simple, clear explanation of what to do. Indeed, the document Mike linked for you was my response to the poor standard of documentation of many of the opencores CPUs! As Mike said, look at a digital design textbook - they often have CPU designs. "Design Recipes for FPGAs" by Wilson has one, for example. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!news2.euro.net!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: any program can generate block diagrams? Date: Fri, 24 Apr 2009 14:36:27 +0200 Lines: 15 Message-ID: <87ljpqp6t0.fsf@harnisch.dyndns.org> References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net ssc32800C9rfWGc3LayLNw7sKpp3MEyRMOt/gXuu6LTo1V6rpt Cancel-Lock: sha1:PxO6p5zdkhAobFHQh2MFwnkGnFY= sha1:zINls7crYL6CQyQYS2oRZySMT0U= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:962 Aiken writes: > I provide RTL code and the program will generate block diagrams with > connection between blocks SpringSoft (formerly Novas) Verdi. Costs a bit, though. Best RTL debug tool I have used so far. Regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!k19g2000prh.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Can you have multiple architecture declarations tied to the same entity? Date: Fri, 24 Apr 2009 09:17:09 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <34b26d60-69cf-47df-9c6a-48c6a4eec42b@k19g2000prh.googlegroups.com> References: NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240589829 2632 127.0.0.1 (24 Apr 2009 16:17:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 16:17:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k19g2000prh.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:963 Hi Aldorus, Before you start writing the VHDL code, make sure you draw a picture (block diagram) of what you want. Often with seven segment displays are connected with a common anode or common cathode connection. This would mean that only one display value can be driven at a time and you can take advantage of this. If you find you have 4 entirely separately controlled segments (such as the Altera/Terasic DE1 has), having 4 instances of a single entity that controls a single segment is fine (as described in other threads). OTOH, if you have a common anode connection (such as the Digilent Basys and Nexsys boards have), then somewhere you will have to multiplex the separate values onto the cathode lines. While the same approach used previously will work, it creates more hardware than you need. You will have 4 copies of the decode logic. Instead, you can multiplex your registers first then only have one copy of the decode logic. In summary: + read your VHDL text or at least a tutorial such as: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html + Before coding, draw a picture of what hardware you want. + Before writing code, write comments in the file that reflect what is in the block diagram + Write code Good luck. Trying to code without reading the book can be both frustrating and time consuming. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!transit4.hitnews.eu!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!border1.nntp.dca.giganews.com!nntp.giganews.com!news-in-01.newsfeed.easynews.com!easynews!core-easynews-01!easynews.com!en-nntp-06.dc1.easynews.com.POSTED!not-for-mail From: Aldorus Subject: Re: Can you have multiple architecture declarations tied to the same entity? Newsgroups: comp.lang.vhdl References: User-Agent: pan 0.119 (Karma Hunters) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 13 Message-ID: <3BmIl.202048$Yx2.190852@en-nntp-06.dc1.easynews.com> X-Complaints-To: abuse@easynews.com Organization: EasyNews, UseNet made Easy! X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 24 Apr 2009 17:24:15 GMT Xref: news.eternal-september.org comp.lang.vhdl:964 On Thu, 23 Apr 2009 23:07:31 -0700, goouse wrote: > decoder1: entity work.decoder(behavioral) > port map (itemstate => stateinput1, > sevseg => display1); > decoder2: entity work.decoder(behavioral) > port map (itemstate => stateinput2, > sevseg => display2); > > Have a nice synthesis > Eilert Thanks this was very helpful From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!t21g2000yqi.googlegroups.com!not-for-mail From: bknpk@hotmail.com Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Fri, 24 Apr 2009 11:02:55 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <36a641cf-c594-4d67-a5a5-e7c2601c989f@t21g2000yqi.googlegroups.com> References: NNTP-Posting-Host: 79.180.113.38 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240596175 18136 127.0.0.1 (24 Apr 2009 18:02:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 18:02:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t21g2000yqi.googlegroups.com; posting-host=79.180.113.38; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; he; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:965 On 22 =D7=90=D7=A4=D7=A8=D7=99=D7=9C, 10:57, Dek = wrote: > Hi everybody, > > I'm new to VHDL an to this group too; as an exercise I'm trying to > import data from several files using package TextIO, but I haven't > found yet a good manual or tutorial about it; may you suggest me some? > > Thanks > > Bye > > Dek You may see this page as an example for text io usyage. ... Sometimes simulation are very long, which makes it impossible to record waves for the entire simulation. The monitor helps you locate those areas, which need debug and waves. ... http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!t36g2000prt.googlegroups.com!not-for-mail From: Daniel Leu Newsgroups: comp.lang.vhdl Subject: Re: any program can generate block diagrams? Date: Fri, 24 Apr 2009 16:46:07 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> <87ljpqp6t0.fsf@harnisch.dyndns.org> NNTP-Posting-Host: 71.131.23.224 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240616767 19533 127.0.0.1 (24 Apr 2009 23:46:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Apr 2009 23:46:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t36g2000prt.googlegroups.com; posting-host=71.131.23.224; posting-account=vg5e4goAAAAGOhAcfiR_nSjiLBi7pokl User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/528.16 (KHTML, like Gecko) Version/4.0 Safari/528.16,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:966 RTLvision from Concept Engineering (http://concept.de/rtl_index.html) would be an other option. Regards, Daniel From newsfish@newsfish Wed Aug 19 13:24:20 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsfeed-0.progon.net!progon.net!news.glorb.com!nlpi057.nbdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi070.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> Subject: Re: TextIO Tutorial Lines: 41 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi070.nbdc.sbc.com 1240618895 ST000 99.184.242.197 (Fri, 24 Apr 2009 20:21:35 EDT) NNTP-Posting-Date: Fri, 24 Apr 2009 20:21:35 EDT Organization: at&t http://my.att.net/ X-UserInfo1: SCSYQNON^ZTGRTPX@JIX_UXBUSXB@DTMNHWB_EYLJZ]BGIELDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Fri, 24 Apr 2009 20:21:31 -0400 Xref: news.eternal-september.org comp.lang.vhdl:967 > I think I can't do anything better, because I have to simulate how an > FPGA would work on data coming from a detector, that are already > stored in many .txt files. > One could ask how did those files get created in the first place. Unless they were generated from an actual detector, then they were artificially generated in the first place. Rather than artificially generating data into text files and then figuring out how to read them into a testbench it is much more productive to model the detector in the VHDL testbench and totally bypass file I/O (which is not really one of VHDL's strengths). But I'll assume though that you have to work with file I/O. > Now the problem is that such files are thousands and it takes a lot of > time to change manually their name in vhdl code. One idea is to use > Generics, name all data files in a "name.do" file and use "do name.do" > command. Even in this case, however, I have to name files manually one > by one. Not really. The name.do file can be easily created with a simple directory listing command (Windows command line "dir /b >name.do"). That's pretty easy to do. > Do you know if there is a way to read all files in a folder > without nameing them? I don't. > The same problem, unfortunately, is for writing, since for each in- > file I have to write one out-file. > Once you've read in a line from 'name.do' you've got a unique input file name. I would construct a similarly unique output file name by modifying the input file name in some fashion (say by appending ".out" to the input file name). Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!border-1.ams.xsnews.nl!feed.xsnews.nl!border-3.ams.xsnews.nl!69.16.177.242.MISMATCH!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe03.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> Subject: Re: TextIO Tutorial Lines: 34 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <7rzIl.110009$AS.28159@newsfe03.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe03.ams2 1240646467 86.16.123.60 (Sat, 25 Apr 2009 08:01:07 UTC) NNTP-Posting-Date: Sat, 25 Apr 2009 08:01:07 UTC Organization: virginmedia.com Date: Sat, 25 Apr 2009 09:01:02 +0100 Xref: news.eternal-september.org comp.lang.vhdl:968 "Dek" wrote in message news:c3686086-6f77-4d96-9498-1c21532af85e@3g2000yqk.googlegroups.com... On 23 Apr, 19:19, Mike Treseler wrote: > Dek wrote: > I think I can't do anything better, because I have to simulate how an > FPGA would work on data coming from a detector, that are already > stored in many .txt files. > > Now the problem is that such files are thousands and it takes a lot of > time to change manually their name in vhdl code. One idea is to use > Generics, name all data files in a "name.do" file and use "do name.do" > command. Even in this case, however, I have to name files manually one > by one. Do you know if there is a way to read all files in a folder > without nameing them? Look into using Tcl which if fully integrated with Modelsim. To read a directory simply use the "glob *" command followed by a "foreach" to handle each filename. Other useful Tcl Modelsim commands are force/when and examine (see manual), Hans www.ht-lab.com >The same problem, unfortunately, is for writing, since for each in- >file I have to write one out-file. > >Thanks > >Bye From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!z8g2000prd.googlegroups.com!not-for-mail From: Zhane Newsgroups: comp.lang.vhdl Subject: std.textio.all procedure read Date: Sat, 25 Apr 2009 02:52:22 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 218.186.10.247 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240653142 8897 127.0.0.1 (25 Apr 2009 09:52:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 25 Apr 2009 09:52:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z8g2000prd.googlegroups.com; posting-host=218.186.10.247; posting-account=Wtkv4AoAAABABUGDjlNxfPauhvUdvQ7z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:969 variable L: Line; variable Tim: time; variable Int: integer; variable cha: character; variable str : string(1 to 6); READLINE(F,L); READ(L, Tim); READ(L, Int); READ(L, cha); READ(L, Str); READ(L, Int); for the above code, what will i get if the input file, F has.. 100 NS 99 ABCDEF 27 as the input stimuli? From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sat, 25 Apr 2009 09:56:32 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: std.textio.all procedure read Date: Sat, 25 Apr 2009 15:54:14 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gHI8AUlh5XONvG+DDjVUYOKIEx0JgQAcFrc4Y+vSeY+DvIyzBvLXHtcfB3Gkj70jGlB9/7P4EsONkBm!dPhnguWuUsrFK9CS89vmqZ9CmqjSjaTPILl7u9B+pAitlYmOpWB/1udCPLxwdQ6wskR/C5EbLGEM!jEwH X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:970 On Sat, 25 Apr 2009 02:52:22 -0700 (PDT), Zhane wrote: >variable L: Line; >variable Tim: time; >variable Int: integer; >variable cha: character; >variable str : string(1 to 6); > >READLINE(F,L); >READ(L, Tim); >READ(L, Int); >READ(L, cha); >READ(L, Str); >READ(L, Int); > >for the above code, what will i get if the input file, F has.. >100 NS 99 ABCDEF 27 > >as the input stimuli? I've seen that example somewhere before.... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!k19g2000prh.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: a simple CPU Design with some basic operations Date: Sat, 25 Apr 2009 08:36:14 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <6f2f80bf-9d2c-4111-8581-ac709afced99@k19g2000prh.googlegroups.com> References: <23471a10-d909-4db4-ad5a-f6e1eddc2618@g19g2000yql.googlegroups.com> <75bql5F176abpU1@mid.individual.net> NNTP-Posting-Host: 217.171.129.70 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240673775 32762 127.0.0.1 (25 Apr 2009 15:36:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 25 Apr 2009 15:36:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k19g2000prh.googlegroups.com; posting-host=217.171.129.70; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB5),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:971 On 23 Apr, 19:34, Mike Treseler wrote: > vhdl_addicted wrote: > > Hi, > > > I would like to design my own first simplest CPU with VHDL codes. > > I would consider something like this:http://www.oxfordbromley.plus.com/fi= les/miniCPU/arch.pdf > > Google for examples. > Every text book has one. > > =A0 =A0 =A0 =A0-- Mike Treseler Not a bad little design. It does worry me some as he wants to multiply as his first operation. Doing the bus routing is a matter of case/when assignments on various decoded signals from opcodes fields. Designing the instruction set architecture is the hardest part. Making it too complex leads to an un-simple CPU, making it too simple can lead to dificult use or lack of turing completeness. Working out which routing choices are best can be done after you have designed the sub-units such as the ALU. You must decide how many operations the ALU will have, as a trade off between size, speed and logic utility per cycle (Computational Use Density). cheers jacko http://nibz.googlecode.com From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc01.gnilink.net.POSTED!f388d8ac!not-for-mail Newsgroups: comp.lang.vhdl Followup-To: comp.lang.vhdl Lines: 62 From: Ken Cecka Subject: global records (xilinx isim) User-Agent: KNode/0.99.01 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Message-ID: Date: Sat, 25 Apr 2009 23:11:27 GMT NNTP-Posting-Host: 98.117.108.7 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1240701087 98.117.108.7 (Sat, 25 Apr 2009 19:11:27 EDT) NNTP-Posting-Date: Sat, 25 Apr 2009 19:11:27 EDT Xref: news.eternal-september.org comp.lang.vhdl:972 X-Original-Bytes: 2457 Hi All, I've got a testbench framework I've been using for a while now in Xilinx ISim and it's been working well, but I recently tried to migrate it to another project and ran into all kinds of problems with ISim hanging. I finally tracked it down to a signal I had removed because it was unused. I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, but I thought I'd ask about it here first in case I'm doing something horribly abusive/invalid with the language. In the code pasted below, things work fine as long as dummy is present. If I comment out dummy, ISim hangs for several minutes and then exits. Other points of interest: - if I change 'r' to an integer, isim never hangs (irrespective of dummy) - if I leave 'r' as a record but put it inside tb, isim always hangs (irrespective of dummy) Ken ------------------------------------------------------------------------------- PACKAGE pkg IS TYPE rec IS RECORD sig : INTEGER; END RECORD; SIGNAL r : rec; COMPONENT dut IS PORT ( r : IN rec ); END COMPONENT; END pkg; ------------------------------------------------------------------------------- USE WORK.pkg.ALL; ENTITY dut IS PORT ( r : IN rec ); END dut; ARCHITECTURE model OF dut IS SIGNAL dummy : INTEGER; BEGIN END; ------------------------------------------------------------------------------- USE WORK.pkg.ALL; ENTITY tb IS END tb; ARCHITECTURE model OF tb IS BEGIN WRAPPER : dut PORT MAP (r => r); PROCESS BEGIN WAIT FOR 1500 ns; ASSERT (FALSE) REPORT "Done!" SEVERITY NOTE; WAIT; END PROCESS; END; From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 26 Apr 2009 06:54:03 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: global records (xilinx isim) Date: Sun, 26 Apr 2009 12:56:10 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-pStbZaDTylKH7otyTiZ2PIFZ1/Z9ZZ8t3NkzHzVWejT8sAhGYV/PIGoKGK6wsm5g5EWfa+viYL6rzRb!EdUOCURDGL0nJ0k8gxHEmFH5pPigSErsKCH53YtlE9pLX1YFYmgJoUCzw26i6nQZdAGl7DuBUKof!Hg== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2554 Xref: news.eternal-september.org comp.lang.vhdl:973 On Sat, 25 Apr 2009 23:11:27 GMT, Ken Cecka wrote: >Hi All, > >I've got a testbench framework I've been using for a while now in Xilinx ISim and it's been working well, but I recently tried to migrate it to another project and ran into all kinds of problems with ISim hanging. I finally tracked it down to a signal I had removed because it was unused. > >I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, but I thought I'd ask about it here first in case I'm doing something horribly abusive/invalid with the language. ISIM still has many issues with "rarely used" parts of VHDL (which of course, I seem to use a lot of the time). At one point I had eight Webcases open, mostly on ISIM, which resulted in five or six CRs to hopefully resolve some of the problems in upcoming releases. This one clearly needs to be a webcase, and pursued (sometimes it takes persistence, depending on the support engineer you get. It's a bad sign if they reply in Lolcat...) until you get a CR. Even if you were doing something illegal here, ISIM should detect it and produce an error message rather than hanging (or aborting with SIGSEGV/Access Violation). But I believe Xilinx are committed to major improvements in ISIM, and in my experience, once you can drive round the minefields it's becoming a useful tool. - Brian From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc01.gnilink.net.POSTED!f388d8ac!not-for-mail Newsgroups: comp.lang.vhdl Followup-To: comp.lang.vhdl Lines: 35 From: Ken Cecka Subject: Re: global records (xilinx isim) References: User-Agent: KNode/0.99.01 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Message-ID: Date: Sun, 26 Apr 2009 15:54:20 GMT NNTP-Posting-Host: 98.117.108.7 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1240761260 98.117.108.7 (Sun, 26 Apr 2009 11:54:20 EDT) NNTP-Posting-Date: Sun, 26 Apr 2009 11:54:20 EDT Xref: news.eternal-september.org comp.lang.vhdl:974 Brian Drummond wrote: > On Sat, 25 Apr 2009 23:11:27 GMT, Ken Cecka > wrote: > >>Hi All, >> >>I've got a testbench framework I've been using for a while now in Xilinx >>ISim and it's been working well, but I recently tried to migrate it to >>another project and ran into all kinds of problems with ISim hanging. I >>finally tracked it down to a signal I had removed because it was unused. >> >>I've boiled it down to a minimal testcase which I'll be submitting to >>Xilinx, but I thought I'd ask about it here first in case I'm doing >>something horribly abusive/invalid with the language. > > ISIM still has many issues with "rarely used" parts of VHDL (which of > course, I seem to use a lot of the time). At one point I had eight > Webcases open, mostly on ISIM, which resulted in five or six CRs to > hopefully resolve some of the problems in upcoming releases. > > This one clearly needs to be a webcase, and pursued (sometimes it takes > persistence, depending on the support engineer you get. It's a bad sign if > they reply in Lolcat...) until you get a CR. Even if you were doing > something illegal here, ISIM should detect it and produce an error message > rather than hanging (or aborting with SIGSEGV/Access Violation). I'll definitely be filing one - I've gotten fairly good responses form Xilinx in the past. Just figured it was worth getting some feedback here first - I've learned VHDL more from experimentation and examples than from rigorous study of the language, and that sometimes gets me in trouble. > > But I believe Xilinx are committed to major improvements in ISIM, and in > my experience, once you can drive round the minefields it's becoming a > useful tool. > > - Brian From newsfish@newsfish Wed Aug 19 13:24:21 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!ecngs!feeder2.ecngs.de!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: global records (xilinx isim) Date: Sun, 26 Apr 2009 12:03:34 -0700 Lines: 23 Message-ID: <75jpg6F17rsscU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net k60KWTw3ee1IxBoPe/4WUQ3gLrFUQySrY6E+hg03OohDdNQtGZ Cancel-Lock: sha1:Jj5nmJ2v6Prh/N6KGV0facrb55w= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:975 Ken Cecka wrote: > I've boiled it down to a minimal testcase which I'll be submitting to Xilinx, > but I thought I'd ask about it here first in case > I'm doing something horribly abusive/invalid with the language. My local language expert is vsim, and he has no complaints. Good luck. -- Mike Treseler ______________________________________________________ # vsim -c tb # ** Note: (vsim-3812) Design is being optimized... # // ModelSim SE 6.2a Jun 16 2006 Linux 2.6.25.16-0.1-default # Loading work.pkg # Loading work.tb(model) # Loading work.dut(model) VSIM 1> run 1 ms # ** Note: Done! # Time: 1500 ns Iteration: 0 Instance: /tb VSIM 2> From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: any program can generate block diagrams? Date: Sun, 26 Apr 2009 21:26:02 +0200 Organization: 502 You are not allowed to talk Lines: 16 Sender: newsmailcomp6@gustad.com Message-ID: <87mya32p4l.fsf@pangea.home.gustad.com> References: <6b85a4de-34a1-4d9f-9234-d4fdf837babf@q16g2000yqg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX198fGgNIe71BghueXbvB7rV7hqvLg7BUFslHgYdGhv4FzXojj0sP/smwnY06LHeJ5DUjMPPX1JDZblVfZH3EIJH28RDsBiVfwhS9OMUqK8b5RQAx4b+v6+h66yODj/Ucii+ewEW/tlqDw== X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Sun, 26 Apr 2009 19:26:09 +0000 (UTC) X-Auth-Sender: U2FsdGVkX196PJF8/xoA13GPMrHXJaESlWrP1lSGCSg= Cancel-Lock: sha1:hiu51N5diUqaecyH4u15rOT+uAk= sha1:XpdpvTXLEyydM/pxu40W/XS8as8= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:976 Aiken writes: > I provide RTL code and the program will generate block diagrams with > connection between blocks If you have access to a Synopsys Design Compiler license you can do this with the create_schematic and plot -output filename.ps commands, but it might be more detailed that what you want depending upon which blocks you set_dont_touch etc. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z8g2000prd.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: global records (xilinx isim) Date: Sun, 26 Apr 2009 17:29:26 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <930db9da-4f5c-42cc-9692-905e7085e89b@z8g2000prd.googlegroups.com> References: NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240792166 7806 127.0.0.1 (27 Apr 2009 00:29:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 00:29:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z8g2000prd.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:977 Hi Ken, > >I've got a testbench framework I've been using for a while now in Xilinx= ISim and it's been working well, but I recently tried to migrate it to ano= ther project and ran into all kinds of problems with ISim hanging. =A0I fin= ally tracked it down to a signal I had removed because it was unused. > > >I've boiled it down to a minimal testcase which I'll be submitting to Xi= linx, but I thought I'd ask about it here first in case I'm doing something= horribly abusive/invalid with the language. =A0 > > ISIM still has many issues with "rarely used" parts of VHDL (which of cou= rse, I > seem to use a lot of the time). At one point I had eight Webcases open, m= ostly > on ISIM, which resulted in five or six CRs to hopefully resolve some of t= he > problems in upcoming releases. I consider record INOUT to be essential for writing transaction level models in VHDL. In my testbench I use records whose elements are resolved types and initialize the ports. In my case the records are exclusively on the testbench entities. For more details, see the 2nd half of the paper titled, "Accelerating Verification Through Pre-Use of System-Level Testbench Components" which is at: http://www.synthworks.com/papers/index.htm Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!d19g2000prh.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: numeric_std resize function Date: Mon, 27 Apr 2009 00:43:25 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> NNTP-Posting-Host: 80.244.206.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240818205 29688 127.0.0.1 (27 Apr 2009 07:43:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 07:43:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000prh.googlegroups.com; posting-host=80.244.206.6; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.0 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:978 I was surprised by how the resize function works. My intention was to substract two 32-bit signals (std_logic_vectors, but representing 2- complement numbers) and decrease the signal width from 32 bits to 14. The code below does not work: daout <= std_logic_vector( resize((signed(tx_mix_i) - signed (tx_mix_q)),14) ); But this code does: idaout <= std_logic_vector( signed(tx_mix_i) - signed(tx_mix_q) ); daout <= idaout(31 downto 18); I seems as the rezise function selects the 14 lowest bits in the argument instead of the 14 highest. Any comments? /Peter From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!z16g2000prd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: numeric_std resize function Date: Mon, 27 Apr 2009 01:16:20 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240820180 4009 127.0.0.1 (27 Apr 2009 08:16:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 08:16:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z16g2000prd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:979 On 27 Apr, 08:43, Peter wrote: > I was surprised by how the resize function works. My intention was to > substract two 32-bit signals (std_logic_vectors, but representing 2- > complement numbers) and decrease the signal width from 32 bits to 14. > The code below does not work: > > daout <= std_logic_vector( resize((signed(tx_mix_i) - signed > (tx_mix_q)),14) ); > > But this code does: > > idaout <= std_logic_vector( signed(tx_mix_i) - signed(tx_mix_q) ); > daout <= idaout(31 downto 18); > > I seems as the rezise function selects the 14 lowest bits in the > argument instead of the 14 highest. > > Any comments? > > /Peter As to exactly why, Im sure someone knows better, but thats exactly what it says in the package in the comments/documentation (as the comments are pretty much the only docs on the package afaik). -- Id: R.1 function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED; attribute builtin_subprogram of RESIZE[SIGNED, NATURAL return SIGNED]: function is "numstd_resize_sns"; -- Result subtype: SIGNED(NEW_SIZE-1 downto 0) -- Result: Resizes the SIGNED vector ARG to the specified size. -- To create a larger vector, the new [leftmost] bit positions -- are filled with the sign bit (ARG'LEFT). When truncating, -- the sign bit is retained along with the rightmost part. This implies that if you declare your signed value as s(0 to n) instead of downto, you will get the desired outcome (and looking at the actual function, it uses the 'left attribute rather than 'high when taking the return value). From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u39g2000pru.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: numeric_std resize function Date: Mon, 27 Apr 2009 01:55:36 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <77f94645-f51e-40d8-a8c9-7ce493e2ba08@u39g2000pru.googlegroups.com> References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> NNTP-Posting-Host: 80.244.206.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240822536 3728 127.0.0.1 (27 Apr 2009 08:55:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 08:55:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u39g2000pru.googlegroups.com; posting-host=80.244.206.6; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.0 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:980 > =A0 -- =A0 =A0 =A0 =A0 are filled with the sign bit (ARG'LEFT). When trun= cating, > =A0 -- =A0 =A0 =A0 =A0 the sign bit is retained along with the rightmost = part. > > This implies that if you declare your signed value as s(0 to n) > instead of downto, you will get the desired outcome (and looking at > the actual function, it uses the 'left attribute rather than 'high > when taking the return value).- I should have checked the most recent version of numeric_std. I had v 1.2 printed out, which is somewhat cryptic on whats coming out. Thanks, Peter. From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newsfeed.straub-nv.de!weretis.net!feeder2.news.weretis.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp16-2.free.fr!not-for-mail Subject: Re: numeric_std resize function From: Bert_Paris References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 27 Apr 2009 12:30:14 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 36 Message-ID: <49f58937$0$26188$426a34cc@news.free.fr> NNTP-Posting-Date: 27 Apr 2009 12:30:15 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240828215 news-4.free.fr 26188 82.66.120.181:4890 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:981 Peter a utilisé son clavier pour écrire : > I was surprised by how the resize function works. My intention was to > substract two 32-bit signals (std_logic_vectors, but representing 2- > complement numbers) and decrease the signal width from 32 bits to 14. > The code below does not work: > > daout <= std_logic_vector( resize((signed(tx_mix_i) - signed > (tx_mix_q)),14) ); > > But this code does: > > idaout <= std_logic_vector( signed(tx_mix_i) - signed(tx_mix_q) ); > daout <= idaout(31 downto 18); > > I seems as the rezise function selects the 14 lowest bits in the > argument instead of the 14 highest. > > Any comments? > > /Peter I'm not sure I understand your concern. By principle & definition, "resize" does not change the number coded in the vector. For example resize("000011",4) returns "0011", still the same number +3. "resize" is great because : - at simulation, it checks that the truncation doesn't alter the number (in the example aboven resize to two bits as signed vectors would get you a warning because the result would be -1) In the submitted case, it's a great feature ! - it does sign-extend when appropriate (up-sizing signed vectors). Bert From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y33g2000prg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: numeric_std resize function Date: Mon, 27 Apr 2009 06:17:41 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> <49f58937$0$26188$426a34cc@news.free.fr> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240838262 19910 127.0.0.1 (27 Apr 2009 13:17:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 13:17:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y33g2000prg.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:982 On Apr 27, 5:30=A0am, Bert_Paris wrote: > Peter a utilis=E9 son clavier pour =E9crire : > > > > > > > I was surprised by how the resize function works. My intention was to > > substract two 32-bit signals (std_logic_vectors, but representing 2- > > complement numbers) and decrease the signal width from 32 bits to 14. > > The code below does not work: > > > daout <=3D std_logic_vector( resize((signed(tx_mix_i) - signed > > (tx_mix_q)),14) ); > > > But this code does: > > > idaout <=3D std_logic_vector( signed(tx_mix_i) - signed(tx_mix_q) ); > > daout <=3D idaout(31 downto 18); > > > I seems as the rezise function selects the 14 lowest bits in the > > argument instead of the 14 highest. > > > Any comments? > > > /Peter > > I'm not sure I understand your concern. > By principle & definition, "resize" does not change the number coded in > the vector. For example resize("000011",4) returns "0011", still the > same number +3. > > "resize" is great because : > - at simulation, it checks that the truncation doesn't alter the number > =A0 (in the example aboven resize to two bits as signed vectors would get > you a warning because the result would be -1) > =A0In the submitted case, it's a great feature ! > - it does sign-extend when appropriate (up-sizing signed vectors). > > Bert- Hide quoted text - > > - Show quoted text - I agree with Bert. The whole purpose of numeric_std is to apply numeric interpretations to SLV-like vectors. Resizing a number should not alter the numeric value, and resize() will issue a warning if it does so. As to the indexing order, numeric_std defines 'left as the numerically MSB, not 'high. So with signed(0 to n), bit 0 is MSB, not LSB, and is still treated as MSB by resize() and other numeric_std functions/ operators. Andy From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!postnews.google.com!d7g2000prl.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: numeric_std resize function Date: Mon, 27 Apr 2009 06:46:29 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <75e12b89-660a-449e-9ec3-3ef5ef10d13f@d7g2000prl.googlegroups.com> References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> <49f58937$0$26188$426a34cc@news.free.fr> NNTP-Posting-Host: 80.244.206.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240839990 4073 127.0.0.1 (27 Apr 2009 13:46:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 13:46:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000prl.googlegroups.com; posting-host=80.244.206.6; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.0 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:983 > I agree with Bert. The whole purpose of numeric_std is to apply > numeric interpretations to SLV-like vectors. Resizing a number should > not alter the numeric value, and resize() will issue a warning if it > does so. > I believe you are right and that the resize function does what its supposed to do. I think I jumped to the wrong conclusion and that my problem has to do with overflow and scaling of the data. /Peter From newsfish@newsfish Wed Aug 19 13:24:22 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d7g2000prl.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 ? Date: Mon, 27 Apr 2009 07:30:42 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <9794897d-f6fd-45d8-baf1-62301cc70173@d7g2000prl.googlegroups.com> References: <49ed78b2$0$664$426a74cc@news.free.fr> <49ede963$0$18750$426a74cc@news.free.fr> <49edf20f$0$21438$426a74cc@news.free.fr> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240842642 12841 127.0.0.1 (27 Apr 2009 14:30:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 14:30:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000prl.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:984 > > I still wouldn't recommend using VHDL2008 yet, and I don't feel it's going > > to save the language, but maybe I'm wrong. > > Saving the language from what? For verification I agree that the ship has > sailed (although you can still see it in the distance) since SV/SC are > simply to far ahead but for design VHDL will be use for a long long > time.....(I hope) I think you are listening too much to marketing people. For RTL, VHDL has better math capabilities (unsigned, signed, signed fixed point, unsigned fixed point, and float). Did SV even bother? Yes for verification SV has more built in language features, however, constrained random, functional coverage, and coverage driven verification can be achieved in VHDL by writing procedural code. See: http://www.synthworks.com/downloads/index.htm This is stuff we are have been teaching for several years in our VHDL Testbenches and Verification classes. I submitted a paper on it to DVCon for the last two years, however, they are so biased that they no longer accept VHDL papers. So if we want a VHDL conference, we will have to start our own or better yet, have more webinars. Best, Jim P.S. In the US at least, WRT job postings, there are more requests for VHDL (144) than Verilog (101). It has been this way for quite a while (even before the economy changes in October). If you further refine the search to VHDL and not Verilog: 79 Verilog and not VHDL: 36 VHDL and Verilog: 65 So basically almost all of the job postings that have VHDL and Verilog would have to be for Verilog in order for Verilog to have a lead in the job market. Perhaps most of the VHDL users use free tools so the vendors don't count them? From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!gegeweb.org!usenet-fr.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp9-1.free.fr!not-for-mail Subject: Advanced use of VHDL - Factorial example From: Bert_Paris Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Mon, 27 Apr 2009 16:55:03 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <49f5c749$0$5255$426a34cc@news.free.fr> NNTP-Posting-Date: 27 Apr 2009 16:55:05 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240844105 news-4.free.fr 5255 82.66.120.181:4709 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:985 I have assembled an Application Note summarizing some VHDL Coding Techniques that can be useful in an number of situations. Covers : some RTL issues, dealing with large integers, recursivity, unconstrained vectors in ports, using operators as function calls... Anyone spotting error(s) is welcome to report ;-) http://www.alse-fr.com/archive/Factorial.pdf Bert Cuzeau From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!l16g2000pra.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Mon, 27 Apr 2009 08:46:47 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: <76dba03d-700d-468c-a4e0-df0d2f2f9c3e@l16g2000pra.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <7rzIl.110009$AS.28159@newsfe03.ams2> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240847207 15516 127.0.0.1 (27 Apr 2009 15:46:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Apr 2009 15:46:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l16g2000pra.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:986 On 25 Apr, 10:01, "HT-Lab" wrote: > "Dek" wrote in message > > news:c3686086-6f77-4d96-9498-1c21532af85e@3g2000yqk.googlegroups.com... > On 23 Apr, 19:19, Mike Treseler wrote: > > > Dek wrote: > > I think I can't do anything better, because I have to simulate how an > > FPGA would work on data coming from a detector, that are already > > stored in many .txt files. > > > Now the problem is that such files are thousands and it takes a lot of > > time to change manually their name in vhdl code. One idea is to use > > Generics, name all data files in a "name.do" file and use "do name.do" > > command. Even in this case, however, I have to name files manually one > > by one. Do you know if there is a way to read all files in a folder > > without nameing them? > > Look into using Tcl which if fully integrated with Modelsim. To read a > directory simply use the "glob *" command followed by a "foreach" to handle > each filename. Other useful Tcl Modelsim commands are force/when and examine > (see manual), > > Hanswww.ht-lab.com > > > > >The same problem, unfortunately, is for writing, since for each in- > >file I have to write one out-file. > > >Thanks > > >Bye- Nascondi testo citato > > - Mostra testo citato - Thanks all I think I'll try first the idea of KJ; since I'm just learning VHDL and ModelSim, I'll leave Tcl for the future. Thanks again Bye Dek From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 05:30:29 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 43 Sender: mdhicks2@outside.world Message-ID: <6004390c1e4478cb95afaaa7c9e8@news.acm.uiuc.edu> References: <49f5c749$0$5255$426a34cc@news.free.fr> NNTP-Posting-Host: c-98-212-165-84.hsd1.il.comcast.net Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1240896629 17845 98.212.165.84 (28 Apr 2009 05:30:29 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 28 Apr 2009 05:30:29 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:987 > I have assembled an Application Note summarizing some VHDL Coding > Techniques that can be useful in an number of situations. > > Covers : some RTL issues, dealing with large integers, recursivity, > unconstrained vectors in ports, using operators as function calls... > > Anyone spotting error(s) is welcome to report ;-) > > http://www.alse-fr.com/archive/Factorial.pdf > > Bert Cuzeau > I had many problems with the coding style... until I read the second part of the paper. You should make sure to mention that all those type conversions in the first part of the paper is a bad coding style. I also think your choice of using recursive functions is overly complex, especially for anyone who is not a VHDL expert. The same effect could be had by using loop and generate statements to explicitly build a look-up table. I also think that this technique is better in that it does not rely as heavily on the synthesis tool's ability to infer the best solution. Also, a very advanced technique, using the knowledge that the predefined operators are just functions to slice their output. I like it, but you should explain why you can do this in a more in-depth manner. You could also overload the operator, creating a result that you don’t have to slice (which requires more explanation). I also, liked, and never thought of, using unconstrained arrays as port signal types and having the higher-level module constrain them. I still prefer using generics for this, but I'll add it to my toolbox just in case. Overall, I would remove most of the first half of the paper and just present the naive (bad) approach, then go into detail on better ways of doing things. P.S. - Can you provide an example where using unconstrained arrays for port objects is better that using arrays constrained by generic values? One plus for generics is that you don't need a wrapper to work with a single unit if you use the defaults. P.P.S - Compiler writers hate you. :) ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Mon, 27 Apr 2009 23:29:49 -0700 Lines: 32 Message-ID: <75nm2nF1988iuU1@mid.individual.net> References: <49f5c749$0$5255$426a34cc@news.free.fr> <6004390c1e4478cb95afaaa7c9e8@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net a0cSwinUwvIr5NDLQxdnHwHxeDVVRcOJdv2J8CiDxSUWsyS8uI Cancel-Lock: sha1:NZS+hsUYThr3YA0jwUBwFOlpPhQ= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <6004390c1e4478cb95afaaa7c9e8@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:988 Matthew Hicks wrote: > I > also think your choice of using recursive functions is overly complex, > especially for anyone who is not a VHDL expert. Some non-vhdl guys know C or python. > The same effect could > be had by using loop and generate statements to explicitly build a > look-up table. Not the same effect. Fewer would learn something new. > P.S. - Can you provide an example where using unconstrained arrays for > port objects is better that using arrays constrained by generic values? Synthesis can't override the default generics on the top entity. However, I'm not sure that a wrapper is less trouble. I would like to thank Bert for taking the trouble to document and publish this example. While it's not exactly my style, it is working code, and I may even pull it out the next time someone complains about the verbosity of vhdl. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp16-2.free.fr!not-for-mail Subject: Re: Advanced use of VHDL - Factorial example From: Bert_Paris References: <49f5c749$0$5255$426a34cc@news.free.fr> <6004390c1e4478cb95afaaa7c9e8@news.acm.uiuc.edu> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 28 Apr 2009 08:58:17 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Lines: 117 Message-ID: <49f6a90a$0$27925$426a74cc@news.free.fr> NNTP-Posting-Date: 28 Apr 2009 08:58:18 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240901898 news-2.free.fr 27925 82.66.120.181:2118 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:989 Hi Matthew, Matthew wrote : >> I have assembled an Application Note summarizing some VHDL Coding >> Techniques that can be useful in an number of situations. >> >> Covers : some RTL issues, dealing with large integers, recursivity, >> unconstrained vectors in ports, using operators as function calls... >> >> Anyone spotting error(s) is welcome to report ;-) >> >> http://www.alse-fr.com/archive/Factorial.pdf >> >> Bert Cuzeau >> > > I had many problems with the coding style... until I read the second part of > the paper. You should make sure to mention that all those type conversions > in the first part of the paper is a bad coding style. They definitely are *NOT* bad style at all !!!! To make a long story short : - ports are SLV - you need numbers internally So you have to juggle with conversions, but that's in no way difficult ! Just looks a bit awkward for someone not knowing the language. With a very little bit of experience, you just write them without thinking. At times, you may come to hate VHDL for being so strongly typed, but when you use Verilog and spend hours finding out gross errors that wouldn't even compile in VHDL, you think it's a nice feature, after all :-) > I also think your > choice of using recursive functions is overly complex, especially for anyone > who is not a VHDL expert. I don't think it takes a VHDL expert to understand fact(I) = I * fact(I-1). Doesn't sound more challenging that a loop. > The same effect could be had by using loop ... I think I mentioned this. But if you took this paper as an apology for recursive definition of functions, I must have been not explicit enough. I think I was clear that it was not the interest of the paper. > and generate statements Why would you need generate ? ? ? > to explicitly build a look-up table. > I also think that > this technique is better in that it does not rely as heavily on the synthesis > tool's ability to infer the best solution. Again, that's not correct. The final solution relies exclusively on the ability of the synthesis tool to reduce combinational logic ! Not very advanced technology I would say. > Also, a very advanced technique, > using the knowledge that the predefined operators are just functions to slice > their output. I like it, but you should explain why you can do this in a > more in-depth manner. This paper is not intended to replace the Expert VHDL Training courses that we deliver ;-) But I don't think I revealed such a big secret either. It's meant to make sure you remember you saw the solution whenever you try to extract a slice from an operation result. > You could also overload the operator, creating a > result that you don’t have to slice (which requires more explanation). I am strongly against overloading standard operators, but that's another story. In that case, it would probably look bad. Can you share your solution ? > I also, liked, and never thought of, using unconstrained arrays as port > signal types and having the higher-level module constrain them. I still > prefer using generics for this, but I'll add it to my toolbox just in case. Using generics add more lines of code and is a potential source of more errors. (the code could use a generic incorrectly) > Overall, I would remove most of the first half of the paper and just present > the naive (bad) approach, then go into detail on better ways of doing things. Don't agree. The first part is certainly not "bad" ! It's the recommended approach usually (when the function is correctly transformed by the synthesis tools). Imagine the Factorial function is an incrementer, do you think the look up table approach is better that saying out <= in + 1 ? With 32 bits inputs (and a 4 gigawords table) ? > P.S. - Can you provide an example where using unconstrained arrays for port > objects is better that using arrays constrained by generic values? One plus > for generics is that you don't need a wrapper to work with a single unit if > you use the defaults. Please, rewrite the example with generics, loops and generate, and compare. Again, nothing better than some coding to understand issues. btw : having generics at the top level also has issues. Some synthesis tools can over-ride them, or you can use the default values. Unconstrained vectors is a very elegant and reliable way of doing things. > P.P.S - Compiler writers hate you. :) I don't think I'm abusing the language ! Bert From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 07:14:06 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 48 Sender: mdhicks2@outside.world Message-ID: <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> References: <75nm2nF1988iuU1@mid.individual.net> NNTP-Posting-Host: c-98-212-165-84.hsd1.il.comcast.net Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1240902846 19642 98.212.165.84 (28 Apr 2009 07:14:06 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 28 Apr 2009 07:14:06 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:990 > Matthew Hicks wrote: > >> I also think your choice of using recursive functions is overly >> complex, especially for anyone who is not a VHDL expert. >> > Some non-vhdl guys know C or python. Well, my views comes from a person with degrees in Computer Science, so I have written my fair share of software language programs, thus I'm well versed in things like recursion. When I write hardware, I am not writing software, I always think about what the synthesized hardware will look like. I guess that is why I prefer Verilog to VHDL. I try to avoid coding styles that abstract the final HW implementation too much, especially when dealing with novices. > >> The same effect could be had by using loop and generate statements to >> explicitly build a look-up table. >> > Not the same effect. > Fewer would learn something new. Agreed, but only for experts in VHDL. For those who aren't, this would just confuse them and teach them a poor way to write code for actual industrial use. Since you mentioned C, there are a lot of fancy things I can do to perform a task, but for most people, the simple, more clear one is the best. >> P.S. - Can you provide an example where using unconstrained arrays >> for port objects is better that using arrays constrained by generic >> values? >> > Synthesis can't override the default generics on the top entity. > However, I'm not sure that a wrapper is less trouble. That doesn't answer my question, as generics are still a better choice in this case, because you can't even synthesize (or simulate for that matter) unconstrained arrays. > > I would like to thank Bert for taking the trouble > to document and publish this example. > While it's not exactly my style, it is working code, > and I may even pull it out the next time someone > complains about the verbosity of vhdl. > -- Mike Treseler > From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 07:37:28 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 154 Sender: mdhicks2@outside.world Message-ID: <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> References: <49f6a90a$0$27925$426a74cc@news.free.fr> NNTP-Posting-Host: c-98-212-165-84.hsd1.il.comcast.net Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1240904248 19984 98.212.165.84 (28 Apr 2009 07:37:28 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 28 Apr 2009 07:37:28 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:991 > Hi Matthew, > > Matthew wrote : > >>> I have assembled an Application Note summarizing some VHDL Coding >>> Techniques that can be useful in an number of situations. >>> >>> Covers : some RTL issues, dealing with large integers, recursivity, >>> unconstrained vectors in ports, using operators as function calls... >>> >>> Anyone spotting error(s) is welcome to report ;-) >>> >>> http://www.alse-fr.com/archive/Factorial.pdf >>> >>> Bert Cuzeau >>> >> I had many problems with the coding style... until I read the second >> part of the paper. You should make sure to mention that all those >> type conversions in the first part of the paper is a bad coding >> style. >> > They definitely are *NOT* bad style at all !!!! > To make a long story short : > - ports are SLV > - you need numbers internally > So you have to juggle with conversions, but that's in no way difficult > ! > Just looks a bit awkward for someone not knowing the language. > With a very little bit of experience, you just write them without > thinking. > At times, you may come to hate VHDL for being so strongly typed, > but when you use Verilog and spend hours finding out gross errors > that wouldn't even compile in VHDL, you think it's a nice feature, > after all :-) >> I also think your choice of using recursive functions is overly >> complex, especially for anyone who is not a VHDL expert. >> > I don't think it takes a VHDL expert to understand > fact(I) = I * fact(I-1). > Doesn't sound more challenging that a loop. It becomes complex when you try to map recursive functions to actual hardware, which the naive approached showed when you tried to implement it. >> The same effect could be had by using loop ... >> > I think I mentioned this. > But if you took this paper as an apology for recursive definition of > functions, I must have been not explicit enough. I think I was clear > that it was not the interest of the paper. >> and generate statements >> > Why would you need generate ? ? ? Just listing the others tools for conditional elaboration. > >> to explicitly build a look-up table. >> >> I also think that this technique is better in that it does not rely >> as heavily on the synthesis tool's ability to infer the best >> solution. >> > Again, that's not correct. The final solution relies exclusively on > the > ability of the synthesis tool to reduce combinational logic ! > Not very advanced technology I would say. Actually, I doubt the tools are reducing much logic in your example as the implementation tools see a table that maps input value to output value (a LUT). Maybe a better example would have dynamic calculations as opposed to one determined statically. This would motivate using a non-explicit LUT-based solution, especially with lots of possibilities (a point you make later in your response). >> Also, a very advanced technique, using the knowledge that the >> predefined operators are just functions to slice their output. I >> like it, but you should explain why you can do this in a more >> in-depth manner. >> > This paper is not intended to replace the Expert VHDL Training courses > that we deliver ;-) > But I don't think I revealed such a big secret either. > It's meant to make sure you remember you saw the solution whenever you > try to extract a slice from an operation result. >> You could also overload the operator, creating a result that you >> don’t have to slice (which requires more explanation). >> > I am strongly against overloading standard operators, but that's > another story. In that case, it would probably look bad. > Can you share your solution ? >> I also, liked, and never thought of, using unconstrained arrays as >> port signal types and having the higher-level module constrain them. >> I still prefer using generics for this, but I'll add it to my >> toolbox just in case. >> > Using generics add more lines of code and is a potential source of > more errors. (the code could use a generic incorrectly) Lines of code isn't an important issue, if it is, you should be using Verilog. I don't see how I could use a generic incorrectly but not an attribute from a unconstrained port signal. > >> Overall, I would remove most of the first half of the paper and just >> present the naive (bad) approach, then go into detail on better ways >> of doing things. >> > Don't agree. > The first part is certainly not "bad" ! > It's the recommended approach usually (when the function is correctly > transformed by the synthesis tools). > Imagine the Factorial function is an incrementer, do you think the > look > up table approach is better that saying out <= in + 1 ? > With 32 bits inputs (and a 4 gigawords table) ? Agree with the second part. See earlier response. >> P.S. - Can you provide an example where using unconstrained arrays >> for port objects is better that using arrays constrained by generic >> values? One plus for generics is that you don't need a wrapper to >> work with a single unit if you use the defaults. >> > Please, rewrite the example with generics, loops and generate, and > compare. Again, nothing better than some coding to understand issues. I actually had modelsim open and played with your code. I re-implemented using generics with default values and didn't see any major drawbacks. I also tried to index the array with a type during declaration to eliminate the remaining conversions when accessing the table, but that didn't pan out. Why not make din a integer/natural type that the parent module constrains to the correct range? > > btw : having generics at the top level also has issues. > Some synthesis tools can over-ride them, or you can use the default > values. Unconstrained vectors is a very elegant and reliable way of > doing things. >> P.P.S - Compiler writers hate you. :) >> > I don't think I'm abusing the language ! > > Bert > As someone who has the pleasure of writing a VHDL (synthesis subset) compiler, take it from me, you code really stresses compilers. It doesn't abuse the language, but it sure does use a lot of its less-used features (which is why I think it's hard for novices). ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 10:47:17 +0200 Lines: 88 Message-ID: <75nu4mF1989q3U1@mid.individual.net> References: <75nm2nF1988iuU1@mid.individual.net> <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net hmHc9s7jLe+TK+w8MUGDGgETSqW25wl4XTVDTrbgTsaSti1baR Cancel-Lock: sha1:vQyyw92sQ1SQTSUlshZvF7xq9d8= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:992 Matthew Hicks wrote: > That doesn't answer my question, as generics are still a better choice > in this case, because you can't even synthesize (or simulate for that > matter) unconstrained arrays. Of course you can. The array becomes constrained as soon as you connect a constrained signal to it. I use this quite often, actually, simulates and synthesizes fine with every tool I've ever tried (ModelSim, ActiveHDL, XST, Precision, Synplify). Simple example: I often do image-processing blocks. The bidtwidth of the pixels can be 8 in one case, 12 or 14 in another, the underlying operations remain the same. Now I can solve this using a GENERIC, but then I'd have to drag that GENERIC all through the hierarchy. Besides, the GENERIC clutters up my entity declarations: entity do_stuff is generic ( BITWIDTH : positive := 8 ); port ( clk : in std_logic; pix_in : in std_logic_vector(BITWIDTH-1 downto 0); pix_out : out std_logic_vector(BITWIDTH-1 downto 0); pix_mean : out std_logic_vector(BITWIDTH-1 downto 0); pix_min : out std_logic_vector(BITWIDTH-1 downto 0); pix_ax : out std_logic_vector(BITWIDTH-1 downto 0) ); end entity do_stuff; Looks ugly IMHO, only gets worse if you e.g. have separate RGB-values and such. Now, I could instead use records or special types to make it look nicer, but then I couldn't use a GENERIC, but would have to use i.e. a constant defined in a package and the corresponding type declarations. Then it would look better, but I'd have to drag a package all through the hierarchy, and into every project I want to use that specific module in. So, what I do is use unconstrained arrays, and declare special types inside the architecture: entity do_stuff is port ( clk : in std_logic; pix_in : in std_logic_vector; pix_out : out std_logic_vector; ); end entity do_stuff; architecture bla of do_stuff is subtype t_pixdata is std_logic_vector(pix_in'length-1 downto 0); -- I think std_logic_vector(pix_in'range) might work, too signal pixel : t_pixdata; begin -- do stuff with pixels end architecture bla; This is "portable" (I can use it in every project without needing any additional files), doesn't need any special constants or packages, doesn't have a cluttered up port list and I don't have to drag a GENERIC all through the hierarchy, which I might forget to hook up somewhere along the line. I like to have only things configurable that need to be configured. In this case, the width of the vectors can unmistakably be deduced from the connected signals, so there's really no need to make it configurable. My experience is that things that can be configured, somebody will configure wrong, so it's better not to even give them the chance :) The only thing you have to take care of is that when you instantiate do_stuff, the signals you connect to the unconstrained ports must be constrained. But I think "constrainedness" even propagates down. So, for me this works well, but I guess it's more of a personal preference. BTW, I use GENERICs, too, but for other stuff, things that can't be deducted from something else. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?). From newsfish@newsfish Wed Aug 19 13:24:23 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 09:06:56 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 97 Sender: mdhicks2@outside.world Message-ID: <6004390c1e48d8cb95cde7dfb51e@news.acm.uiuc.edu> References: <75nu4mF1989q3U1@mid.individual.net> NNTP-Posting-Host: c-98-212-165-84.hsd1.il.comcast.net Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1240909616 21594 98.212.165.84 (28 Apr 2009 09:06:56 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 28 Apr 2009 09:06:56 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:993 > Matthew Hicks wrote: > >> That doesn't answer my question, as generics are still a better >> choice in this case, because you can't even synthesize (or simulate >> for that matter) unconstrained arrays. >> > Of course you can. The array becomes constrained as soon as you > connect a constrained signal to it. I use this quite often, actually, > simulates and synthesizes fine with every tool I've ever tried > (ModelSim, ActiveHDL, XST, Precision, Synplify). I think you missed what I was trying to say. I meant unconstrained as in a top-level entity whose port signal is an unconstrained array. I agree that unconstrained port signals work great as soon as you constrain them. I like your point about having to drag generics through the design hierarchy, as the processor I'm working with uses this methodology and it is a pain to track down their values. One option would be to use constants in a package (which you mentioned the drawbacks of) for this.. This works if the constant and its value are common to many blocks in the design. > > Simple example: > > I often do image-processing blocks. The bidtwidth of the pixels can be > 8 in one case, 12 or 14 in another, the underlying operations remain > the same. Now I can solve this using a GENERIC, but then I'd have to > drag that GENERIC all through the hierarchy. Besides, the GENERIC > clutters up my entity declarations: > > entity do_stuff is > generic ( > BITWIDTH : positive := 8 > ); > port ( > clk : in std_logic; > pix_in : in std_logic_vector(BITWIDTH-1 downto 0); > pix_out : out std_logic_vector(BITWIDTH-1 downto 0); > pix_mean : out std_logic_vector(BITWIDTH-1 downto 0); > pix_min : out std_logic_vector(BITWIDTH-1 downto 0); > pix_ax : out std_logic_vector(BITWIDTH-1 downto 0) > ); > end entity do_stuff; > Looks ugly IMHO, only gets worse if you e.g. have separate RGB-values > and such. Now, I could instead use records or special types to make it > look nicer, but then I couldn't use a GENERIC, but would have to use > i.e. a constant defined in a package and the corresponding type > declarations. Then it would look better, but I'd have to drag a > package all through the hierarchy, and into every project I want to > use that specific module in. > > So, what I do is use unconstrained arrays, and declare special types > inside the architecture: > > entity do_stuff is > port ( > clk : in std_logic; > pix_in : in std_logic_vector; > pix_out : out std_logic_vector; > ); > end entity do_stuff; > architecture bla of do_stuff is > > subtype t_pixdata is std_logic_vector(pix_in'length-1 downto 0); > > begin > -- do stuff with pixels > end architecture bla; > This is "portable" (I can use it in every project without needing any > additional files), doesn't need any special constants or packages, > doesn't have a cluttered up port list and I don't have to drag a > GENERIC all through the hierarchy, which I might forget to hook up > somewhere along the line. I like to have only things configurable that > need to be configured. In this case, the width of the vectors can > unmistakably be deduced from the connected signals, so there's really > no need to make it configurable. My experience is that things that can > be configured, somebody will configure wrong, so it's better not to > even give them the chance :) > > The only thing you have to take care of is that when you instantiate > do_stuff, the signals you connect to the unconstrained ports must be > constrained. But I think "constrainedness" even propagates down. > > So, for me this works well, but I guess it's more of a personal > preference. BTW, I use GENERICs, too, but for other stuff, things that > can't be deducted from something else. > > cu, > Sean By the way, yes you can declare an array's range using range attributes ('range or 'reverse_range). I just added them today as part of my type test package for my VHDL compiler. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 11:33:04 +0200 Lines: 23 Message-ID: <75o0qhF18r8eqU1@mid.individual.net> References: <75nu4mF1989q3U1@mid.individual.net> <6004390c1e48d8cb95cde7dfb51e@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /B0+Awx+AOasdPHXqKcd1g1pDS9iJx//E4l3g5tYqxv3tkiTUR Cancel-Lock: sha1:SOkSEYdEd/3c9MzceQbK44FdGAY= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <6004390c1e48d8cb95cde7dfb51e@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:994 Matthew Hicks wrote: > I think you missed what I was trying to say. I meant unconstrained as > in a top-level entity whose port signal is an unconstrained array. OK, didn't get that. But on the other hand, this never is an issue for me, since there is *ALWAYS* some top-level entity above that, be it a wrapper (often simply used to adapt my port names to the ones used by everyone else in the project, or convert types so all top-level ports are std_logic_vectors and such) or a structural top-level that connects the blocks, so there's always that place to constrain what needs to be constrained. So, I can understand someone saying that it's a bit ugly that you need that wrapper, but IMHO in most cases that's not a restriction since you usually have one anyway. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?). From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x29g2000prf.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 02:42:36 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <82d275f1-28b8-4135-b49f-205fa050892c@x29g2000prf.googlegroups.com> References: <75nm2nF1988iuU1@mid.individual.net> <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> <75nu4mF1989q3U1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240911757 13297 127.0.0.1 (28 Apr 2009 09:42:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Apr 2009 09:42:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x29g2000prf.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.9) Gecko/2009040821 Firefox/3.0.9,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:995 > > This is "portable" (I can use it in every project without needing any > additional files), doesn't need any special constants or packages, > doesn't have a cluttered up port list and I don't have to drag a GENERIC > all through the hierarchy, which I might forget to hook up somewhere > along the line. I like to have only things configurable that need to be > configured. In this case, the width of the vectors can unmistakably be > deduced from the connected signals, so there's really no need to make it > configurable. My experience is that things that can be configured, > somebody will configure wrong, so it's better not to even give them the > chance :) > But you can prevent incorrect configs, or at least throw up warnings as discussed in another thread. The following code throws a warning in most synthesisers, and actually halts Quartus: function check_setup return boolean is begin assert (ip'length = 8 or ip'length = 10 or ip'length = 12) report "Invalid Input Length detected" severity failure; return true; end check_setup; constant CONFIG_CHECKED : boolean := check_setup; This method can also be used to check for illegal generic combinations. From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi067.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <75nm2nF1988iuU1@mid.individual.net> <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> <75nu4mF1989q3U1@mid.individual.net> Subject: Re: Advanced use of VHDL - Factorial example Lines: 32 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <8aCJl.31059$ZP4.30574@nlpi067.nbdc.sbc.com> NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi067.nbdc.sbc.com 1240919812 ST000 99.184.242.197 (Tue, 28 Apr 2009 07:56:52 EDT) NNTP-Posting-Date: Tue, 28 Apr 2009 07:56:52 EDT Organization: at&t http://my.att.net/ X-UserInfo1: FKPO@MC@@S@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WHC@EK[WDXJHVKHGFFIZHBL@FX\NIOC@FWYNV\DMNS[HTLIXX\^BUGBXLR@PB@\FKCLXSWAIDFOKG^MFT[GZN^NWY_GVLSRGDYY^AW_MS_RW][KBYZMADO@Y[ABPSPE_TA@LTLFXVTC@RJM Date: Tue, 28 Apr 2009 07:56:51 -0400 Xref: news.eternal-september.org comp.lang.vhdl:996 > > The only thing you have to take care of is that when you instantiate > do_stuff, the signals you connect to the unconstrained ports must be > constrained. But I think "constrainedness" even propagates down. > Also remember that unconstrained means that you don't even know which 'direction' the bits go (i.e. 0 to 7 or 7 downto 0). It's quite easy to muck something up because in your mental model and your testbench you only considered the following form of port map signal xyz: std_logic_vector(7 downto 0); ... dut : entity work.widget port map(a => xyz); And haven't tested or considered if widget works correctly for this... signal xyz: std_logic_vector(0 to 7); ... dut : entity work.widget port map(a => xyz); For code that you intend to only reuse yourself, this likely won't be an issue since you'll probably always use it in the same manner. For code intended for the masses, that will not be the case. If nothing else, using unconstrained arrays rather than a generic does imply that some additional testing *should* be performed to make sure that it works with "x to y", "x downto 5" and null arrays Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp18-1.free.fr!not-for-mail Subject: Re: Advanced use of VHDL - Factorial example From: Bert_Paris References: <75nm2nF1988iuU1@mid.individual.net> <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> <75nu4mF1989q3U1@mid.individual.net> <8aCJl.31059$ZP4.30574@nlpi067.nbdc.sbc.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Tue, 28 Apr 2009 14:18:09 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 34 Message-ID: <49f6f402$0$679$426a74cc@news.free.fr> NNTP-Posting-Date: 28 Apr 2009 14:18:10 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240921090 news-1.free.fr 679 82.66.120.181:3205 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:997 KJ wrote : >> >> The only thing you have to take care of is that when you instantiate >> do_stuff, the signals you connect to the unconstrained ports must be >> constrained. But I think "constrainedness" even propagates down. > > Also remember that unconstrained means that you don't even know which > 'direction' the bits go (i.e. 0 to 7 or 7 downto 0). It's quite easy to muck > something up because in your mental model and your testbench you only > considered the following form of port map Hi Kevin, Interesting question. I assume the users of this module follow my VHDL Coding Style Guide that I published here in the past. In particular, I am adamant at enforcing "downto 0" ranges when vectors represent numbers ! Exceptions are a pain (PPC) and I don't even imagine an output like (7 to 47) for the Factorial output vector. And even... would this be really a problem ? What reliability do you gain by using "40 downto 0" ? This doesn't say the MSBit is 40, does it ? For an IP, I definitely agree that it is a good idea to add assertions that verify the ports are defined as expected. Note that not all synthesis tools accept passive processes, otherwise it's tempting to put these assertions in the entity itself. Thx for your feedback. Bert From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!y34g2000prb.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Tue, 28 Apr 2009 06:01:42 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240923703 20368 127.0.0.1 (28 Apr 2009 13:01:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Apr 2009 13:01:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y34g2000prb.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:998 On 25 Apr, 02:21, "KJ" wrote: > > I think I can't do anything better, because I have to simulate how an > > FPGA would work on data coming from a detector, that are already > > stored in many .txt files. > > One could ask how did those files get created in the first place. =A0Unle= ss > they were generated from an actual detector, then they were artificially > generated in the first place. =A0Rather than artificially generating data= into > text files and then figuring out how to read them into a testbench it is > much more productive to model the detector in the VHDL testbench and tota= lly > bypass file I/O (which is not really one of VHDL's strengths). > > But I'll assume though that you have to work with file I/O. > > > Now the problem is that such files are thousands and it takes a lot of > > time to change manually their name in vhdl code. One idea is to use > > Generics, name all data files in a "name.do" file and use "do name.do" > > command. Even in this case, however, I have to name files manually one > > by one. > > Not really. =A0The name.do file can be easily created with a simple direc= tory > listing command > (Windows command line "dir /b >name.do"). =A0That's pretty easy to do. > > > Do you know if there is a way to read all files in a folder > > without nameing them? > > I don't. > > > The same problem, unfortunately, is for writing, since for each in- > > file I have to write one out-file. > > Once you've read in a line from 'name.do' you've got a unique input file > name. =A0I would construct a similarly unique output file name by modifyi= ng > the input file name in some fashion (say by appending ".out" to the input > file name). > > Kevin Jennings Ok, I'll definitively thank this group in my thesis! Your idea seems to work, but there is still a little problem: the name are of different length! If i do like this: ----------------------------------------------- Architecture... Begin process VARIABLE filename : String (23 downto 1); ----------------------------------------------- it works until it find a filename of lenght different from 23. I tried to do something like this: VARIABLE filename : String; or VARIABLE filename : String (natural range<>); but I always get an error message. Have any suggestion? Thanks Dek From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!f41g2000pra.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Tue, 28 Apr 2009 06:28:22 -0700 (PDT) Organization: http://groups.google.com Lines: 92 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1240925302 25560 127.0.0.1 (28 Apr 2009 13:28:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Apr 2009 13:28:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f41g2000pra.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:999 On 28 Apr, 14:01, Dek wrote: > On 25 Apr, 02:21, "KJ" wrote: > > > > > > I think I can't do anything better, because I have to simulate how an > > > FPGA would work on data coming from a detector, that are already > > > stored in many .txt files. > > > One could ask how did those files get created in the first place. =A0Un= less > > they were generated from an actual detector, then they were artificiall= y > > generated in the first place. =A0Rather than artificially generating da= ta into > > text files and then figuring out how to read them into a testbench it i= s > > much more productive to model the detector in the VHDL testbench and to= tally > > bypass file I/O (which is not really one of VHDL's strengths). > > > But I'll assume though that you have to work with file I/O. > > > > Now the problem is that such files are thousands and it takes a lot o= f > > > time to change manually their name in vhdl code. One idea is to use > > > Generics, name all data files in a "name.do" file and use "do name.do= " > > > command. Even in this case, however, I have to name files manually on= e > > > by one. > > > Not really. =A0The name.do file can be easily created with a simple dir= ectory > > listing command > > (Windows command line "dir /b >name.do"). =A0That's pretty easy to do. > > > > Do you know if there is a way to read all files in a folder > > > without nameing them? > > > I don't. > > > > The same problem, unfortunately, is for writing, since for each in- > > > file I have to write one out-file. > > > Once you've read in a line from 'name.do' you've got a unique input fil= e > > name. =A0I would construct a similarly unique output file name by modif= ying > > the input file name in some fashion (say by appending ".out" to the inp= ut > > file name). > > > Kevin Jennings > > Ok, I'll definitively thank this group in my thesis! Your idea seems > to work, but there is still a little problem: > > the name are of different length! If i do like this: > ----------------------------------------------- > Architecture... > Begin > process > =A0 =A0 VARIABLE filename : String (23 downto 1); > ----------------------------------------------- > it works until it find a filename of lenght different from 23. > > I tried to do something like this: > VARIABLE filename : String; > or > VARIABLE filename : String (natural range<>); > but I always get an error message. > Have any suggestion? > > Thanks > > Dek I assume you are reading the string from a line? well, a line is actually a pointer to a string. So, assuming you just have 1 filename per line, you can do something like: readline(namefile, inline); FILE_OPEN(f, inline.all, READ_MODE); DEALLOCATE(inline); --drops the pointer You could do the same if its not just 1 file name per line, but the parsing would get more complicated. But the method above means you can have filenames as long as you want. From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 08:52:41 -0700 Lines: 46 Message-ID: <75on2bF193tpdU1@mid.individual.net> References: <75nm2nF1988iuU1@mid.individual.net> <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /h/gVCu7uufn/zIfqgj5IgNHa1g9hDSRgvoe7G2IhLhVXHyc1K Cancel-Lock: sha1:gZceRiBOXPSfTdzT054x8h8610Y= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <6004390c1e4658cb95be2446b468@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:1000 Matthew Hicks wrote: > Well, my views comes from a person with degrees in Computer Science, so > I have written my fair share of software language programs, thus I'm > well versed in things like recursion. When I write hardware, I am not > writing software, I always think about what the synthesized hardware > will look like. The synthesized hardware looks like LUTs, flops and wires. > I guess that is why I prefer Verilog to VHDL. I try to > avoid coding styles that abstract the final HW implementation too much, > especially when dealing with novices. I'll stick with a bit of abstraction >>> The same effect could be had by using loop and generate statements to >>> explicitly build a look-up table. >>> >> Not the same effect. >> Fewer would learn something new. > > Agreed, but only for experts in VHDL. For those who aren't, this would > just confuse them and teach them a poor way to write code for actual > industrial use. I don't agree. Generated structures are very fussy around the edges. I'll stick with structured registers. Custom types and subtypes are vhdl's advantage. >>> P.S. - Can you provide an example where using unconstrained arrays >>> for port objects is better that using arrays constrained by generic >>> values? >>> >> Synthesis can't override the default generics on the top entity. >> However, I'm not sure that a wrapper is less trouble. > > That doesn't answer my question, as generics are still a better choice > in this case, because you can't even synthesize (or simulate for that > matter) unconstrained arrays. Like I said, I agree with that, but top generics are a synthesis annoyance nevertheless. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!v1g2000prd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 09:08:30 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> References: <49f6a90a$0$27925$426a74cc@news.free.fr> <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240934910 25224 127.0.0.1 (28 Apr 2009 16:08:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Apr 2009 16:08:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v1g2000prd.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1001 A couple of my own thoughts on this. First, I applaud the use of recursion! Yes we still design hardware, but at some point we have to move on from coding netlists of gates and flops, just like SW progressed from assembly code through higher and higher levels of abstraction. I usually code the simplest description of the behavior I can come up with, and then, only if the synthesis tool cannot meet timing/area/power/etc. will I try a harder-to-read/ write/understand description that the synthesis tool may like better. Use of unconstrained std_logic_vector on ports: I like it, but... since the ports must be constrained by an upper level signal or port, then by definition, this is not a primary (device level port), and there is absolutely no need to hobble oneself with SLV ports when integer, unsigned or something else will work better. Non-SL/SLV primary ports are only a "bad thing" if you want/need to be able to simulate a post-synthesis or post-P&R netlist without a wrapper to convert the tool-generated SL/SLV ports back to whatever your test bench (written for the original RTL description/ports) expects. To my way of thinking, SLV should only be used when a uniform numerical interpretation of the contents is not appropriate. If I'll write When I do have to use SLV, I usually throw in a subtype definition: subtype slv is std_logic_vector; -- unconstrained subtype This way, "slv" can be used for signal/variable declarations and conversions instead of "std_logic_vector". Finally, the table array effectively constrains the input size to 31 bits (maximum width of the table index) anyway. Andy From newsfish@newsfish Wed Aug 19 13:24:24 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 14:22:13 -0700 Lines: 23 Message-ID: <75pac6F19o6odU1@mid.individual.net> References: <49f6a90a$0$27925$426a74cc@news.free.fr> <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net i3sqrgyrQEDTUlYga7ft4gk12cMbUMW8g9ODR/jw0rz2yV1SeA Cancel-Lock: sha1:I/yCBQLYQGNRPeMLRnCKpaNM/7M= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1002 Andy wrote: > I usually code the simplest description > of the behavior I can come up with, and then, only if the synthesis > tool cannot meet timing/area/power/etc. will I try a harder-to-read/ > write/understand description that the synthesis tool may like better. Yes. Why generate half adders, if c := a + b; works just as well. > Use of unconstrained std_logic_vector on ports: I like it, but... > since the ports must be constrained by an upper level signal or port, > then by definition, this is not a primary (device level port), and > there is absolutely no need to hobble oneself with SLV ports when > integer, unsigned or something else will work better. That's the main point. For registers inside the top wrapper, synthesis can keep track of the bit encoding. If want an enumerated array of signed counters, let it be. For device pins, explicit SLVs make sense for verilog compatibility. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!i28g2000prd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Tue, 28 Apr 2009 16:51:21 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <0a235949-6a1e-49dd-9b9e-8354cd4e3acf@i28g2000prd.googlegroups.com> References: <49f6a90a$0$27925$426a74cc@news.free.fr> <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1240962681 16617 127.0.0.1 (28 Apr 2009 23:51:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Apr 2009 23:51:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000prd.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1003 More comments: The function call notation trick for the multiply is not a good idea, especially when numeric_std provides a resize() function that also warns when the numeric value is truncated: res := resize(d * fact(d-1), res'range); More readable & more functional. I'm not crazy about widespread use of one-liner flops, but in limited doses they work well. Andy From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp7-1.free.fr!not-for-mail Subject: Re: Advanced use of VHDL - Factorial example From: Bert_Paris References: <49f6a90a$0$27925$426a74cc@news.free.fr> <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> <0a235949-6a1e-49dd-9b9e-8354cd4e3acf@i28g2000prd.googlegroups.com> Newsgroups: comp.lang.vhdl Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Wed, 29 Apr 2009 09:25:28 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 28 Message-ID: <49f800e9$0$21817$426a74cc@news.free.fr> NNTP-Posting-Date: 29 Apr 2009 09:25:29 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1240989929 news-2.free.fr 21817 82.66.120.181:3020 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:1004 Andy wrote : > The function call notation trick for the multiply is not a good idea, > especially when numeric_std provides a resize() function that also > warns when the numeric value is truncated: > > res := resize(d * fact(d-1), res'range); > > More readable & more functional. Thanks for the comments ! In this specific case, you're absolutely right. I will mention this in a revised version. I always recommend using resize for the benefit of being warned during simulation, and I could have applied it here. I think the function notation trick is still useful to know (like for just extracting a slice "in the middle" of a vector, or for testing the carry only, etc). > I'm not crazy about widespread use of one-liner flops, but in limited > doses they work well. I use them essentially for resynch (especially when no reset). I don't think using a process in this case enhances the readability. Bert From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Wed, 29 Apr 2009 11:56:11 -0700 Lines: 13 Message-ID: <75rm6cF18p0t8U1@mid.individual.net> References: <49f6a90a$0$27925$426a74cc@news.free.fr> <6004390c1e46b8cb95c16806c4ec@news.acm.uiuc.edu> <0a1b1908-c938-4772-92eb-5b46f74d20d4@v1g2000prd.googlegroups.com> <0a235949-6a1e-49dd-9b9e-8354cd4e3acf@i28g2000prd.googlegroups.com> <49f800e9$0$21817$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net IJJRaLG6v3D0AMRsTDu0LwkwKoDr2kUm17KR/18KaKGI0jpoFT Cancel-Lock: sha1:MxuNO+I01Z9PPs4LUaxun5hPTng= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <49f800e9$0$21817$426a74cc@news.free.fr> Xref: news.eternal-september.org comp.lang.vhdl:1005 > Andy wrote : >> I'm not crazy about widespread use of one-liner flops, but in limited >> doses they work well. Bert_Paris wrote: > I use them essentially for resynch (especially when no reset). > I don't think using a process in this case enhances the readability. Maybe not, but it might enhance maintainability when I add a feature or a reset. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!v35g2000pro.googlegroups.com!not-for-mail From: Massi Newsgroups: comp.lang.vhdl Subject: Simple question about hexadecimal values Date: Wed, 29 Apr 2009 01:55:00 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <52542cfd-e0d6-4b53-8ef9-d836b95a9909@v35g2000pro.googlegroups.com> NNTP-Posting-Host: 150.145.11.89 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241042804 16742 127.0.0.1 (29 Apr 2009 22:06:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Apr 2009 22:06:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v35g2000pro.googlegroups.com; posting-host=150.145.11.89; posting-account=WWUlQQoAAAA7X1fJ_0M7jreoB5ymf0dg User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1006 Hi everyone...another newbie question, I'm writing a testbench to send different address to my unit under test.Each address is compute starting from a base address (say for example a 32 bit address like X"10000400"). The piece of code which doesn't work is the following: for i in 0 to 10 loop temp := i*4+X"10000400"; address_in_sig <= std_logic_vector(to_unsigned(temp, 32)); -- Send the address to the UUT and verify the output... end loop; If I replace X"10000400" with the corresponding unsigned value everything works, but I wonder which is the right way to code it using the hexadecima value (which is more readable than 268436480...). Thanks in advance for your help! From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 29 Apr 2009 17:11:33 -0500 Date: Wed, 29 Apr 2009 15:11:39 -0700 From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Simple question about hexadecimal values Message-ID: <20090429151139.000068fb@unknown> References: <52542cfd-e0d6-4b53-8ef9-d836b95a9909@v35g2000pro.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-l7m00PKYzoCVU5QZ9HVFRuk7A2pBKYyJwsUPlxnowFcG+roA/bQhkBEcwkWBs2z/fkrunp5Owf0fAhc!00MrTPKLZU4ajWziNY9XWZ4+aHQWVB2eHr/Yq5iCj0Eu+9cmU4PMBv1hvmtPFjM9DA== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1007 On Wed, 29 Apr 2009 01:55:00 -0700 (PDT) Massi wrote: > Hi everyone...another newbie question, I'm writing a testbench to send > different address to my unit under test.Each address is compute > starting from a base address (say for example a 32 bit address like > X"10000400"). The piece of code which doesn't work is the following: > > for i in 0 to 10 loop > temp := i*4+X"10000400"; > address_in_sig <= std_logic_vector(to_unsigned(temp, 32)); > -- Send the address to the UUT and verify the output... > end loop; > > If I replace X"10000400" with the corresponding unsigned value > everything works, but I wonder which is the right way to code it using > the hexadecima value (which is more readable than 268436480...). > Thanks in advance for your help! While you're not clear, I'm assuming that your variable temp is defined as an integer. In that case: temp := i*4 + 16#10000400# -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!y33g2000prg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Defining Stimulus type and encapsulating parameters Date: Wed, 29 Apr 2009 08:12:01 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241043526 20092 127.0.0.1 (29 Apr 2009 22:18:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Apr 2009 22:18:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y33g2000prg.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1008 I have the following type I can use in testbenches, normally as a generic: type stimulus_type is (random, count, from_file) following the generic, I have to have other generics like: RANDOM_SEED, COUNT_FROM, FILE_PATH that define how the stimulus is constrained. But these generics have to always be present and given some value, even if they are not used. Annoyingly, I have to have these 3 secondary generics for each ip stimulus. Would there be a more clever way of doing it to encapsulate the parameters better, via subtyped records or something (if thats even allowed) where I could do something like: generic ( IP_A_STIM : stimulus_type := (type => from_file, filepath => "c:\data \some_data"); IP_B_STIM : stimulus_type := (type => random, seed => 12345); ....etc ); This would probably make it difficult, if not impossible to override the generic via TCL when you call VSIM, but I thought it was an interesting thought experiment. I cant think how Id even start - parsing it might fail as the types wouldnt be the same. Anyone else with some clever ideas? From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!f41g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Simple question about hexadecimal values Date: Wed, 29 Apr 2009 15:42:02 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <73c8f22f-865b-4720-b81d-450504afeb94@f41g2000pra.googlegroups.com> References: <52542cfd-e0d6-4b53-8ef9-d836b95a9909@v35g2000pro.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241044922 6793 127.0.0.1 (29 Apr 2009 22:42:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Apr 2009 22:42:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f41g2000pra.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1009 Massi, > Hi everyone...another newbie question, I'm writing a testbench to send > different address to my unit under test.Each address is compute > starting from a base address (say for example a 32 bit address like > X"10000400"). The piece of code which doesn't work is the following: > > for i in 0 to 10 loop > =A0 =A0 =A0 =A0 temp :=3D i*4+X"10000400"; > =A0 =A0 =A0 =A0 address_in_sig <=3D std_logic_vector(to_unsigned(temp, 32= )); > =A0 =A0 =A0 =A0 -- Send the address to the UUT and verify the output... > end loop; If I were feeling lazy I would do the following: use ieee.std_logic_unsigned.all ; address_in_sig <=3D i*4 + X"10000400" ; On the other hand, if you feel the need to avoid this package, you can do the following: use ieee.numeric_std.all ; . . . signal address_in_sig_uv : unsigned (31 downto 0) ; . . . address_in_sig_uv <=3D i*4 + X"10000400" ; Then do a type conversion in the port map: U_comp1 : comp1 port map ( address_port =3D> std_logic_vector(address_in_sig_uv), . . . ) ; Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Wed, 29 Apr 2009 16:45:10 -0700 Lines: 16 Message-ID: <75s748F19e63hU1@mid.individual.net> References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net mforWUQ+sroNyfpnLRubMwqBwI7ag/ORMv2x1LKKkoaT9IcZtm Cancel-Lock: sha1:DppECS3MKLStAyiI0IRgU9KNPKM= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1010 Tricky wrote: > This would probably make it difficult, if not impossible to override > the generic via TCL when you call VSIM, but I thought it was an > interesting thought experiment. My brain is too tired for such an experiment. I put canned data into the testbench package as some constant structure. The generic could just be an index the defaults to the simplest version. If the stim data is computable, I generate the constants in the testbench using a vhdl function. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:25 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v1g2000prd.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 30 Apr 2009 00:43:34 -0700 (PDT) Organization: http://groups.google.com Lines: 125 Message-ID: <2e7d3368-2e8a-482e-a57c-892de7168d84@v1g2000prd.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> NNTP-Posting-Host: 93.37.211.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241077414 13621 127.0.0.1 (30 Apr 2009 07:43:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 07:43:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v1g2000prd.googlegroups.com; posting-host=93.37.211.36; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1011 On 28 Apr, 15:28, Tricky wrote: > On 28 Apr, 14:01, Dek wrote: > > > > > > > On 25 Apr, 02:21, "KJ" wrote: > > > > > I think I can't do anything better, because I have to simulate how = an > > > > FPGA would work on data coming from a detector, that are already > > > > stored in many .txt files. > > > > One could ask how did those files get created in the first place. =A0= Unless > > > they were generated from an actual detector, then they were artificia= lly > > > generated in the first place. =A0Rather than artificially generating = data into > > > text files and then figuring out how to read them into a testbench it= is > > > much more productive to model the detector in the VHDL testbench and = totally > > > bypass file I/O (which is not really one of VHDL's strengths). > > > > But I'll assume though that you have to work with file I/O. > > > > > Now the problem is that such files are thousands and it takes a lot= of > > > > time to change manually their name in vhdl code. One idea is to use > > > > Generics, name all data files in a "name.do" file and use "do name.= do" > > > > command. Even in this case, however, I have to name files manually = one > > > > by one. > > > > Not really. =A0The name.do file can be easily created with a simple d= irectory > > > listing command > > > (Windows command line "dir /b >name.do"). =A0That's pretty easy to do= . > > > > > Do you know if there is a way to read all files in a folder > > > > without nameing them? > > > > I don't. > > > > > The same problem, unfortunately, is for writing, since for each in- > > > > file I have to write one out-file. > > > > Once you've read in a line from 'name.do' you've got a unique input f= ile > > > name. =A0I would construct a similarly unique output file name by mod= ifying > > > the input file name in some fashion (say by appending ".out" to the i= nput > > > file name). > > > > Kevin Jennings > > > Ok, I'll definitively thank this group in my thesis! Your idea seems > > to work, but there is still a little problem: > > > the name are of different length! If i do like this: > > ----------------------------------------------- > > Architecture... > > Begin > > process > > =A0 =A0 VARIABLE filename : String (23 downto 1); > > ----------------------------------------------- > > it works until it find a filename of lenght different from 23. > > > I tried to do something like this: > > VARIABLE filename : String; > > or > > VARIABLE filename : String (natural range<>); > > but I always get an error message. > > Have any suggestion? > > > Thanks > > > Dek > > I assume you are reading the string from a line? well, a line is > actually a pointer to a string. > > So, assuming you just have 1 filename per line, you can do something > like: > > readline(namefile, inline); > > FILE_OPEN(f, inline.all, READ_MODE); > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > You could do the same if its not just 1 file name per line, but the > parsing would get more complicated. But the method above means you can > have filenames as long as you want.- Nascondi testo citato > > - Mostra testo citato - Sorry but I didn't get what you mean; When I use the deallocate command don't I lose all informations pointed by infile? If I understood right the deallocate command serves to free memory, so if I write : DEALLOCATE(inline); I will free the memory block used to store the contents of infile; how can I find the same contents in a string whose lenght is not constrained? Another question: is there a command to know the lenght of a line? Because I could do so: READFILE (infile, inline); int :=3D LENGHT (inline); -- int already defined as an integer than i could continue with an IF clause. Unfortunately LENGHT is not the right keyword. Thanks again From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 30 Apr 2009 00:45:15 -0700 (PDT) Organization: http://groups.google.com Lines: 132 Message-ID: <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> NNTP-Posting-Host: 93.37.211.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241077515 14093 127.0.0.1 (30 Apr 2009 07:45:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 07:45:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=93.37.211.36; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1012 On 28 Apr, 15:28, Tricky wrote: > On 28 Apr, 14:01, Dek wrote: > > > > > > > On 25 Apr, 02:21, "KJ" wrote: > > > > > I think I can't do anything better, because I have to simulate how = an > > > > FPGA would work on data coming from a detector, that are already > > > > stored in many .txt files. > > > > One could ask how did those files get created in the first place. =A0= Unless > > > they were generated from an actual detector, then they were artificia= lly > > > generated in the first place. =A0Rather than artificially generating = data into > > > text files and then figuring out how to read them into a testbench it= is > > > much more productive to model the detector in the VHDL testbench and = totally > > > bypass file I/O (which is not really one of VHDL's strengths). > > > > But I'll assume though that you have to work with file I/O. > > > > > Now the problem is that such files are thousands and it takes a lot= of > > > > time to change manually their name in vhdl code. One idea is to use > > > > Generics, name all data files in a "name.do" file and use "do name.= do" > > > > command. Even in this case, however, I have to name files manually = one > > > > by one. > > > > Not really. =A0The name.do file can be easily created with a simple d= irectory > > > listing command > > > (Windows command line "dir /b >name.do"). =A0That's pretty easy to do= . > > > > > Do you know if there is a way to read all files in a folder > > > > without nameing them? > > > > I don't. > > > > > The same problem, unfortunately, is for writing, since for each in- > > > > file I have to write one out-file. > > > > Once you've read in a line from 'name.do' you've got a unique input f= ile > > > name. =A0I would construct a similarly unique output file name by mod= ifying > > > the input file name in some fashion (say by appending ".out" to the i= nput > > > file name). > > > > Kevin Jennings > > > Ok, I'll definitively thank this group in my thesis! Your idea seems > > to work, but there is still a little problem: > > > the name are of different length! If i do like this: > > ----------------------------------------------- > > Architecture... > > Begin > > process > > =A0 =A0 VARIABLE filename : String (23 downto 1); > > ----------------------------------------------- > > it works until it find a filename of lenght different from 23. > > > I tried to do something like this: > > VARIABLE filename : String; > > or > > VARIABLE filename : String (natural range<>); > > but I always get an error message. > > Have any suggestion? > > > Thanks > > > Dek > > I assume you are reading the string from a line? well, a line is > actually a pointer to a string. > > So, assuming you just have 1 filename per line, you can do something > like: > > readline(namefile, inline); > > FILE_OPEN(f, inline.all, READ_MODE); > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > You could do the same if its not just 1 file name per line, but the > parsing would get more complicated. But the method above means you can > have filenames as long as you want.- Nascondi testo citato > > - Mostra testo citato - Sorry but I didn't get what you mean; When I use the deallocate command don't I lose all informations pointed by inline? If I understood right the deallocate command serves to free memory, so if I write : DEALLOCATE(inline); I will free the memory block used to store the contents of infile; how can I find the same contents in a string whose lenght is not constrained? Another question: is there a command to know the lenght of a line? Because I could do so: READFILE (infile, inline); int :=3D LENGHT (inline); -- int already defined as an integer than i could continue with an IF clause. Unfortunately LENGHT is not the right keyword. Thanks again From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 30 Apr 2009 03:22:36 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 09:20:16 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <1tmiv4prsrdft1gotcnc11cj55958nf202@4ax.com> References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 94 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Nt5H8PFVvPHUyL/s9RpPUAXG7qOgAwEbYlrbE3SAuHPcp3vNNJBw2isKavwerbKj1TQV1/Mdw88rfg6!U+Nlvboo1MCT9/5ptTXISbu/9Pvv8APxumKiiDj9j95OhoLerbukrTVGwIQ5rEr2/vUBQF7pkrbC!/GZt X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 4286 Xref: news.eternal-september.org comp.lang.vhdl:1013 On Wed, 29 Apr 2009 08:12:01 -0700 (PDT), Tricky wrote: >I have the following type I can use in testbenches, normally as a >generic: > >type stimulus_type is (random, count, from_file) > >following the generic, I have to have other generics like: >RANDOM_SEED, COUNT_FROM, FILE_PATH that define how the stimulus is >constrained. But these generics have to always be present and given >some value, even if they are not used. Annoyingly, I have to have >these 3 secondary generics for each ip stimulus. > >Would there be a more clever way of doing it to encapsulate the >parameters better, via subtyped records or something Interesting question. VHDL doesn't have any notion of variant types, so that's out. But I think your records idea, together with Mike's point about using functions, would cut it. 1) Make a record with all the possibilities in it (in a package, of course): type t_stim_control is record kind: stinulus_type; -- (random, count, from_file) random_seed: integer; count_from: integer; file_path: string (1 to 100); -- sadly this must be constrained end record; 2) Make a function that constructs one of these from arguments, but has defaults on most of the args, also in the package: function stim_control ( kind: stinulus_type ; random_seed: integer := 1 ; count_from: integer := 0 ; file_path: string := "" ) return t_stim_control is variable SC: t_stim_control; begin SC.kind := kind; -- other elements default-initialise case kind is random => SC.random_seed := random_seed; count => SC.count_from := count_from; from_file => file_path := str_pad(file_path, 100); default => null; endcase; return SC; end; 3) Now you can patch-up your generics nicely, specifying only the fields you care about: test1: entity work.test_widget generic map ( stim_control ( kind => random, random_seed => 42 ) ); test2: entity work.test_widget generic map ( stim_control ( kind => from_file, file_path => "stuff.txt" ) ); You'll need to create the "str_pad" function to convert the function argument's unconstrained string into a suitable constrained string to fit in the record - I reckon you're OK with that! One nice aspect of this is that, if you add more new stuff to the record, you will need to update the "stim_control" function but all your other existing code will still be backward-compatible with the new definitions. Hope this helps -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!y10g2000prc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 02:38:26 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <1125c227-35c2-4693-8b96-41dba50d4afc@y10g2000prc.googlegroups.com> References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <1tmiv4prsrdft1gotcnc11cj55958nf202@4ax.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241084306 2493 127.0.0.1 (30 Apr 2009 09:38:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 09:38:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y10g2000prc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1014 > > =A0 type t_stim_control is record > =A0 =A0 kind: stinulus_type; -- (random, count, from_file) > =A0 =A0 random_seed: integer; > =A0 =A0 count_from: =A0integer; > =A0 =A0 file_path: string (1 to 100); =A0-- sadly this must be constraine= d > =A0 end record; Am I right in thinking with VHDL-2008 standard, when its fully adopted in 2018, would remove this constraining restriction, allowing the function to return the record with the given constant string defining the length? Another question, how am I going to now override this function call via the VSIM -gGENERIC=3Dstuff call in TCL? my knowledge of TCL extends to calling VLIB, VMAP, VCOM and VSIM, though willing to learn/see some more clever stuff. Thanks for the help, I think ill borrow this into my Testbench_tools_package. :) Richard From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe29.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <1tmiv4prsrdft1gotcnc11cj55958nf202@4ax.com> <1125c227-35c2-4693-8b96-41dba50d4afc@y10g2000prc.googlegroups.com> Subject: Re: Defining Stimulus type and encapsulating parameters Lines: 36 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe29.ams2 1241085732 86.16.123.60 (Thu, 30 Apr 2009 10:02:12 UTC) NNTP-Posting-Date: Thu, 30 Apr 2009 10:02:12 UTC Organization: virginmedia.com Date: Thu, 30 Apr 2009 11:02:06 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1015 "Tricky" wrote in message news:1125c227-35c2-4693-8b96-41dba50d4afc@y10g2000prc.googlegroups.com... >> >> type t_stim_control is record >> kind: stinulus_type; -- (random, count, from_file) >> random_seed: integer; >> count_from: integer; >> file_path: string (1 to 100); -- sadly this must be constrained >> end record; > >Am I right in thinking with VHDL-2008 standard, when its fully adopted >in 2018, I am hoping for 2017 but then again I am an optimist :-) > would remove this constraining restriction, allowing the >function to return the record with the given constant string defining >the length? Not sure if it is answering your question but VHDL2008 allow type generics and generics on packages, >Another question, how am I going to now override this function call >via the VSIM -gGENERIC=stuff call in TCL? my knowledge of TCL extends >to calling VLIB, VMAP, VCOM and VSIM, though willing to learn/see some >more clever stuff. As a minimum I would learn 3 extra Modelsim Tcl commands, force, examine and when Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u9g2000pre.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 30 Apr 2009 03:56:52 -0700 (PDT) Organization: http://groups.google.com Lines: 138 Message-ID: <3b03d737-0722-4773-85d3-a28a205c0eec@u9g2000pre.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> NNTP-Posting-Host: 93.37.195.38 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241089012 16961 127.0.0.1 (30 Apr 2009 10:56:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 10:56:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u9g2000pre.googlegroups.com; posting-host=93.37.195.38; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1016 On 30 Apr, 09:45, Dek wrote: > On 28 Apr, 15:28, Tricky wrote: > > > > > > > On 28 Apr, 14:01, Dek wrote: > > > > On 25 Apr, 02:21, "KJ" wrote: > > > > > > I think I can't do anything better, because I have to simulate ho= w an > > > > > FPGA would work on data coming from a detector, that are already > > > > > stored in many .txt files. > > > > > One could ask how did those files get created in the first place. = =A0Unless > > > > they were generated from an actual detector, then they were artific= ially > > > > generated in the first place. =A0Rather than artificially generatin= g data into > > > > text files and then figuring out how to read them into a testbench = it is > > > > much more productive to model the detector in the VHDL testbench an= d totally > > > > bypass file I/O (which is not really one of VHDL's strengths). > > > > > But I'll assume though that you have to work with file I/O. > > > > > > Now the problem is that such files are thousands and it takes a l= ot of > > > > > time to change manually their name in vhdl code. One idea is to u= se > > > > > Generics, name all data files in a "name.do" file and use "do nam= e.do" > > > > > command. Even in this case, however, I have to name files manuall= y one > > > > > by one. > > > > > Not really. =A0The name.do file can be easily created with a simple= directory > > > > listing command > > > > (Windows command line "dir /b >name.do"). =A0That's pretty easy to = do. > > > > > > Do you know if there is a way to read all files in a folder > > > > > without nameing them? > > > > > I don't. > > > > > > The same problem, unfortunately, is for writing, since for each i= n- > > > > > file I have to write one out-file. > > > > > Once you've read in a line from 'name.do' you've got a unique input= file > > > > name. =A0I would construct a similarly unique output file name by m= odifying > > > > the input file name in some fashion (say by appending ".out" to the= input > > > > file name). > > > > > Kevin Jennings > > > > Ok, I'll definitively thank this group in my thesis! Your idea seems > > > to work, but there is still a little problem: > > > > the name are of different length! If i do like this: > > > ----------------------------------------------- > > > Architecture... > > > Begin > > > process > > > =A0 =A0 VARIABLE filename : String (23 downto 1); > > > ----------------------------------------------- > > > it works until it find a filename of lenght different from 23. > > > > I tried to do something like this: > > > VARIABLE filename : String; > > > or > > > VARIABLE filename : String (natural range<>); > > > but I always get an error message. > > > Have any suggestion? > > > > Thanks > > > > Dek > > > I assume you are reading the string from a line? well, a line is > > actually a pointer to a string. > > > So, assuming you just have 1 filename per line, you can do something > > like: > > > readline(namefile, inline); > > > FILE_OPEN(f, inline.all, READ_MODE); > > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > > You could do the same if its not just 1 file name per line, but the > > parsing would get more complicated. But the method above means you can > > have filenames as long as you want.- Nascondi testo citato > > > - Mostra testo citato - > > Sorry but I didn't get what you mean; When I use the deallocate > command don't I lose all informations pointed by inline? If I > understood right the deallocate command serves to free memory, so if > I > write : > > DEALLOCATE(inline); > > I will free the memory block used to store the contents of infile; > how > can I find the same contents in a string whose lenght is not > constrained? > > Another question: is there a command to know the lenght of a line? > Because I could do so: > > READFILE (infile, inline); > int :=3D LENGHT (inline); =A0-- int already defined as an integer > > than i could continue with an IF clause. Unfortunately LENGHT is not > the right keyword. > > Thanks again- Nascondi testo citato > > - Mostra testo citato - Ok found the right command: int :=3D inline'Length; Bye! From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 30 Apr 2009 05:58:57 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 11:56:36 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <1tmiv4prsrdft1gotcnc11cj55958nf202@4ax.com> <1125c227-35c2-4693-8b96-41dba50d4afc@y10g2000prc.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 37 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-IeKf0Y8v7SwT51IHWKHkysKu5Bl8u3Fy27XCLX+mDpqtFxqBbIOaE0wX3y76OP3iijXSY3GlJ0fJl2/!Gv55eB39vJ9PB/LqNEOhq/jkQpgEJRw8tT7bPmvWzCht4zX76qXWthlvx4deFON0prjbo8jEeiq1!7rDe X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2586 Xref: news.eternal-september.org comp.lang.vhdl:1017 On Thu, 30 Apr 2009 02:38:26 -0700 (PDT), Tricky wrote: > >> >>   type t_stim_control is record >>     kind: stinulus_type; -- (random, count, from_file) >>     random_seed: integer; >>     count_from:  integer; >>     file_path: string (1 to 100);  -- sadly this must be constrained >>   end record; > >Am I right in thinking with VHDL-2008 standard, when its fully adopted >in 2018, would remove this constraining restriction, allowing the >function to return the record with the given constant string defining >the length? I believe that's correct; Jim Lewis or Alan Fitch will be more authoritative though. I've somewhat ignored VHDL-2008, having been overly occupied with SystemVerilog :-( >Another question, how am I going to now override this function call >via the VSIM -gGENERIC=stuff call in TCL? Oh £$%^&*, that blows it: you can't set record generics from the ModelSim command line. Grrrr. Sorry. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!nx02.iad01.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 30 Apr 2009 07:26:42 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 13:24:20 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 93 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-GgrVjpt9lSLtKDZi6rqAXcZGl9CbAWfxyzARyLJ6wD3pyoFnaoi2fa4Z3p1oIXB62joUBPzYnQye+EO!310BQ4cOolIxt0/bXs/E88LbLwUv2+H4zhC9Onoc0IL0dRe3V0b2bsGa7c4qSW5OlP4JSXOOeLdq!3lDP X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 4407 Xref: news.eternal-september.org comp.lang.vhdl:1018 On Wed, 29 Apr 2009 08:12:01 -0700 (PDT), Tricky wrote: >generic: > >type stimulus_type is (random, count, from_file) > >following the generic, I have to have other generics like: >RANDOM_SEED, COUNT_FROM, FILE_PATH that define how the stimulus is >constrained. But these generics have to always be present and given >some value, even if they are not used. Annoyingly, I have to have >these 3 secondary generics for each ip stimulus. It suddenly occurred to me: WHY do you need to provide them all? Why not give them all default values? You could easily arrange that the default was a sufficiently silly value that it could be regarded as an error if it _were_ needed. And then you can override only the generics you actually need. entity TB_TOP is generic ( kind: stimulus_type -- no default ; random_seed : integer := 0 ; count_from : integer := integer'low -- silly value ; file_path : string := "" -- silly value ); ... Now it's OK to do.... test1: entity work.TB_TOP generic map (kind => count, count_from => 1); -- don't bother to override other generics But I guess you've thought of that, and have a specific reason why you don't want it??? Anyway, having done that, I suggest that you would then do something like this inside the entity's architecture: architecture STUFF of TB_TOP is ... function validate_generics return boolean is -- Returns TRUE if all is OK, FALSE if any problem. -- Gives information on all known problems, -- using warning-level reports, before returning. begin report "Running test in " & stimulus_type'image(kind) & " mode"; case kind is when random => if random_seed <= 0 then report "random_seed must be positive!" severity warning; -- NOT error or failure!!!!! return false; end if; when count => if count_from = integer'low report "count_from must be overridden!" severity warning; return false; end if; ... and so on end case; return true; -- if everything was OK end; Note that the function only yields NOTE and WARNING reports, so that you don't kill off the sim just yet - you want as much diagnostic info as you can get, even in error conditions. But then you can put the whole function into an ASSERT: ... begin -- the testbench architecture assert validate_generics -- runs the function at time 0 report "INVALID CONFIGURATION - Review previous warnings" severity FAILURE; ... I quite like this technique - it gives lots of useful config checking and diagnostics, and then halts the sim if it's wrong. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z16g2000prd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 06:29:13 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <628368fa-8dd6-4dc1-8f94-241cf78f3e4e@z16g2000prd.googlegroups.com> References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241098153 12895 127.0.0.1 (30 Apr 2009 13:29:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 13:29:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z16g2000prd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1019 > > But I guess you've thought of that, and have a specific > reason why you don't want it??? > Actually I didnt really think of that - I was coming at this from the POV of someone else being presented with the TB and then being overwhelmed with setup generics, but actually what I didnt consider was that they are more likely to run it from a TCL script, so this second method makes ALOT more sense. Ill still keep the first function in the tool package though - might be useful one day :) From newsfish@newsfish Wed Aug 19 13:24:26 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!q33g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 08:14:06 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <628368fa-8dd6-4dc1-8f94-241cf78f3e4e@z16g2000prd.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241104446 30930 127.0.0.1 (30 Apr 2009 15:14:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 15:14:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q33g2000pra.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1020 Tricky, Since Jonathan has already thrown several stones at your problem, first I will comment. WRT using records such as, "type t_stim_control is record": I use these for dynamic controls and make them signals. This way if I can switch between configurations of my UARTs during a given test and I don't have to have separate test cases for it. Note you have to use appropriate synchronization when switching between different configurations. I like the initialized generics approach and use this frequently. Since your switching is static, you could also use separate architectures for the random and from_file. This adds some complexity WRT controlling it from a simulation. I typically use a configuration. With a configuration, I can select the architecture and map any generics that need to be mapped or re-mapped. Typically I will leave the generics off the component and have them only on the entity - this means I can only map them in the configuration. This also means that each entity only needs the generics that it uses. Alternately you could put the entire set of generics on each entity and the component, but this seems like lots of busy work. Configurations seem to add some complexity to running your testbench, but at the end of the day (or project) when you need to run regressions, all this information is either specified in a configuration or in your simulation run script with command line generics. Configurations allow you to do this in a organized, language standard fashion. They also allow you to reach down levels of hierarchy, so there is no need to pass generics through the hierarchy to get access to them - so I only do this when there is a logical, encapsulation reason to do this. With that said, the fine print would also say that I don't do everything with configurations. For example, I select between the gate and rtl versions of my design by using default binding (most recently compiled architecture). Otherwise, you quickly double the number of configurations you need. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!u9g2000pre.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 08:50:58 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <1tmiv4prsrdft1gotcnc11cj55958nf202@4ax.com> <1125c227-35c2-4693-8b96-41dba50d4afc@y10g2000prc.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241106658 7103 127.0.0.1 (30 Apr 2009 15:50:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 15:50:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u9g2000pre.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1021 Richard, > > =A0 type t_stim_control is record > > =A0 =A0 kind: stinulus_type; -- (random, count, from_file) > > =A0 =A0 random_seed: integer; > > =A0 =A0 count_from: =A0integer; > > =A0 =A0 file_path: string (1 to 100); =A0-- sadly this must be constrai= ned > > =A0 end record; > > Am I right in thinking with VHDL-2008 standard, when its fully adopted > in 2018, would remove this constraining restriction, allowing the > function to return the record with the given constant string defining > the length? Yes and that works within the function, however, the object to which you assign the value to must know the size. OTOH, a protected type with internal variables does this very well. Unfortunately shared variables cannot currently be design ports. For now that means putting them in a package and dealing with issues if you have multiple instances of the same component - the same issues as putting a record signal in a package. In VHDL-2008 an interesting option that becomes available is define the shared variable within the BFM that needs to be configured and access the shared variable using a hierarchical reference. > Another question, how am I going to now override this function call > via the VSIM -gGENERIC=3Dstuff call in TCL? my knowledge of TCL extends > to calling VLIB, VMAP, VCOM and VSIM, though willing to learn/see some > more clever stuff. You can avoid the command line switches by using a VHDL configuration :) Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j18g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Defining Stimulus type and encapsulating parameters Date: Thu, 30 Apr 2009 10:53:46 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: References: <205e0b0e-968e-4ede-b2ed-1a06928e9bf4@y33g2000prg.googlegroups.com> <628368fa-8dd6-4dc1-8f94-241cf78f3e4e@z16g2000prd.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241114026 29913 127.0.0.1 (30 Apr 2009 17:53:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Apr 2009 17:53:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prm.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1022 I like to use a package to define a record with fields for all the different generics I might need. Then I pass that record down through the hierarchy as a generic on every entity (you can use sub-records for sub-levels of hierarchy if you want). This gives me a language- defined way (works on any simulator or synthesis tool) to manage generics in an easy way. If you need to add a generic for a lower- level entity, just add it to the record, define it at the top, and extract the value only where it is needed. The record is just a modifiable conduit through which you can pass anything that you want down through the hierarchy, without having to manually plumb it through each intervening level of the hierarchy. The value of the record generic can be defined at the top level, or defined in a package, or set by a top-level generic index into an array of such records defined in a package. I like to avoid the maintenance headaches of configurations and component declarations. What I really want is to use records as signal ports, but with user defined modes for each element (a single record port consisting of in, out & inout sub-ports). That way you could use the same "conduit" technique to pass an entire interface up and down through multiple levels of hierarchy easily. Andy From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!r31g2000prh.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Fri, 1 May 2009 08:58:36 -0700 (PDT) Organization: http://groups.google.com Lines: 141 Message-ID: <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241193516 30934 127.0.0.1 (1 May 2009 15:58:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 May 2009 15:58:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r31g2000prh.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1023 On 30 Apr, 08:45, Dek wrote: > On 28 Apr, 15:28, Tricky wrote: > > > > > On 28 Apr, 14:01, Dek wrote: > > > > On 25 Apr, 02:21, "KJ" wrote: > > > > > > I think I can't do anything better, because I have to simulate ho= w an > > > > > FPGA would work on data coming from a detector, that are already > > > > > stored in many .txt files. > > > > > One could ask how did those files get created in the first place. = =A0Unless > > > > they were generated from an actual detector, then they were artific= ially > > > > generated in the first place. =A0Rather than artificially generatin= g data into > > > > text files and then figuring out how to read them into a testbench = it is > > > > much more productive to model the detector in the VHDL testbench an= d totally > > > > bypass file I/O (which is not really one of VHDL's strengths). > > > > > But I'll assume though that you have to work with file I/O. > > > > > > Now the problem is that such files are thousands and it takes a l= ot of > > > > > time to change manually their name in vhdl code. One idea is to u= se > > > > > Generics, name all data files in a "name.do" file and use "do nam= e.do" > > > > > command. Even in this case, however, I have to name files manuall= y one > > > > > by one. > > > > > Not really. =A0The name.do file can be easily created with a simple= directory > > > > listing command > > > > (Windows command line "dir /b >name.do"). =A0That's pretty easy to = do. > > > > > > Do you know if there is a way to read all files in a folder > > > > > without nameing them? > > > > > I don't. > > > > > > The same problem, unfortunately, is for writing, since for each i= n- > > > > > file I have to write one out-file. > > > > > Once you've read in a line from 'name.do' you've got a unique input= file > > > > name. =A0I would construct a similarly unique output file name by m= odifying > > > > the input file name in some fashion (say by appending ".out" to the= input > > > > file name). > > > > > Kevin Jennings > > > > Ok, I'll definitively thank this group in my thesis! Your idea seems > > > to work, but there is still a little problem: > > > > the name are of different length! If i do like this: > > > ----------------------------------------------- > > > Architecture... > > > Begin > > > process > > > =A0 =A0 VARIABLE filename : String (23 downto 1); > > > ----------------------------------------------- > > > it works until it find a filename of lenght different from 23. > > > > I tried to do something like this: > > > VARIABLE filename : String; > > > or > > > VARIABLE filename : String (natural range<>); > > > but I always get an error message. > > > Have any suggestion? > > > > Thanks > > > > Dek > > > I assume you are reading the string from a line? well, a line is > > actually a pointer to a string. > > > So, assuming you just have 1 filename per line, you can do something > > like: > > > readline(namefile, inline); > > > FILE_OPEN(f, inline.all, READ_MODE); > > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > > You could do the same if its not just 1 file name per line, but the > > parsing would get more complicated. But the method above means you can > > have filenames as long as you want.- Nascondi testo citato > > > - Mostra testo citato - > > Sorry but I didn't get what you mean; When I use the deallocate > command don't I lose all informations pointed by inline? If I > understood right the deallocate command serves to free memory, so if > I > write : > > DEALLOCATE(inline); > > I will free the memory block used to store the contents of infile; > how > can I find the same contents in a string whose lenght is not > constrained? > the READLINE function just copies the next line from the file into "inline". if you call DEALLOCATE(inline) you are just removing the pointer to the copy of the line, the file itself is unnaffected and the next call to readline will correctly read off the next line from the file. the previous example still stands. I was only using DEALLOCATE because I wasnt actually reading anything from the line, I was dereferencing the pointer with the inline.all call. if you dont deallocate it without reading all the data off it, the next readline call will just append the next line onto the end of whatever is left (and in my example, the whole line would be left) so the following example is still good, assuming you dont have anything else on the line other than the filename: readline(namefile, inline); FILE_OPEN(f, inline.all, READ_MODE); DEALLOCATE(inline); --drops the pointer the good thing about this method is you dont need to declare a string to read the data off "inline" and restrict it's length, you can just use the line itself, as the "line" type is just a pointer to a string. From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!r36g2000vbr.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Sun, 3 May 2009 08:22:30 -0700 (PDT) Organization: http://groups.google.com Lines: 189 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> NNTP-Posting-Host: 93.37.220.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241364150 17009 127.0.0.1 (3 May 2009 15:22:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 3 May 2009 15:22:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbr.googlegroups.com; posting-host=93.37.220.165; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1024 On 1 Mag, 17:58, Tricky wrote: > On 30 Apr, 08:45, Dek wrote: > > > > > > > On 28 Apr, 15:28, Tricky wrote: > > > > On 28 Apr, 14:01, Dek wrote: > > > > > On 25 Apr, 02:21, "KJ" wrote: > > > > > > > I think I can't do anything better, because I have to simulate = how an > > > > > > FPGA would work on data coming from a detector, that are alread= y > > > > > > stored in many .txt files. > > > > > > One could ask how did those files get created in the first place.= =A0Unless > > > > > they were generated from an actual detector, then they were artif= icially > > > > > generated in the first place. =A0Rather than artificially generat= ing data into > > > > > text files and then figuring out how to read them into a testbenc= h it is > > > > > much more productive to model the detector in the VHDL testbench = and totally > > > > > bypass file I/O (which is not really one of VHDL's strengths). > > > > > > But I'll assume though that you have to work with file I/O. > > > > > > > Now the problem is that such files are thousands and it takes a= lot of > > > > > > time to change manually their name in vhdl code. One idea is to= use > > > > > > Generics, name all data files in a "name.do" file and use "do n= ame.do" > > > > > > command. Even in this case, however, I have to name files manua= lly one > > > > > > by one. > > > > > > Not really. =A0The name.do file can be easily created with a simp= le directory > > > > > listing command > > > > > (Windows command line "dir /b >name.do"). =A0That's pretty easy t= o do. > > > > > > > Do you know if there is a way to read all files in a folder > > > > > > without nameing them? > > > > > > I don't. > > > > > > > The same problem, unfortunately, is for writing, since for each= in- > > > > > > file I have to write one out-file. > > > > > > Once you've read in a line from 'name.do' you've got a unique inp= ut file > > > > > name. =A0I would construct a similarly unique output file name by= modifying > > > > > the input file name in some fashion (say by appending ".out" to t= he input > > > > > file name). > > > > > > Kevin Jennings > > > > > Ok, I'll definitively thank this group in my thesis! Your idea seem= s > > > > to work, but there is still a little problem: > > > > > the name are of different length! If i do like this: > > > > ----------------------------------------------- > > > > Architecture... > > > > Begin > > > > process > > > > =A0 =A0 VARIABLE filename : String (23 downto 1); > > > > ----------------------------------------------- > > > > it works until it find a filename of lenght different from 23. > > > > > I tried to do something like this: > > > > VARIABLE filename : String; > > > > or > > > > VARIABLE filename : String (natural range<>); > > > > but I always get an error message. > > > > Have any suggestion? > > > > > Thanks > > > > > Dek > > > > I assume you are reading the string from a line? well, a line is > > > actually a pointer to a string. > > > > So, assuming you just have 1 filename per line, you can do something > > > like: > > > > readline(namefile, inline); > > > > FILE_OPEN(f, inline.all, READ_MODE); > > > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > > > You could do the same if its not just 1 file name per line, but the > > > parsing would get more complicated. But the method above means you ca= n > > > have filenames as long as you want.- Nascondi testo citato > > > > - Mostra testo citato - > > > Sorry but I didn't get what you mean; When I use the deallocate > > command don't I lose all informations pointed by inline? If I > > understood right the deallocate command serves to free memory, so if > > I > > write : > > > DEALLOCATE(inline); > > > I will free the memory block used to store the contents of infile; > > how > > can I find the same contents in a string whose lenght is not > > constrained? > > the READLINE function just copies the next line from the file into > "inline". if you call DEALLOCATE(inline) you are just removing the > pointer to the copy of the line, the file itself is unnaffected and > the next call to readline will correctly read off the next line from > the file. > > the previous example still stands. I was only using DEALLOCATE because > I wasnt actually reading anything from the line, I was dereferencing > the pointer with the inline.all call. if you dont deallocate it > without reading all the data off it, the next readline call will just > append the next line onto the end of whatever is left (and in my > example, the whole line would be left) > > so the following example is still good, assuming you dont have > anything else on the line other than the filename: > > readline(namefile, inline); > > FILE_OPEN(f, inline.all, READ_MODE); > DEALLOCATE(inline); =A0 =A0 =A0 =A0 --drops the pointer > > the good thing about this method is you dont need to declare a string > to read the data off "inline" and restrict it's length, you can just > use the line itself, as the "line" type is just a pointer to a string.- N= ascondi testo citato > > - Mostra testo citato - Ok, I think I should explane better what I have to do; my purpose is to write something like this: ---------------------------------------------------------------------------= ------------------------------------- READLINE ( filein, buf1); --filein: file where names are stored; buf1 e buf2 defined as a line; READ (buf1, filename); --filename define as a string WRITE ( buf2, string'("My command 1")); Write (buf2, filename); WRITE ( buf2, string'("My command 2")); WRITELINE (fileout, buf2); ---------------------------------------------------------------------------= ------------------------------------- Now, I tried to write something like this: ------ readline ( namefile, L); FILE_OPEN(namefile, L.all, READ_MODE); DEALLOCATE(L); --drops the pointer write (buf, L); writeline (outfile, buf); -------- but it doesn't work; It would be really nice to don't be forced declaring string lenght, but I didn't understood yet how to use properly the deallocate command. Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!de-l.enfer-du-nord.net!gegeweb.org!news.glorb.com!news2.glorb.com!postnews.google.com!n8g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Using Generics to Define Ranges Date: Sun, 3 May 2009 11:49:02 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241376542 11126 127.0.0.1 (3 May 2009 18:49:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 3 May 2009 18:49:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n8g2000vbb.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1025 I thought it would be a good idea to use Generics to define the ranges on std_logic_vector and unsigned signals. However, when I try to then create aggregates I get errors of "Choices for an array aggregate (DownTo) must be locally static unless there is only one choice." Carry <= (SPWTH-1 downto 1 => Pop, 0 => PassN); I understand what this is saying, but it seems to be a major difficulty. If I replace the generic with an attribute such as Carry'high, I still get the error. I suppose because this is still defined by the generic. So is it barking up the wrong tree to use generics to define data path widths or is there another way to then use these paths in aggregates that I am missing? Funny that this didn't seem to be a problem using the Lattice tools (Synplify), but it is flagged by XST. Rick From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi143.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com> Subject: Re: Using Generics to Define Ranges Lines: 35 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi143.ffdc.sbc.com 1241382126 ST000 99.184.242.197 (Sun, 03 May 2009 16:22:06 EDT) NNTP-Posting-Date: Sun, 03 May 2009 16:22:06 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PAPDON^ZTGRTPX@JIX_UXBUSXB@DTMNHWB_EYLJZ]BGIELNVUEAE[YETZPIWWI[FCIZA^NBFXZ_D[BFNTCNVPDTNTKHWXKB@X^B_OCJLPZ@ET_O[G\XSG@E\G[ZKVLBL^CJINM@I_KVIOR\T_M_AW_M[_BWU_HFA_]@A_A^SGFAUDE_DFTMQPFWVW[QPJN Date: Sun, 3 May 2009 16:25:42 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1026 "rickman" wrote in message news:9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com... >I thought it would be a good idea to use Generics to define the ranges > on std_logic_vector and unsigned signals. However, when I try to then > create aggregates I get errors of "Choices for an array aggregate > (DownTo) must be locally static unless there is only one choice." > > Carry <= (SPWTH-1 downto 1 => Pop, 0 => PassN); > > I understand what this is saying, but it seems to be a major > difficulty. If I replace the generic with an attribute such as > Carry'high, I still get the error. I suppose because this is still > defined by the generic. > > So is it barking up the wrong tree to use generics to define data path > widths or is there another way to then use these paths in aggregates > that I am missing? > For this particular instance, you should turn it around a bit and avoid the generic in the assignment. Carry <= (0 => PassN, others => Pop); For other cases, if the vector is representing some form of number you might want to express carry something like this... X <= std_logic_vector(to_unsigned(55, SPWTH)); Or if the assignment is particularly complicated, use a function. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!pfeed09.wxs.nl!newsfeed.kpn.net!pfeed08.wxs.nl!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Sun, 03 May 2009 20:35:23 -0700 Lines: 12 Message-ID: <76763sF1bar8jU1@mid.individual.net> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net dNsSF8Srxaa4AU/78Uf0fwDBplYMxdggUDMScVAD7l6C7XMSA8 Cancel-Lock: sha1:P2iSa717mWp0ajEfLGkczzHJbpY= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1027 Dek wrote: > but it doesn't work; It would be really nice to don't be forced > declaring string length, but I didn't understood yet how to use > properly the deallocate command. Consider using the REPORT command for text, and get on with the testbench. TextIO has already stolen two weeks of your time. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Using Generics to Define Ranges Date: Mon, 4 May 2009 16:28:55 -0700 (PDT) Organization: http://groups.google.com Lines: 65 Message-ID: References: <9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com> NNTP-Posting-Host: 64.241.37.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241479735 17086 127.0.0.1 (4 May 2009 23:28:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 May 2009 23:28:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=64.241.37.140; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1028 On May 3, 4:25 pm, "KJ" wrote: > "rickman" wrote in message > > news:9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com... > > > > >I thought it would be a good idea to use Generics to define the ranges > > on std_logic_vector and unsigned signals. However, when I try to then > > create aggregates I get errors of "Choices for an array aggregate > > (DownTo) must be locally static unless there is only one choice." > > > Carry <= (SPWTH-1 downto 1 => Pop, 0 => PassN); > > > I understand what this is saying, but it seems to be a major > > difficulty. If I replace the generic with an attribute such as > > Carry'high, I still get the error. I suppose because this is still > > defined by the generic. > > > So is it barking up the wrong tree to use generics to define data path > > widths or is there another way to then use these paths in aggregates > > that I am missing? > > For this particular instance, you should turn it around a bit and avoid the > generic in the assignment. > > Carry <= (0 => PassN, others => Pop); > > For other cases, if the vector is representing some form of number you might > want to express carry something like this... > > X <= std_logic_vector(to_unsigned(55, SPWTH)); > > Or if the assignment is particularly complicated, use a function. > > Kevin Jennings Certainly I could write it differently, but I do this in several places and it is just a PITA to have to do this. I also find that it is not consistent as to what it rejects, unless I just don't understand what is wrong. (MSByte => '1', others => '0') This gets flagged because MSByte is a generic. DatZero <= '1' when (DatAdd = (DatAdd'high downto 0 => '0')) else '0'; This is not flagged even though DatAdd'high is defined by a generic. I tried to work around the problem elsewhere by using the attribute and still got a yellow card. (IPWTH-1 downto IVWTH => '0') & IVEC when IPSR_IVEC, This is also not flagged where IPWTH and IVWTH are generics. The only difference between 1) and 3) is that 1) assigns different parts of the vector separately. Can anyone explain why these are all different or is the XST tool just missing them? Synplify didn't have a problem with any of this, but then I guess this is something that might be more of a problem in simulation than synthesis. I haven't tried that yet. Rick From newsfish@newsfish Wed Aug 19 13:24:27 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r31g2000prh.googlegroups.com!not-for-mail From: aralimaradsir@gmail.com Newsgroups: comp.lang.vhdl Subject: file missing error Date: Mon, 4 May 2009 21:10:02 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 210.212.197.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241496602 4174 127.0.0.1 (5 May 2009 04:10:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 04:10:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r31g2000prh.googlegroups.com; posting-host=210.212.197.162; posting-account=n5XdswoAAABwvo0dMWxBsOKUpPSvJHxg User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1029 Hi i am working on xilinx while executing my program its giving error as ERROR:cxl[lib]:3- file missing 'C:\Xilinx\vhdl\src\XilinxCoreLib \vhdl_analyze_order' i am not getting how solve this problem. From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.pimp.lart.info!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!j18g2000prm.googlegroups.com!not-for-mail From: LittleAlex Newsgroups: comp.lang.vhdl Subject: Re: file missing error Date: Tue, 5 May 2009 08:21:59 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: NNTP-Posting-Host: 132.190.112.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241536919 31717 127.0.0.1 (5 May 2009 15:21:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 15:21:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prm.googlegroups.com; posting-host=132.190.112.111; posting-account=htNwywoAAAAyrKHu0vPbiXZtaUyq3l0o User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1030 On May 4, 9:10 pm, aralimarad...@gmail.com wrote: > Hi i am working on xilinx while executing my program its giving error > as > ERROR:cxl[lib]:3- file missing 'C:\Xilinx\vhdl\src\XilinxCoreLib > \vhdl_analyze_order' > i am not getting how solve this problem. My guess would be that the file is missing. A failed "IP Update" install can cause this. AL From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.k-dsl.de!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!s38g2000prg.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Using Generics to Define Ranges Date: Tue, 5 May 2009 08:22:48 -0700 (PDT) Organization: http://groups.google.com Lines: 72 Message-ID: <7a38f726-a6df-44a3-a1ea-71a6d3858fb0@s38g2000prg.googlegroups.com> References: <9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241536968 19517 127.0.0.1 (5 May 2009 15:22:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 15:22:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s38g2000prg.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1031 Rickman, In your second example, I see you using an aggregate in an expression. I recommend only using aggregates when you are assigning directly to an object without an expression. Consider: library ieee ; use ieee.std_logic_1164.all ; use std.textio.all ; entity aggregate_issues is end entity aggregate_issues ; architecture behavioral of aggregate_issues is signal X_slv : std_logic_vector (0 to 7) ; signal Y_slv : std_logic_vector (7 downto 0) ; begin testproc : process begin X_slv <= (0 => '1', others => '0') ; -- set left bit to a 1 Y_slv <= (7 => '1', others => '0') ; wait for 10 ns ; if X_slv = (0 => '1', 1 to 7 => '0') then -- compare left bit 1? write(Output, "X SLV: True" & LF) ; else write(Output, "X SLV: FALSE" & LF) ; end if ; if Y_slv = (7 => '1', 6 downto 0 => '0') then -- compare left bit 1? -- if Y_slv = (7 => '1', others => '0') then -- error as aggregate does not size the array write(Output, "Y SLV: True" & LF) ; else write(Output, "Y SLV: FALSE" & LF) ; end if ; wait ; end process ; end behavioral ; Result: # X SLV: True # Y SLV: FALSE The assignment is ok since it is coerced by the range of the type. However, once it is put in an expression, some how the range of the aggregate needs to be derived and it is not from the aggregate itself. Instead it is based on the index range for the type which is constrained to be a natural which starts with 0 and goes to the highest integer. Hence the default range for std_logic_vector (and all std_logic based vectors) is "0 to ...". So when I write something like this: > DatZero <= '1' when (DatAdd = (DatAdd'high downto 0 => '0')) else '0'; I use a math package (numeric_std if DatAddr is unsigned) and compare with integers: DatZero <= '1' when (DatAdd = 0) else '0'; If DatAddr is std_logic_vector either use std_logic_unsigned or add type conversion: DatZero <= '1' when (unsigned(DatAdd) = 0) else '0'; Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!j18g2000prm.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Tue, 5 May 2009 08:33:45 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241537625 21735 127.0.0.1 (5 May 2009 15:33:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 15:33:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prm.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1032 Dek, Here is something I have used. Make sure that FileName length (20 here) is big enough to allow you to get the file name. This assumes that there is no white space at the end of the line. Note though I used this in a toy program. I only read files for testbenches when I have a big data set to read in, like a video image or something of that sort. use std.textio.all; TestProc : process File TestFile : Text ; variable FileInLine : Line ; variable FileName : string (1 to 20 ) ; variable NameLength : natural ; begin Write( OUTPUT, "File Name to Read: " & LF); Read ( INPUT, FileName, NameLength) ; if (FileName(NameLength) = LF) then NameLength := NameLength - 1 ; end if ; file_open(TestFile, FileName(1 to NameLength), READ_MODE); Best, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d39g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Tue, 5 May 2009 08:38:39 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241537919 2341 127.0.0.1 (5 May 2009 15:38:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 15:38:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d39g2000pra.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1033 This one handles spaces on the same line as the name, but is much more tedious Main : Process begin write(WriteBuf, String'("Enter File Name to Read: ")) ; writeline(OUTPUT, WriteBuf) ; Readline (INPUT, ReadBuf) ; i := 1 ; loop Read(ReadBuf, InputString(i), Valid) ; exit when not Valid ; i := i + 1 ; end loop ; if i = 1 then wait; end if ; -- add error handling here file_open(TestFile, InputString(1 to i-1), READ_MODE) ; Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!postnews.google.com!u9g2000pre.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Tue, 5 May 2009 08:55:00 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241538900 25907 127.0.0.1 (5 May 2009 15:55:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 15:55:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u9g2000pre.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1034 This needs a small modification for your code: > This one handles spaces on the same line as the name, but is much more > tedious > > Main : Process > > begin > =A0 write(WriteBuf, String'("Enter File Name to Read: ")) ; > =A0 writeline(OUTPUT, WriteBuf) ; > =A0 Readline (INPUT, ReadBuf) ; > =A0 i :=3D 1 ; > =A0 loop > =A0 =A0 Read(ReadBuf, InputString(i), Valid) ; =A0 =A0 exit when not Valid or InputString(i) =3D ' ' or InputString(i) = =3D HT ; > =A0 =A0 i :=3D i + 1 ; > =A0 end loop ; > =A0 if i =3D 1 then wait; end if ; =A0 -- add error handling here > =A0 file_open(TestFile, InputString(1 to i-1), READ_MODE) ; > Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e23g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Using Generics to Define Ranges Date: Tue, 5 May 2009 09:31:54 -0700 (PDT) Organization: http://groups.google.com Lines: 90 Message-ID: References: <9ebb027c-a197-44fc-ab22-04d59f1216fd@n8g2000vbb.googlegroups.com> <7a38f726-a6df-44a3-a1ea-71a6d3858fb0@s38g2000prg.googlegroups.com> NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241541114 924 127.0.0.1 (5 May 2009 16:31:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 May 2009 16:31:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e23g2000vbe.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1035 Thanks for your reply. You pointed out a few things I had forgotten, like being able to compare unsigned to integers. I don't agree with the general rule of avoiding aggregates in expressions however. Yes, they have to have a defined range, but that was not an issue in my case. The problem was that the range was defined by a generic which is not defined at compile time. This problem is made tricky because of the need to have some uses defined at compile time, (aggregate ranges) but not other uses (array ranges). I've got workarounds, I just don't like some of them. Rick On May 5, 11:22 am, JimLewis wrote: > Rickman, > In your second example, I see you using an aggregate in an expression. > I recommend only using aggregates when you are assigning directly to > an > object without an expression. > > Consider: > > library ieee ; > use ieee.std_logic_1164.all ; > use std.textio.all ; > > entity aggregate_issues is > end entity aggregate_issues ; > architecture behavioral of aggregate_issues is > signal X_slv : std_logic_vector (0 to 7) ; > signal Y_slv : std_logic_vector (7 downto 0) ; > begin > > testproc : process > begin > X_slv <= (0 => '1', others => '0') ; -- set left bit to a 1 > Y_slv <= (7 => '1', others => '0') ; > > wait for 10 ns ; > > if X_slv = (0 => '1', 1 to 7 => '0') then -- compare left bit 1? > write(Output, "X SLV: True" & LF) ; > else > write(Output, "X SLV: FALSE" & LF) ; > end if ; > > if Y_slv = (7 => '1', 6 downto 0 => '0') then -- compare left bit > 1? > -- if Y_slv = (7 => '1', others => '0') then -- error as > aggregate does not size the array > write(Output, "Y SLV: True" & LF) ; > else > write(Output, "Y SLV: FALSE" & LF) ; > end if ; > > wait ; > end process ; > end behavioral ; > > Result: > # X SLV: True > # Y SLV: FALSE > > The assignment is ok since it is coerced by the range of the type. > However, once it is put in an expression, some how the range of the > aggregate needs to be derived and it is not from the aggregate itself. > Instead it is based on the index range for the type which is > constrained > to be a natural which starts with 0 and goes to the highest integer. > Hence the default range for std_logic_vector (and all std_logic based > vectors) is "0 to ...". > > So when I write something like this: > > > DatZero <= '1' when (DatAdd = (DatAdd'high downto 0 => '0')) else '0'; > > I use a math package (numeric_std if DatAddr is unsigned) and compare > with integers: > DatZero <= '1' when (DatAdd = 0) else '0'; > > If DatAddr is std_logic_vector either use std_logic_unsigned or add > type conversion: > DatZero <= '1' when (unsigned(DatAdd) = 0) else '0'; > > Cheers, > Jim From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!l5g2000vbc.googlegroups.com!not-for-mail From: French Newsgroups: comp.lang.vhdl Subject: Custom Synthesis Error Generation Date: Tue, 5 May 2009 22:55:01 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> NNTP-Posting-Host: 87.65.54.150 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241589301 31831 127.0.0.1 (6 May 2009 05:55:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 05:55:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l5g2000vbc.googlegroups.com; posting-host=87.65.54.150; posting-account=3UGYAwoAAAC9eA-TzfPN3GYofbz5QgdZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; fr; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1036 Hi, Does anybody know how I can generate custom error during synthesis (and not during runtime) inside my vhdl code. For example, I have defined an entity feature two generics and I would like to generate a specific error during the synthesis of the current block is a forbidden combination of my generic parameters occurs. i.e: entity test is generic ( param1 : integer := 23; param2 : integer := 24); -- always works but when both param1 and param2 are equal to 32 ... it would be very helpfull to detect missuses of some component defined in libraries that would not be explicitely reported otherwhise. I have found some ways to do it during simulation using assert commands with severity parameters but, as assert must be used in a sequential process it cannot work during synthesis From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g31g2000pra.googlegroups.com!not-for-mail From: aralimaradsir@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: file missing error Date: Tue, 5 May 2009 23:20:33 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: NNTP-Posting-Host: 210.212.197.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241590833 2560 127.0.0.1 (6 May 2009 06:20:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 06:20:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g31g2000pra.googlegroups.com; posting-host=210.212.197.162; posting-account=n5XdswoAAABwvo0dMWxBsOKUpPSvJHxg User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1037 On May 5, 8:21=A0pm, LittleAlex wrote: > On May 4, 9:10 pm, aralimarad...@gmail.com wrote: > > > Hi i am working on xilinx while executing my program its giving error > > as > > ERROR:cxl[lib]:3- file missing 'C:\Xilinx\vhdl\src\XilinxCoreLib > > \vhdl_analyze_order' > > i am not getting how solve this problem. > > My guess would be that the file is missing. > > A failed "IP Update" install can cause this. > > AL Ya sir that folder is not there.so now how can i get that folder i reinstalled it but still the same error and that folder is missing so how can i get it.waiting for reply thank you From newsfish@newsfish Wed Aug 19 13:24:28 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.news-service.com!news2.euro.net!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Custom Synthesis Error Generation Date: Wed, 06 May 2009 08:53:05 +0200 Lines: 32 Message-ID: <76cqejF1bqhfaU1@mid.individual.net> References: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 5tpKDU7IgYg2sQqVZwhe7gIWQVYQw/ATe7G9wXsLABDJSKg43V Cancel-Lock: sha1:H5je8Kw8tA6DFtqZDOOC3g20h5o= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1038 French wrote: > I have found some ways to do it during simulation using assert > commands with severity parameters but, as assert must be used in a > sequential process it cannot work during synthesis Many synthesis tools do in fact evaluate assertions. All the ones I've seen at least issue a warning, some even halt synthesis when the severity level is "error" or "failure". I know it works with XST, and for Mentor's Precision there's a command-line switch that enables this behaviour: setup_design -var "rtl_extra_options=-allow_assert_error" Not sure how it is with Quartus or Synplify. In some cases there's the possibility to do something similar with range constraints. Example: You have a generic that should only have valid values from 1 to 12. Now you could create an integer subtype with range 1 to 12 and make the generic of that type. That way, when someone sets the generic to an invalid value, the synthesis tool will halt with an "out of range" error. This definitely should work with any synthesis tool. But this only works in simple cases, obviously, and you can't customize the error message that is generated. HTH, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?). From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n8g2000vbb.googlegroups.com!not-for-mail From: Matthieu Newsgroups: comp.lang.vhdl Subject: Re: Custom Synthesis Error Generation Date: Wed, 6 May 2009 00:19:27 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> NNTP-Posting-Host: 213.215.9.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241594367 15629 127.0.0.1 (6 May 2009 07:19:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 07:19:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n8g2000vbb.googlegroups.com; posting-host=213.215.9.6; posting-account=5oQcuwoAAACOCJROem8055IdXL4jGrpA User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; fr; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 ipcop-lesulis.localdomain:800 (squid/2.6.STABLE17) Xref: news.eternal-september.org comp.lang.vhdl:1039 On May 6, 7:55=A0am, French wrote: > Hi, > > Does anybody know how I can generate custom error during synthesis > (and not during runtime) inside my vhdl code. > > For example, I have defined an entity feature two generics and I would > like to generate a specific error during the synthesis of the current > block is a forbidden combination of my generic parameters occurs. > Hey French You may want to take a closer look at the "assert" statement: The assert statement isn't required to be called within a sequential process, as a matter of fact, it can also be used as a concurrent statement as well. Usually I would place these assert statements just before the end of the architecture implementation. The following code snippet is correctly interpreted by the Xilinx design flow and Modelsim. ------- (...) ARG_CHECK: assert (MUST_ALWAYS_BE_TRUE_GENERIC =3D true) report "Invalid argument: MUST_ALWAYS_BE_TRUE_GENERIC boolean is not tru.e" severity failure; end architecture RTL; ------- Hope this helps. From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!s20g2000vbp.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Custom Synthesis Error Generation Date: Wed, 6 May 2009 00:59:38 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <28bcae27-990a-4283-9f75-1ed1ef0c1788@s20g2000vbp.googlegroups.com> References: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241596779 22816 127.0.0.1 (6 May 2009 07:59:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 07:59:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000vbp.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1040 There has been some discussion about this previously: http://groups.google.co.uk/group/comp.lang.vhdl/browse_frm/thread/d5598c92bfe80b1d?tvc=1&q=generics+assert&fwc=1 Overall conclusions: Synplify and Synopsis DC = Completly ignored it Precision = Threw a warning and carried on even for ERROR and FAILURE states XST and Quartus = Handled them correctly. Hope this helps. From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Halt synthesiser with an assert? Date: Wed, 06 May 2009 13:18:57 +0200 Lines: 27 Message-ID: <76da11F19vn9sU1@mid.individual.net> References: <1av5i4lt89m7hatppgnflnhkl192ccs4jk@4ax.com> <808f02a6-0d96-4069-830c-83903beee6ad@g17g2000prg.googlegroups.com> <3f6ecec0-86c6-4b97-8988-1c9518dba912@v5g2000prm.googlegroups.com> <1471f587-1099-46ef-bcf6-d854514b2df8@s9g2000prg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net okzNN/I+so9mHe54aUbZHgEeeLwWkClqkqD3t0fvEaRwPX4y0S Cancel-Lock: sha1:KTV7NyDAiqQspaMp0DSRN8t8yaI= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1041 Jonathan Bromley wrote: > Indeed. I'm amazed the design-IP community hasn't already > beaten the synth vendors' doors down about this. FWIW, I recently contacted Mentor about this, since Precision only issues warnings when an assertion with severity error or failure occurs. They responded that some of their biggest customers explicitely wanted that behaviour, since assertions should be used for simulation only and some of their code would not synthesize anymore. I suppose it's similar for other vendor's tools. At least, for Precision there's an undocumented command-line switch that enables it. Just so it propagates into all the search engines: setup_design -var "rtl_extra_options=-allow_assert_error" Mentor opened a DR to introduce this as an official "feature" in some future release. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?). From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: French Newsgroups: comp.lang.vhdl Subject: Re: Custom Synthesis Error Generation Date: Wed, 6 May 2009 04:39:24 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: References: <1f2939b3-30e4-4a81-92e6-2b46a18d0d8b@l5g2000vbc.googlegroups.com> <28bcae27-990a-4283-9f75-1ed1ef0c1788@s20g2000vbp.googlegroups.com> NNTP-Posting-Host: 87.66.24.4 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241609964 31175 127.0.0.1 (6 May 2009 11:39:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 11:39:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=87.66.24.4; posting-account=3UGYAwoAAAC9eA-TzfPN3GYofbz5QgdZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1042 Thanks to all of you for the very quick answer, it made my day. From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x31g2000prc.googlegroups.com!not-for-mail From: LittleAlex Newsgroups: comp.lang.vhdl Subject: Re: file missing error Date: Wed, 6 May 2009 08:03:19 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <2116fa5e-04bb-46ef-a80c-d35b6992eadb@x31g2000prc.googlegroups.com> References: NNTP-Posting-Host: 132.190.112.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241622200 9352 127.0.0.1 (6 May 2009 15:03:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 15:03:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x31g2000prc.googlegroups.com; posting-host=132.190.112.111; posting-account=htNwywoAAAAyrKHu0vPbiXZtaUyq3l0o User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1043 On May 5, 11:20 pm, aralimarad...@gmail.com wrote: > On May 5, 8:21 pm, LittleAlex wrote: > > > On May 4, 9:10 pm, aralimarad...@gmail.com wrote: > > > > Hi i am working on xilinx while executing my program its giving error > > > as > > > ERROR:cxl[lib]:3- file missing 'C:\Xilinx\vhdl\src\XilinxCoreLib > > > \vhdl_analyze_order' > > > i am not getting how solve this problem. > > > My guess would be that the file is missing. > > > A failed "IP Update" install can cause this. > > > AL > > Ya sir that folder is not there.so now how can i get that folder i > reinstalled it but still the same error and that folder is missing so > how can i get it.waiting for reply thank you If that folder is missing, your installation is bad broken. Un-install before re-installing ISE. Verify that the un-install clears the Xilinx environment variables before re-installing. If that doesn't work, get a new copy of the installation software. AL From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!not-for-mail From: Nicholas Paul Collin Gloucester Newsgroups: comp.lang.vhdl Subject: Re: Advanced use of VHDL - Factorial example Date: Wed, 6 May 2009 19:24:20 +0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <49f5c749$0$5255$426a34cc@news.free.fr> <6004390c1e4478cb95afaaa7c9e8@news.acm.uiuc.edu> <75nm2nF1988iuU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.eternal-september.org U2FsdGVkX1/cUPBh1hRCExvRNoD+CnPWEHZRVZA15C37cZPy8UcL3buDRQyHfT6jah1ykRDCHyoA2XbwEVu2Kf3YHGShYYtFRQvrgXxPFxYfcWAOLyYRE1MSfX8cg0+LnIiRvtcYwrX3/U9WhzWRJj+tvYKcvsj6 X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Wed, 6 May 2009 19:24:20 +0000 (UTC) X-Auth-Sender: U2FsdGVkX1/fMyUsz6HfdxvL0Id2cdmpyZ0AvLXb+6+p6Pmn1mIThcx2fyrDOQ3b0tE7f0daqvI= Cancel-Lock: sha1:rmkOzMx4MZanP29JBmkOFkRCU88= User-Agent: slrn/0.9.9p1 (Linux) Xref: news.eternal-september.org comp.lang.vhdl:1044 On 2009-04-28, Mike Treseler wrote: |-------------------------------------------------------------------------| |"Matthew Hicks wrote: | | | |[..] | | | |> The same effect could | |> be had by using loop and generate statements to explicitly build a | |> look-up table. | | | |Not the same effect. | |Fewer would learn something new. | | | |[..]" | |-------------------------------------------------------------------------| Mr. T., I love you. Love, C. P. G. From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!i28g2000prd.googlegroups.com!not-for-mail From: Abhishek Newsgroups: comp.lang.vhdl Subject: Requiring VHDL code for filter design using add and shift method Date: Wed, 6 May 2009 12:57:35 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 122.172.29.176 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241639855 27357 127.0.0.1 (6 May 2009 19:57:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 May 2009 19:57:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000prd.googlegroups.com; posting-host=122.172.29.176; posting-account=SpDfUwoAAAAhxniut2QTu7YpAIAQA8ob User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.59 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1045 Hello Group, I am working on a project entitled High speed filter design. For the design i have to use the add and shift method. Working over it, got stuck, If anybody can gimme the code for the filter design using add and shift method, it would be of immense help... U can send the code to my mail address: absoluterick@gmail.com. PLS PLS PLS.. any body help me out.. asap Thanks.. From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Requiring VHDL code for filter design using add and shift method Date: Wed, 06 May 2009 14:58:20 -0700 Lines: 16 Message-ID: <76effsF1ch5ssU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 377VvGJSNFkKjlwJJaUNDQPgUZgkf9MjCMnFGgHh9OWhbgjfEC Cancel-Lock: sha1:uObnIHFzN6sd/ngqHIVow+C3X0M= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1046 Abhishek wrote: > I am working on a project entitled High speed filter design. > For the design i have to use the add and shift method. Working over > it, got stuck, > If anybody can gimme the code for the filter design using add and > shift method, it would be of immense help... > U can send the code to my mail address: absoluterick@gmail.com. > > PLS PLS PLS.. any body help me out.. asap I would drop the class. It doesn't sound very interesting. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:29 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: kennheinrich@sympatico.ca Newsgroups: comp.lang.vhdl Subject: Re: Requiring VHDL code for filter design using add and shift method Date: Wed, 6 May 2009 18:57:50 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <76effsF1ch5ssU1@mid.individual.net> NNTP-Posting-Host: 70.50.190.136 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241661470 29505 127.0.0.1 (7 May 2009 01:57:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 01:57:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=70.50.190.136; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1047 On May 6, 5:58=A0pm, Mike Treseler wrote: > Abhishek wrote: > > I am working on a project entitled High speed filter design. > > For the design i have to use the add and shift method. Working over > > it, got stuck, > > If anybody can gimme the code for the filter design using add and > > shift method, it would be of immense help... > > U can send the code to my mail address: absoluter...@gmail.com. > > > PLS PLS PLS.. any body help me out.. asap > > I would drop the class. > It doesn't sound very interesting. > > =A0 =A0 -- Mike Treseler Add and shift what? You can use add and shift to implement a multiplier, if your synthesizer won't do it for you. For example, a FIR filter with a coefficient of 17 needs an x17 multiplier in it. You can implement that by shift and add: k*17 =3D k*16+k =3D (k<<4)+k. True horror story: I once saw a guy fill up something like 114 hard multipliers, in DSP slices, in a V4FX60 in order to multiply numbers by 5 and 20. If you're talking about adding shifted data, and how it affects frequency response, you need to reread the math stuff - it's kind of important that you understand what's happening in order to do a sensible implementation. - Kenn From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.unit0.net!uio.no!newsfeed1.funet.fi!newsfeeds.funet.fi!newsfeed.sunet.se!news01.sunet.se!news.lysator.liu.se!not-for-mail From: Andreas Ehliar Newsgroups: comp.lang.vhdl Subject: Re: Requiring VHDL code for filter design using add and shift method Date: Thu, 7 May 2009 04:28:38 +0000 (UTC) Organization: Lysator ACS, Linkoping University, Sweden Lines: 31 Message-ID: References: NNTP-Posting-Host: sabor.isy.liu.se X-Trace: news.lysator.liu.se 1241670518 2974 130.236.55.37 (7 May 2009 04:28:38 GMT) X-Complaints-To: root@lysator.liu.se NNTP-Posting-Date: Thu, 7 May 2009 04:28:38 +0000 (UTC) User-Agent: slrn/0.9.8.1pl1 (Linux) Xref: news.eternal-september.org comp.lang.vhdl:1048 On 2009-05-06, Abhishek wrote: > If anybody can gimme the code for the filter design using add and > shift method, it would be of immense help... > U can send the code to my mail address: absoluterick@gmail.com. > > PLS PLS PLS.. any body help me out.. asap Hi. normally I'm sure that many people would jump on the chance to do your homework for you. I simply don't understand why you haven't received a solution yet. Perhaps everyone in the group is simply busy researching the ultimate shift and add based filters for your perusal. Why don't you read the following related documents while waiting for the group to finish your homework? I'm sure they are going to be very interesting for you: METHOD AND APPARATUS FOR IMPLEMENTING A DIGITAL FILTER EMPLOYING COEFFICIENTS EXPRESSED AS SUMS OF 2 TO AN INTEGER POWER http://www.google.com/patents?id=KZEiAAAAEBAJ SHIFT AND ADD DIGITAL SIGNAL PROCESSOR http://www.google.com/patents?id=Q3goAAAAEBAJ DIGITAL FIR FILTERS WITH ENHANCED TAP WEIGHT RESOLUTION http://www.google.com/patents?id=hhM9AAAAEBAJ HTH, HAND /Andreas From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e23g2000vbe.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 7 May 2009 03:37:54 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: <9f6457c4-628b-44bf-965d-f2232285f184@e23g2000vbe.googlegroups.com> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241692674 28819 127.0.0.1 (7 May 2009 10:37:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 10:37:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e23g2000vbe.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1049 On 5 Mag, 17:55, JimLewis wrote: > This needs a small modification for your code: > > > This one handles spaces on the same line as the name, but is much more > > tedious > > > Main : Process > > > begin > > =A0 write(WriteBuf, String'("Enter File Name to Read: ")) ; > > =A0 writeline(OUTPUT, WriteBuf) ; > > =A0 Readline (INPUT, ReadBuf) ; > > =A0 i :=3D 1 ; > > =A0 loop > > =A0 =A0 Read(ReadBuf, InputString(i), Valid) ; > > =A0 =A0 =A0 exit when not Valid or InputString(i) =3D ' ' or InputString(= i) =3D > HT ; > > > =A0 =A0 i :=3D i + 1 ; > > =A0 end loop ; > > =A0 if i =3D 1 then wait; end if ; =A0 -- add error handling here > > =A0 file_open(TestFile, InputString(1 to i-1), READ_MODE) ; > > Cheers, > Jim > SynthWorks VHDL Training Thanks all, it seems a good idea, but finally I used Tcl, it's quite simple Bye Dek From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!e23g2000vbe.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: ModelSim & Multithreading Date: Thu, 7 May 2009 03:39:57 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241692798 29108 127.0.0.1 (7 May 2009 10:39:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 10:39:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e23g2000vbe.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1050 Hi all, do you know anything about Multithreading with Modelsim PE student edition? I'm simulating with a big testbanch and it takes a lot of time, but I see that vsimk.exe uses just 50% of CPU; since I have a dual core processor I think that for simulations Modelsim is using just one core. The question is: is there a setting or something to use both cores? Thanks Bye From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.news-service.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder2.news.saunalahti.fi!uutiset.elisa.fi!7564ea0f!not-for-mail From: Kim Enkovaara User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: Date: Thu, 07 May 2009 14:01:36 +0300 NNTP-Posting-Host: 138.111.130.175 X-Complaints-To: newsmaster@saunalahti.com X-Trace: uutiset.elisa.fi 1241694098 138.111.130.175 (Thu, 07 May 2009 14:01:38 EEST) NNTP-Posting-Date: Thu, 07 May 2009 14:01:38 EEST Organization: Elisa Customer Xref: news.eternal-september.org comp.lang.vhdl:1051 Dek wrote: > dual core processor I think that for simulations Modelsim is using > just one core. The question is: is there a setting or something to use > both cores? There is no such setting, not even in the SE version or Questa. If you are heavily dumping waveforms etc. then the waveform writing can be threaded, and at least in the expensive versions it is threaded as a default. --Kim From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading Date: Thu, 07 May 2009 13:21:42 +0200 Lines: 24 Message-ID: <87tz3x88ft.fsf@harnisch.dyndns.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net xkv53jwcLi5K7wrxoAyuLQFZCxZfyBcO/73NTA+2xfLsaaLByC Cancel-Lock: sha1:feLIS2xTKZ2tQB6w4aXxy0VeBFI= sha1:taqED+QlosYV+KLvHd4Y11zBVL4= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:1052 Dek writes: > do you know anything about Multithreading with Modelsim PE student > edition? I'm simulating with a big testbanch and it takes a lot of > time, but I see that vsimk.exe uses just 50% of CPU; since I have a > dual core processor I think that for simulations Modelsim is using > just one core. The question is: is there a setting or something to use > both cores? Currently EDA tool makers seem to agree that the overhead of resynchronizing many individual simulation threads back to the HDL timing model is simply too big to make it worthwhile. But I am sure you have more than just one test... Just run simulations concurrently. Regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!e24g2000vbe.googlegroups.com!not-for-mail From: Paddy3118 Newsgroups: comp.lang.vhdl Subject: Reason for compile ordering? Date: Thu, 7 May 2009 05:58:04 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 217.10.60.85 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241701084 22405 127.0.0.1 (7 May 2009 12:58:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 12:58:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e24g2000vbe.googlegroups.com; posting-host=217.10.60.85; posting-account=p34d-wkAAAC60rn_Tuk_HKyjfq-hlvCF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.2; SV1; .NET CLR 1.1.4322; .NET CLR 1.0.3705; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1053 Would someone reply with /why/ it is that an instantiated component must be compiled before that which instantiates it in VHDL? I find it irksome to create a compile orderwhich may span sources in multiple libraries and think I would be less annoyed if i knew what this rule is /for/. I've been told that VHDL is based on some mil. language that had this feature (Algol? Ada?), but if so, what is the reason it was added to its precursor language, and why do we keep it now? I can see that maybe compiler checks for source code updates against compiled libraries (a la make), are useful, but I cannot find what this VHDL compile rule gives you. - Paddy. Thanks in advance for your help. From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 07 May 2009 08:26:25 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 07 May 2009 14:23:57 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 98 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-z2B/aBm0nqIBiiU4mkGxr7UI5sNN7WCMAXVD02r+9p9PNWQeLScAJoiPl3+AI481/OZnWNY29ROWAii!4EKWL/M0ghauG7kg4G8joQtXyuQm4AA8CY09dNKE+jOfUF9KqlP9wZMvGBLbheKWDCosISD7lp8T!tFRT X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 5524 Xref: news.eternal-september.org comp.lang.vhdl:1054 On Thu, 7 May 2009 05:58:04 -0700 (PDT), Paddy3118 wrote: >Would someone reply with /why/ it is that an instantiated component >must be compiled before that which instantiates it in VHDL? Be careful with your terminology; there are two quite different cases here. 1) COMPONENT instantiation In this case, a COMPONENT declaration provides a prototype of the thing you aim to instantiate. This declaration details the types and names of generics and ports, and of course the name of the thing, but no more than that. At some point you will create, and compile, an entity and architecture to match that component prototype. But you can compile the instantiating architecture before that is done. Component instantiation facilitates a separate-compilation flow, and top-down design. Of course the component declaration must be compiled first. You can do this either by putting the component declaration in the architecture's declarative region, in which case it obviously gets compiled before the instance, or else you can put it in a package and "use" that package, in which case your compilation won't get past the "use" clause until the package has already been compiled. You are very unlikely to suffer compile-order difficulties in this case. A VHDL component is somewhat like a footprint - complete with pads, pin locations and names, etc - in a PCB layout package; you can put the footprint down on a PCB long before you have the chip that will be used to populate that footprint. 2) DIRECT instantiation ~~~~~~~~~~~~~~~~~~~~~~~ In this case you explicitly instantiate an entity. instance_name: entity work.component_name port map (...); No component declaration is needed. Clearly, in this case the compiler must already know about the "footprint" (ports, generics) of the entity, otherwise it can't check that the instantiation makes sense. Direct instantiation enforces the bottom-up compilation order that you're probably complaining about, because an entity must have been compiled before the compiler encounters an instance of it. >I find it irksome to create a compile orderwhich may span sources in >multiple libraries and think I would be less annoyed if i knew what >this rule is /for/. Have you ever tried calling a C function with more arguments than it expects? Fewer? In classic K&R C there is almost no compile-time checking of function arguments, and it can cause all manner of hard-to-find bugs; hence ANSI C's function prototypes. Components are VHDL's "entity prototypes". Verilog freely allows you to instantiate a module without having compiled it, and does not support anything like VHDL component declarations (prototypes). Such an instance cannot be checked in any way by the compiler; you could get the port connections completely wrong, and the compiler is none the wiser. All that checking gets done much later, when you elaborate the design (i.e. you specify a top-level module and ask your simulator or synth tool to put its structure together). This is very, very late in the day to be finding out that you completely screwed-up a connection list somewhere. VHDL stops you making that error, right up front. In some VHDL compilers, you can play games with compiler command line options to simplify things. For example, ModelSim has the "-just" option; it tells the compiler to scan source files and compile just one kind of design unit (entity, architecture, package etc). This flow of compile commands works in almost all practical cases: vcom -just p ;# compile packages vcom -just b ;# compile package bodies vcom -just e ;# compile entities vcom -just a ;# compile architectures vcom -just c ;# compile configurations Compiling all entities before you try to compile any architecture will generally fix the majority of compile-order issues. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g31g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 7 May 2009 08:33:13 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241710393 8745 127.0.0.1 (7 May 2009 15:33:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 15:33:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g31g2000pra.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1055 My favorite example that the compile rules prevents is: Designer A uses shared declarations from an external file and compiles their design. Designer B modifies the shared declarations in the external file and compiles their design. In VHDL, Designer A must recompile their design before it can be simulated with designer B's chip. Also note that dependencies in VHDL are on the primary units (entity, package declaration, and configurations) and not architectures. So if you change an architecture in a design and do not change the entity ports, you can simply recompile with the vcom -just a trick that jonathan showed. Pragmatically speaking, either use the project compile capability of the simulator or a script file to recompile. I find that the compilers are fast enough these days that you can generally run a lazy script that recompiles either your entire design or a large portion of it and starts a simulation is faster than typing or using the GUI to recompile one or two designs and restarting a simulation. Cheers, Jim SynthWorks VHDL Training www.SynthWorks.com From newsfish@newsfish Wed Aug 19 13:24:30 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Requiring VHDL code for filter design using add and shift method Date: Thu, 07 May 2009 08:51:59 -0700 Lines: 11 Message-ID: <4A03039F.2040703@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net eJnPUQyyQ5OsbXjMxzWbjwrOe6f+zmpv/BtF0yi0q++E2/rMzI Cancel-Lock: sha1:YvYxv6d0w/8FSFIsvMAUHjXIWdM= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1056 Abhishek wrote: > I am working on a project entitled High speed filter design. > For the design i have to use the add and shift method. Andreas has your solution. Tell the Prof that the 'shift and add method' has been patented, and you must consult with your attorney before proceeding ;) -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x31g2000prc.googlegroups.com!not-for-mail From: hepmehepme@comcast.net Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Seeding random number generator Date: Thu, 7 May 2009 09:08:03 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: <5e8e0bc9-c47e-409b-ad3a-d02f8e6f26e6@x31g2000prc.googlegroups.com> NNTP-Posting-Host: 128.138.131.247 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241712483 25644 127.0.0.1 (7 May 2009 16:08:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 16:08:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x31g2000prc.googlegroups.com; posting-host=128.138.131.247; posting-account=Uj_x9woAAABNBctIsgWwJCIxiu47SFLj User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.2; WOW64; SV1; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1057 comp.arch.fpga:3148 Sorry if this has been covered already. I am developing a testbench for a design and I want the behavioral models for external devices to use random parameters within the constraints of the data sheets. I figured out how to start up a sim with a seed variable in Modelsim, but now I'm confused about how to use that seed. Say I have two processes, each controlling one aspect of an ADC. Does each process have its own random number stream or do they share some global random number stream? In other words, does each process access a global seed or do they each maintain their own seeds. I was thinking that a global seed may be dangerous because it may change in a non-deterministic fashion. Here is an example with local seeds. The first process controls the ADC convert to busy timing, the second process controls the prop delay through a mux. Each takes the initial value for the seed from the generic for the testbench and then keeps a local copy of the seed. Is this the right way to do this? procedure rand_time( variable seed1, seed2 : inout positive; min, max : in integer; result : out time ) is variable rand : real; begin uniform(seed1, seed2, rand); result := (integer(real(min) + (rand * (real(max)-real(min)) ) ))* 1 ps; end procedure; -- ADC busy timing convert : process variable s1 : integer; variable s2 : integer; variable t6 : time; variable tconv : time; variable init : std_logic; begin -- Init seeds from generic if not already initialized if(init /= '1')then s1 := gSEED; s2 := s1/2 + 50; init := '1'; end if; busy_n <= '1'; wait until falling_edge(convst_n); if(cs_n = '0')and(shtdn_n = '1')then rand_time(s1, s2, MIN_T6, MAX_T6, t6); rand_time(s1, s2, MIN_TCONV, MAX_TCONV, tconv); busy_n <= '0' after t6; wait for (tconv - t6); busy_n <= '1'; dtemp <= din; end if; end process convert; -- mux timing mux : process (en_n, mux_sel) variable s1: integer; variable s2: integer; variable p : time; variable init : std_logic; begin -- Init seeds from generic if not already initialized if(init /= '1')then s1 := gSEED; s2 := s1/2 + 50; init := '1'; end if; rand_time(s1, s2, MIN_DELAY, MAX_DELAY, p); if(en_n = '1') then dout <= (others => 'Z') after p; else dout(15 downto 12) <= mux_sel after p; dout(11 downto 0) <= (others => '0') after p; end if; end process mux; From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!21g2000vbk.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Seeding random number generator Date: Thu, 7 May 2009 09:34:27 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <5e8e0bc9-c47e-409b-ad3a-d02f8e6f26e6@x31g2000prc.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241714068 20945 127.0.0.1 (7 May 2009 16:34:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 16:34:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 21g2000vbk.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1058 comp.arch.fpga:3151 There is no Global seed. The seeds are stored in the seed variables (s1 and s2 in each process) you have. If you monitored them you'd notice that they change every time you call the uniform function, and hence why they are of mode "inout". So in effect there is no "random number stream" as you put it - just a formula that gives you a value based on s1 and s2, and s1 and s2 are changed after each call. This is useful because it allows repeatability of random streams. You can check output by seeding the expected output sequence with the same seeds you initialised the input sequence with. From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 07 May 2009 11:34:48 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Seeding random number generator Date: Thu, 07 May 2009 17:32:20 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <5e8e0bc9-c47e-409b-ad3a-d02f8e6f26e6@x31g2000prc.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 96 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-h6Qr3L6BjzKXazH2yiLPoR3K4dd1exkkZydpftIA10MzzL75dXFzhAYpwHhTzQL4vfNEZT6kfPb5qql!2ud/GmmB+vd2doYFj0/QoNT0gx7PqMh2Y/vLT32/k9F48WcYdEbuNsb+/V+/6PJTqEuRwsiRYm80!a3Q/ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 4642 Xref: news.eternal-september.org comp.lang.vhdl:1059 On Thu, 7 May 2009 09:08:03 -0700 (PDT), hepmehepme@comcast.net wrote: >Sorry if this has been covered already. I am developing a testbench >for a design and I want the behavioral models for external devices to >use random parameters within the constraints of the data sheets. I >figured out how to start up a sim with a seed variable in Modelsim, >but now I'm confused about how to use that seed. Say I have two >processes, each controlling one aspect of an ADC. Does each process >have its own random number stream or do they share some global random >number stream? In other words, does each process access a global seed >or do they each maintain their own seeds. I was thinking that a global >seed may be dangerous because it may change in a non-deterministic >fashion. Here is an example with local seeds. The first process >controls the ADC convert to busy timing, the second process controls >the prop delay through a mux. Each takes the initial value for the >seed from the generic for the testbench and then keeps a local copy of >the seed. Is this the right way to do this? Yes. The seeds must be variables, and variables are local to a process, so each process's randomization has its own seeds and doesn't interfere with the others. This gives you "random stability"; changing the code and behaviour of one process will not affect the random number stream you get in the other. You can get the same effect within a single process, by having additional seed variables - the randomization state is entirely held in two variables, and if you want two independent streams of random numbers within a process you simply create four variables and use two of them in one bunch of randomize calls, and two in the other. >procedure rand_time( >variable seed1, seed2 : inout positive; >min, max : in integer; >result : out time >) Nice; this procedure can go in a package so that it can be re-used across various processes and even various different testbenches. However, it's pretty tedious to be forced to supply the two seeds every time you call the procedure. I like to create a "partially applied" procedure within each process that uses it: process variable s1, s2: positive; -- seeds for this process procedure rand_time ( min, max: in integer; result: out time) is begin -- invoke the general-purpose package procedure -- with the correct seed variables rand_time(s1, s2, min, max, result); end; ....... other declarations etc .... begin ..... rand_time(3, 10, t); -- no need to specify seeds! ..... You can even smarten up the syntax to look like a function call: impure function f_rand_time (min, max: in integer) return time is variable t: time; begin rand_time(s1, s2, min, max, t); return t; end; so that you can then do t := rand_time(3, 10); By the way, stupid question: why does rand_time have INTEGER minimum and maximum parameters? Wouldn't it make more sense for them to be of type TIME? HTH -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.k-dsl.de!newsfeed.freenet.de!bolzen.all.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Thu, 07 May 2009 09:42:32 -0700 Lines: 10 Message-ID: <76ghbpF1chl11U1@mid.individual.net> References: <91f494fa-23af-4a3b-9d59-4f46dd4ef378@z14g2000yqa.googlegroups.com> <6e48c3e0-04b5-4af5-a3bc-ea4a61fbccce@z14g2000yqa.googlegroups.com> <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> <9f6457c4-628b-44bf-965d-f2232285f184@e23g2000vbe.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4GwkGvtqkj+4FH1p8wIC7gQVlvUKMnfkxE65XZ+hS6iA4NlMYT Cancel-Lock: sha1:yPvMAFlpyB5NUAzwwnTnlbstUsQ= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <9f6457c4-628b-44bf-965d-f2232285f184@e23g2000vbe.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1060 Dek wrote: > Thanks all, it seems a good idea, but finally I used Tcl, it's quite > simple Glad you saw the light. tcl is much better at text than vhdl, as is python, bash script, emacs-lisp, perl, ... -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vbi.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Seeding random number generator Date: Thu, 7 May 2009 09:50:24 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: References: <5e8e0bc9-c47e-409b-ad3a-d02f8e6f26e6@x31g2000prc.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241715024 24046 127.0.0.1 (7 May 2009 16:50:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 16:50:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vbi.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1061 comp.arch.fpga:3152 > procedure rand_time( > variable seed1, seed2 : inout positive; > min, max : in integer; > result : out time > ) is > variable rand : real; > begin > uniform(seed1, seed2, rand); > result := (integer(real(min) + (rand * (real(max)-real(min)) ) ))* 1 > ps; > end procedure; Another point: this function doesnt have the correct probability for min and max occuring. If n is the probability for any value occuring, the values of Min and Max themselves have a probability of n/2. This is because the integer conversion function rounds to nearest rather than truncate which means min and max only have a 0-0.5 range each, rather than 0-1.0. eg: Min = 0, Max = 3. result Actual output before rounding 0.0-0.5 0 0.5-1.5 1 1.5-2.5 2 2.5-3.0 3 Therefore 1 and 2 are each twice as likely to occur than 0 and 3. I have a very similar procedure for integers, and found the solution to the problem thus (thanks to who posted the random testing package the other week :) ): procedure rand_int( variable seed1, seed2 : inout positive; min, max : in integer; result : out integer) is variable rand : real; variable val_range : real; begin assert (max >= min) report "Rand_int: Range Error" severity Failure; uniform(seed1, seed2, rand); val_range := real(Max - Min + 1); result := integer( trunc(rand * val_range )) + min; end procedure; This increases the From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!postnews.google.com!g19g2000vbi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Dual Port RAM Inference Date: Thu, 7 May 2009 11:57:34 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241722655 24633 127.0.0.1 (7 May 2009 18:57:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 18:57:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000vbi.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1062 comp.arch.fpga:3154 I am using block rams in three places in my design. One of them is what some call a pseudo dual port with a write port and a read port. Another has a read/write port and a second read port. Both of these have been successfully inferred using some code I found here. However, the third block ram has two read/write ports although they share a common clock. I have not been able to infer this third block ram. I did some searching here and found a number of posts on the subject. But I still have not found anything that will infer full dual port block ram. Anyone else have success? Rick From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r13g2000vbr.googlegroups.com!not-for-mail From: Paddy3118 Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 7 May 2009 11:59:59 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <6da5cbec-56d2-49b0-bea8-f7ef8bc168d9@r13g2000vbr.googlegroups.com> References: NNTP-Posting-Host: 82.40.173.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241722799 25031 127.0.0.1 (7 May 2009 18:59:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 18:59:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000vbr.googlegroups.com; posting-host=82.40.173.26; posting-account=p34d-wkAAAC60rn_Tuk_HKyjfq-hlvCF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1063 Thanks Jonathan and Jim for spending the time to reply, it's appreciated. I gueess my problem is that we always elaborate, in fatc we simulate before releasing anything. Our flows often combine compilation and elaboration in a single script. Because we do projects with both Verilog and VHDl, in practice, we would find I/O miss-matches at roughly the same time when using either Verilog or VHDL but with the VHDL flow we have the extra ordering to do. Both Cadence as well as your example with Mentor seem to recognise some of the practicalities of VHDL in use versus the languages definition and provide ways to alleviaate the problem. Is this insistance on bottom-up compiling really such a win? A better use of todays multi-cores might be to compile in parallel, disregarding compile order, then always elaborate (one or multiple top levels in parallel) for the extra checks that compiling in bottom-up fashion would give you. Just a thought, Donald 'Paddy' McCarthy. From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Peter Alfke Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 7 May 2009 12:45:49 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: NNTP-Posting-Host: 75.18.187.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241725549 26487 127.0.0.1 (7 May 2009 19:45:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 19:45:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=75.18.187.109; posting-account=9YFuAQoAAAA9ibAkXMKsebfCIaLKFs5s User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.27.1 (KHTML, like Gecko) Version/3.2.1 Safari/525.27.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1064 comp.arch.fpga:3156 On May 7, 11:57=A0am, rickman wrote: > I am using block rams in three places in my design. =A0One of them is > what some call a pseudo dual port with a write port and a read port. > Another has a read/write port and a second read port. =A0Both of these > have been successfully inferred using some code I found here. > However, the third block ram has two read/write ports although they > share a common clock. =A0I have not been able to infer this third block > ram. > > I did some searching here and found a number of posts on the subject. > But I still have not found anything that will infer full dual port > block ram. > > Anyone else have success? > > Rick Rick, Xilinx uses the terms "true dual-port" when both ports are read/ write, and "simple dual-port" when one is read, the other write. True dual port is obviously a superset of simple dual port, but there is one limitation: True dual-port cannot handle the widest data path (the one that simple dual port can handle). The reason is that true dual port needs four data buses to connect to the BRAM. Hope this helps. Peter Alfke, from home. From newsfish@newsfish Wed Aug 19 13:24:31 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p4g2000vba.googlegroups.com!not-for-mail From: pontus.stenstrom@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 7 May 2009 12:51:28 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <0a79e851-8cce-42ec-90f3-639d3490d790@p4g2000vba.googlegroups.com> References: NNTP-Posting-Host: 90.233.167.173 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241725888 27579 127.0.0.1 (7 May 2009 19:51:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 19:51:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p4g2000vba.googlegroups.com; posting-host=90.233.167.173; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; sv-SE; rv:1.9.0.10) Gecko/2009042513 Ubuntu/8.04 (hardy) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1065 On 7 Maj, 14:58, Paddy3118 wrote: > Would someone reply with /why/ it is that an instantiated component > must be compiled before that which instantiates it in VHDL? > I find it irksome to create a compile orderwhich may span sources in > multiple libraries and think I would be less annoyed if i knew what > this rule is /for/. > > I've been told that VHDL is based on some mil. language that had this > feature (Algol? Ada?), but if so, what is the reason it was added to > its precursor language, and why do we keep it now? > > I can see that maybe compiler checks for source code updates against > compiled libraries (a la make), are useful, but I cannot find what > this VHDL compile rule gives you. > > - Paddy. > > Thanks in advance for your help. If you are using emacs to edit your files you can generate Makefiles automatically - it/he/she will parse the instantiation hierachy and reflect that in the generated Makefile. You can also run emacs in batch mode to generate the Makefile. As far as I got it, emacs generated makefiles will recompile entities/architectures that instantiate components (i.e. not only direct instatiation) if those component's corresponding entities have changed. This is strictly not needed, but may put some issues to compile time instead of elaboration time. Direct instantiated entities will thus also work. Note that the emacs generated Makefile can not handle dependencies towards external libraries. If you are using modelsim you can use "vmake" to produce a makefile. vmake gives you a makefile (on stdout) that can be used to re-create the current vhdl library you have. So once you are satisfied with your library - run vmake and you get the Makefile required to recreate that library - with correct compile order. All this [makefile stuff] is probably not so interesting when you are actively working in a design (except that you may save some time, only recompiling whats necessary) but much more so when you come back after a year or two, or dive into someone else's design. Regards -- Pontus From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!207.99.111.53.MISMATCH!newspeer1.nac.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 07 May 2009 15:07:15 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 07 May 2009 21:04:46 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-klUxqp+gSaFI+7GPyAjaR7lb2BFJHuzYAH0fqeK9sjiR6qEDuBcRA45dTASxowdwQV5VQsCuBuELI72!3gFvKZrphGY/Iz/w84B3VUyd7XxrAOffXqyDXT+hpUR6puwWWij6/03x08MueV0Jti+ahlvvqrXw!NfSL X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1066 comp.arch.fpga:3157 On Thu, 7 May 2009 11:57:34 -0700 (PDT), rickman wrote: >I am using block rams in three places in my design. One of them is >what some call a pseudo dual port with a write port and a read port. >Another has a read/write port and a second read port. Both of these >have been successfully inferred using some code I found here. >However, the third block ram has two read/write ports although they >share a common clock. I have not been able to infer this third block >ram. > >I did some searching here and found a number of posts on the subject. >But I still have not found anything that will infer full dual port >block ram. > >Anyone else have success? No, I'm banging my head against the same issue right now. The XST User Guide for version 11 says it can be done, but I haven't yet installed ISE11. Can't seem to do it in Quartus either. Nor can I get Synplify or Precision to understand it, though in fairness I haven't done enough rummaging in the docs yet. Back to the dreaded component wizards, I guess :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 7 May 2009 13:08:35 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <3d532494-0d3b-498f-945b-9eb64928b067@s28g2000vbp.googlegroups.com> References: NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241726915 5584 127.0.0.1 (7 May 2009 20:08:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 20:08:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1067 comp.arch.fpga:3158 On May 7, 3:45 pm, Peter Alfke wrote: > On May 7, 11:57 am, rickman wrote: > > > I am using block rams in three places in my design. One of them is > > what some call a pseudo dual port with a write port and a read port. > > Another has a read/write port and a second read port. Both of these > > have been successfully inferred using some code I found here. > > However, the third block ram has two read/write ports although they > > share a common clock. I have not been able to infer this third block > > ram. > > > I did some searching here and found a number of posts on the subject. > > But I still have not found anything that will infer full dual port > > block ram. > > > Anyone else have success? > > > Rick > > Rick, Xilinx uses the terms "true dual-port" when both ports are read/ > write, and "simple dual-port" when one is read, the other write. > True dual port is obviously a superset of simple dual port, but there > is one limitation: > True dual-port cannot handle the widest data path (the one that simple > dual port can handle). The reason is that true dual port needs four > data buses to connect to the BRAM. > Hope this helps. > Peter Alfke, from home. Thanks for the reply. I am only using 18 bit wide memory, so that should still be workable with true dual port ram. I am also only asking for half the size of a single block ram. I assume the tools are capable of setting the high order address bit to a constant. Just in case anyone would like to see the code... DPT_INFR: process (SysClk) begin if (rising_edge(SysClk)) then DatRdAddr <= DatAddr; RetRdAddr <= RetAddr; if (DatPop = '0') then InstRAM(to_integer(unsigned(DatAddr))) <= std_logic_vector (DatToS); end if; if (RetPop = '0') then InstRAM(to_integer(unsigned(RetAddr))) <= std_logic_vector (RetToS); end if; end if; end process DPT_INFR; DatMem <= InstRAM(to_integer(unsigned(DatRdAddr))); RetMem <= InstRAM(to_integer(unsigned(RetRdAddr))); -- Rick From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!t10g2000vbg.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 7 May 2009 13:14:33 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241727274 32039 127.0.0.1 (7 May 2009 20:14:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 20:14:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t10g2000vbg.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1068 comp.arch.fpga:3160 On May 7, 4:04=A0pm, Jonathan Bromley wrote: > On Thu, 7 May 2009 11:57:34 -0700 (PDT), rickman > wrote: > > >I am using block rams in three places in my design. =A0One of them is > >what some call a pseudo dual port with a write port and a read port. > >Another has a read/write port and a second read port. =A0Both of these > >have been successfully inferred using some code I found here. > >However, the third block ram has two read/write ports although they > >share a common clock. =A0I have not been able to infer this third block > >ram. > > >I did some searching here and found a number of posts on the subject. > >But I still have not found anything that will infer full dual port > >block ram. > > >Anyone else have success? > > No, I'm banging my head against the same issue right now. =A0 > The XST User Guide for version 11 says it can be done, > but I haven't yet installed ISE11. =A0Can't seem to do it in > Quartus either. =A0Nor can I get Synplify or Precision > to understand it, though in fairness I haven't done > enough rummaging in the docs yet. > > Back to the dreaded component wizards, I guess :-( > -- > Jonathan Bromley, Consultant I seem to recall that a thread here just a few months ago came to the same conclusion. But I also found info saying that it could be done, they just didn't give examples that were for "Write First" read access which I need. I also recall that one of the problems was that most of the code specifies some particular operation when both ports write to the same address simultaneously while the ram operation is undefined. I think there is a similar issue when one port writes to an address while the other port reads the same address. Because of a possible mismatch between synthesis and simulation, they don't infer a block ram or infer a block ram with additional logic. In my case I'm getting 9000 FFs! You would think if there were an inference solution, they would make it crystal clear in the docs, wouldn't you? Rick From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Thu, 07 May 2009 15:40:43 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 07 May 2009 21:38:14 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 48 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-RtKJUaiRRTczrRZNRxpkuax/k2TS8MZH33Ka8wtK47nEiwD9O0mO6FISzQUoIvsOQiayFiP4ygtcDMj!syw7XYMPUUF6bth2ALYU2HwMV6PHtNhrsfW0ZvQPGfAszGUnXS4Y1RRvcudYJdKtkgRq18X1pY3m!jN9d X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2831 Xref: news.eternal-september.org comp.lang.vhdl:1069 comp.arch.fpga:3164 >>  Nor can I get Synplify or Precision >> to understand it, though in fairness I haven't done >> enough rummaging in the docs yet. OK, I take it all back, I was doing something stupid - no change there then :-) Precision Synthesis correctly generated write-first dual-port blockRAM in Spartan3 from this code: reg [DATA_BITS-1:0] mem [0:(1< Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Seeding random number generator Date: Thu, 7 May 2009 14:54:44 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <9b14ad4d-1433-4ddd-a441-2a891cccfee3@d25g2000prn.googlegroups.com> References: <5e8e0bc9-c47e-409b-ad3a-d02f8e6f26e6@x31g2000prc.googlegroups.com> NNTP-Posting-Host: 98.232.132.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241733284 19352 127.0.0.1 (7 May 2009 21:54:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 May 2009 21:54:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d25g2000prn.googlegroups.com; posting-host=98.232.132.172; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1070 comp.arch.fpga:3168 You can simplify this greatly by using the packages that I developed. They layer on top of procedure uniform. Packages and usage notes are available at: http://www.synthworks.com/downloads/index.htm The presentation focuses on randomizing integers, however, time values can be generated by multiplying by 1 ns. To inspire you, your process would be: Compile packages - directions are in the download Use SynthWorks.RandomPkg.all ; -- reference package process variable RV : RandomPType ; -- declare randomization variable begin -- Initialize Seed -- done once RV.SetSeed( (7, 1) ) ; -- optional if you only are doing one thread of randomization ... p := 1 ns * RV.RandInt(MIN_DELAY, MAX_DELAY) ; Cheers, Jim SynthWorks VHDL Training P.S. We teach randomization plus self-checking, transaction-based testing, and verification data structures (linked-lists, scoreboards, memories), in our VHDL Testbenches and Verification classes. See: http://www.synthworks.com/vhdl_testbench_verification.htm From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x29g2000prf.googlegroups.com!not-for-mail From: Peter Alfke Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 7 May 2009 18:06:41 -0700 (PDT) Organization: http://groups.google.com Lines: 65 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> NNTP-Posting-Host: 75.18.187.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241744802 24909 127.0.0.1 (8 May 2009 01:06:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 01:06:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x29g2000prf.googlegroups.com; posting-host=75.18.187.109; posting-account=9YFuAQoAAAA9ibAkXMKsebfCIaLKFs5s User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.27.1 (KHTML, like Gecko) Version/3.2.1 Safari/525.27.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1071 comp.arch.fpga:3169 On May 7, 1:38=A0pm, Jonathan Bromley wrote: > >> =A0Nor can I get Synplify or Precision > >> to understand it, though in fairness I haven't done > >> enough rummaging in the docs yet. > > OK, I take it all back, I was doing something > stupid - no change there then :-) > > Precision Synthesis correctly generated > write-first dual-port blockRAM in Spartan3 > from this code: > > =A0 reg [DATA_BITS-1:0] mem [0:(1< > =A0 always @(posedge clock0) begin > =A0 =A0 if (WrEna0) mem[adrs0] =3D dataWr0; > =A0 =A0 dataRd0 <=3D mem[adrs0]; > =A0 end > =A0 always @(posedge clock1) begin > =A0 =A0 if (WrEna1) mem[adrs1] =3D dataWr1; > =A0 =A0 dataRd1 <=3D mem[adrs1]; > =A0 end > > but NOTE CAREFULLY that I kept the two clocks separate; > with a common clock, I got the anti-contention circuit > (equality check on addresses for simultaneous write). > So I don't know how this would pan out if I were to > put this block down into a bigger design where clock0 > and clock1 happened to be the same signal. > > XST gave me the right results for write-first (use <=3D > instead of =3D in the write assignments) even with a > single clock, but I haven't yet sorted out the read-first > form. > > I'll try to do some more work on this with up-to-date > versions of the various tools and report back. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Here is a short Xiinx tutorial: When you write, you also ("or free") perform a read operation on the same port, at the same address. Clock timing is internally manipulated such that you either read first before writing, or write first before reading. You can also select to not update the read output. This can get tricky when you use both ports with a common address. The small timing adjustment might not be big enough to cover up any possible clock timing differences between the two ports. All this is irrelevant if you do not care about the "free" read output during a write access, or you know that you will never access the same location from both ports "simultaneously". Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o30g2000vbc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Thu, 7 May 2009 20:52:47 -0700 (PDT) Organization: http://groups.google.com Lines: 74 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241754767 26517 127.0.0.1 (8 May 2009 03:52:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 03:52:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o30g2000vbc.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1072 comp.arch.fpga:3172 On May 7, 9:06=A0pm, Peter Alfke wrote: > On May 7, 1:38=A0pm, Jonathan Bromley > wrote: > > > > > >> =A0Nor can I get Synplify or Precision > > >> to understand it, though in fairness I haven't done > > >> enough rummaging in the docs yet. > > > OK, I take it all back, I was doing something > > stupid - no change there then :-) > > > Precision Synthesis correctly generated > > write-first dual-port blockRAM in Spartan3 > > from this code: > > > =A0 reg [DATA_BITS-1:0] mem [0:(1< > > =A0 always @(posedge clock0) begin > > =A0 =A0 if (WrEna0) mem[adrs0] =3D dataWr0; > > =A0 =A0 dataRd0 <=3D mem[adrs0]; > > =A0 end > > =A0 always @(posedge clock1) begin > > =A0 =A0 if (WrEna1) mem[adrs1] =3D dataWr1; > > =A0 =A0 dataRd1 <=3D mem[adrs1]; > > =A0 end > > > but NOTE CAREFULLY that I kept the two clocks separate; > > with a common clock, I got the anti-contention circuit > > (equality check on addresses for simultaneous write). > > So I don't know how this would pan out if I were to > > put this block down into a bigger design where clock0 > > and clock1 happened to be the same signal. > > > XST gave me the right results for write-first (use <=3D > > instead of =3D in the write assignments) even with a > > single clock, but I haven't yet sorted out the read-first > > form. > > > I'll try to do some more work on this with up-to-date > > versions of the various tools and report back. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > Here is a short Xiinx tutorial: > When you write, you also ("or free") perform a read operation on the > same port, at the same address. > Clock timing is internally manipulated such that you either read first > before writing, or write first before reading. You can also select to > not update the read output. > This can get tricky when you use both ports with a common address. The > small timing adjustment might not be big enough to cover up any > possible clock timing differences between the two ports. > > All this is irrelevant if you do not care about the "free" read output > during a write access, or you know that you will never access the same > location from both ports "simultaneously". > Peter Alfke I don't think anyone has a problem understanding how the parts work. The issue we are having is how to specify the hardware we want in the HDL. Rick From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "Volker" Newsgroups: comp.lang.vhdl Subject: Problem with case-statement Date: Fri, 8 May 2009 07:07:09 +0200 Lines: 66 Message-ID: <76ht1kF1cvb60U1@mid.individual.net> X-Trace: individual.net gSseZk0lNAIJhC+p9Tg0LQIjB4oxrYxOtHsV6HZFo+LnWysr0= Cancel-Lock: sha1:AuJ4A9io3ZlR+FtQjZLMT/mj4WU= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Xref: news.eternal-september.org comp.lang.vhdl:1073 Hi, I have a VHDL Design containing a case statement. If I compile this design with QuartusII 9.0 I get no error; compiling this design in ModelSim Altera Starter Edition I get some errors like "Array type case expression must be of a locally static subtype" and "Case choice must be a locally static expression". I Think the reason is that I use a "generic expression" in the case-statement. Why did Quartus compile that without errors and ModelSim do not? The synthesized Design will work, but I will do the simulation as well. Any ideas to solve the problem? The code: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity VERSION_REGISTER is generic(CPLD_VER: NATURAL:= 0; HW_VER : NATURAL:= 2; HW_TYPE : NATURAL:= 3; MAX_CS_LINES: POSITIVE:= 16;-- max generated CS-Lines in complete design START_CS_NR : NATURAL:= 0);-- CS-Line number of first version-register port(CS : in BIT_VECTOR((MAX_CS_LINES-1) downto 0); nRD : in STD_LOGIC; DATA : out STD_LOGIC_VECTOR(7 downto 0)); end VERSION_REGISTER; architecture BEHAVIOR of VERSION_REGISTER is begin process(CS, nRD) variable ZERO : BIT_VECTOR((MAX_CS_LINES-1) downto 0):=(others=>'0');-- zero vector of length MAX_CS_LINES variable SHIFT_PATTERN : BIT_VECTOR((MAX_CS_LINES-1) downto 0):=(0=>'1',others=>'0');-- pattern of length MAX_CS_LINES all zero but Bit0=1 begin if (CS = ZERO) then -- if no CS for CPLD active, set Databus to high Z DATA <= (others =>'Z'); elsif (nRD'EVENT and nRD='0') then case CS is when (SHIFT_PATTERN sll START_CS_NR) => DATA <= CONV_STD_LOGIC_VECTOR(CPLD_VER, 8);--CPLD version register when (SHIFT_PATTERN sll (START_CS_NR +1))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_VER, 8);--HW version register when (SHIFT_PATTERN sll (START_CS_NR +2))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_TYPE, 8);--HW type register when others => DATA <= (others =>'Z'); end case; end if; end process; end BEHAVIOR; Thanks for help! From newsfish@newsfish Wed Aug 19 13:24:32 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!t11g2000vbc.googlegroups.com!not-for-mail From: Paddy3118 Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 7 May 2009 23:51:37 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: References: <0a79e851-8cce-42ec-90f3-639d3490d790@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 82.45.18.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241765497 26740 127.0.0.1 (8 May 2009 06:51:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 06:51:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t11g2000vbc.googlegroups.com; posting-host=82.45.18.116; posting-account=p34d-wkAAAC60rn_Tuk_HKyjfq-hlvCF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1074 On May 7, 8:51=A0pm, pontus.stenst...@gmail.com wrote: > On 7 Maj, 14:58, Paddy3118 wrote: > > > > > Would someone reply with /why/ it is that an instantiated component > > must be compiled before that which instantiates it in VHDL? > > I find it irksome to create a compile orderwhich may span sources in > > multiple libraries and think I would be less annoyed if i knew what > > this rule is /for/. > > > I've been told that VHDL is based on some mil. language that had this > > feature (Algol? Ada?), but if so, what is the reason it was added to > > its precursor language, and why do we keep it now? > > > I can see that maybe compiler checks for source code updates against > > compiled libraries (a la make), are useful, but I cannot find what > > this VHDL compile rule gives you. > > > - Paddy. > > > Thanks in advance for your help. > > If you are using emacs to edit your files you can generate > Makefiles automatically - it/he/she will parse the instantiation > hierachy and reflect that in the generated Makefile. > You can also run emacs in batch mode to generate the Makefile. > > As far as I got it, emacs generated makefiles will recompile > entities/architectures that instantiate components (i.e. not > only direct instatiation) if those component's corresponding > entities have changed. > This is strictly not needed, but may put some issues to compile > time instead of elaboration time. Direct instantiated entities > will thus also work. > > Note that the emacs generated Makefile can not handle > dependencies towards external libraries. > > If you are using modelsim you can use "vmake" to produce a > makefile. vmake gives you a makefile (on stdout) that can be used > to re-create the current vhdl library you have. So once you > are satisfied with your library - run vmake and you get > the Makefile required to recreate that library - with correct > compile order. > > All this [makefile stuff] is probably not so interesting when > you are actively working in a design (except that you may save > some time, only recompiling whats necessary) but much more so > when you come back after a year or two, or dive into someone > else's design. > > Regards -- Pontus Thanks Pontus for your reply. It is not so much how to create the compile order, it is the need to do so in the first place that I question. - Paddy. From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p4g2000vba.googlegroups.com!not-for-mail From: Paddy3118 Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 7 May 2009 23:51:46 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <09784c10-3863-4e05-a4ef-8033a7e24d0a@p4g2000vba.googlegroups.com> References: <0a79e851-8cce-42ec-90f3-639d3490d790@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 82.45.18.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241765506 26753 127.0.0.1 (8 May 2009 06:51:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 06:51:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p4g2000vba.googlegroups.com; posting-host=82.45.18.116; posting-account=p34d-wkAAAC60rn_Tuk_HKyjfq-hlvCF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1075 On May 7, 8:51=A0pm, pontus.stenst...@gmail.com wrote: > On 7 Maj, 14:58, Paddy3118 wrote: > > > > > Would someone reply with /why/ it is that an instantiated component > > must be compiled before that which instantiates it in VHDL? > > I find it irksome to create a compile orderwhich may span sources in > > multiple libraries and think I would be less annoyed if i knew what > > this rule is /for/. > > > I've been told that VHDL is based on some mil. language that had this > > feature (Algol? Ada?), but if so, what is the reason it was added to > > its precursor language, and why do we keep it now? > > > I can see that maybe compiler checks for source code updates against > > compiled libraries (a la make), are useful, but I cannot find what > > this VHDL compile rule gives you. > > > - Paddy. > > > Thanks in advance for your help. > > If you are using emacs to edit your files you can generate > Makefiles automatically - it/he/she will parse the instantiation > hierachy and reflect that in the generated Makefile. > You can also run emacs in batch mode to generate the Makefile. > > As far as I got it, emacs generated makefiles will recompile > entities/architectures that instantiate components (i.e. not > only direct instatiation) if those component's corresponding > entities have changed. > This is strictly not needed, but may put some issues to compile > time instead of elaboration time. Direct instantiated entities > will thus also work. > > Note that the emacs generated Makefile can not handle > dependencies towards external libraries. > > If you are using modelsim you can use "vmake" to produce a > makefile. vmake gives you a makefile (on stdout) that can be used > to re-create the current vhdl library you have. So once you > are satisfied with your library - run vmake and you get > the Makefile required to recreate that library - with correct > compile order. > > All this [makefile stuff] is probably not so interesting when > you are actively working in a design (except that you may save > some time, only recompiling whats necessary) but much more so > when you come back after a year or two, or dive into someone > else's design. > > Regards -- Pontus Thanks Pontus for your reply. It is not so much how to create the compile order, it is the need to do so in the first place that I question. - Paddy. From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!nx02.iad01.newshosting.com!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!novia!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 08 May 2009 03:47:37 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Problem with case-statement Date: Fri, 08 May 2009 09:45:06 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <2rr7059v990e07587av65jtqlr42a88o40@4ax.com> References: <76ht1kF1cvb60U1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 62 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-8Dafw7L8Zqv+CXS3iL5QcQLv0oEBZskGLgQSeFkyI3ahqnIh2siUHk9MM3AXelDFyFp6lYqJWe5IJHU!E/YJB+X1PFc7qbWu6YeipTmruMuGOv0z9eqXgSWf/K9tkS0vnUeDcTaF0yU4+hJ2tluamd+XGecJ!YCil X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1076 On Fri, 8 May 2009 07:07:09 +0200, "Volker" wrote: >I have a VHDL Design containing a case statement. If I compile this design >with QuartusII 9.0 I get no error; compiling this design in ModelSim Altera >Starter Edition I get some errors like "Array type case expression must be >of a locally static subtype" and "Case choice must be a locally static >expression". > >I Think the reason is that I use a "generic expression" in the >case-statement. Partly, yes. Generics are "globally static", whereas case choices must be "locally static" - a much stronger requirement. > Why did Quartus compile that without errors and ModelSim do >not? ModelSim rather strictly obeys the VHDL language rules, and correctly gave you an error for code that is technically wrong. Quartus (like many synthesis tools) understands what you mean, and bends the language rules enough to make it work. >Any ideas to solve the problem? It is possible to rewrite the code in various ways, but the simplest solution is to ask ModelSim to bend the rules in the same way as Quartus. Look inside your modelsim.ini file and find this section: ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Treat as errors: ; case statement static warnings ; warnings caused by aggregates that are not locally static ; Overrides NoCaseStaticError, NoOthersStaticError settings. ; PedanticErrors = 1 Un-comment the line "NoCaseStaticError = 1". Make sure that PedanticErrors is NOT set (the standard default is OK). VHDL language pedants will perhaps be displeased with me for telling you this, but it's useful to know..... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading Date: Fri, 08 May 2009 11:37:37 +0200 Organization: 502 You are not allowed to talk Lines: 38 Sender: newsmailcomp6@gustad.com Message-ID: <874ovwlyu6.fsf@pangea.home.gustad.com> References: <87tz3x88ft.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.eternal-september.org U2FsdGVkX19hKfUUhzgzLnJGW4dZLO2XuzsV/xDqWUZJn5qwuLxgPg3o7s/9cHFEawDWkfvnuTQlLCjyQTSS1hXky4P/mXAZ0PkaT8vJwzbBNxpJjlJlpn0r1WSM36PreyRzQHqbbLs6vC6HoDuiPQ== X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Fri, 8 May 2009 09:37:45 +0000 (UTC) X-Auth-Sender: U2FsdGVkX1/EkHzVMfP8A2e2n8DYVFJZw8fcqWj1GpA= Cancel-Lock: sha1:yMBkb1gWYuPq0HH2DF5EPBav+Zo= sha1:jgBAsw08JM0/09R8O+eRa1j4UWU= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1077 Marcus Harnisch writes: > Currently EDA tool makers seem to agree that the overhead of > resynchronizing many individual simulation threads back to the HDL > timing model is simply too big to make it worthwhile. Synopsys VCS claims 2X performance increase on multicore CPU's: "VCS® multicore technology delivers a 2x verification speed-up that helps users find design bugs early in the product development cycle. VCS multicore technology cuts down verification time by running the design, testbench, assertions, coverage and debug in parallel on machines with multiple cores." http://www.synopsys.com/tools/verification/functionalverification/pages/vcs.aspx If you can partition the design so that you minimize the latency intensive communication (this might result in dynamic partition and process migration) you should be able to archive a decent speed increase. An FPGA is a parallel processor where each LE is a small processor element. However, the latency between each LE is extremely short, which is not the case for some memory, or even network attached bus. Hence the challenge is to hide the latency. A very complex problem, which is very difficult to bolt-on to an existing simulator. Probably easier to design from scratch, but still very complex. Hopefully we will see more parallel simulators in the future. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Fri, 08 May 2009 07:45:07 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Fri, 08 May 2009 13:42:38 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 54 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-062Cb3TjLqKEAf9ZNBF8Q4BbuYJ7+LXiQZf4HCab/JLaOd9bqGTNi8midLlaNvEJBaGderF1OMyPock!mVisUa83ocViA9P8hN1CuLi4PrhqbwZDb3z5cpMJrViL6lJtrJFn6hXpdbTk3YFig8Rat8mqsNFv!Pb/S X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1078 comp.arch.fpga:3179 On Thu, 7 May 2009 20:52:47 -0700 (PDT), rickman wrote: >On May 7, 9:06 pm, Peter Alfke wrote: >> Here is a short Xilinx tutorial: >I don't think anyone has a problem understanding how the parts work. >The issue we are having is how to specify the hardware we want in the >HDL. Rick is right, but Peter's explanation is perhaps timely. It's comparatively easy to describe both write-first and read-first behavior in HDL if there is only one write port, but it's a lot more tricky (especially in VHDL) if there are two write ports with independent clocks. But the main problem is as Peter pointed out: there are some corner cases (for example, simultaneous write to the same location from both write ports) whose behavior is ill-defined. Of course, sensible designers will ensure that their memory controller never allows those ill-defined cases to occur. But you can't easily explain to your synthesis tool that you have done so. As a result, the synth tool must take your HDL description at face value, and do whatever it takes to ensure that the finished hardware obeys that description *in all cases* - hence the nonsense with logic (which wouldn't work right anyway) to avoid conflicting writes to the same address, because your HDL says that the behavior is well-defined but the memory doesn't work quite like that. As promised, I'll take this offline, do some work on it over the weekend, and report back. I haven't yet seen a concise description of the right way to cope with this across a range of synth tools, so it's something I'd like to do anyway. If all else fails, I can grudgingly go back to instantiation of wizard-generated components. But I don't like doing that; it screws up my design's portability, makes simulation tiresome and slow, and makes the HDL code butt-ugly. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "Volker" Newsgroups: comp.lang.vhdl Subject: Re: Problem with case-statement Date: Fri, 8 May 2009 16:17:24 +0200 Lines: 46 Message-ID: <76it9fF1cs2qiU1@mid.individual.net> References: <76ht1kF1cvb60U1@mid.individual.net> <2rr7059v990e07587av65jtqlr42a88o40@4ax.com> X-Trace: individual.net JjrHw8U3Vs0Ft/n83i5YFAsnv66+1Xyo1njVu+wbmRLBfOdMU= Cancel-Lock: sha1:l/qDVXAVgqcCRT5qG3VUUcZVdpI= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Xref: news.eternal-september.org comp.lang.vhdl:1079 Thanks for telling this, but I use the ModelSim Altera Starter Edition and in the modelsim.ini file there is no such entry :-( Can I add these commands? >>Any ideas to solve the problem? > > It is possible to rewrite the code in various ways, > but the simplest solution is to ask ModelSim to > bend the rules in the same way as Quartus. Look > inside your modelsim.ini file and find this section: > > ; Keep silent about case statement static warnings. > ; Default is to give a warning. > ; NoCaseStaticError = 1 > > ; Keep silent about warnings caused by aggregates that are not locally > static. > ; Default is to give a warning. > ; NoOthersStaticError = 1 > > ; Treat as errors: > ; case statement static warnings > ; warnings caused by aggregates that are not locally static > ; Overrides NoCaseStaticError, NoOthersStaticError settings. > ; PedanticErrors = 1 > > Un-comment the line "NoCaseStaticError = 1". Make sure > that PedanticErrors is NOT set (the standard default is OK). > > VHDL language pedants will perhaps be displeased with me > for telling you this, but it's useful to know..... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 08 May 2009 09:41:11 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Problem with case-statement Date: Fri, 08 May 2009 15:43:36 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <76ht1kF1cvb60U1@mid.individual.net> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 184 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-w7QBH1csjj2k1zl40/aAW8wSD75oesYy7qKuqGk+6VNErD66KF3/ogrBn4L67NyA0P0bjGxLTRU8y9D!qXyTWxz63xHZdDoPVV/VJHJhDYx1Mi61Q8MW2DzW3ZFM6bLYAm7/U13p3/SgAAEBGk/cgLUOnkXP!63E= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1080 On Fri, 8 May 2009 07:07:09 +0200, "Volker" wrote: >Hi, > >I have a VHDL Design containing a case statement. If I compile this design >with QuartusII 9.0 I get no error; compiling this design in ModelSim Altera >Starter Edition I get some errors like "Array type case expression must be >of a locally static subtype" and "Case choice must be a locally static >expression". > >I Think the reason is that I use a "generic expression" in the >case-statement. Why did Quartus compile that without errors and ModelSim do >not? The synthesized Design will work, but I will do the simulation as well. > >Any ideas to solve the problem? In my opinion, CASE really comes into its own where the expression arms contain ranges or lists. case Inst is when Mult downto Add => ... when Load | Store => ... Synthesis can take advantage of this to optimise well. The problem here is that the actual value of the START_CS_NR generic is not known when the entity is compiled. I believe this makes the optimisation impossible; so CASE cannot really do better than IF/THEN/ELSIF. To reject the code altogether may be a bit severe, but I (grudgingly) appreciate the warning that something is amiss. IF is not subject to the same restrictions as CASE, and is just as compact in this example. So one option is... ----------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; entity VERSION_REGISTER is generic( CPLD_VER : NATURAL := 0; HW_VER : NATURAL := 2; HW_TYPE : NATURAL := 3; MAX_CS_LINES: POSITIVE:= 16; -- max generated CS-Lines in complete design START_CS_NR : NATURAL :=0); -- CS-Line number of first version-register port( CS : in BIT_VECTOR((MAX_CS_LINES-1) downto 0); nRD : in STD_LOGIC; DATA : out STD_LOGIC_VECTOR(7 downto 0)); end VERSION_REGISTER; architecture BEHAVIOR of VERSION_REGISTER is begin process(CS, nRD) constant ZERO : BIT_VECTOR((MAX_CS_LINES-1) downto 0):=(others=>'0'); constant SHIFT_PATTERN : BIT_VECTOR((MAX_CS_LINES-1) downto 0):= (0=>'1',others=>'0'); function SLV8(NUM : NATURAL) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(to_unsigned(NUM, 8)); end SLV8; begin if CS = ZERO then -- if no CS for CPLD active, set Databus to high Z DATA <= (others =>'Z'); elsif (nRD'EVENT and nRD='0') then if CS = SHIFT_PATTERN sll (START_CS_NR) then DATA <= SLV8(CPLD_VER); elsif CS = SHIFT_PATTERN sll (START_CS_NR + 1) then DATA <= SLV8(HW_VER); elsif CS = SHIFT_PATTERN sll (START_CS_NR + 2) then DATA <= SLV8(HW_TYPE); else DATA <= (others =>'Z'); end if; end if; end process; end BEHAVIOR; ----------------------------- My preference is to use the standard libs, not std_logic_arith etc. I also prefer to factor out type conversion ugliness into a function, wherever it's used more than once. (I also omit the redundant parentheses around expressions; it helps to remind me not to descend into bad habits from my old C days) Another solution is to make START_CS_NR visible at compile time. One way is to place it in a package, instead of passing it as a generic. Whether this is a good thing is a design decision; should it really be variable on an instance-by-instance basis in the same design, or is it fixed for this design but subject to change in a future version? I suggest you might want the latter for MAX_CS_LINES, or there is a danger of propagating different widths of chip select bus around different parts of the design, especially when you have to change it and forget to update one generic. If you can live with defining the register map in a package, here's another option... (the package is a separate file; "use work.mytypes.all;" in every file that needs it) ----------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; package mytypes is constant MAX_CS_LINES : POSITIVE:= 16; -- max generated CS-Lines in complete design constant START_VERSION_CS_NR : NATURAL :=0; -- add other blocks to register map here constant START_DMA_CS_NR : NATURAL :=3; -- new type removes a lot of clutter and helps make the design intent clearer subtype CS_Type is BIT_VECTOR((MAX_CS_LINES-1) downto 0); constant ZERO : CS_Type := (others=>'0'); constant SHIFT_PATTERN : CS_Type := (0=>'1', others=>'0'); -- define the register map in this package constant CPLD_VER_CS : CS_Type := SHIFT_PATTERN sll START_VERSION_CS_NR; constant HW_VER_CS : CS_Type := SHIFT_PATTERN sll (START_VERSION_CS_NR + 1); constant HW_TYPE_CS : CS_Type := SHIFT_PATTERN sll (START_VERSION_CS_NR + 2); -- ditto for DMA regs, whatever -- Trivially easy to port to 16-bit or even 23-bit(!) later... subtype Data_Type is STD_LOGIC_VECTOR(7 downto 0); function To_Data(NUM : NATURAL) return Data_Type; end package mytypes; package body mytypes is function To_Data(NUM : NATURAL) return Data_Type is begin return STD_LOGIC_VECTOR(to_unsigned(NUM, Data_Type'Length)); end To_Data; end package body mytypes; ----------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; use work.mytypes.all; entity VERSION_REGISTER is generic( CPLD_VER : NATURAL := 0; HW_VER : NATURAL := 2; HW_TYPE : NATURAL := 3); port( CS : in CS_Type; nRD : in STD_LOGIC; DATA : out Data_Type ); end VERSION_REGISTER; architecture BEHAVIOR of VERSION_REGISTER is begin process(CS, nRD) -- constant ZERO : CS_Type := (others=>'0'); -- moved to package begin if CS = ZERO then -- if no CS for CPLD active, set Databus to high Z DATA <= (others =>'Z'); elsif nRD'EVENT and nRD='0' then case CS is -- when SHIFT_PATTERN sll START_CS_NR => DATA <= To_Data(CPLD_VER); when CPLD_VER_CS => DATA <= To_Data(CPLD_VER); when HW_VER_CS => DATA <= To_Data(HW_VER); when HW_TYPE_CS => DATA <= To_Data(HW_TYPE); when others => DATA <= (others =>'Z'); end case; end if; end process; end BEHAVIOR; ----------------------------- From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Fri, 08 May 2009 08:20:00 -0700 Lines: 26 Message-ID: <4A044DA0.60705@gmail.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net e+96jsepkWe0Ghy/XdxwpQDz76f7ID3KltkoZ1JYvRejbT5aHz Cancel-Lock: sha1:mRe/hjutVwF6UV0s/eD53U8UdIU= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1081 comp.arch.fpga:3186 Jonathan Bromley wrote: > I haven't > yet seen a concise description of the right way to > cope with this across a range of synth tools, so > it's something I'd like to do anyway. I long ago gave up trying, so I will be interested to see your results. > If all else fails, I can grudgingly go back to > instantiation of wizard-generated components. > But I don't like doing that; it screws up my > design's portability, makes simulation tiresome > and slow, and makes the HDL code butt-ugly. I agree with the downside, but I stick with Peter's "simple dual-port" block rams which are portable across vendors and tools, with the same template. This is all I need for fifos. I use multiple instances and my own synchronous controllers to make more complicated memories. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!x31g2000prc.googlegroups.com!not-for-mail From: peter@xilinx.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Fri, 8 May 2009 10:01:30 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241802090 11209 127.0.0.1 (8 May 2009 17:01:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 17:01:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x31g2000prc.googlegroups.com; posting-host=149.199.62.254; posting-account=XWkVzQoAAABTt_uQ5LvDXJs5hs3-FJh- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.18.1 (KHTML, like Gecko) Version/3.1.2 Safari/525.20.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1082 comp.arch.fpga:3194 On May 8, 8:20=A0am, Mike Treseler wrote: > Jonathan Bromley wrote: > > I haven't > > yet seen a concise description of the right way to > > cope with this across a range of synth tools, so > > it's something I'd like to do anyway. > > I long ago gave up trying, so I will be interested > to see your results. > > > If all else fails, I can grudgingly go back to > > instantiation of wizard-generated components. > > But I don't like doing that; it screws up my > > design's portability, makes simulation tiresome > > and slow, and makes the HDL code butt-ugly. > > I agree with the downside, > but I stick with Peter's "simple dual-port" block rams > which are portable across vendors and tools, > with the same template. > > This is all I need for fifos. > I use multiple instances and my own synchronous > controllers to make more complicated memories. > > =A0 -- Mike Treseler This is not a Xilinx or Altera circuit design problem, nor is it a VHDL problem. It is a systems design issue. My favorite solution is to clock the two ports on opposite clock polarity edges. "If you cannot solve it, avoid it." Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:33 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Fri, 08 May 2009 11:07:58 -0700 Lines: 23 Message-ID: <76januF1d6isqU1@mid.individual.net> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net QTwo+bsH0ApZ3RWKelQiJQmeCKl4XpMDsClkLknC8Qi+kW5QzE Cancel-Lock: sha1:ZkjZC51T5lVmvSJ0CpPbyrYnM24= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1083 comp.arch.fpga:3196 peter@xilinx.com wrote: > This is not a Xilinx or Altera circuit design problem, nor is it a > VHDL problem. > It is a systems design issue. Some existing FPGA structures like PLLs and dpram arbiters can't be described by a synchronous process. My synthesis code can either instance the netlist or use something else. > My favorite solution is to clock the two ports on opposite clock > polarity edges. If I couldn't avoid two write ports, I would time slice one clock. > "If you cannot solve it, avoid it." True. But I can't avoid talking about it ;) ... and what is the time limit on 'cannot solve it'? -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Problem with case-statement Date: Fri, 08 May 2009 11:17:56 -0700 Lines: 20 Message-ID: <76jbakF1cp7t6U1@mid.individual.net> References: <76ht1kF1cvb60U1@mid.individual.net> <2rr7059v990e07587av65jtqlr42a88o40@4ax.com> <76it9fF1cs2qiU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net XI5plWBWJsVDEh56YmCw6Q+tvFCMGg1NQOVcL08gG3XgC3H8HG Cancel-Lock: sha1:Liaztfk9ZzH70nSpKI8a8moSihs= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <76it9fF1cs2qiU1@mid.individual.net> Xref: news.eternal-september.org comp.lang.vhdl:1084 Volker wrote: > Thanks for telling this, but I use the ModelSim Altera Starter Edition and > in the modelsim.ini file there is no such entry :-( > Can I add these commands? 89 Wed May 06 tmp> mkdir foo 90 Fri May 08 tmp> cd foo 91 Fri May 08 tmp/foo> ls 92 Fri May 08 tmp/foo> vlib work 93 Fri May 08 tmp/foo> ls work 94 Fri May 08 tmp/foo> vmap work work Copying /flip/usr1/modeltech/linux/../modelsim.ini to modelsim.ini Modifying modelsim.ini 95 Fri May 08 tmp/foo> ls modelsim.ini work -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!t11g2000vbc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Fri, 8 May 2009 11:54:21 -0700 (PDT) Organization: http://groups.google.com Lines: 75 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> NNTP-Posting-Host: 71.176.139.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241808861 8889 127.0.0.1 (8 May 2009 18:54:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 May 2009 18:54:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t11g2000vbc.googlegroups.com; posting-host=71.176.139.249; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1085 comp.arch.fpga:3197 On May 8, 8:42 am, Jonathan Bromley wrote: > On Thu, 7 May 2009 20:52:47 -0700 (PDT), rickman wrote: > >On May 7, 9:06 pm, Peter Alfke wrote: > >> Here is a short Xilinx tutorial: > >I don't think anyone has a problem understanding how the parts work. > >The issue we are having is how to specify the hardware we want in the > >HDL. > > Rick is right, but Peter's explanation is perhaps > timely. It's comparatively easy to describe both > write-first and read-first behavior in HDL if there > is only one write port, but it's a lot more tricky > (especially in VHDL) if there are two write ports > with independent clocks. But the main problem is > as Peter pointed out: there are some corner cases > (for example, simultaneous write to the same location > from both write ports) whose behavior is ill-defined. > Of course, sensible designers will ensure that > their memory controller never allows those ill-defined > cases to occur. But you can't easily explain to > your synthesis tool that you have done so. As a result, > the synth tool must take your HDL description at face > value, and do whatever it takes to ensure that the > finished hardware obeys that description *in all > cases* - hence the nonsense with logic (which > wouldn't work right anyway) to avoid conflicting > writes to the same address, because your HDL says > that the behavior is well-defined but the memory > doesn't work quite like that. > > As promised, I'll take this offline, do some work > on it over the weekend, and report back. I haven't > yet seen a concise description of the right way to > cope with this across a range of synth tools, so > it's something I'd like to do anyway. > > If all else fails, I can grudgingly go back to > instantiation of wizard-generated components. > But I don't like doing that; it screws up my > design's portability, makes simulation tiresome > and slow, and makes the HDL code butt-ugly. I don't like the instantiation approach either. But I don't pretend to expect that inference is just a matter of finding the right way to describe a dual port memory. If the chip makers and the tool vendors can't tell us how to do it, then I can only assume that is because it doesn't work. I think the way to solve this problem is not by trying to be creative in writing code, rather a direct conversation with the vendors is needed. I tried looking in all sorts of Xilinx docs and the only one that has example code for write first dual port block ram is the XST manual, equivalent to the Verilog code shown earlier in the thread. I tried that and got the following error... ERROR:Xst - You are apparently trying to describe a RAM with several write ports for signal . This RAM cannot be implemented using distributed resources. --> So it clearly understands what I am trying to do, but still wants to use distributed ram! One thing I find odd is that they are using a variable for the RAM and perform the write before the read. But then they give two examples for write first memory, one that has direct logic to mux the input data and the memory data. The other uses the sequence of the assignments to infer the write first behavior. Either way gives the same error. I guess I would have expected the vendors to know how to use their own software. Rick From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sat, 09 May 2009 07:05:04 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 09 May 2009 13:02:32 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 46 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-BSWsJDL5YPqAXagQyGiEmC9Pp7gzq/7RsvK1s67tsxk9xXSNzv6ZGAvylgCUzldynRGHFd3LrWIpTPK!WRTyt3SG5i2vxRS3dJhKgkLsSKrgvN2l0g0egWzqphuGJuN8H+toU90WVQju2Lpwf4Rn36gGORxg!Q8x9 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3539 Xref: news.eternal-september.org comp.lang.vhdl:1086 comp.arch.fpga:3203 On Fri, 8 May 2009 10:01:30 -0700 (PDT), peter@xilinx.com wrote: >This is not a Xilinx or Altera circuit design problem, > nor is it a VHDL problem. It is a systems design issue. With respect, Peter, it is definitely neither a circuit design nor a system design problem. Speaking for myself (and for Rick too, I'm pretty sure) I know well enough what the capabilities and limitations of the BRAMs are, and how to work with them successfully. I already know what form of BRAM I want, and I can easily enough instantiate it. I have already chosen a set of behaviours that I know are available in both Xilinx and Altera BRAMs. But I don't want the grotesque non-portable ugliness of instantiated and/or wizard-generated BRAM components. So I seek a way of writing VHDL and Verilog code that correctly describes the memories' simulation behaviour, at the appropriate level of abstraction, and that will allow a range of synthesis tools to infer correctly the BRAM properties that I need. As has already been said by others, it is not hard to do this for BRAM configurations with only one write port. As soon as you add a second write port, things get much more vexatious and you get significantly less help from the coding guidelines in vendor documentation. There are good reasons for this, as have already been discussed; I made a promise (which I aim to keep) to find out just what can be done, and to write it up in a convenient vendor-neutral form. Systems design it ain't; it's all about finding a valid HDL coding style that reliably gets a desired result out of a range of different vendors' tools. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sat, 09 May 2009 07:07:12 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Problem with case-statement Date: Sat, 09 May 2009 13:04:41 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <76ht1kF1cvb60U1@mid.individual.net> <2rr7059v990e07587av65jtqlr42a88o40@4ax.com> <76it9fF1cs2qiU1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wtudQvyZHMFPEyzo6D/njBnzJJRxMCGRFV/wHVREzCvVaYha9ZkBuZbkUSsKLKd8j87nPDLj2w7eihd!NKrkeUoAdMx6IPaeEG9IwY8wffyJdw5Tvx8Z9NZGCS9XNg9TLU6tqG93j0QAk0B8kQtLyFichd8N!2VAG X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1087 On Fri, 8 May 2009 16:17:24 +0200, "Volker" wrote: >I use the ModelSim Altera Starter Edition and >in the modelsim.ini file there is no such entry :-( >Can I add these commands? Go for it. The worst that can happen is that ModelSim AE will simply ignore the added options. But I reckon that's unlikely. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d25g2000prn.googlegroups.com!not-for-mail From: Peter Alfke Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 11:03:08 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> NNTP-Posting-Host: 75.18.187.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241892188 27650 127.0.0.1 (9 May 2009 18:03:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 18:03:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d25g2000prn.googlegroups.com; posting-host=75.18.187.109; posting-account=9YFuAQoAAAA9ibAkXMKsebfCIaLKFs5s User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.27.1 (KHTML, like Gecko) Version/3.2.1 Safari/525.27.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1088 comp.arch.fpga:3205 On May 9, 5:02=A0am, Jonathan Bromley wrote: > On Fri, 8 May 2009 10:01:30 -0700 (PDT), pe...@xilinx.com wrote: > >This is not a Xilinx or Altera circuit design problem, > > nor is it a VHDL problem. It is a systems design issue. > > With respect, Peter, it is definitely neither a circuit > design nor a system design problem. =A0Speaking for myself > (and for Rick too, I'm pretty sure) I know well enough > what the capabilities and limitations of the BRAMs are, > and how to work with them successfully. =A0I already > know what form of BRAM I want, and I can easily enough > instantiate it. =A0I have already chosen a set of > behaviours that I know are available in both Xilinx > and Altera BRAMs. > > But I don't want the grotesque non-portable ugliness > of instantiated and/or wizard-generated BRAM components. > > So I seek a way of writing VHDL and Verilog code that > correctly describes the memories' simulation behaviour, > at the appropriate level of abstraction, and that will > allow a range of synthesis tools to infer correctly the > BRAM properties that I need. =A0As has already been said by > others, it is not hard to do this for BRAM configurations > with only one write port. =A0As soon as you add a second > write port, things get much more vexatious and you > get significantly less help from the coding guidelines > in vendor documentation. =A0There are good reasons for > this, as have already been discussed; I made a promise > (which I aim to keep) to find out just what can be > done, and to write it up in a convenient vendor-neutral > form. =A0Systems design it ain't; it's all about finding > a valid HDL coding style that reliably gets a desired > result out of a range of different vendors' tools. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Why did I call it a systems problem? The BRAM behaves like a synchronous two-port RAM should, common clock or uncorrelated clocks, as long as you do not perform "simultaneous" write and read operations on the same location. Two writes with conflicting data will leave the content undefined, while a write and a read can result in an undefined output. Two reads are no problem. Protecting against these system issues is quite complicated, and would sacrifice performance. What does the user community expect from us (Xilinx)? Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 09 May 2009 11:18:19 -0700 Lines: 15 Message-ID: <4A05C8EB.3040801@gmail.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Nj+lP1FigIvnJpepq2ez7AL0Fnqrld0Blkfkrv7anUCYa4k7ql Cancel-Lock: sha1:ohDTGXDShdPNoD0Mzmr01S9ZE0k= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1089 comp.arch.fpga:3207 Peter Alfke wrote: > Protecting against these system issues is quite complicated, and would > sacrifice performance. > What does the user community expect from us (Xilinx)? What if we wrote you a vhdl and verilog model that captures your English description above and a testbench to demonstrate that modelsim agrees. Then you would give the models to the right person and see to it that ise will synthesize a netlist that passes the same testbench. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!newsreader2.netcologne.de!not-for-mail From: Frank Buss Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 20:25:04 +0200 Organization: IT4 Systems GmbH & Co. KG Lines: 29 Distribution: world Message-ID: <9wszi59akghj.ic61apa70w2z.dlg@40tude.net> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> NNTP-Posting-Host: static-87-79-64-220.netcologne.de Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Trace: newsreader2.netcologne.de 1241893485 10630 87.79.64.220 (9 May 2009 18:24:45 GMT) X-Complaints-To: abuse@netcologne.de NNTP-Posting-Date: Sat, 9 May 2009 18:24:45 +0000 (UTC) User-Agent: 40tude_Dialog/2.0.15.1de (1192b149.506.21) X-Face: %YY1%+t;W[+|ouOcW@NKjAg*Phu"MA}lC{FGuAG-O6\3Y,2A$ol]tIca&& Xref: news.eternal-september.org comp.lang.vhdl:1090 comp.arch.fpga:3208 Peter Alfke wrote: > Why did I call it a systems problem? > The BRAM behaves like a synchronous two-port RAM should, common clock > or uncorrelated clocks, as long as you do not perform "simultaneous" > write and read operations on the same location. > Two writes with conflicting data will leave the content undefined, > while a write and a read can result in an undefined output. Two reads > are no problem. > Protecting against these system issues is quite complicated, and would > sacrifice performance. > What does the user community expect from us (Xilinx)? I didn't need such a feature so far, but with Altera Quartus you can specify for dual port RAMs, if you want to read the old content when simultaneous writing at the same location, or you can speficy "I don't care" (which I assume is faster). Maybe this features makes sense for some projects. But I don't think that it makes sense to specify the behaviour, if a BRAM has two write ports and from both ports are written to the same address simultaneously. And if it makes sense, it should be easy to catch this rare case in user logic, e.g. a simple priority algorithm with static logic. Implementing this for the write/read-case in user logic would be more complicated and maybe slower than what is possible with low-level support. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!m24g2000vbp.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 13:03:16 -0700 (PDT) Organization: http://groups.google.com Lines: 83 Message-ID: <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241899396 11903 127.0.0.1 (9 May 2009 20:03:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 20:03:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m24g2000vbp.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1091 comp.arch.fpga:3213 On May 9, 2:03=A0pm, Peter Alfke wrote: > On May 9, 5:02=A0am, Jonathan Bromley > wrote: > > > > > On Fri, 8 May 2009 10:01:30 -0700 (PDT), pe...@xilinx.com wrote: > > >This is not a Xilinx or Altera circuit design problem, > > > nor is it a VHDL problem. It is a systems design issue. > > > With respect, Peter, it is definitely neither a circuit > > design nor a system design problem. =A0Speaking for myself > > (and for Rick too, I'm pretty sure) I know well enough > > what the capabilities and limitations of the BRAMs are, > > and how to work with them successfully. =A0I already > > know what form of BRAM I want, and I can easily enough > > instantiate it. =A0I have already chosen a set of > > behaviours that I know are available in both Xilinx > > and Altera BRAMs. > > > But I don't want the grotesque non-portable ugliness > > of instantiated and/or wizard-generated BRAM components. > > > So I seek a way of writing VHDL and Verilog code that > > correctly describes the memories' simulation behaviour, > > at the appropriate level of abstraction, and that will > > allow a range of synthesis tools to infer correctly the > > BRAM properties that I need. =A0As has already been said by > > others, it is not hard to do this for BRAM configurations > > with only one write port. =A0As soon as you add a second > > write port, things get much more vexatious and you > > get significantly less help from the coding guidelines > > in vendor documentation. =A0There are good reasons for > > this, as have already been discussed; I made a promise > > (which I aim to keep) to find out just what can be > > done, and to write it up in a convenient vendor-neutral > > form. =A0Systems design it ain't; it's all about finding > > a valid HDL coding style that reliably gets a desired > > result out of a range of different vendors' tools. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > Why did I call it a systems problem? > The BRAM behaves like a synchronous two-port RAM should, common clock > or uncorrelated clocks, as long as you do not perform "simultaneous" > write and read operations on the same location. > Two writes with conflicting data will leave the content undefined, > while a write and a read can result in an undefined output. Two reads > are no problem. > Protecting against these system issues is quite complicated, and would > sacrifice performance. > What does the user community expect from us (Xilinx)? I'm not sure you are talking about the same problem that we are. We don't have a problem with how the block ram works. We just want to be able to use them without using instantiation, for a number of reasons. Block rams can be inferred as long as they are used in single port or pseudo dual port modes. But if they are needed with two write ports, the tools have a lot of trouble inferring a dual port block ram. The error message I got from XST 10.1 clearly showed that the tools understood that I wanted a ram with two write ports, but it could not figure out that I wanted it to use the block ram. Or am I missing something about your statements that affect this issue? Actually, the VHDL description of a block ram that uses two processes to write to the same memory also has undefined behavior. If both processes write to the same location using the same clock edge, it is undefined which process will run first and which will run second; so the result written to the block ram is undefined... maybe not in the same way as the hardware, but it is still undefined. Rick From newsfish@newsfish Wed Aug 19 13:24:34 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000vbo.googlegroups.com!not-for-mail From: Sandro Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 14:26:06 -0700 (PDT) Organization: http://groups.google.com Lines: 84 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> NNTP-Posting-Host: 84.221.81.59 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241904366 27992 127.0.0.1 (9 May 2009 21:26:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 21:26:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000vbo.googlegroups.com; posting-host=84.221.81.59; posting-account=OSNX1AoAAABZtvrWgfgFvYi2krfS2o9W User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009030814 Iceweasel/3.0.9 (Debian-3.0.9-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1092 comp.arch.fpga:3216 Rick, I hope this can help... below you can find the code to infer dual port-ram with both port sharing the same clock. I suppose the secret could be using a shared variable (instead of a signal) as RAM... regards Sandro entity ramInference is generic ( g_data_w : natural := 9; g_addr_w : natural := 11 ); port ( i_clkA : in std_logic; --i_clkB : in std_logic; i_enA : std_logic; i_weA : std_logic; i_addrA : in std_logic_vector (g_addr_w - 1 downto 0); i_dataA : in std_logic_vector (g_data_w - 1 downto 0); o_dataA : out std_logic_vector (g_data_w - 1 downto 0); i_enB : std_logic; i_weB : std_logic; i_addrB : in std_logic_vector (g_addr_w - 1 downto 0); i_dataB : in std_logic_vector (g_data_w - 1 downto 0); o_dataB : out std_logic_vector (g_data_w - 1 downto 0) ); end ramInference; architecture Behavioral of ramInference is constant c_ram_sz : natural := 2**(g_addr_w); type t_ram is array (c_ram_sz - 1 downto 0) of std_logic_vector (g_data_w - 1 downto 0); shared variable v_ram : t_ram := ( 1 => X"05", 2 => X"08", 3 => X"1A", -- ... others => X"00" ); begin p_portA : process (i_clkA) begin if rising_edge(i_clkA) then if (i_enA = '1') then -- READ FIRST o_dataA(g_data_w - 1 downto 0) <= v_ram(conv_integer (i_addrA)); -- WRITE AFTER if (i_weA = '1') then v_ram(conv_integer(i_addrA)) := i_dataA(g_data_w - 1 downto 0); end if; end if; end if; end process; p_portB : process (i_clkA) begin if rising_edge(i_clkA) then if (i_enB = '1') then -- WRITE FIRST if (i_weB = '1') then v_ram(conv_integer(i_addrB)) := i_dataB(g_data_w - 1 downto 0); end if; -- READ AFTER o_dataB(g_data_w - 1 downto 0) <= v_ram(conv_integer (i_addrB)); end if; end if; end process; end Behavioral; From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!o30g2000vbc.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 14:26:38 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> NNTP-Posting-Host: 217.171.129.71 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1241904398 32528 127.0.0.1 (9 May 2009 21:26:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 21:26:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o30g2000vbc.googlegroups.com; posting-host=217.171.129.71; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.59 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1093 comp.arch.fpga:3217 The BRAM does not have the necessary dual address decoders. The best option is to clock at half speed and multiplex. Read before write is most usual. From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Peter Alfke Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 15:15:55 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <2fd09633-fb66-4e68-b46a-36a6fbf5655e@b6g2000pre.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> NNTP-Posting-Host: 75.18.187.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241907355 9257 127.0.0.1 (9 May 2009 22:15:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 22:15:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=75.18.187.109; posting-account=9YFuAQoAAAA9ibAkXMKsebfCIaLKFs5s User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.27.1 (KHTML, like Gecko) Version/3.2.1 Safari/525.27.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1094 comp.arch.fpga:3218 On May 9, 2:26=A0pm, Jacko wrote: > The BRAM does not have the necessary dual address decoders. The best > option is to clock at half speed and multiplex. Read before write is > most usual. All Xilinx BRAMs have dual address decoders, and each port also has the option of read before or after write or retain previous output. It seems there is no argument about the hardware, but there is about the software... Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vbi.googlegroups.com!not-for-mail From: Sandro Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 15:31:27 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <9a1f28e9-4458-47a1-840a-bb749e0f3b95@r34g2000vbi.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> <2fd09633-fb66-4e68-b46a-36a6fbf5655e@b6g2000pre.googlegroups.com> NNTP-Posting-Host: 84.221.81.59 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241908287 12068 127.0.0.1 (9 May 2009 22:31:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 May 2009 22:31:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vbi.googlegroups.com; posting-host=84.221.81.59; posting-account=OSNX1AoAAABZtvrWgfgFvYi2krfS2o9W User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009030814 Iceweasel/3.0.9 (Debian-3.0.9-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1095 comp.arch.fpga:3219 On May 10, 12:15=A0am, Peter Alfke wrote: > All Xilinx BRAMs have dual address decoders, and each port also has > the option of read before or after write or retain previous output. > It seems there is no argument about the hardware, but there is about > the software... > Peter Alfke Peter, This time... (quite) no argument about the software too (see my previous post). XST (your software [xilinx]) infers the bram with two r/w ports both with "READ FIRST" and with "WRITE FIRST" options... Maybe the only software (vhdl) argument could be "how to infer dual port BRAM with different bus sizes for the two ports" regards Sandro From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 09 May 2009 18:41:45 -0500 From: "Ira Baxter" Newsgroups: comp.lang.vhdl References: <2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com> Subject: Re: Generating C header files? Date: Sat, 9 May 2009 18:41:44 -0500 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.3790.3959 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.4325 X-RFC2646: Format=Flowed; Original Message-ID: <_radnRcx44EkiZvXnZ2dnUVZ_g-dnZ2d@giganews.com> Lines: 25 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-3elAfmiqH6+W8PjQIrA7fRNlR9ouALehW2pyGfKfGFmv8V51+I6Tvzc4aGWzyBm1yeKJD4LDsKVbC5p!vpZbGywDzzdAZDAjbhkPcMvXoFRihKZcOFkGMdl703ldpTEvItEi1mABxGb0Hu6l2Fzxzmj7YITe!PA== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2032 Xref: news.eternal-september.org comp.lang.vhdl:1096 "T" wrote in message news:2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com... > Greetings: > > We have a VHDL file with register definitions, does anyone know of a > tool/script which will parse this code and be capable of generating a > C header file for the software folks? Other have suggested ad hoc parsers (e.g., regular expressions). If these work well enough for you, then that's fine. If you need to parse real VHDL as opposed to some significantly constrained subset, regular expressions won't do the trick, you need real parsers. The DMS Software Reengineering Toolkit has full VHDL parsers, and can apply custom transformation rules to generate C headers as you suggest. See http://www.semanticdesigns.com/Products/DMS/DMSToolkit.html Ira D. Baxter, CTO Semantic Designs From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Generating C header files? Date: Sun, 10 May 2009 03:18:38 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 41 Sender: mdhicks2@outside.world Message-ID: <6004390c1fb8a8cb9f0b3c718b5c@news.acm.uiuc.edu> References: <_radnRcx44EkiZvXnZ2dnUVZ_g-dnZ2d@giganews.com> NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1241925517 2846 98.220.249.110 (10 May 2009 03:18:37 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Sun, 10 May 2009 03:18:37 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1097 There are also free tools you can use to parse VHDL. We based our VHDL tools on a free VHDL grammar for the Java Compiler Compiler (JavaCC). The VHDL grammar can be found on the JavaCC site itself. You will have to do the work of editing the grammar or java source files to get and manipulate the information you want. Trust me though, this is no easy task. There is a steep learning curve with the tools, especially if you're not a compiler person. Looking back, I would have preferred to use a closed-source VHDL front end (see previous post) that expose a good API, but they are extremely expensive and I'm in an academic research environment. I would be willing to contract with you to work-out a solution using free tools, saving you both time and money. ---Matthew Hicks > "T" wrote in message > news:2ba9531e-715a-4451-a4c4-a40f5588ad82@z9g2000yqi.googlegroups.com. > .. > >> Greetings: >> >> We have a VHDL file with register definitions, does anyone know of a >> tool/script which will parse this code and be capable of generating a >> C header file for the software folks? >> > Other have suggested ad hoc parsers (e.g., regular expressions). If > these work well enough for you, then that's fine. > > If you need to parse real VHDL as opposed to some significantly > constrained subset, regular expressions won't do the trick, > you need real parsers. > The DMS Software Reengineering Toolkit has full VHDL parsers, > and can apply custom transformation rules to generate C headers > as you suggest. See > http://www.semanticdesigns.com/Products/DMS/DMSToolkit.html > Ira D. Baxter, CTO > Semantic Designs From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: Brian Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sat, 9 May 2009 21:00:40 -0700 (PDT) Organization: http://groups.google.com Lines: 87 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> <2fd09633-fb66-4e68-b46a-36a6fbf5655e@b6g2000pre.googlegroups.com> <9a1f28e9-4458-47a1-840a-bb749e0f3b95@r34g2000vbi.googlegroups.com> NNTP-Posting-Host: 12.41.166.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241928040 7051 127.0.0.1 (10 May 2009 04:00:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 May 2009 04:00:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=12.41.166.9; posting-account=W6OcCAoAAADxWvbHWnyOvS40dzrNyeqp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1098 comp.arch.fpga:3220 On May 9, 4:31=A0pm, Sandro wrote: > > Peter, > This time... (quite) no argument about the software too (see my > previous post). > XST (your software [xilinx]) infers the bram with two r/w ports both > with "READ FIRST" and with "WRITE FIRST" options... > > Maybe the only software (vhdl) argument could be "how to infer dual > port BRAM with > different bus sizes for the two ports" > > regards > Sandro Thought I would chime in on some of the comments and observations from this thread. Starting with the most recent comment, if you need different port widths in either the read vs. write of the same port or different widths on the dual port, you do need to instantiate. Neither XST, Synplify or Precision support RAMs with different port widths. I can comment from the XST side that we have investigated this and plan to some day offer this however to date, have not been able to include this capability. As Sandro explains, you should be able to infer a common clock dual port RAM (assuming same port widths) in any of the READ_FIRST, WRITE_FIRST or NO_CHANGE modes. It is fairly straightforward in verilog to code this however for VHDL as explained, you do need to use a shared variable to accomplish this. I am more familiar with Verilog than VHDL but my understanding is that the shared variable is necessary for proper simulation when accessing the same array at the same time. In terms of coding examples for these RAMs, most of the coding examples can be found in the Xilinx Language Templates which are accessible from Xilinx Project Navigator. Open the Templates and look in VHDL or Verilog --> Synthesis Constructs --> Coding Examples -- > RAM to see several examples. In the Single-Port descriptions you can see the differences between READ_FIRST, WRITE_FIRST and NO_CHANGE mode however unfortunately for the dual port not all have been adapted there but in theory should work. I will see if in 11.2 we can get the templates updated to include all of the dual port examples for these. One other note, if you are inferring a BRAM in which you never plan to read from the same port at the time you are writing, describe NO_CHANGE mode. It will save power but not many realize this. In terms of memory collisions (writing to the same memory address on a dual port RAM as either reading or writing on the other) this described in the device User Guides and the Synthesis and Simulation Design Guide so I hope that most understand what it is and what should be done to avoid them however as for inferring dual-port BRAM, you do need to heed more caution. A behavioral RTL simulation will not alert or model a collision so you can very well simulate a collision behaviorally and get a seemingly valid result but the implementation can give something different. This is not covered by static timing analysis as this is a dynamic situation. It can be covered and alerted by timing simulation however many choose not to do timing simulations so in lieu of that some synthesis tools have decided to arbitrate the access to the same memory locations with additional logic around the BRAM. Both Synplicity and Precision do this however XST does not. Most people who are aware of this, disable the addition of the collision avoidance logic using a synthesis attribute as it can slow the RAM down, add more resources and add more power to the FPGA design and in many cases is not needed however if you do disable this, you need to take extra care to ensure an undetected collision will not give undesired results in your design. I too try to avoid instantiation of BRAM however one advantage it does give you is it will alert you to a memory collision as it is modeled in the UNISIM. As mentioned before a timing simulation (no matter how the RAM was entered) can also detect this. In system testing, can not detect this. Reason being, collisions are as unpredictable as a timing error and while a system may behave one way in one device in one environmental condition (temperature or voltage) during a collision, it may behave differently in another device or under a different environmental condition) so I would not trust in-system testing to this any more than I would a timing violation. Hopefully this clears up some of the issues identified in this thread. I often do infer RAMs in my designs however there are certain circumstances (such as different port widths) that necessitate instantiation so we are still not in a full RTL world when it comes to RAMs. However more situations than most know can be inferred with relative ease (i.e. dual-port, byte enables, read modes, initialization from an external file, all can be inferred now). Regards, -- Brian Philofsky -- Xilinx Applications From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n8g2000vbb.googlegroups.com!not-for-mail From: Sandro Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sun, 10 May 2009 00:50:45 -0700 (PDT) Organization: http://groups.google.com Lines: 108 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> <2fd09633-fb66-4e68-b46a-36a6fbf5655e@b6g2000pre.googlegroups.com> <9a1f28e9-4458-47a1-840a-bb749e0f3b95@r34g2000vbi.googlegroups.com> NNTP-Posting-Host: 84.221.81.59 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1241941845 16828 127.0.0.1 (10 May 2009 07:50:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 May 2009 07:50:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n8g2000vbb.googlegroups.com; posting-host=84.221.81.59; posting-account=OSNX1AoAAABZtvrWgfgFvYi2krfS2o9W User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009030814 Iceweasel/3.0.9 (Debian-3.0.9-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1099 comp.arch.fpga:3221 On May 10, 6:00=A0am, Brian wrote: > On May 9, 4:31=A0pm, Sandro wrote: > > > > > Peter, > > This time... (quite) no argument about the software too (see my > > previous post). > > XST (your software [xilinx]) infers the bram with two r/w ports both > > with "READ FIRST" and with "WRITE FIRST" options... > > > Maybe the only software (vhdl) argument could be "how to infer dual > > port BRAM with > > different bus sizes for the two ports" > > > regards > > Sandro > > Thought I would chime in on some of the comments and observations from > this thread. =A0Starting with the most recent comment, if you need > different port widths in either the read vs. write of the same port or > different widths on the dual port, you do need to instantiate. > Neither XST, Synplify or Precision support RAMs with different port > widths. =A0I can comment from the XST side that we have investigated > this and plan to some day offer this however to date, have not been > able to include this capability. > > As Sandro explains, you should be able to infer a common clock dual > port RAM (assuming same port widths) in any of the READ_FIRST, > WRITE_FIRST or NO_CHANGE modes. =A0It is fairly straightforward in > verilog to code this however for VHDL as explained, you do need to use > a shared variable to accomplish this. =A0I am more familiar with Verilog > than VHDL but my understanding is that the shared variable is > necessary for proper simulation when accessing the same array at the > same time. =A0In terms of coding examples for these RAMs, most of the > coding examples can be found in the Xilinx Language Templates which > are accessible from Xilinx Project Navigator. =A0Open the Templates and > look in VHDL or Verilog --> Synthesis Constructs --> Coding Examples --> = RAM to see several examples. =A0In the Single-Port descriptions you > > can see the differences between READ_FIRST, WRITE_FIRST and NO_CHANGE > mode however unfortunately for the dual port not all have been adapted > there but in theory should work. =A0I will see if in 11.2 we can get the > templates updated to include all of the dual port examples for these. > One other note, if you are inferring a BRAM in which you never plan to > read from the same port at the time you are writing, describe > NO_CHANGE mode. =A0It will save power but not many realize this. > > In terms of memory collisions (writing to the same memory address on a > dual port RAM as either reading or writing on the other) this > described in the device User Guides and the Synthesis and Simulation > Design Guide so I hope that most understand what it is and what should > be done to avoid them however as for inferring dual-port BRAM, you do > need to heed more caution. =A0A behavioral RTL simulation will not alert > or model a collision so you can very well simulate a collision > behaviorally and get a seemingly valid result but the implementation > can give something different. =A0This is not covered by static timing > analysis as this is a dynamic situation. =A0It can be covered and > alerted by timing simulation however many choose not to do timing > simulations so in lieu of that some synthesis tools have decided to > arbitrate the access to the same memory locations with additional > logic around the BRAM. =A0Both Synplicity and Precision do this however > XST does not. =A0Most people who are aware of this, disable the addition > of the collision avoidance logic using a synthesis attribute as it can > slow the RAM down, add more resources and add more power to the FPGA > design and in many cases is not needed however if you do disable this, > you need to take extra care to ensure an undetected collision will not > give undesired results in your design. =A0I too try to avoid > instantiation of BRAM however one advantage it does give you is it > will alert you to a memory collision as it is modeled in the UNISIM. > As mentioned before a timing simulation (no matter how the RAM was > entered) can also detect this. In system testing, can not detect > this. =A0Reason being, collisions are as unpredictable as a timing error > and while a system may behave one way in one device in one > environmental condition (temperature or voltage) during a collision, > it may behave differently in another device or under a different > environmental condition) so I would not trust in-system testing to > this any more than I would a timing violation. > > Hopefully this clears up some of the issues identified in this > thread. =A0I often do infer RAMs in my designs however there are certain > circumstances (such as different port widths) that necessitate > instantiation so we are still not in a full RTL world when it comes to > RAMs. =A0However more situations than most know can be inferred with > relative ease (i.e. dual-port, byte enables, read modes, > initialization from an external file, all can be inferred now). > > Regards, > > -- =A0Brian Philofsky > -- =A0Xilinx Applications Brian, thanks for your answer ... you avoided me to waste time trying to figure out how the ram can be represented (in vhdl) as two array with "different geometry" (read dual port with different bus sizes). Peter Alfke wrote: > ... > What does the user community expect from us (Xilinx)? > ... (...winking to Peter) that is what the user community expect from you (Xilinx) ;-) regards Sandro From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.posted.plusnet!news.posted.plusnet.POSTED!not-for-mail NNTP-Posting-Date: Sun, 10 May 2009 11:54:32 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Sun, 10 May 2009 17:52:01 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> <3c2a0504-db1f-455a-a9b1-c7ee46b1e272@o30g2000vbc.googlegroups.com> <2fd09633-fb66-4e68-b46a-36a6fbf5655e@b6g2000pre.googlegroups.com> <9a1f28e9-4458-47a1-840a-bb749e0f3b95@r34g2000vbi.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 90 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-T3fIqsXjRnL67YEdxfTqjeDB8seU2/m9PyoIymtdEpIsaBEJ8nsjZ9au8+NQOxxbr9idqW9Cu62A2Qs!pqZ2TJ8sDQYMQojh+WRCk7dx5j5QcBs5h0k+y6Vat46Rhyv7Fpiylw0HJHLOCvKl0T5i8otrJGf5!571F X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 5138 Xref: news.eternal-september.org comp.lang.vhdl:1100 comp.arch.fpga:3228 On Sat, 9 May 2009 21:00:40 -0700 (PDT), Brian wrote: >Thought I would chime in on some of the comments and observations from >this thread. Many thanks for an authoritative and very helpful post. I'd worked some of that stuff out for myself, but there are a few important things you've taught me. Much appreciated. >Neither XST, Synplify or Precision support RAMs with different port >with different port widths. Thanks for saving me some investigation time. This happens to be a feature that I don't need in my current project, but it's worth being aware of the restriction. > my understanding is that the [VHDL] shared variable is >necessary for proper simulation when accessing the same array at the >array at the same time. Yes, if you want WRITE_FIRST behaviour. It should be possible to avoid it if you want READ_FIRST, but since we need shared variables for the WRITE_FIRST template it seems sensible to use them in all forms. Alternatively, a doubly-clocked template would allow the variable to stay local to the process - but that's stretching things a bit. One downside of the shared variable is that it's not strictly VHDL language-compliant, since it doesn't use protected types. Those simulators that understand protected types (VHDL >= 2000) will usually issue a warning for it. This warning can safely be ignored (although, of course, it is in a sense alerting you to the risk of write-write collision!). >In the Single-Port descriptions you >can see the differences between READ_FIRST, WRITE_FIRST and NO_CHANGE >mode however unfortunately for the dual port not all have been adapted Yes, and sometimes it's far from obvious how to extrapolate from the single-port to dual-write description. >I will see if in 11.2 we can get the >templates updated to include all of the dual port examples for these. Simply having authoritative and complete examples in the docs would be a really good start. >One other note, if you are inferring a BRAM in which you never plan to >read from the same port at the time you are writing, describe >NO_CHANGE mode. It will save power but not many realize this. I certainly didn't. Can you (or Peter???) elaborate a bit more? Is the power saving significant in practice? > A behavioral RTL simulation will not alert >or model a collision An assertion could easily be added. I would be very suspicious of an inference template that did not include such an assertion to generate at least a warning. >some synthesis tools have decided to >arbitrate the access to the same memory locations with additional >logic around the BRAM. Both Synplicity and Precision do this however >XST does not. Yes, I'd noticed that. My preference would by far be for XST's approach, but with a suitable assertion in the template. Best of all would be the synth tool checking for existence of such an assertion, and complaining if it was absent :-) > Most people who are aware of this, disable the addition >of the collision avoidance logic using a synthesis attribute I have not yet had the persistence to track down those attributes in the vendor docs. Thanks for alerting me to their existence. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:35 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Mon, 11 May 2009 01:02:19 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <7c7ccdb0-8e4c-4d4a-b03b-292de340ec94@r34g2000vba.googlegroups.com> References: <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> <9f6457c4-628b-44bf-965d-f2232285f184@e23g2000vbe.googlegroups.com> <76ghbpF1chl11U1@mid.individual.net> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242028939 23642 127.0.0.1 (11 May 2009 08:02:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 08:02:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1101 On 7 Mag, 18:42, Mike Treseler wrote: > Dek wrote: > > Thanks all, it seems a good idea, but finally I used Tcl, it's quite > > simple > > Glad you saw the light. > tcl is much better at text than vhdl, > as is python, bash script, emacs-lisp, perl, ... > > =A0 =A0 =A0 =A0 =A0 =A0-- Mike Treseler Hemm... actually I used Tcl just as a macro to be used with modelsim (as HT-Lab suggested); in my VHDL TextIO is still present, but since I use the files name as generics, they don't have to be constrained anymore. Maybe, as you say, I did better if I used just Tcl or Python or so on, but I want to take confidence with VHDL for further applications, and I had data from an actual detector already stored in .txt files. Anyway I think it's nice to know how TextIO works because, even if it's not very powerful, it gives you the chance to understeand how an hardware model would work on data already stored; and I don't think this is a so rare application. From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!nuzba.szn.dk!pnx.dk!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 11 May 2009 04:30:08 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: Help needed with memory initialization file. Date: Mon, 11 May 2009 02:27:30 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 202.12.94.215 Lines: 47 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rjDfcr0uiIibuyVUnoWjAOPxvsfTWnW5wg7Fwo32dyFIQgtzY3nuXoodQsnkbttduGRr4olTpaJ2pkW!aiQ1BE9eVOdVpSTy24gWhdg4CgY8SJ8M36+eMxYG91rCNBPchTP/fei8zq9p3g== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 38 Xref: news.eternal-september.org comp.lang.vhdl:1102 Can someone help me ? why illegal Intel Hex Format! show up when i try to simulate my project. Below is the mif file for my rom. (WIDTH=8,DEPTH=32) 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 Thanks, if anyone can help me. -- BomberMan ------------------------------------------------------------------------ BomberMan's Profile: http://www.fpgacentral.com/group/member.php?userid=83 View this thread: http://www.fpgacentral.com/group/showthread.php?t=89972 From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!feeder.erje.net!news-xfer.nntp.sonic.net!news.astraweb.com!border2.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Help needed with memory initialization file. Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.132 (Waxed in Black) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 11 May 2009 12:03:17 GMT Lines: 23 Message-ID: <02180730$0$20636$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: e56c7dc2.news.astraweb.com X-Trace: DXC=`f0h1AD9IWK6;?e@]GfeBGL?0kYOcDh@J;>GTR`=ZX:BM0HSRaiKfJFkRfKD@`FWWNS9RC\c7oKFG Xref: news.eternal-september.org comp.lang.vhdl:1103 On Mon, 11 May 2009 02:27:30 -0700, 'use_real_email' wrote: > Can someone help me ? > why illegal Intel Hex Format! show up when i try to simulate my project. > Below is the mif file for my rom. (WIDTH=8,DEPTH=32) > > 00000000 > 00000001 [snip] > 00011110 > 00011111 That is clearly not Intel Hex format. I can't find the canonical definition of the format on Intel's web site, but here is a copy: http://pages.interlog.com/~speff/usefulinfo/Hexfrmt.pdf The Wikipedia page is also ok: http://en.wikipedia.org/wiki/.hex BTW, it looks like you are just returning the address. You don't really need a ROM for that. (I guess you are just doing this for testing?) Regards, Allan From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!motzarella.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading Date: Mon, 11 May 2009 15:06:44 +0200 Lines: 45 Message-ID: <87vdo7dc0r.fsf@harnisch.dyndns.org> References: <87tz3x88ft.fsf@harnisch.dyndns.org> <874ovwlyu6.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net 3ZMthaDuHHbPg9O01C0YjgrX1EaaS9dh67QVfXDLl88KG7aj8m Cancel-Lock: sha1:nwnBgJ/vF8BeV4WnC7ZVB1w0eU4= sha1:FNZxsL2M99DmukhnQvAx5oZ0pDo= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:1104 Petter Gustad writes: > Marcus Harnisch writes: > >> Currently EDA tool makers seem to agree that the overhead of >> resynchronizing many individual simulation threads back to the HDL >> timing model is simply too big to make it worthwhile. > > Synopsys VCS claims 2X performance increase on multicore CPU's: > > "VCS® multicore technology delivers a 2x verification speed-up that > helps users find design bugs early in the product development cycle. > VCS multicore technology cuts down verification time by running the > design, testbench, assertions, coverage and debug in parallel on > machines with multiple cores." But that's not really simulation threads. Other vendors claim similar things (wave form dump in a separate thread). > If you can partition the design so that you minimize the latency > intensive communication (this might result in dynamic partition and > process migration) you should be able to archive a decent speed > increase. I guess the "If" is a significant issue. The analysis might be costly. But there is more than just this optimization task, which is difficult enough I gather. Another requirement in simulation is the capability to rerun a test *exactly* the same way it was executed before. Having the simulation run in different threads in an inherently non-deterministic environment (OS, other processes) and putting these threads into a deterministic execution sequence almost contradicts itself. I am sure EDA vendors are racking their heads for a solution to this. It is much less of an effort to running several simulations in parallel. You can do that today. Kind regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading Date: Mon, 11 May 2009 17:14:56 +0200 Organization: 502 You are not allowed to talk Lines: 60 Sender: newsmailcomp6@gustad.com Message-ID: <87bppzllhr.fsf@pangea.home.gustad.com> References: <87tz3x88ft.fsf@harnisch.dyndns.org> <874ovwlyu6.fsf@pangea.home.gustad.com> <87vdo7dc0r.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.eternal-september.org U2FsdGVkX18e//++fhSItl+UeS3H4x0Ic9b0fvzdGIUO/e39F72ybWyk3TV/wKZO+iMedhC8/YhBOcPZQKjCrHx1Npu7zKc4KdyJ4vLnds/5C7mKQuJ4DdPWaOSo39DJfuMYhN1EPFNN+GNVsWi9Tw== X-Complaints-To: Please send complaints to abuse@motzarella.org with full headers NNTP-Posting-Date: Mon, 11 May 2009 15:15:11 +0000 (UTC) X-Auth-Sender: U2FsdGVkX1/oEYngDexO7IBGokg3uM0oQI3RFGfEE9U= Cancel-Lock: sha1:Ns176ZlCmm5SNZhYMVoL8qld1cA= sha1:DT4YmdUkoi7CpjJqCZArpUfhfkY= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1105 Marcus Harnisch writes: >> "VCS® multicore technology delivers a 2x verification speed-up that >> helps users find design bugs early in the product development cycle. >> VCS multicore technology cuts down verification time by running the >> design, testbench, assertions, coverage and debug in parallel on >> machines with multiple cores." > > But that's not really simulation threads. Other vendors claim similar > things (wave form dump in a separate thread). Synopsys talks about both Application Level Parallelism (ALP) and Design Level Parallelism (DLP). The latter is simulation threads. The former might not be. However, I haven't used this version of VCS so I can't verify what Synopsys are saying in their FAQ's, press releases etc. >> If you can partition the design so that you minimize the latency >> intensive communication (this might result in dynamic partition and >> process migration) you should be able to archive a decent speed >> increase. > > I guess the "If" is a significant issue. The analysis might be Yes. It's easy to imagine a design consisting of two small modules where one input is fed into the other and vice versa. Both depend upon the others output and the latency would hurt the performance and you would probably not split it across two cores/processors. However a design where a testbench is generating stimuli for the DUT and the data are all inputs to the DUT it would be feasible to split the two across multiple processors depending upon the bandwidth of the data to go from the stimuli generator to the DUT. The analysis is costly and it might be difficult to determine on compile time in many cases, e.g. the toggling frequency of some input might be a function of external data. > difficult enough I gather. Another requirement in simulation is the > capability to rerun a test *exactly* the same way it was executed > before. Having the simulation run in different threads in an > inherently non-deterministic environment (OS, other processes) and > putting these threads into a deterministic execution sequence almost > contradicts itself. I am sure EDA vendors are racking their heads for > a solution to this. I can't see why it's so difficult to keep track of thread statistics and synchronization points (should probably be simulator option) so you can re-run the simulation on the same processors etc. but possibly resulting in lower performance since the loads of the other processors might be different from the previous runs. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: TextIO Tutorial Date: Mon, 11 May 2009 10:16:55 -0700 Lines: 23 Message-ID: <76r4s9F1eepruU1@mid.individual.net> References: <75bm8eF16r1tkU1@mid.individual.net> <42656745-d211-4e1f-a7f8-0f8103511fd6@b6g2000pre.googlegroups.com> <9db665a8-34e3-4ed7-93f4-b341a3b522e3@r31g2000prh.googlegroups.com> <9f6457c4-628b-44bf-965d-f2232285f184@e23g2000vbe.googlegroups.com> <76ghbpF1chl11U1@mid.individual.net> <7c7ccdb0-8e4c-4d4a-b03b-292de340ec94@r34g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 46RfOg20ho+JMS9fagFlAQ2MPnJwdOCYDSYT7OL0ikLsClnTVP Cancel-Lock: sha1:BXZsXMO1mRdgrcTx/C9joACJRT0= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <7c7ccdb0-8e4c-4d4a-b03b-292de340ec94@r34g2000vba.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1106 >> Dek wrote: >>> Thanks all, it seems a good idea, but finally I used Tcl, it's quite >>> simple Dek wrote: > Hemm... actually I used Tcl just as a macro to be used with modelsim > (as HT-Lab suggested); in my VHDL TextIO is still present, but since I > use the files name as generics, they don't have to be constrained > anymore. Sorry that I misinterpreted your posting. Congratulations for conquering textio. > Maybe, as you say, I did better if I used just Tcl or Python or so on, > but I want to take confidence with VHDL for further applications, and > I had data from an actual detector already stored in .txt files. I prefer to convert existing text files to vhdl packages using a scripting language, since I am using one anyway to run modelsim. This isn't better, just different. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!z19g2000vbz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 10:46:00 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> NNTP-Posting-Host: 71.171.68.146 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242063960 29111 127.0.0.1 (11 May 2009 17:46:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 17:46:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000vbz.googlegroups.com; posting-host=71.171.68.146; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1107 comp.arch.fpga:3246 My code is virtually this same thing. The tool tells me I am trying to infer two ports using distributed memory which it can't do. Rick On May 9, 5:26=A0pm, Sandro wrote: > Rick, > I hope this can help... > below you can find the code to infer dual port-ram with > both port sharing the same clock. > I suppose the secret could be using a shared variable (instead of a > signal) as RAM... > > regards > Sandro > > entity ramInference is > =A0 generic ( > =A0 =A0 g_data_w : natural :=3D 9; > =A0 =A0 g_addr_w : natural :=3D 11 > =A0 =A0 ); > =A0 port ( > =A0 =A0 i_clkA =A0: in =A0std_logic; > =A0 =A0 --i_clkB =A0: in =A0std_logic; > =A0 =A0 i_enA =A0 : =A0 =A0 std_logic; > =A0 =A0 i_weA =A0 : =A0 =A0 std_logic; > =A0 =A0 i_addrA : in =A0std_logic_vector (g_addr_w - 1 downto 0); > =A0 =A0 i_dataA : in =A0std_logic_vector (g_data_w - 1 downto 0); > =A0 =A0 o_dataA : out std_logic_vector (g_data_w - 1 downto 0); > > =A0 =A0 i_enB =A0 : =A0 =A0 std_logic; > =A0 =A0 i_weB =A0 : =A0 =A0 std_logic; > =A0 =A0 i_addrB : in =A0std_logic_vector (g_addr_w - 1 downto 0); > =A0 =A0 i_dataB : in =A0std_logic_vector (g_data_w - 1 downto 0); > =A0 =A0 o_dataB : out std_logic_vector (g_data_w - 1 downto 0) > =A0 =A0 ); > end ramInference; > > architecture Behavioral of ramInference is > > =A0 constant c_ram_sz : natural :=3D 2**(g_addr_w); > > =A0 type t_ram is array (c_ram_sz - 1 downto 0) of > =A0 =A0 std_logic_vector (g_data_w - 1 downto 0); > > =A0 shared variable v_ram : t_ram :=3D ( > =A0 =A0 1 =A0 =A0 =A0=3D> X"05", > =A0 =A0 2 =A0 =A0 =A0=3D> X"08", > =A0 =A0 3 =A0 =A0 =A0=3D> X"1A", > =A0 =A0 -- ... > =A0 =A0 others =3D> X"00" > =A0 =A0 ); > > begin > > =A0 p_portA : process (i_clkA) > =A0 begin > =A0 =A0 if rising_edge(i_clkA) then > =A0 =A0 =A0 if (i_enA =3D '1') then > =A0 =A0 =A0 =A0 -- READ FIRST > =A0 =A0 =A0 =A0 o_dataA(g_data_w - 1 downto 0) <=3D v_ram(conv_integer > (i_addrA)); > =A0 =A0 =A0 =A0 -- WRITE AFTER > =A0 =A0 =A0 =A0 if (i_weA =3D '1') then > =A0 =A0 =A0 =A0 =A0 v_ram(conv_integer(i_addrA)) :=3D i_dataA(g_data_w - = 1 downto > 0); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > =A0 p_portB : process (i_clkA) > =A0 begin > =A0 =A0 if rising_edge(i_clkA) then > =A0 =A0 =A0 if (i_enB =3D '1') then > =A0 =A0 =A0 =A0 -- WRITE FIRST > =A0 =A0 =A0 =A0 if (i_weB =3D '1') then > =A0 =A0 =A0 =A0 =A0 v_ram(conv_integer(i_addrB)) :=3D i_dataB(g_data_w - = 1 downto > 0); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 -- READ AFTER > =A0 =A0 =A0 =A0 o_dataB(g_data_w - 1 downto 0) <=3D v_ram(conv_integer > (i_addrB)); > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > end Behavioral; From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!n4g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Mon, 11 May 2009 10:47:58 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <9bbff7bf-472f-4a5e-9c5a-277b271a0817@n4g2000vba.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242064078 29401 127.0.0.1 (11 May 2009 17:47:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 17:47:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n4g2000vba.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1108 On May 7, 8:23=A0am, Jonathan Bromley wrote: > Compiling all entities before you try to compile any architecture > will generally fix the majority of compile-order issues. Compiling all entities and then all architectures in an arbitrary order will usually work unless you also specify the architecture name in the instantiation: instance_name: entity work.entity_name(architecture_name)... Doing so puts complete configuration control in the existing source code, not leaving anything up to LRA rules or to separate configuration files and their requisite component declarations. There are times when configurations and components give you additional flexibility, particularly without modifying the "source code", but most applications simply don't need it. And don't get me started on configurations of components in a library other than that containing the configuration... Some tools (e.g. NC-sim) will automatically scan a list of files, directories, etc., and given a top level module, will determine the correct order of compilation for you, then compile it all in that order. I'v even had it work on a single file where it needed to re- order the compilation order from what was shown in the file. Andy From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!d25g2000prn.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 12:43:31 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: References: NNTP-Posting-Host: 65.160.57.101 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242071011 23819 127.0.0.1 (11 May 2009 19:43:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 19:43:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d25g2000prn.googlegroups.com; posting-host=65.160.57.101; posting-account=oRX64woAAABTa-nV9zEYMkva4yias-ah User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1109 comp.arch.fpga:3247 I know I'm a little late on this thread, but offer my two cents, on what we use, and a warning as well. We use dual-port RAMS (same clock) with inference, and don't have trouble. It's in verilog, and it's READ_FIRST. So two strikes against it for what you're looking for Rick. (you want VHDL, and WRITE_FIRST, I beleive). We call this our "mem2rw1clk" module. But here's what we do (minus header/etc): always @( posedge clk ) begin if( en0 ) begin if( wren0 ) mem[ addr0 ] <= wdata0; rdata0 <= mem[ addr0 ]; end end always @( posedge clk ) begin if( en1 ) begin if( wren1 ) mem[ addr1 ] <= wdata1; rdata1 <= mem[ addr1 ]; end end So, two almost identical always blocks, operating on the same RAM. Since we use non-blocking assignments, the READ_FIRST is implied (correctly by XST). Works, and we've been using it for many designs no trouble. Now the warning: We use almost the EXACT same structure for implementing a pseudo dual port - i.e. an independant READ port, and a WRITE port (same clock) "mem1r1w1clk". I.e. the type of memory you'd use for a synchronous fifo. The logic is again clearly coded for READ_FIRST. Well, XST was (sometimes) inferring WRITE_FIRST. So, simulation vs implementation mismatch. It only mattered in a few places we were specifically ALWAYS reading the same location as we were writing in the same cycle. You get quite different results. Spent 2-3 weeks on the bench figuring out this one. So - check the XST report to make sure it's inferring the correct READ_FIRST vs. WRITE_FIRST behaviour. XST can get things wrong here. Regards, Mark From newsfish@newsfish Wed Aug 19 13:24:36 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!feeder.news-service.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: peter@xilinx.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 13:29:05 -0700 (PDT) Organization: http://groups.google.com Lines: 75 Message-ID: References: NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242073745 32403 127.0.0.1 (11 May 2009 20:29:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 20:29:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=149.199.62.254; posting-account=XWkVzQoAAABTt_uQ5LvDXJs5hs3-FJh- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.18.1 (KHTML, like Gecko) Version/3.1.2 Safari/525.20.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1110 comp.arch.fpga:3248 On May 11, 12:43=A0pm, Mark wrote: > I know I'm a little late on this thread, but offer my two cents, > on what we use, and a warning as well. > > We use dual-port RAMS (same clock) with inference, and don't have > trouble. =A0It's in verilog, and it's READ_FIRST. =A0So two strikes > against it for what you're looking for Rick. =A0(you want VHDL, and > WRITE_FIRST, I beleive). =A0We call this our "mem2rw1clk" module. > > But here's what we do (minus header/etc): > > always @( posedge clk ) > begin > =A0 if( en0 ) > =A0 begin > =A0 =A0 if( wren0 ) > =A0 =A0 =A0 mem[ addr0 ] <=3D wdata0; > =A0 =A0 rdata0 <=3D mem[ addr0 ]; > =A0 end > end > > always @( posedge clk ) > begin > =A0 if( en1 ) > =A0 begin > =A0 =A0 if( wren1 ) > =A0 =A0 =A0 mem[ addr1 ] <=3D wdata1; > =A0 =A0 rdata1 <=3D mem[ addr1 ]; > =A0 end > end > > So, two almost identical always blocks, operating on the same RAM. > Since we use non-blocking assignments, the READ_FIRST is implied > (correctly by XST). > > Works, and we've been using it for many designs no trouble. > > Now the warning: > > We use almost the EXACT same structure for implementing a pseudo > dual port - i.e. an independant READ port, and a WRITE port > (same clock) "mem1r1w1clk". =A0 =A0I.e. the type of memory you'd > use for a synchronous fifo. =A0The logic is again clearly coded for > READ_FIRST. > > Well, XST was (sometimes) inferring WRITE_FIRST. =A0So, simulation > vs implementation mismatch. =A0It only mattered in a few places > we were specifically ALWAYS reading the same location as we > were writing in the same cycle. You get quite different results. > Spent 2-3 weeks on the bench figuring out this one. > > So - check the XST report to make sure it's inferring the > correct READ_FIRST vs. WRITE_FIRST behaviour. =A0XST can get things > wrong here. > > Regards, > > Mark I am surprised about the interest in write_first vs read_first. The read output during a write operation came really about as an afterthought. ("It's easy, the port is already there, so it costs nothing"). But why do you want to read from the same location that you are writing to? Especially when you are reading what you already know, since you simultaneously are writing it (which was the original mode). Then we found that read-before-write was an easy modification, and more valuable. But still: why do you read from the write address, when you have a separate read port with its own dedicated addressing available? But, judging from the interest in this thread, it seems to be valuable. Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!transit3.readnews.com!news-out.readnews.com!transit4.readnews.com!postnews.google.com!s31g2000vbp.googlegroups.com!not-for-mail From: Sandro Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 13:41:54 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <8960dc91-7df2-473b-b133-0ab6111d587a@s31g2000vbp.googlegroups.com> References: <2me605lnnl3mnn0j73bta8vhvl51c1st91@4ax.com> <05897bcc-93f1-40f5-904a-1a8c0fe6d733@t10g2000vbg.googlegroups.com> <4A044DA0.60705@gmail.com> <97eab81b-29d5-46a7-8db2-5ae4371b3e50@x31g2000prc.googlegroups.com> <4bra05di2hslvjvjg3k824h2l73pgepifg@4ax.com> <0520e480-2a2e-49a8-954b-ada00890327a@m24g2000vbp.googlegroups.com> NNTP-Posting-Host: 84.220.118.25 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242074514 31411 127.0.0.1 (11 May 2009 20:41:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 20:41:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s31g2000vbp.googlegroups.com; posting-host=84.220.118.25; posting-account=OSNX1AoAAABZtvrWgfgFvYi2krfS2o9W User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009030814 Iceweasel/3.0.9 (Debian-3.0.9-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1111 comp.arch.fpga:3249 On May 11, 7:46=A0pm, rickman wrote: > My code is virtually this same thing. =A0The tool tells me I am trying > to infer two ports using distributed memory which it can't do. Rick, I don't know! It works fine to me (webpack ISE 10.1.03 - linux). Did you try to use shared variable ? In your previous example I saw only "<=3D" instead of ":=3D" to "assign" a shared variable... Sandro From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!w35g2000prg.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 16:04:48 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: NNTP-Posting-Host: 65.160.57.101 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242083088 27565 127.0.0.1 (11 May 2009 23:04:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 23:04:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000prg.googlegroups.com; posting-host=65.160.57.101; posting-account=oRX64woAAABTa-nV9zEYMkva4yias-ah User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1112 comp.arch.fpga:3252 On May 11, 1:29=A0pm, pe...@xilinx.com wrote: > I am surprised about the interest in write_first vs read_first. > The read output during a write operation came really about as an > afterthought. ("It's easy, theportis already there, so it costs > nothing"). > But why do you want to read from the same location that you are > writing to? For "READ_FIRST" it makes sense. Your reading an old value and the same time your updating a new value. For us it's an image processing algorithm, where pixels are going into a line buffer. We needed line[n-1] pixel value now (the READ data), along with the current value (the WRITE data). On the next line the previously written data is now line[n-1], repeat. So the address of the READ, and WRITE are ALWAYS the same (the column address). So (depending on how you count things) this consumes one RAM port. > Especially when you are reading what you already know, since you > simultaneously are writing it (which was the original mode). > Then we found that read-before-write was an easy modification, and > more valuable. I agree, "WRITE_FIRST" has more limited utility. I didn't know the history that was the only available mode previously. > But still: why do you read from the write address, when you have a > separate readportwith its own dedicated addressing available? Yes, Xilinx has "True Dual Port", but I'd rather code to the minimum that I need in tech independant manner, and let the tool build from what's available. If the tool can't build it I'd rather it barf and quit, rather than just build something willy-nilly that doesn't match the description. (okay, a bit snarky - I guess I'm still a little sore over all that time in the lab debugging an XST issue...) --Mark From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!k9g2000pra.googlegroups.com!not-for-mail From: peter@xilinx.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 16:39:25 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <6f1eceb6-92ce-45fb-bce8-ec1452d9b092@k9g2000pra.googlegroups.com> References: NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242085165 1711 127.0.0.1 (11 May 2009 23:39:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 May 2009 23:39:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000pra.googlegroups.com; posting-host=149.199.62.254; posting-account=XWkVzQoAAABTt_uQ5LvDXJs5hs3-FJh- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.18.1 (KHTML, like Gecko) Version/3.1.2 Safari/525.20.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1113 comp.arch.fpga:3253 On May 11, 4:04=A0pm, Mark wrote: > On May 11, 1:29=A0pm, pe...@xilinx.com wrote: > > > I am surprised about the interest in write_first vs read_first. > > The read output during a write operation came really about as an > > afterthought. ("It's easy, theportis already there, so it costs > > nothing"). > > But why do you want to read from the same location that you are > > writing to? > > For "READ_FIRST" it makes sense. =A0Your reading an old value and > the same time your updating a new value. =A0For us it's an image > processing algorithm, where pixels are going into a line buffer. > We needed line[n-1] pixel value now (the READ data), along with > the current value (the WRITE data). =A0On the next line the > previously written data is now line[n-1], repeat. =A0So the > address of the READ, and WRITE are ALWAYS the same (the column > address). =A0So (depending on how you count things) this consumes > one RAM port. > > > Especially when you are reading what you already know, since you > > simultaneously are writing it (which was the original mode). > > Then we found that read-before-write was an easy modification, and > > more valuable. > > I agree, "WRITE_FIRST" has more limited utility. =A0I didn't know > the history that was the only available mode previously. > > > But still: why do you read from the write address, when you have a > > separate readportwith its own dedicated addressing available? > > Yes, Xilinx has "True Dual Port", but I'd rather > code to the minimum that I need in tech independant manner, > and let the tool build from what's available. > > If the tool can't build it I'd rather it barf and quit, rather > than just build something willy-nilly that doesn't match the > description. =A0(okay, a bit snarky - I guess I'm still a little > sore over all that time in the lab debugging an XST issue...) > > --Mark Mark, there are clearly several different ways to implement your design: single port with read-before-write (the most elegant way), or dual-port with duplicated offset addressing, or even time-sequenced read-then-write, time permitting. It is frustrating to know that it can be done, but not be able to do it. Maybe you expect the synthesizers to be more versatile and smarter than they really are. Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!b7g2000pre.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Mon, 11 May 2009 17:57:09 -0700 (PDT) Organization: http://groups.google.com Lines: 74 Message-ID: <13b1780d-61c3-4573-8184-46369cdf8efc@b7g2000pre.googlegroups.com> References: 6f1eceb6-92ce-45fb-bce8-ec1452d9b092@k9g2000pra.googlegroups.com NNTP-Posting-Host: 65.160.57.101 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242089829 17344 127.0.0.1 (12 May 2009 00:57:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 00:57:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b7g2000pre.googlegroups.com; posting-host=65.160.57.101; posting-account=oRX64woAAABTa-nV9zEYMkva4yias-ah User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1114 comp.arch.fpga:3254 On May 11, 4:39=A0pm, pe...@xilinx.com wrote: > On May 11, 4:04=A0pm, Mark wrote: > > > > > > > On May 11, 1:29=A0pm, pe...@xilinx.com wrote: > > > > I am surprised about the interest in write_first vs read_first. > > > The read output during a write operation came really about as an > > > afterthought. ("It's easy, theportis already there, so it costs > > > nothing"). > > > But why do you want to read from the same location that you are > > > writing to? > > > For "READ_FIRST" it makes sense. =A0Your reading an old value and > > the same time your updating a new value. =A0For us it's an image > > processing algorithm, where pixels are going into a line buffer. > > We needed line[n-1] pixel value now (the READ data), along with > > the current value (the WRITE data). =A0On the next line the > > previously written data is now line[n-1], repeat. =A0So the > > address of the READ, and WRITE are ALWAYS the same (the column > > address). =A0So (depending on how you count things) this consumes > > one RAMport. > > > > Especially when you are reading what you already know, since you > > > simultaneously are writing it (which was the original mode). > > > Then we found that read-before-write was an easy modification, and > > > more valuable. > > > I agree, "WRITE_FIRST" has more limited utility. =A0I didn't know > > the history that was the only available mode previously. > > > > But still: why do you read from the write address, when you have a > > > separate readportwith its own dedicated addressing available? > > > Yes, Xilinx has "TrueDualPort", but I'd rather > > code to the minimum that I need in tech independant manner, > > and let the tool build from what's available. > > > If the tool can't build it I'd rather it barf and quit, rather > > than just build something willy-nilly that doesn't match the > > description. =A0(okay, a bit snarky - I guess I'm still a little > > sore over all that time in the lab debugging an XST issue...) > > > --Mark > > Mark, there are clearly several different ways to implement your > design: singleportwith read-before-write (the most elegant way), > ordual-portwith duplicated offset addressing, > or even time-sequenced read-then-write, time permitting. > It is frustrating to know that it can be done, but not be able to do > it. > Maybe you expect the synthesizers to be more versatile and smarter > than they really are. I'm not asking the synthesis tool to optimize across multiple solutions. A time-sequenced read-then-write would be an architecture change that certainly outside the scope of a synthesis tool. Inferring "Read_First" vs. "Write_First" behaviour correctly is quite easily within the scope of the tool. I just wanted to warn folks to check their template results closely in the log files for these inferred RAMS. I was bitten, and don't want others to repeat. --Mark From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!newsfeed1.swip.net!newsfeed1.funet.fi!newsfeed2.funet.fi!newsfeed3.funet.fi!newsfeeds.funet.fi!feeder2.news.saunalahti.fi!uutiset.elisa.fi!7564ea0f!not-for-mail From: Kim Enkovaara User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading References: <87tz3x88ft.fsf@harnisch.dyndns.org> <874ovwlyu6.fsf@pangea.home.gustad.com> <87vdo7dc0r.fsf@harnisch.dyndns.org> In-Reply-To: <87vdo7dc0r.fsf@harnisch.dyndns.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 24 Message-ID: Date: Tue, 12 May 2009 08:04:58 +0300 NNTP-Posting-Host: 138.111.130.175 X-Complaints-To: newsmaster@saunalahti.com X-Trace: uutiset.elisa.fi 1242104694 138.111.130.175 (Tue, 12 May 2009 08:04:54 EEST) NNTP-Posting-Date: Tue, 12 May 2009 08:04:54 EEST Organization: Elisa Customer Xref: news.eternal-september.org comp.lang.vhdl:1115 Marcus Harnisch wrote: > difficult enough I gather. Another requirement in simulation is the > capability to rerun a test *exactly* the same way it was executed > before. Having the simulation run in different threads in an > inherently non-deterministic environment (OS, other processes) and > putting these threads into a deterministic execution sequence almost > contradicts itself. I am sure EDA vendors are racking their heads for In theory the language should protect from this, the event rules are defined in the LRMs. And I think VHDL will be easier in this context because it is harder to do hazards in VHDL. But for Verilog this will be a real problem. Many commercial behavioral verilog models very often assume many things that are not guaranteed by the LRM (order of process execution etc.). Quite often "-keep_delta -compat" flags are needed in modelsim to get verilog models to work. But I would guess that the parallel execution will be done at least on design unit level. And most problematic language uses are usually contained inside design units, and the perimeter is pure synchronous logic. --Kim From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!b1g2000vbc.googlegroups.com!not-for-mail From: Dek Newsgroups: comp.lang.vhdl Subject: .txt files as testbench Date: Tue, 12 May 2009 01:10:29 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <319b44a2-9410-492e-ae55-fb93173799d4@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 193.206.247.117 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242115830 4668 127.0.0.1 (12 May 2009 08:10:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 08:10:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b1g2000vbc.googlegroups.com; posting-host=193.206.247.117; posting-account=MI-JoQoAAAClNCa-XUBGRwn6vFRujLck User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; WOW64; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.0.04506; Media Center PC 5.0; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1116 Hi everybody, I'm trying to simulate the behavior of an hardware design using as testbench data already stored in .txt files. In another thread Mike Treseler suggest me to do so: I prefer to convert existing text files to vhdl packages using a scripting language, since I am using one anyway to run modelsim. Now I would really like to try this way, but I have no idea of how to do that; in particular, do you have any exemple of packages containing data to be used for testbench? Sorry for the newbie question, but I have just started with VHDL. Thanks Bye Dek P.S. I already post this question, but since it was more focused on using TextIO I thought to create a new thread; I hope this doesn't bother anyone From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q2g2000vbr.googlegroups.com!not-for-mail From: goouse@twinmail.de Newsgroups: comp.lang.vhdl Subject: Re: .txt files as testbench Date: Tue, 12 May 2009 02:47:58 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: <319b44a2-9410-492e-ae55-fb93173799d4@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242121678 23882 127.0.0.1 (12 May 2009 09:47:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 09:47:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbr.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.9) Gecko/2009050519 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1117 On 12 Mai, 10:10, Dek wrote: > Hi everybody, > > I'm trying to simulate the behavior of an hardware design using as > testbench data already stored in .txt files. In another thread Mike > Treseler suggest me to do so: > > I prefer to convert existing text files to vhdl packages > using a scripting language, since I am using one anyway > to run modelsim. > > Now I would really like to try this way, but I have no idea of how to > do that; in particular, do you have any exemple of packages containing > data to be used for testbench? Sorry for the newbie question, but I > have just started with VHDL. > > Thanks > > Bye > > Dek > > P.S. I already post this question, but since it was more focused on > using TextIO I thought to create a new thread; I hope this doesn't > bother anyone Hi Dek, matlab uses this approach for generating testbenches. The test vectors there are derived from a simulink environment, but the vectors are written to a (large) array and fed to the DUT. The feeding procedure and the test vector array are part of a package that is generated by the matlab tools (generatetb). But writing some functions/procedures/processes that read the vectors directly from a text file is simpler and much more straight forward. There is an opencores project that may be helpful for your purpose: http://www.opencores.org/?do=project&who=vhld_tb Have a nice simulation Eilert From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: ModelSim & Multithreading Date: Tue, 12 May 2009 14:39:10 +0200 Lines: 27 Message-ID: <87octycx75.fsf@harnisch.dyndns.org> References: <87tz3x88ft.fsf@harnisch.dyndns.org> <874ovwlyu6.fsf@pangea.home.gustad.com> <87vdo7dc0r.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net MxyqEWWS6HgWzG2QQvfIEQblyBwLioFnYIpICdQ2YReHR54Kb7 Cancel-Lock: sha1:hETzUoBC1SKNzZVW2qVfHksQ21w= sha1:Gm2DaYmp/k8bRRrmQAFM8d/peco= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:1118 Kim Enkovaara writes: > In theory the language should protect from this, the event rules are > defined in the LRMs. And I think VHDL will be easier in this context > because it is harder to do hazards in VHDL. Likely. But honestly, who cares. > But for Verilog this will be a real problem. Many commercial > behavioral verilog models very often assume many things that are not > guaranteed by the LRM (order of process execution etc.). That is the point. EDA tools are written with Verilog in mind. It has got to work with Verilog and, worse because of additional timing phases, SystemVerilog. Everything else is secondary to EDA vendors. Nobody would implement such a feature for VHDL, saying that Verilog support was planned for a future release. Regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:37 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!q2g2000vbr.googlegroups.com!not-for-mail From: Kenneth Brun Nielsen Newsgroups: comp.lang.vhdl Subject: Generate pulse on change Date: Tue, 12 May 2009 08:33:17 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: NNTP-Posting-Host: 80.196.98.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242142398 17424 127.0.0.1 (12 May 2009 15:33:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 15:33:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbr.googlegroups.com; posting-host=80.196.98.142; posting-account=Y2qrgwkAAACbbT37NX8gk-aSqpI-3T6p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; SLCC1; .NET CLR 2.0.50727; InfoPath.2; .NET CLR 3.5.30729; .NET CLR 3.0.30618; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1119 I want to monitor a (vector) signal and generate a pulse of a specified length (in time) whenever (any of the bits in) the signal changes value. Does VHDL feature a simple way to do that? A primitive solution would be to XOR each signal bit with a delayed replica of itself, but I assume that VHDL has better ways of implementing this? It does only have to work in simulations. Best regards, Kenneth From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p4g2000vba.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Generate pulse on change Date: Tue, 12 May 2009 08:45:57 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <72a94edd-1c2e-497c-ae65-7639889f451b@p4g2000vba.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242143158 19863 127.0.0.1 (12 May 2009 15:45:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 15:45:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p4g2000vba.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1120 On 12 May, 16:33, Kenneth Brun Nielsen wrote: > I want to monitor a (vector) signal and generate a pulse of a > specified length (in time) whenever (any of the bits in) the signal > changes value. > > Does VHDL feature a simple way to do that? > > A primitive solution would be to XOR each signal bit with a delayed > replica of itself, but I assume that VHDL has better ways of > implementing this? > > It does only have to work in simulations. > > Best regards, > Kenneth If its for simulation only, try this (modify for your own needs: pulse_proc : process begin --initialise pulse (if you havent already) pulse <= '0'; while true loop --only needed if you leave the above line in wait until my_bus'event; pulse <= '1', '0' after 10ns; end loop; end process; With this, the pulse will be extended if there is another change during the pulse high period. From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g3g2000pra.googlegroups.com!not-for-mail From: peter@xilinx.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Tue, 12 May 2009 09:09:42 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <6ed9b233-ab38-4221-948e-f09c8c72a8e7@g3g2000pra.googlegroups.com> References: NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242144582 2225 127.0.0.1 (12 May 2009 16:09:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 16:09:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g3g2000pra.googlegroups.com; posting-host=149.199.62.254; posting-account=XWkVzQoAAABTt_uQ5LvDXJs5hs3-FJh- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_5_6; en-us) AppleWebKit/525.18.1 (KHTML, like Gecko) Version/3.1.2 Safari/525.20.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1121 comp.arch.fpga:3268 On May 11, 4:04=A0pm, Mark wrote: > On May 11, 1:29=A0pm, pe...@xilinx.com wrote: > > > I am surprised about the interest in write_first vs read_first. > > The read output during a write operation came really about as an > > afterthought. ("It's easy, theportis already there, so it costs > > nothing"). > > But why do you want to read from the same location that you are > > writing to? > > For "READ_FIRST" it makes sense. =A0Your reading an old value and > the same time your updating a new value. =A0For us it's an image > processing algorithm, where pixels are going into a line buffer. > We needed line[n-1] pixel value now (the READ data), along with > the current value (the WRITE data). =A0On the next line the > previously written data is now line[n-1], repeat. =A0So the > address of the READ, and WRITE are ALWAYS the same (the column > address). =A0So (depending on how you count things) this consumes > one RAM port. > > > Especially when you are reading what you already know, since you > > simultaneously are writing it (which was the original mode). > > Then we found that read-before-write was an easy modification, and > > more valuable. > > I agree, "WRITE_FIRST" has more limited utility. =A0I didn't know > the history that was the only available mode previously. > > > But still: why do you read from the write address, when you have a > > separate readportwith its own dedicated addressing available? > > Yes, Xilinx has "True Dual Port", but I'd rather > code to the minimum that I need in tech independant manner, > and let the tool build from what's available. > > If the tool can't build it I'd rather it barf and quit, rather > than just build something willy-nilly that doesn't match the > description. =A0(okay, a bit snarky - I guess I'm still a little > sore over all that time in the lab debugging an XST issue...) > > --Mark Mark, I listened to Obama's comment that his wife "has the right to bear (bare) arms". That was a very clever pun, but it would not translate into any other language. If you expect your talk to be translated automatically (or even by humans) into French, German, or Chinese, you have to avoid all such clever constructs, and go for boring middle-of-the-road statements. Same with logic design. If you design generically, you miss out on many subtleties. This is not meant as an excuse for Xilinx to misunderstand relatively simple BRAM constructs... Peter Alfke From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f1g2000prb.googlegroups.com!not-for-mail From: shrinivas.jyothi@gmail.com Newsgroups: comp.lang.vhdl Subject: Read and Write process verification Date: Tue, 12 May 2009 09:23:33 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: NNTP-Posting-Host: 125.99.249.124 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242145414 26906 127.0.0.1 (12 May 2009 16:23:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 May 2009 16:23:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f1g2000prb.googlegroups.com; posting-host=125.99.249.124; posting-account=IRxnLgkAAAA4H7uc0muXvvWJOHXd2rcp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1122 Hi All, Presently i am working on a verification project and writing Testcase's for a funtional element requirements. I have a requirement: Bit 0 of the rcom_ctl_sts register returns a 1 within 1 us when a one valid message has been received on the RCOM receiver and written to buffer 0. So for this requirement i am writing steps to verify a valid rcom message (with Manchester encoding) received to buffer 0. The rcom message where its format is : Start Bits - Header word - Data word- Check word - Parity Steps: ------- 1). After transmition a single word message 2). I am reading the every rcom message word from the register READ (0x01080) // Read process, and this register gives header READ (0x01081) // This register address gives data word so my question is Can we READ these values continously without any waiting or We should be wait for some time and then read next value. Say : WAIT FOR 50 ns READ (0x01080) WAIT FOR 50 ns READ (0x01081) Is this correct way or without waiting Reading the values is correct way? Where all the values will displays on dsp_d(31:0) output signal. Please anyone suggest me which one has to follow... Sreeni.J From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Read and Write process verification Date: Tue, 12 May 2009 10:19:21 -0700 Lines: 55 Message-ID: <76tpcpF1e0sgcU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net kbTuWvk8ab67mCumuLtdIgaxSi63LNQwHE54fXaelKMBiwYpKK Cancel-Lock: sha1:SeQeloGS7x6HEavXE1u4YZQnpyg= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1123 shrinivas.jyothi@gmail.com wrote: > We should wait for some time and then read next value. Yes, unless your read procedure has enough delay. > Say : WAIT FOR 50 ns > READ (0x01080) > WAIT FOR 50 ns > READ (0x01081) That would be ok with a few of these ';' I would prefer to say handshake(rd_ack_s,clk_en_s); using procedures something like this: procedure tic (arg : natural := 1) is begin for i in 1 to arg loop wait until rising_edge(clk_s); end loop; end procedure tic; procedure handshake( signal waiting_on : in std_ulogic; signal enable : inout std_ulogic; happy : in string := "handshake: Saw ack."; sad : in string := "handshake: Gave up waiting."; goal : in std_ulogic := '1'; bail : in natural := 10) is variable delay_v : natural := 0; begin while waiting_on /= goal loop -- report("handshake: waiting "); delay_v := delay_v + 1; if delay_v = bail then report sad; tic(10) enable <= '0'; -- stop sim clock tic; end if; tic; -- wait one sim clock period end loop; --report(happy); end procedure handshake; > Where all the values will displays on dsp_d(31:0) output signal. for modelsim use: add wave -r /* before running the sim. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r36g2000vbr.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Dual Port RAM Inference Date: Tue, 12 May 2009 22:15:03 -0700 (PDT) Organization: http://groups.google.com Lines: 92 Message-ID: <06fa04d9-dcc3-4797-9635-4ba111f9e810@r36g2000vbr.googlegroups.com> References: NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242191703 8099 127.0.0.1 (13 May 2009 05:15:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 May 2009 05:15:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbr.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1124 comp.arch.fpga:3281 On May 11, 4:29=A0pm, pe...@xilinx.com wrote: > On May 11, 12:43=A0pm, Mark wrote: > > > > > I know I'm a little late on this thread, but offer my two cents, > > on what we use, and a warning as well. > > > We use dual-port RAMS (same clock) with inference, and don't have > > trouble. =A0It's in verilog, and it's READ_FIRST. =A0So two strikes > > against it for what you're looking for Rick. =A0(you want VHDL, and > > WRITE_FIRST, I beleive). =A0We call this our "mem2rw1clk" module. > > > But here's what we do (minus header/etc): > > > always @( posedge clk ) > > begin > > =A0 if( en0 ) > > =A0 begin > > =A0 =A0 if( wren0 ) > > =A0 =A0 =A0 mem[ addr0 ] <=3D wdata0; > > =A0 =A0 rdata0 <=3D mem[ addr0 ]; > > =A0 end > > end > > > always @( posedge clk ) > > begin > > =A0 if( en1 ) > > =A0 begin > > =A0 =A0 if( wren1 ) > > =A0 =A0 =A0 mem[ addr1 ] <=3D wdata1; > > =A0 =A0 rdata1 <=3D mem[ addr1 ]; > > =A0 end > > end > > > So, two almost identical always blocks, operating on the same RAM. > > Since we use non-blocking assignments, the READ_FIRST is implied > > (correctly by XST). > > > Works, and we've been using it for many designs no trouble. > > > Now the warning: > > > We use almost the EXACT same structure for implementing a pseudo > > dual port - i.e. an independant READ port, and a WRITE port > > (same clock) "mem1r1w1clk". =A0 =A0I.e. the type of memory you'd > > use for a synchronous fifo. =A0The logic is again clearly coded for > > READ_FIRST. > > > Well, XST was (sometimes) inferring WRITE_FIRST. =A0So, simulation > > vs implementation mismatch. =A0It only mattered in a few places > > we were specifically ALWAYS reading the same location as we > > were writing in the same cycle. You get quite different results. > > Spent 2-3 weeks on the bench figuring out this one. > > > So - check the XST report to make sure it's inferring the > > correct READ_FIRST vs. WRITE_FIRST behaviour. =A0XST can get things > > wrong here. > > > Regards, > > > Mark > > I am surprised about the interest in write_first vs read_first. > The read output during a write operation came really about as an > afterthought. ("It's easy, the port is already there, so it costs > nothing"). > But why do you want to read from the same location that you are > writing to? > Especially when you are reading what you already know, since you > simultaneously are writing it (which was the original mode). > Then we found that read-before-write was an easy modification, and > more valuable. > But still: why do you read from the write address, when you have a > separate read port with its own dedicated addressing available? > > But, judging from the interest in this thread, it seems to be > valuable. > Peter Alfke That's easy. In my case I am using the ram as a stack, two actually. Each port has to read whatever was last written because it does *not* have an independent read port and the read data has to reflect the top of the stack at all times. The ram is shared as two stacks to save space since the entire depth of the block ram is not needed. Thinking that the read port does not need to reflect the last written data is a very limited perspective. *I* may know what was written, but whatever is connected to the read port does not know it unless the read port reflects it. Rick From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: Kenneth Brun Nielsen Newsgroups: comp.lang.vhdl Subject: Re: Generate pulse on change Date: Wed, 13 May 2009 04:47:38 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <58fb50ac-8180-4f5f-9ac3-5357ac26dfbb@r34g2000vba.googlegroups.com> References: <72a94edd-1c2e-497c-ae65-7639889f451b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 80.196.98.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242215259 7590 127.0.0.1 (13 May 2009 11:47:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 May 2009 11:47:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=80.196.98.142; posting-account=Y2qrgwkAAACbbT37NX8gk-aSqpI-3T6p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; SLCC1; .NET CLR 2.0.50727; InfoPath.2; .NET CLR 3.5.30729; .NET CLR 3.0.30618; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1125 On 12 Maj, 17:45, Tricky wrote: > =A0 =A0 pulse <=3D '1', '0' after 10ns; Thanks. Just what I needed :) /Kenneth From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: .txt files as testbench Date: Wed, 13 May 2009 11:34:38 -0700 Lines: 44 Message-ID: <770i60F1equm7U1@mid.individual.net> References: <319b44a2-9410-492e-ae55-fb93173799d4@b1g2000vbc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net kwFgW3WuUjMRWPkadlq72A6tNlJ2wDvl9bVqe04DvUcABM1NDX Cancel-Lock: sha1:Nmi+eAZ1OQ94mLfVFqlpDcKL3gY= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <319b44a2-9410-492e-ae55-fb93173799d4@b1g2000vbc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1126 Dek wrote: > do you have any exemple of packages containing > data to be used for testbench? Here is an example vector array constant that could be used by a testbench. In simple cases, I might use a editor macro rather than a script to convert the raw text file. -- Mike Treseler ___________________________________ library ieee; use ieee.std_logic_1164.all; package my_pkg is constant data_length : natural := 16; constant add_length : natural := 10; constant mem_size : natural := 2**add_length; type mem_type is array (mem_size-1 downto 0) of std_logic_vector (data_length-1 downto 0); constant mem : mem_type := ( 0 => x"abcd", 1 => x"beef", 2 => x"5555", 3 => x"1010", 4 => x"5a6b", 5 => x"f0f0", 6 => x"1234", 7 => x"fabc", 8 => x"2345", 9 => x"9876", 10 => x"5432", 11 => x"6666", 12 => x"0101", 13 => x"abab", others => x"4247"); end package my_pkg; From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!m24g2000vbp.googlegroups.com!not-for-mail From: Kenneth Brun Nielsen Newsgroups: comp.lang.vhdl Subject: Lazy man's testbench Date: Thu, 14 May 2009 04:31:01 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <18afdcd6-64ca-4915-8490-236ad9cc3ef8@m24g2000vbp.googlegroups.com> NNTP-Posting-Host: 80.196.98.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242300661 19646 127.0.0.1 (14 May 2009 11:31:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 May 2009 11:31:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m24g2000vbp.googlegroups.com; posting-host=80.196.98.142; posting-account=Y2qrgwkAAACbbT37NX8gk-aSqpI-3T6p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; SLCC1; .NET CLR 2.0.50727; InfoPath.2; .NET CLR 3.5.30729; .NET CLR 3.0.30618; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1127 A testbench, that reads input levels from columns in an input file, and writes outputs to another file, must be a widely used block(?). Does any of you have (a link to) a template I can use? Or do I have to spend the entire day coding one? Best regards, Kenneth From newsfish@newsfish Wed Aug 19 13:24:38 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Lazy man's testbench Date: Thu, 14 May 2009 10:39:18 -0700 Lines: 21 Message-ID: <7733a6F1fg6jlU1@mid.individual.net> References: <18afdcd6-64ca-4915-8490-236ad9cc3ef8@m24g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ezPvwnrfGuLwBMyYy0TBOAqAHT46cTfdoVGhzMcAX6s3/dFMCJ Cancel-Lock: sha1:aYrS76HudzBxVhHKilFDF9d9txw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <18afdcd6-64ca-4915-8490-236ad9cc3ef8@m24g2000vbp.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1128 Kenneth Brun Nielsen wrote: > A testbench, that reads input levels from columns in an input file, > and writes outputs to another file, must be a widely used block(?). If I already have a device model, and an appropriate testbench, I could collect such files from my simulator. Writing the model and testbench is the problem, and there is no generic solution. Unless I am feeding a device tester, I have no need of such "test vector" files. If you do, google a bit: http://www.actel.com/documents/TestVector_AN.pdf > Do any of you have (a link to) a template I can use? Or do I have to > spend the entire day coding one? It might take more than a day. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v17g2000vbb.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: comp.lang.vhdl Subject: CFP with Deadline of May 27, 2009: WORLDCOMP'09 (joint conferences in computer science, computer engineering, and applied computing), USA, July 13-16, 2009 Date: Thu, 14 May 2009 19:02:56 -0700 (PDT) Organization: http://groups.google.com Lines: 181 Message-ID: NNTP-Posting-Host: 70.64.147.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242352976 21460 127.0.0.1 (15 May 2009 02:02:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 May 2009 02:02:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v17g2000vbb.googlegroups.com; posting-host=70.64.147.19; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1129 Call For Papers - Deadline: May 27, 2009 WORLDCOMP'09 The 2009 World Congress in Computer Science, Computer Engineering, and Applied Computing Date and Location: July 13-16, 2009, Las Vegas, USA http://www.world-academy-of-science.org/ Indexing: Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others. You are invited to submit a paper (see instructions below.) This announcement is ONLY for those who missed the opportunity to submit their papers in response to earlier announcements (authors who have already been notified that their papers have been accepted/not-accepted should IGNORE this announcement.) WORLDCOMP'09 is composed of a number of tracks (joint-conferences, tutorials, and workshops); all will be held simultaneously, same location and dates: July 13-16, 2009. For the complete list of joint conferences, see: http://www.world-academy-of-science.org/ This is a Call For Papers for publication in the Final Edition of the conference proceedings. All papers submitted in response to this announcement will be evaluated for publication in the Final Edition of the proceedings which will go to press soon after the conference (publication date: late August 2009). IMPORTANT DATES: May 27, 2009: Submission of full papers for evaluation (about 7 pages) June 10, 2009: Notification of acceptance June 24, 2009: Registration July 13-16, 2009: WORLDCOMP'09 Congress (all joint-conferences) July 24, 2009: Camera-Ready Papers Due for publication in the Final Edition of the proceedings. SUBMISSION OF PAPERS: Prospective authors are invited to submit/upload their papers in pdf or MS doc (about 7 pages, single spaced with the font size of 10 or 11) to the following web site: http://worldcomp.cviog.uga.edu/ All reasonable typesetting formats are acceptable. Authors of accepted papers will later be asked to follow a particular typing instructions to prepare their final paper for publication. Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. Accepted papers will be published in the final edition of the respective proceedings/books. All submissions will be evaluated for originality, significance, clarity, and soundness. Each paper will be refereed by two researchers in the topical area. All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others. LIST OF CONFERENCES: BIOCOMP'09: International Conf. on Bioinformatics & Computational Biology CDES'09: International Conf. on Computer Design CGVR'09: International Conf. on Computer Graphics & Virtual Reality CSC'09: International Conf. on Scientific Computing DMIN'09: International Conf. on Data Mining EEE'09: International Conf. on e-Learning, e-Business, Enterprise Information Systems, & e-Government ERSA'09: International Conf. on Engineering of Reconfigurable Systems and Algorithms ESA'09: International Conf. on Embedded Systems & Applications FCS'09: International Conf. on Foundations of Computer Science FECS'09: International Conf. on Frontiers in Education: Computer Science & Computer Engineering GCA'09: International Conf. on Grid Computing & Applications GEM'09: International Conf. on Genetic & Evolutionary Methods ICAI'09: International Conf. on Artificial Intelligence ICOMP'09: International Conf. on Internet Computing ICWN'09: International Conf. on Wireless Networks IKE'09: International Conf. on Information & Knowledge Engineering IPCV'09: International Conf. on Image Processing, Computer Vision, & Pattern Recognition MSV'09: International Conf. on Modeling, Simulation & Visualization Methods PDPTA'09: International Conf. on Parallel and Distributed Processing Techniques & Applications SAM'09: International Conf. on Security and Management SERP'09: International Conf. on Software Engineering Research and Practice SWWS'09: International Conf. on Semantic Web and Web Services PLANNED TUTORIALS: See the following web site for a partial list: http://www.world-academy-of-science.org/worldcomp09/ws/tutorials KEYNOTE LECTURES: See the following web site for a partial list: http://www.world-academy-of-science.org/worldcomp09/ws/keynotes LOCATION OF CONFERENCE: WORLDCOMP will be held in the Monte Carlo hotel, Las Vegas, USA (with any overflows at other near-by hotels). This is a mega hotel with excellent conference facilities and over 3,000 rooms. It is minutes from the airport with 24-hour shuttle service to and from the airport. This hotel has many recreational attractions, including: spa, pools, sunning decks, Easy River, wave pool, lighted tennis courts, nightly shows, a number of restaurants, ... The negotiated room rate for conference attendees is very reasonable. The hotel is within walking distance from most other attractions. SPONSORS: Academic/Technical Co-Sponsors: (a partial list) -> United States Military Academy, Network Science Center -> Biomedical Cybernetics Lab., HST of Harvard University and MIT, USA -> Argonne's Leadership Computing Facility of Argonne National Laboratory, USA -> Functional Genomics Laboratory, University of Illinois at Urbana-Champaign, USA -> Minnesota Supercomputing Institute, University of Minnesota, USA -> Intelligent Data Exploration and Analysis Laboratory, University of Texas at Austin, Austin, Texas, USA -> Harvard Statistics Department Genomics & Bioinformatics Laboratory, Harvard University, USA -> Texas Advanced Computing Center, The University of Texas at Austin, Texas, USA -> Center for the Bioinformatics and Computational Genomics, Georgia Institute of Technology, Atlanta, Georgia, USA -> Bioinformatics & Computational Biology Program, George Mason University, Virginia, USA -> Institute of Discrete Mathematics and Geometry, Vienna University of Technology, Austria -> BioMedical Informatics & Bio-Imaging Laboratory, Georgia Institute of Technology and Emory University, Georgia, USA -> Knowledge Management & Intelligent System Center (KMIS) of University of Siegen, Germany -> National Institute for Health Research, UK -> Hawkeye Radiology Informatics, Department of Radiology, College of Medicine, University of Iowa, Iowa, USA -> Institute for Informatics Problems of the Russian Academy of Sciences, Moscow, Russia. -> Medical Image HPC & Informatics Lab (MiHi Lab), University of Iowa, Iowa, USA -> SECLAB University of Naples Federico II, University of Naples Parthenope, and the Second University of Naples, Italy -> The University of North Dakota, Grand Forks, North Dakota, USA -> Intelligent Cyberspace Engineeing Lab., ICEL, Texas A&M University (Com./Texas), USA -> International Society of Intelligent Biological Medicine -> World Academy of Biomedical Sciences and Technologies Other Co-Sponsors: -> European Commission -> Super Micro Computer, Inc., San Jose, California, USA -> High Performance Computing for Nanotechnology (HPCNano) -> HoIP - Health without Boundaries -> The International Council on Medical and Care Compunetics -> The UK Department for Business, Enterprise & Regulatory Reform -> VMW Solutions Ltd. -> Scientific Technologies Corporation -> Hodges' Health -> Bentham Science Publishers -> GridToday From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r36g2000vbr.googlegroups.com!not-for-mail From: Paddy3118 Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Thu, 14 May 2009 22:33:46 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <6af95655-ad72-4aa5-b0b6-dfda5f364289@r36g2000vbr.googlegroups.com> References: NNTP-Posting-Host: 62.30.218.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242365626 26425 127.0.0.1 (15 May 2009 05:33:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 May 2009 05:33:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbr.googlegroups.com; posting-host=62.30.218.93; posting-account=p34d-wkAAAC60rn_Tuk_HKyjfq-hlvCF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1130 On May 7, 1:58=A0pm, Paddy3118 wrote: > Would someone reply with /why/ it is that an instantiated component > must be compiled before that which instantiates it in VHDL? > I find it irksome to create a compile orderwhich may span sources in > multiple libraries and think I would be less annoyed if i knew what > this rule is /for/. > > I've been told that VHDL is based on some mil. language that had this > feature (Algol? Ada?), but if so, what is the reason it was added to > its precursor language, and why do we keep it now? > > I can see that maybe compiler checks for source code updates against > compiled libraries (a la make), are useful, but I cannot find what > this VHDL compile rule gives you. > > - Paddy. > > Thanks in advance for your help. >From the answers given so far, (my thanks); it seems that this compilation ordering restriction allows more static language checking to be done at compilation, but no more than could be done by un- ordered compilation followed by machine ordering during elaboration. I still think you would be more productive by dropping this sometimes arduous constraint from the language and moving to machine ordering during elaboration for a slight drop in what can be checked at compile time. You will have to elaborate to complete the static compiler-type checks anyway so why not let the computer take the strain? - Paddy. From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p4g2000vba.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Version Control for VHDL Project Date: Fri, 15 May 2009 18:28:05 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 84.119.14.99 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242437285 21930 127.0.0.1 (16 May 2009 01:28:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 May 2009 01:28:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p4g2000vba.googlegroups.com; posting-host=84.119.14.99; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1131 Hi, I've worked on a few tiny VHDL projects in the past and since I have to write a bigger project for my university, I wanted to ask how you guys use source control on projects using multiple libraries. I know how to use version control in general, the question is how to work with those libraries. For example: Consider a design using some sort of softcore processor and peripheral modules for that processor. I would make a seperate library for each module as well as for the processor itself. This way the modules itself could be reused. In that case I would also use a different repository for each module (We use Subversion and Git for Version control). If I would do it that way, I would have a problem taging a specific revision (for example the first version delivered to the client). Do you use tags? Do you use SVN/Git externals/submodules? Do you structurize you code in a way to make is neccesary to use more than one "level" of libraries in you projects? (For example a Design using an AES core itself using a librarie providing the S-Box for AES (shared by AES and DES))? I would really appreciate information how you handle multiple libraries, because each scenario we thought of seems to be flawed in some way. The second reason I ask this is: While I do study electronics, I'm also very much into programming. Because I that, a colleague and I started working on a program to edit VHDL/Verilog Code, much like HDL Designer from Mentor. (Yes we know this is a lot of work, and yes we have done project in a reasonable size before to know what awaits us). Although It is not ready to be tested in a real world situation, I was interested how you handle such version control issues, so we might be able to incorporate such functionality. (At the moment the only thing it can do is managing various libraries and open VHDL files to edit them) I hope I have explained myself clear and not missed a note regarding that issue in my search on the list. Regards, Andreas From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.unit0.net!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 16 May 2009 00:00:08 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: AHB monitor-would like to share free code Date: Fri, 15 May 2009 21:56:22 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 79.178.102.105 Lines: 20 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-9AiB1ARWcfPqX+exMene02CG7V+uRZ8vNBN9YRKY65HAZTboV9AUj6GhY6HitzljKJAxkRC2NDglaGr!LpehjpXPW6qcEz/8mKbunBo+utnOpF2AYKp3LRjaeFlvplut7UB6RXDCERfDgQ== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 7 X-Original-Bytes: 1784 Xref: news.eternal-september.org comp.lang.vhdl:1132 The following will show a simple AHB monitor. The monitor can be applied to any AHB bus to debug the activity of the bus. 1. The monitor is easily attached to an AHB interface. 2. The monitor does not replace a conventional debug with waves procedure. 3. Sometimes simulation are very long, which makes it impossible to record waves for the entire simulation. The monitor helps you locate those areas, which need debug and waves. ... 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html) -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90148 From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 16 May 2009 05:47:01 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Sat, 16 May 2009 11:44:26 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <6af95655-ad72-4aa5-b0b6-dfda5f364289@r36g2000vbr.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 67 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-QTphSQFVlSa9S8kkyl6l6HCX/JIPX3OgBdqJPJVLq5xKa1pMqi7coTIhGnnNfV7eW0x6U3saK8L0sLq!c6V68j2NiE4Mjlh6lYPGN9qUxjTM4AwqElVKM18MtWsvWWHBNSGs/WmztYxeuriyPpJvsrLtKFHi!n10qk9Y65u3jvg0O X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1133 On Thu, 14 May 2009 22:33:46 -0700 (PDT), Paddy3118 wrote: >From the answers given so far, (my thanks); it seems that this >compilation ordering restriction First, please get your facts straight. VHDL does *not* require ordered compilation if you choose to use component declaration rather than direct entity instantiation. Many folk choose not to take advantage of this, because they find that direct instantiation (with the consequent compile-ordering concerns) is less trouble and at least as flexible. > allows more static language checking >to be done at compilation, but no more than could be done by un- >ordered compilation followed by machine ordering during elaboration. Yes, but the static checking gets done module-by-module in VHDL, so your errors are localized. That, surely, is precisely why any half-decent language separates interface (component declaration, function prototype) from implementation (entity/architecture, function body). If you are happy to write all your code and find critical errors of interconnect only right at the very end, then good luck to you. If, like me, you prefer to localize your decisions and have those decisions checked early in the coding process, then VHDL's way is good. Verilog is the obvious existence-proof that you can indeed design a language that does not require such declaration of module interfaces, and performs all the interface-connectivity checking at the end of elaboration, long after you've made all your mistakes. >I still think you would be more productive by dropping this sometimes >arduous constraint from the language and moving to machine ordering >during elaboration for a slight drop in what can be checked at compile >time. Personally I very much disagree, but you're entitled to your opinion and many others share it with you. > You will have to elaborate to complete the static compiler-type >checks anyway Why so? VHDL's rules for all practical purposes ensure that complete, successful compilation will produce a bunch of library objects that are guaranteed to elaborate successfully. Of course you must do the elaboration at some point, but in VHDL that's not primarily to complete the checking; it's to build the model that you will simulate/synthesize. > so why not let the computer take the strain? On this point I totally agree with you. But I don't find it any strain at all to tell VHDL what I think I'm doing, so that it can check my assumptions for me. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp6-2.free.fr!not-for-mail Date: Sat, 16 May 2009 18:31:23 +0200 From: Nicolas Matringe User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? References: <6af95655-ad72-4aa5-b0b6-dfda5f364289@r36g2000vbr.googlegroups.com> In-Reply-To: <6af95655-ad72-4aa5-b0b6-dfda5f364289@r36g2000vbr.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 8 Message-ID: <4a0eea5b$0$27552$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 16 May 2009 18:31:23 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1242491483 news-2.free.fr 27552 82.246.229.10:1089 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:1134 Paddy3118 a écrit : > [...] why not let the computer take the strain? With emacs VHDL mode I let the computer take the strain of generating a complete and ordered makefile so that I don't have to bother about compile order. Nicolas From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Reason for compile ordering? Date: Sat, 16 May 2009 09:42:15 -0700 Lines: 15 Message-ID: <4A0EECE7.8020204@gmail.com> References: <6af95655-ad72-4aa5-b0b6-dfda5f364289@r36g2000vbr.googlegroups.com> <4a0eea5b$0$27552$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net Ia/9CPtZDADXyN3nWf0m7AlGRgjCc+7rpP3aK+TGCKjS+XT4Q9 Cancel-Lock: sha1:nJzywLRkQjITRTbpOHrJqW5X/lM= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <4a0eea5b$0$27552$426a74cc@news.free.fr> Xref: news.eternal-september.org comp.lang.vhdl:1135 Nicolas Matringe wrote: > Paddy3118 a écrit : >> [...] why not let the computer take the strain? > > With emacs VHDL mode I let the computer take the strain of generating a > complete and ordered makefile so that I don't have to bother about > compile order. ... or having to look at the makefile, or bother with a license server. Right-click, [Make] Indeed, let the computer do some work. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 16 May 2009 16:32:50 -0700 Lines: 18 Message-ID: <4A0F4D22.5010907@gmail.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net yEerDhfeViY+FtaUonoJSwhWDdbsikU8kbb4dn8CTzd7bqwInF Cancel-Lock: sha1:mqn86NvwLSEtOIcrw+34atI6Sb4= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1136 AndreasWallner wrote: > I've worked on a few tiny VHDL projects in the past and since I have > to write a bigger project for my university, I wanted to ask how you > guys use source control on projects using multiple libraries. I prefer multiple packages, but one library (work) to simplify the sources and be compatible with vhdl-mode makefiles. > The second reason I ask this is: While I do study electronics, I'm > also very much into programming. Because I that, a colleague and I > started working on a program to edit VHDL/Verilog Code, much like HDL > Designer from Mentor. Have a look at vhdl-mode first. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:39 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o30g2000vbc.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 16 May 2009 16:53:19 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> NNTP-Posting-Host: 84.119.14.99 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242517999 16891 127.0.0.1 (16 May 2009 23:53:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 May 2009 23:53:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o30g2000vbc.googlegroups.com; posting-host=84.119.14.99; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1137 On May 17, 1:32=A0am, Mike Treseler wrote: > AndreasWallner wrote: > > I've worked on a few tiny VHDL projects in the past and since I have > > to write a bigger project for my university, I wanted to ask how you > > guys use source control on projects using multiple libraries. > > I prefer multiple packages, but one library (work) to > simplify the sources and be compatible with > vhdl-mode makefiles. Ok, I think we misunderstood each other. Thats because I did not mean library in the sense of an VHDL Library (like work or ieee), but library in the sense of a module providing some sort of functionality. (So more in the sense of a normal software library). Excuse me, but that's the way HDL Designer uses the term library too...while writing I forgot it could be misleading. The question I had in mind was really more: How do you manage to track the state of self written IP Cores and the top level project with your version tracking system. Espacially if you want to tag the whole project, how do you ensure the correct version of the used IP cores is used. I hope that cleared our misunderstanding. > Have a look at vhdl-mode first. I know vhdl-mode and it is somehow great...but it's not as much fun as writing your own piece of software (everybody has to have a hobby ;-) ) Regards, Andreas From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 16 May 2009 18:31:32 -0700 Lines: 24 Message-ID: <4A0F68F4.7080608@gmail.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net B8ZwmR4449boUOuuyCyyuwSvdyoH4/P2eMqtMyWhd08SO2wzNG Cancel-Lock: sha1:xBsWOYg6KOsIq17fP/8WPFl2Kgg= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1138 AndreasWallner wrote: > The question I had in mind was really more: How do you manage to track > the state of self written IP Cores and the top level project with your > version tracking system. Especially if you want to tag the whole > project, how do you ensure the correct version of the used IP cores is > used. There's little difference between tags and branches in Subversion. Both are directories that are created by a copy. If I don't commit changes, it stays a tag or "snapshot". If I commit a change, it becomes a branch. >> Have a look at vhdl-mode first. > I know vhdl-mode and it is somehow great...but it's not as much fun as > writing your own piece of software (everybody has to have a > hobby ;-) ) Go for it. But vhdl-mode sets the bar high. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi067.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> Subject: Re: Version Control for VHDL Project Lines: 62 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Response X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi067.nbdc.sbc.com 1242526033 ST000 99.184.242.197 (Sat, 16 May 2009 22:07:13 EDT) NNTP-Posting-Date: Sat, 16 May 2009 22:07:13 EDT Organization: at&t http://my.att.net/ X-UserInfo1: OP[EB[SE[RUABQTY]BCBNWX@RJ_XPDLMN@GZ_GYO^BSZUSAANVUEAE[YETZPIWWI[FCIZA^NBFXZ_D[BFNTCNVPDTNTKHWXKB@X^B_OCJLPZ@ET_O[G\XSG@E\G[ZKVLBL^CJINM@I_KVIOR\T_M_AW_M[_BWU_HFA_]@A_A^SGFAUDE_DFTMQPFWVW[QPJN Date: Sat, 16 May 2009 22:07:11 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1139 "Mike Treseler" wrote in message news:4A0F68F4.7080608@gmail.com... > AndreasWallner wrote: > >> The question I had in mind was really more: How do you manage to track >> the state of self written IP Cores and the top level project with your >> version tracking system. Especially if you want to tag the whole >> project, how do you ensure the correct version of the used IP cores is >> used. > > There's little difference between tags and branches in Subversion. > Both are directories that are created by a copy. > If I don't commit changes, it stays a tag or "snapshot". > If I commit a change, it becomes a branch. > I think what Adreas is asking about has to do with reusable (or potentially) reusable IP. You create some widget and put it into a Subversion (or other) repository. Sometime later you're working on a *new* design that happens to need the same widget. There are a couple ways to go about getting the old IP 1. Copy/replicate. Export the IP you need into the folder for the new design. Then when you check in the new design into its repository it's archived. The drawback here is the usual thing that happens with copy/paste, you've created a totally new widget that begins life exactly the same as the first widget, but they can each evolve down different paths if you find out later that you'd like to update the widget (in fact there is no 'the widget' anymore, there are 'two widgets', then three, four, more). 2. Have the new design reference widget. In Subversion you do this via the 'svn_external', the potential problem here is that the only way to totally lock down exactly what you're getting for widget is to specify the revision to pull when you reference the widget. This is OK if widget is firm and solid, but a pain if widget is also undergoing development and you're still in the development phase of your new thing that uses widget and you'd like to get 'latest/greatest'. The pain then becomes at the end when you're trying to exit that mode, going back into each of those svn_externals to then specify the revision you want is a manual, prone to problems effort. If you don't do this, then when you try to check out/export an archived design your references to widget will pull the 'head' revision, not the revision that existed at the time you wanted to archive. 3. Have the new design reference the new widget as in #2. But when you get to the point of releasing something and want to be able to create a tag that you can use as a real archive so that you go back and pull the design as it really existed at some prior time, but still have the benefits of referencing a single widget design when you're in development mode, then you need to use 'svncopy.pl' (http://svn.collab.net/repos/svn/trunk/contrib/client-side/svncopy/svncopy.README). This is one particular area of source control where MS Source Safe beats Subversion hands down. The fact that you can't reference a widget in some repository and be able to later tag it down to a specific revision at design complete without a lot of effort (#2) or having to use scripts to help along the source control tool's weakness (#3) is a major weakness, 'specially considering that this is after all a source control tool. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!eternal-september.org!news.unit0.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 16 May 2009 23:50:48 -0700 Lines: 17 Message-ID: <4A0FB3C8.4010802@gmail.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 6ERT3vjOQb1IoW/VQqgvbgvv6dxqiv8cegH02mor0IAgbJNRMU Cancel-Lock: sha1:hSCyy7Xh+IFOrbz0XeE7zntNwew= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1140 AndreasWallner wrote: > The question I had in mind was really more: How do you manage to track > the state of self written IP Cores and the top level project with your > version tracking system. Especially if you want to tag the whole > project, how do you ensure the correct version of the used IP cores is > used. This is similar to the problem of two developers working on the same module at the same time. Sometimes there are conflicts that have to be manually merged. I prefer KJ's "copy/replicate" method. My top priority is to get the project finished. I can merge back changes to reusable modules when the pressure is off. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 13:56:39 +0200 Organization: T-Online Lines: 13 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1242561399 03 n14343 nZIpQ1d118lxmIE 090517 11:56:39 X-Complaints-To: usenet-abuse@t-online.de X-ID: E6-imwZX8epxZrcYCFV0QsNhrvFTgBth2qhDKaAliBrRnDyNUsv3w3 User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1141 I have been using subversion for this purpose for maybe three years now. I have a number of reusable cores (varieties of Timers, Uarts, wishbone-to-whatever adapters, dma controllers etc.) and link them into a customer project as required by simply setting subversion externals. Each 'core' is developed as a project on it's own. Essentially, I have a repository for my reusable stuff, a different repository for customer projects and so on. I think one of the most important parts is a suitable directory structure. If you design things regularily enough, it's not much of a problem to include a core as part of another core and to include the super-core as part of a customer project. From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e20g2000vbc.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 09:13:18 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <2062927f-aaf1-4af9-adbe-2510f8418486@e20g2000vbc.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 84.119.1.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242576798 26902 127.0.0.1 (17 May 2009 16:13:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 May 2009 16:13:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbc.googlegroups.com; posting-host=84.119.1.165; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1142 On May 17, 1:56=A0pm, Charles Gardiner wrote: > I have been using subversion for this purpose for maybe three years now. > I have a number of reusable cores (varieties of Timers, Uarts, > wishbone-to-whatever adapters, dma controllers etc.) and link them into > a customer project as required by simply setting subversion externals. > Each 'core' is developed as a project on it's own. > > Essentially, I have a repository for my reusable stuff, a different > repository for customer projects and so on. Do you use a single repository for all your reusable stuff? With subfolders for each IP? > I think one of the most important parts is a suitable directory > structure. If you design things regularily enough, it's not much of a > problem to include a core as part of another core and to include the > super-core as part of a customer project. Would you mind telling me about the folder structure you use? From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o30g2000vbc.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 09:25:58 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> NNTP-Posting-Host: 84.119.1.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242577558 29299 127.0.0.1 (17 May 2009 16:25:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 May 2009 16:25:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o30g2000vbc.googlegroups.com; posting-host=84.119.1.165; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1143 Excuse the duplicate answer, but I used the wrong button the answer the first time... > I think what Adreas is asking about has to do with reusable (or potential= ly) > reusable IP. =A0You create some widget and put it into a Subversion (or o= ther) > repository. =A0Sometime later you're working on a *new* design that happe= ns to > need the same widget. =A0There are a couple ways to go about getting the = old > IP You are right on that point. Excuse me for not being clear here. > 1. Copy/replicate. We thought about that, but bringing the changes made to an core back into the main repository is the hard part here, as you pointed out. > 2. Have the new design reference widget. Thanks for that information, I'll look into that subversion feature. I didn't know svn provides that functionality. (I never needed to use something like that on my previous projects (especially since I do software projects (C/C++) most of the time, there we mostly install the needed libraries to system paths, which is not quite applicable for VHDL projects) > 3. Have the new design reference the new widget as in #2. =A0But when you= get > to the point of releasing something and want to be able to create a tag t= hat > you can use as a real archive... I think you should really have a look at git, it is really easy to use (after you have understood the differences from DVCS to traditional VCSs ;-)) and provides a feature called 'submodule' which is excatly what you described. If you create a tag, the content of the whole project is saved, and since a submodule not only contains the location of the imported repository, but also the precise commit currently used, the state of the IP cores is also preserved From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!postnews.google.com!m24g2000vbp.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 09:30:06 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <4758c4e6-e294-4d05-a078-47f8a85b5a0c@m24g2000vbp.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0FB3C8.4010802@gmail.com> NNTP-Posting-Host: 84.119.1.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242577808 7616 127.0.0.1 (17 May 2009 16:30:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 May 2009 16:30:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m24g2000vbp.googlegroups.com; posting-host=84.119.1.165; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1144 > I prefer KJ's "copy/replicate" method. My top priority is > to get the project finished. I can merge back changes to reusable > modules when the pressure is off. Since we are a university time is not a pressure (most of the time). The bigger problem would be if people forget to push their changes back into the IP core repository. If you have a disciplined development team, or are developing alone I can imagine that this would not be a problem, but my environment that could lead to serious problem. Like someone chaging an IP core, but introducing a bug, fixing that bug in the project repository, but forgetting to push the changes into the IP repo. Other than that we would also loose the information who did specific changes, and why... From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi067.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Subject: Re: Version Control for VHDL Project Lines: 17 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi067.nbdc.sbc.com 1242588640 ST000 99.184.242.197 (Sun, 17 May 2009 15:30:40 EDT) NNTP-Posting-Date: Sun, 17 May 2009 15:30:40 EDT Organization: at&t http://my.att.net/ X-UserInfo1: FKPO@MC@@S@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WHC@EK[WDXJHVKHGFFIZHBL@FX\NIOC@FWYNV\DMNS[HTLIXX\^BUGBXLR@PB@\FKCLXSWAIDFOKG^MFT[GZN^NWY_GVLSRGDYY^AW_MS_RW][KBYZMADO@Y[ABPSPE_TA@LTLFXVTC@RJM Date: Sun, 17 May 2009 15:30:38 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1145 "Charles Gardiner" wrote in message news:guou1n$e07$03$1@news.t-online.com... > > Essentially, I have a repository for my reusable stuff, a different > repository for customer projects and so on. > What method do you use to lock down the revision of the subversion external references within the customer repository (for archival purposes) but still allow the latest/greatest revision to be used for development (or future customer enhancements)? svncopy.pl? Manually? Something else? KJ From newsfish@newsfish Wed Aug 19 13:24:40 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 21:39:35 +0200 Organization: T-Online Lines: 82 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <2062927f-aaf1-4af9-adbe-2510f8418486@e20g2000vbc.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1242589176 02 n16690 nyxpQ85vuRSWwIn 090517 19:39:36 X-Complaints-To: usenet-abuse@t-online.de X-ID: XpbTI2ZEgeJeBhQAQivQxMQrA8YAHyo6-Jdte6UxfNGIKv2Fu1pr4+ User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <2062927f-aaf1-4af9-adbe-2510f8418486@e20g2000vbc.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1146 AndreasWallner schrieb: > > Do you use a single repository for all your reusable stuff? With > subfolders for each IP? > Exactly, I use a single repository for the reusable stuff with each having it's own substructure > > Would you mind telling me about the folder structure you use? No Problem. This is only my suggestion, though. I'm sure at least 100 others will also work. I think the important thing is a structure that is regular, reproducable and scalable but still flexible. My (ASIC/FPGA) Project structure looks like this (not all line-breaks are intentional). BTW, each reusable unit also has a similar structure. design doc flow image impl reports resources scripts verify work Sometimes there is a 'driver' directory here too. >From a chip perspective, design and impl are the important ones. 'impl' contains target-specific stuff like PLLs, Memories etc. Often generated by perl or tcl scripts in tool-related directories below 'scripts' 'design' has the further subdirectories common top units Under 'common', I have things like my utility libraries and frequently used smaller blocks such as say FIFO controllers. (Yes, I prefer to roll my own). These nearly all come from the reusable repository. 'top' usually just contains a core and top-level pin-out block. i.e. the core is the only thing instanced in the 'top' block along with any additional polarity inversions, tri-state etc. The most interesting is the 'units' tree. This is a mix of project-specific and reusable cores. Each unit can have it's own top and/or units subdirectories depending on complexity. Often, there is just a directory called 'verilog' or 'vhdl' directly under a unit, containing the source code for that unit. Looking at one of my current designs, the following as an excerpt from below the /design/units path: credit_config lscc_pcie_wb01 wb_spi_ad7490_c32 Here, the first and last are project-specific, the middle one is from the reusable repository and is a wishbone adapter for the Lattice PCIe core. Running 'svn propget svn:externals' on this (middle one) gives: lscc_pcie_wb01 - top http://regulus/svn/SoC/lscc_pcie_wb01/trunk/design/top units http://regulus/svn/SoC/lscc_pcie_wb01/trunk/design/units So, the project-local dirs /design/units/lscc_pcie_wb01/top and /design/units/lscc_pcie_wb01/units are imported from the reusable-stuff repository. There is also a directory tree /design/units/lscc_pcie_wb01/config which is local to the design and just contains a package taking care of some project-specific configurations, but which is required by the files from the repository (this is an example of what I mean above by flexible. A directory tree that basically stradles the reusable and project repositories) The test-bench resides below the 'verify' path and is very similar to the directory structure below 'design'. Depending on the design, there can be various BFMs etc. Reusable test-bench stuff gets hooked in here the same way as above. Beside all this, I have a collection of perl/java scripts for generating make-files, testbench skeletons etc. which of course are designed to work with this structure. As I said, just look on this as food for thought. You may have other requirements. Best of luck with your projects. From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 21:56:29 +0200 Organization: T-Online Lines: 31 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1242590190 01 n22649 esypQ7cL5sv9DB 090517 19:56:30 X-Complaints-To: usenet-abuse@t-online.de X-ID: Ek6a3sZfgeCKaTUdFPrAj5bKz+M2u0uABp2RdpSpRlts5bxWQfaNwm User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1147 KJ schrieb: > > What method do you use to lock down the revision of the subversion external > references within the customer repository (for archival purposes) but still > allow the latest/greatest revision to be used for development (or future > customer enhancements)? svncopy.pl? Manually? Something else? > > KJ > > I followed the subversion suggestions here. Each reusable unit (and of course each customer project) has a tags, branches and trunk subdirectory. Every project release to a customer is tagged (svn copy) and the output of 'svn -R propget svn:externals .' documented just for safety. Every version of a reusable unit included in a customer project is also taken from an entry under ///SoC//tags and never directly from the trunk Continued development, fixes etc. to a resuable core are done as a project on it's own (under trunk). If a customer gets an upgraded/fixed version, I generally just remove the previous sub-tree to the reusable block in his project and modify the svn:externals to pick up a new tagged version. Unfortunately, I'm currently running subversion Version 1.4.4. According to my understanding, the newest releases give much better merging options but I just don't have time to take my system down for a few days at the moment. But it's on my task-list. From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi069.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Subject: Re: Version Control for VHDL Project Lines: 35 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi069.nbdc.sbc.com 1242595495 ST000 99.184.242.197 (Sun, 17 May 2009 17:24:55 EDT) NNTP-Posting-Date: Sun, 17 May 2009 17:24:55 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[OER[ODPRUORRPXIZOD]_\@VR]^@B@MCPWZKB]MPXHBTWICYFWUQBKZQLYJX\_ITFD_KFVLUN[DOM_A_NSYNWPFWNS[XV\I]PZ@BQ[@CDQDPCL^FKCBIPC@KLGEZEFNMDYMKHRL_YYYGDSSODXYN@[\BK[LVTWI@AXGQCOA_SAH@TPD^\AL\RLGRFWEARBM Date: Sun, 17 May 2009 17:24:53 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1148 "Charles Gardiner" wrote in message news:gupq5e$m3p$01$1@news.t-online.com... > KJ schrieb: > > >> >> What method do you use to lock down the revision of the subversion >> external >> references within the customer repository (for archival purposes) but >> still >> allow the latest/greatest revision to be used for development (or future >> customer enhancements)? svncopy.pl? Manually? Something else? >> >> KJ >> >> > > I followed the subversion suggestions here. Each reusable unit (and of > course each customer project) has a tags, branches and trunk > subdirectory. Every project release to a customer is tagged (svn copy) > and the output of 'svn -R propget svn:externals .' documented just for > safety. Creating tags using 'svn copy' though doesn't lock down the revision of externals when creating the tag so when you go back later to get the tag and check it out, anything from an 'svn_external' will return the 'head' revision of the referenced folder, not the revision that existed at the time that you created the tag...good thing you have the 'svn -R propget svn:externals .' documented so you know which revision was really used at the time the tag was created. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!q14g2000vbn.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sun, 17 May 2009 15:34:44 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 84.119.1.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242599684 11223 127.0.0.1 (17 May 2009 22:34:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 May 2009 22:34:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q14g2000vbn.googlegroups.com; posting-host=84.119.1.165; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1149 Thank you two for taking the time to explain your approaches to me, I'm really grateful. I think we will try using the approach Charles presented, but we'll stick with git as a version tracker. I don't want to advertise git here, but you should really have a look at it, as it provides exactly the functionality Kevin was missing from this idea. (Tagging through all external imports) Andreas Wallner PS: Would you use an editor which forced you to use git? From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g3g2000pra.googlegroups.com!not-for-mail From: shweta Newsgroups: comp.lang.vhdl Subject: re:query Date: Sun, 17 May 2009 23:25:54 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: NNTP-Posting-Host: 203.199.132.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242627954 391 127.0.0.1 (18 May 2009 06:25:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 May 2009 06:25:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g3g2000pra.googlegroups.com; posting-host=203.199.132.40; posting-account=wEHAWQoAAAAZu5J8_J8HFzSNle_bgqrr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 proxy2.cdac.in:8080 (squid/2.6.STABLE6) Xref: news.eternal-september.org comp.lang.vhdl:1150 hi, i am a new user to VHDL and trying to port a bio-informatics application onto RCS card. could anybody help me regarding the Application which is suitable for implementing onto RCS card, configured with FPGA. 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Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 47 Message-ID: <4a112dd5$0$90274$14726298@news.sunsite.dk> Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 91.143.113.214 X-Trace: news.sunsite.dk DXC==]VSHSUT2jB?ZCK:;haR=OYSB=nbEKnkKjL0kO3l6odN_hN;Vo;0KjHZPcL;PaZCSES^2KnhMoT`IGNR17K7IN>DA@oBhPaHIJEV2k:i Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Mon, 18 May 2009 03:54:01 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 62.218.221.187 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242644041 19349 127.0.0.1 (18 May 2009 10:54:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 May 2009 10:54:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbr.googlegroups.com; posting-host=62.218.221.187; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.64 (X11; Linux i686; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 none.fh-joanneum.at.fh-joanneum.at (squid/3.0.STABLE4) Xref: news.eternal-september.org comp.lang.vhdl:1153 I also had a look at the other two big DVCS's, those too have such a feature (Mercurial calls them Nested Repositories, Bazaar Nested Trees) if you don't like git. Bazaar can also easily be used as a centralized VCS, that's just a setting. They might be worth a look, especially for this issue. From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 May 2009 08:08:01 -0500 Date: Mon, 18 May 2009 14:08:04 +0100 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Standard library packages for bit and strings? References: <4a112dd5$0$90274$14726298@news.sunsite.dk> In-Reply-To: <4a112dd5$0$90274$14726298@news.sunsite.dk> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 66 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-IqdqPPpe4P3SfNR2drJLOna0nd+B9s+gCuvSKoUtzH3vmGy+beMpKPZYnbHMu/BobjeBiRp3HBU4L0S!yxoc3nq5A3BRyouvvu0dl98Xa0VyPP3Cz9DbtZgn12kTexxRqYsHV7lXDn8YuN2IQmK06LXtB49m!DLijlHstKLV7EPAPoQgC4RfLcQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3559 Xref: news.eternal-september.org comp.lang.vhdl:1154 Peter Soerensen wrote: > I have used VHDL for many years now. > I believe I have a good overview over existing packages. > > I think two essential packages are missing: > > I will call them BIT_LOGIC and STRING. > > Can anyone explain why they have not been made long ago? > > STRING (simulation only) > The standard TEXTIO is very primite and simple string functions that can > convert any signal type to a string for write to std_out are missing. > I have made my own and could not do any serious testbench and simulation > work without it. But I simply do not understand why the VHDL committee > has not made a standard lib. > I would propose something like the printf functions in C. > I know it is very easy to do, when you have tryed it ones, but it is a > large step for beginners and it is a vaste or resources that we all do it. > You can get my simple lib for a start, but is very primitive compared to > the printf statement. Anyone with a SW+VHDL background got do it better > than me within a very short time. > There's a lot more string functionality in VHDL-2008. Also you might want to look at the Mentor SDK, which is supplied with Modelsim. I'm not sure what it's licensing is for other simulators. Also the company Easics used to have a package PCK_FIO which emulated some printf-like behaviour. > > BIT_LOGIC > Originally VHDL was made without packages for synthesis because it was > made for simulation only. Later when synopsis started to support > synthesis and made the synopsys packages that support std_logic but to > day I would recommend these and only use VHDL standard libs: numeric_std > and numeric_bit. However no libs support a number of functions for bits > that exits in std_logic_1164; E.g: > Sounds like you need IEEE.numeric_bit regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:41 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 May 2009 08:15:31 -0500 Date: Mon, 18 May 2009 14:15:33 +0100 From: Alan Fitch User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Standard library packages for bit and strings? References: <4a112dd5$0$90274$14726298@news.sunsite.dk> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 46 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-1dERc9rCD5MoZXFl/RhBR3Q9ihwHcI5GBKQGCOWPteAof0bu9Yu2ZwkddQ1sYFsSO8ZqEavde30aK1I!ix/WAY2Y5cgWRVv521fPlPdX1CDGJd0XUpKTN2eNHJ35uFq+zGWkOO6tUfS462OgTbzR1kwvXH+0!x+m8tJ/547ey/tWPHY4galIi6A== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2650 Xref: news.eternal-september.org comp.lang.vhdl:1155 Alan Fitch wrote: > Peter Soerensen wrote: >> BIT_LOGIC >> Originally VHDL was made without packages for synthesis because it was >> made for simulation only. Later when synopsis started to support >> synthesis and made the synopsys packages that support std_logic but to >> day I would recommend these and only use VHDL standard libs: >> numeric_std and numeric_bit. However no libs support a number of >> functions for bits that exits in std_logic_1164; E.g: >> > > Sounds like you need IEEE.numeric_bit > Whoops, sorry I didn't notice numeric_bit in your list - which operators trouble you? According to the VHDL-2002 standard "The logical operators and, or, nand, nor, xor, xnor, and not are defined for predefined types BIT and BOOLEAN. They are also defined for any one-dimensional array type whose element type is BIT or BOOLEAN." regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Mon, 18 May 2009 09:32:45 -0700 Lines: 10 Message-ID: <77dgtdF1ha25gU1@mid.individual.net> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0FB3C8.4010802@gmail.com> <4758c4e6-e294-4d05-a078-47f8a85b5a0c@m24g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net eHd5/nvNIccZCvt6SqZ2lgsnDr8tgvEdaF4E7QO1VCmeE/ZYvK Cancel-Lock: sha1:3D+danbToBfTVKIvZiWi+QeDOt8= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <4758c4e6-e294-4d05-a078-47f8a85b5a0c@m24g2000vbp.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1156 AndreasWallner wrote: > Since we are a university time is not a pressure (most of the time). > The bigger problem would be if people forget to push their changes > back into the IP core repository. I don't follow. Version control can't remind a developer to do that. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k9g2000pra.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Mon, 18 May 2009 11:04:32 -0700 (PDT) Organization: http://groups.google.com Lines: 115 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242669872 4163 127.0.0.1 (18 May 2009 18:04:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 May 2009 18:04:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000pra.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1157 On May 17, 2:24=A0pm, "KJ" wrote: > "Charles Gardiner" wrote in message > > news:gupq5e$m3p$01$1@news.t-online.com... > > > > > KJ schrieb: > > >> What method do you use to lock down the revision of the subversion > >> external > >> references within the customer repository (for archival purposes) but > >> still > >> allow the latest/greatest revision to be used for development (or futu= re > >> customer enhancements)? =A0svncopy.pl? =A0Manually? =A0Something else? > > >> KJ > > > I followed the subversion suggestions here. Each reusable unit (and of > > course each customer project) has a tags, branches and trunk > > subdirectory. Every project release to a customer is tagged (svn copy) > > and the output of 'svn -R propget svn:externals .' documented just for > > safety. > > Creating tags using 'svn copy' though doesn't lock down the revision of > externals when creating the tag so when you go back later to get the tag = and > check it out, anything from an 'svn_external' will return the 'head' > revision of the referenced folder, not the revision that existed at the t= ime > that you created the tag...good thing you have the 'svn -R propget > svn:externals .' documented so you know which revision was really used at > the time the tag was created. Kevin, I've been using Subversion for FPGA designs for quite awhile now and I've come up with what I think is a reasonable workflow. Of course lots of things are reusable, and anything that is so is a separate project in the repository. As an overview, my repository structure is as follows: --------------------------------------------------------------- root\fpga\projects <-- All chip-level designs go here \projects\A\tags\ \branches\ \trunk\src\ <-- VHDL goes here \projects\A\trunk\fitter\ <- synthesis/P+R stuff \projects\A\trunk\testbench\ <- obvious! \fpga\models <- various simulation models for testbenches \fpga\modules <- resuable "cores" go here \fpga\modules\spimaster\tags\ \branches\ \trunk\src \trunk\testbench \pwm\tags\ \branches\ \trunk\src\ \trunk\testbench\ ---------------------------------------------------- Now here is how it works. When I'm doing a new FPGA design that needs an existing module, I always use TAGGED versions of those modules. This means I put the svn:externals property on the design's src directory as follows: spi svn://repo/fpga/modules/spi/tags/spi_v1.0.0/src pwm svn://repo/fpga/modules/spi/tags/spi_v1.1.0/src (don't forget the src, otherwise you get the testbench for the module too!) Now when you check out the FPGA design, you get the tagged (by convention, immutable) versions of those modules. If you are developing a new module along with your FPGA design, still keep it as a module, but just include the trunk of that module until you decide that it's ready for "release," at which point you tag it. Oftentimes I will check out the submodule into its own working copy, code it up, verify with the testbench, and commit, and only after that's done will I add it to the externals for the larger design. If you decide to change a tagged module, change the external to reference either the trunk of that module, or create a branch of it. Update the FPGA design's working copy and now you are developing on the module's trunk. When you are finished and satisfied that the module works as required, create a new tag, then change the chip design's src directory's externals to reference the module's new tag. Basically, then, when you decide to release the whole design, ALL of the submodules pulled in by svn:externals should be TAGGED versions, not from their respective trunks. So when you check out your design's released tagged version you get what you expect, regardless of later changes to any modules, which I suppose is the whole point of version control. I like to add the .bit and .mcs files to my design release tags, too. Here's what I do. Before you tag your FPGA design for release, check out a working copy (all tagged submodules!) _from the trunk_ and build it. When complete, do an svn add on the .bit and .mcs files. (You might wish to create a separate directory for these files under the project root, and add that directory instead.) Do NOT commit the change. Instead, create a tag from the _working copy_ (very easy in TortoiseSVN). When that's done, your repo has a tagged release version of the FPGA including .bit and .mcs. The working copy remains on the Now, do an svn revert on the .bit and .mcs files because there's no reason the trunk should contain build results. Anyways, it's actually easier to use than to describe, and it works for me. -a From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r3g2000vbp.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Mon, 18 May 2009 11:50:05 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <9be4269c-1cd7-4688-8f7f-76298f7a411a@r3g2000vbp.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0FB3C8.4010802@gmail.com> <4758c4e6-e294-4d05-a078-47f8a85b5a0c@m24g2000vbp.googlegroups.com> <77dgtdF1ha25gU1@mid.individual.net> NNTP-Posting-Host: 84.119.1.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242672605 12823 127.0.0.1 (18 May 2009 18:50:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 May 2009 18:50:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r3g2000vbp.googlegroups.com; posting-host=84.119.1.165; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1158 On May 18, 6:32=A0pm, Mike Treseler wrote: > AndreasWallner wrote: > > Since we are a university time is not a pressure (most of the time). > > The bigger problem would be if people forget to push their changes > > back into the IP core repository. > > I don't follow. > Version control can't remind a developer to do that. Yes it can: If a developer needs to copy the changed files back into another folder and commit his changes into another folder (the repository of the core) we won't be able to ensure all changes (e.g. bugfixes) because people are just too lazy to do this, or pretend not to have time for it. Since they are students like me they can't be forced, and certainly cannot loose their job or something else because of such problems. If we use a system where you have to import IP cores as subtrees like Kevin suggested, commiting the project results in a commit of the changes made to the subtree, so the IP core repository is automatically updated with the changes made in the project repository. That's how version control can remind you. Regards, Andreas Wallner From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Mon, 18 May 2009 12:49:53 -0700 Lines: 15 Message-ID: <77dsf2F1h6ufpU1@mid.individual.net> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0FB3C8.4010802@gmail.com> <4758c4e6-e294-4d05-a078-47f8a85b5a0c@m24g2000vbp.googlegroups.com> <77dgtdF1ha25gU1@mid.individual.net> <9be4269c-1cd7-4688-8f7f-76298f7a411a@r3g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net eHrVvnf4z4z+IncVNEU8OQj1aV+mieIri4m832Wl0T1L+42V+y Cancel-Lock: sha1:Wu+SzEf4DtDo9fdeelQ23XrWdfM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <9be4269c-1cd7-4688-8f7f-76298f7a411a@r3g2000vbp.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1159 AndreasWallner wrote: > If we use a system where you have to import IP cores as subtrees like > Kevin suggested, commiting the project results in a commit of the > changes made to the subtree, so the IP core repository is > automatically updated with the changes made in the project > repository. I hear what you are saying, but this assumes that all changes are worthy, or that someone is monitoring the core repository, fixing testbenches and scripts to cover the changes as they come in. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s31g2000vbp.googlegroups.com!not-for-mail From: VIPS Newsgroups: comp.lang.vhdl Subject: i2c Start and stop detection Date: Mon, 18 May 2009 13:27:25 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: NNTP-Posting-Host: 70.108.245.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242678445 17345 127.0.0.1 (18 May 2009 20:27:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 May 2009 20:27:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s31g2000vbp.googlegroups.com; posting-host=70.108.245.211; posting-account=WPnTdQoAAADxtUw2WpFzf9cv-eCysaC_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 GTB5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1160 Hi all I am implementing the I2C Slave and I am using the I2C clock SCL for detecting the start and stop condition . I am detecting the start and stop successfully in simulation but i am not able to do the same in the post synthesis scenario. More so I am getting a setup time violation for the same in the timing analysis . I am running the I2C at a very slow speed of 100KHz. The code is below process (SDA_IN, START_RST,rst) begin if rst ='1' then STARTOP <='0'; -- elsif (START_RST = '1') then -- STARTOP <= '0'; elsif (SDA_IN'event and SDA_IN = '0') then STARTOP <= scl; end if; end process; ------------------------------------------------------------------------------ -- stop condition detection process (RST, SCL, SDA_IN, STARTOP) begin if RST = '1' or SCL = '0' or STARTOP='1' then STOPOP <= '0'; elsif SDA_IN = '1' and SDA_IN'event then if SCL = '1' then STOPOP <= '1'; end if ; end if; end process; Can any one give me a reliable way to detect the start and stop condition that the synthesis tool doesnot give any setup time violation. I am not using a high clock for sampling as the requirement is to use the SCL only. May be to save board resourse and space. Help will be appreciated. I am using Altera max II CPLD and the synthesis tool is quartus 9.0 Thanks Vipul From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!aioe.org!news.k-dsl.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 May 2009 15:40:08 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: [vhdl] microcontroller 8051 Date: Mon, 18 May 2009 13:37:49 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 89.174.102.41 Lines: 18 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-OHtb7PX2TxhkS02261zvIOHADaOg+DfuXprepQK4dh2Xa5B3nogGOvcSkjl+HCMywqXqVSpipx/wzOR!bxH+DtSKLmIERGIssJv7hjoLLrOmetZlJQBsPlNwxyZVgkLMM7wDbw2h X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 7 Xref: news.eternal-september.org comp.lang.vhdl:1161 Hi, I have to implement microcontroller 8051 in VHDL ( in Xilinx program) and in next step I should write program ( for example in C) which shows work of microcontroller . The VHDL code I have to upload to kit board ( digilent D2E & DIO2) But I haven't ideas how should I begin it. Maybe someboady made something similar and can write me how I can start. Thanks. Pawel -- gegry ------------------------------------------------------------------------ gegry's Profile: http://www.fpgacentral.com/group/member.php?userid=91 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90222 From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news.nask.pl!news.nask.org.pl!news2.icm.edu.pl!not-for-mail From: "qharz" Newsgroups: comp.lang.vhdl Subject: modulo function Date: Mon, 18 May 2009 23:39:01 +0200 Organization: http://news.icm.edu.pl/ Lines: 8 Message-ID: NNTP-Posting-Host: mikrus.nat.student.pw.edu.pl Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-2"; reply-type=original Content-Transfer-Encoding: 7bit X-Trace: achot.icm.edu.pl 1242682743 22555 194.29.137.2 (18 May 2009 21:39:03 GMT) X-Complaints-To: abuse@icm.edu.pl NNTP-Posting-Date: Mon, 18 May 2009 21:39:03 +0000 (UTC) Importance: Normal X-MimeOLE: Produced By Microsoft MimeOLE V14.0.8064.206 X-Priority: 3 X-Newsreader: Microsoft Windows Live Mail 14.0.8064.206 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:1162 Hi I am quite fresh with vhdl and i have a problem. How to realize modulo function using signals not variables? For example: modulo_signal <= sample_signal mod 65536; Best regards, qharz From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!weretis.net!feeder2.news.weretis.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: i2c Start and stop detection Date: Mon, 18 May 2009 16:12:10 -0700 Lines: 29 Message-ID: <77e8acF1d11hlU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net kSgj7FM5IyrpIhbfWyROvgeJQh54A5ysw9gZkVoXHb9LFAG98F Cancel-Lock: sha1:/l/TV2cy7zIvyTdHYWpH1k2MTR8= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1163 VIPS wrote: > I am implementing the I2C Slave and I am using the I2C clock SCL for > detecting the start and stop condition . I am detecting the start and > stop successfully in simulation but i am not able to do the same in > the post synthesis scenario. That scenario requires a synchronous process something like this: ... begin if reset = '1' then init_regs; elsif rising_edge(clock) then update_regs; end if; update_ports; end process; > Help will be appreciated. An i2c controller is a complex shift register with case statements for bit and byte control. A working design will require several hundred lines of code. Google a bit. This has been done. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:42 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!z7g2000vbh.googlegroups.com!not-for-mail From: AndreasWallner Newsgroups: comp.lang.vhdl Subject: Re: modulo function Date: Mon, 18 May 2009 17:05:53 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <8400e056-536e-4bf8-a96a-3a61d62d45cd@z7g2000vbh.googlegroups.com> References: NNTP-Posting-Host: 85.127.9.80 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242691553 25842 127.0.0.1 (19 May 2009 00:05:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 00:05:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z7g2000vbh.googlegroups.com; posting-host=85.127.9.80; posting-account=KUpDlgoAAAAsph7PcClrLhZ5qPqKv8qY User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.63 (Windows NT 5.1; U; en) Presto/2.1.1,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1164 On May 18, 11:39=A0pm, "qharz" wrote: > Hi > I am quite fresh with vhdl and i have a problem. How to realize modulo > function using signals not variables? > For example: modulo_signal <=3D sample_signal mod 65536; > > Best regards, > qharz If you need to calculate mod 2^n it is as simple as just using the array slice containing the data you seek. You know x mod m gives you the rest of the division of x/m. If m is 2^n, you simply need to take the lower n bits of the array to get your result. x / m for m =3D 2^n is x >> m, the rest is then the part shifted away, or x - (( x >> m ) << m), or if x is an std_logic_vector( ? downto 0), result <=3D x( n - 1 downto 0); Hope that helps, Andreas Wallner From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news.nask.pl!news.nask.org.pl!news2.icm.edu.pl!not-for-mail From: "qharz" Newsgroups: comp.lang.vhdl Subject: Re: modulo function Date: Tue, 19 May 2009 02:27:59 +0200 Organization: http://news.icm.edu.pl/ Lines: 9 Message-ID: References: <8400e056-536e-4bf8-a96a-3a61d62d45cd@z7g2000vbh.googlegroups.com> NNTP-Posting-Host: mikrus.nat.student.pw.edu.pl Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="ISO-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Trace: achot.icm.edu.pl 1242692882 12788 194.29.137.2 (19 May 2009 00:28:02 GMT) X-Complaints-To: abuse@icm.edu.pl NNTP-Posting-Date: Tue, 19 May 2009 00:28:02 +0000 (UTC) Importance: Normal In-Reply-To: <8400e056-536e-4bf8-a96a-3a61d62d45cd@z7g2000vbh.googlegroups.com> X-MimeOLE: Produced By Microsoft MimeOLE V14.0.8064.206 X-Priority: 3 X-Newsreader: Microsoft Windows Live Mail 14.0.8064.206 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:1165 > x / m for m = 2^n is x >> m, the rest is then the part shifted away, > or x - (( x >> m ) << m), or if x is an std_logic_vector( ? downto 0), > result <= x( n - 1 downto 0); > It helps, Thank You very much qharz From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 May 2009 23:40:09 -0500 From: 'use_real_email' Newsgroups: comp.lang.vhdl Subject: Re: [vhdl] microcontroller 8051 Date: Mon, 18 May 2009 21:37:43 -0700 Message-ID: Organization: NewsGroup User-Agent: vBulletin USENET gateway X-Newsreader: vBulletin USENET gateway X-Originating-IP: 79.178.100.75 References: Lines: 15 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ZHDe1J9iPcY9VJbLgIheQGQbUVEi303YqJpuAiv5XbkKLo7ZcyED22XuOiZvPS0Ru/2dNDrfAITCoV4!eh83G+Md0U2z6MykNwMZ5axko4S4g7eGy1awvGHZATV5zo1Be8Wm55Ro43qoHQ== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:1166 CPU 8051 translation from VHDL to verilog. I used 8051 from .. When it comes for generating the hex file of the assembly code, I strongly recommend to add remarks with the code itself: .. 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/cpu_8051_ver/top.html) -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90222 From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b1g2000vbc.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 02:06:43 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242724003 11487 127.0.0.1 (19 May 2009 09:06:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 09:06:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b1g2000vbc.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1167 Hi, i'm make some simples VHDL design to keep alive my knowledges (i try :) ). But, i've got a little problem in my code, it's a shift register. When i simulate this design, i haven't the execpted value on the signal s1 (out) because i've not the good value on my internal signal (it doesn't take the value of the input as it would be to). I hope i'm clear in my explications. Here my design : library ieee; use ieee.std_logic_1164.all; --entity entity accushift32 is port ( e1 : in std_logic_vector(31 downto 0); rst : in std_logic; clk : in std_logic; s1 : out std_logic); end accushift32; --design architecture d_accushift32 of accushift32 is signal internal : std_logic_vector(31 downto 0) := (others => '0'); begin -- d_accushift32 s1 <= internal(0); process (clk, rst) begin -- process if rst = '0' then -- asynchronous reset (active low) internal <= e1; elsif clk'event and clk = '1' then -- rising clock edge internal <= '0' & internal(31 downto 1); end if; end process; end d_accushift32; Thanks to all of you for your answers (or your comments) From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 19 May 2009 04:22:30 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 10:19:49 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 57 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-AV1rBhJGuJpsT4bRhy4SoPcDn1aTrUTvPSnjVVkR627+lPs2iUAEgilLF1NJz6NP8CZQgyOmXpUyZKF!WN1sbZ+Td1PyvUmh/WSb1xNkGuHTBKCydX0vajfhqgzuzaiQl0TVncmlMioPt2Wl5q67aTupuvRB!rWiIVr/gjarvmOuQ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1168 On Tue, 19 May 2009 02:06:43 -0700 (PDT), Beware wrote: hi Mathieu, >When i simulate this design, i haven't the execpted value on the >signal s1 (out) because i've not the good value on my internal signal >(it doesn't take the value of the input as it would be to). There is one important problem with your design, which I will explain later. However, I do not understand why you have trouble with simulation. The design is good VHDL and should simulate OK. Can you show us the testbench code you used to simulate it? I guess your problem is related to timing of signals in the testbench. Here is the problem I mentioned: > process (clk, rst) > begin -- process > if rst = '0' then -- asynchronous reset (active low) > internal <= e1; > elsif clk'event and clk = '1' then -- rising clock edge > internal <= '0' & internal(31 downto 1); > end if; > end process; Your reset is NOT a reset! It is an asynchronous preload. This will not work in most FPGAs, because their flip-flops do not have asynchronous preload capability. It would be much better to make the preload signal SYNCHRONOUS: process (clk) begin if rising_edge(clk) then -- this is better style!!! if rst = '0' then -- Synchronous preload internal <= e1; else -- Synchronous right-shift internal <= '0' & internal(31 downto 0); end if; end if; end process; For FPGA design, asynchronous set/reset MUST set the flip-flops to a constant value, NOT to the value of an input signal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n8g2000vbb.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 03:21:50 -0700 (PDT) Organization: http://groups.google.com Lines: 65 Message-ID: <19fbf9ed-744c-4396-befc-0cea8b8d8fbd@n8g2000vbb.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242728510 9529 127.0.0.1 (19 May 2009 10:21:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 10:21:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n8g2000vbb.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1169 On 19 mai, 11:19, Jonathan Bromley wrote: Hi Jonathan > There is one important problem with your design, which > I will explain later. =A0However, I do not understand why > you have trouble with simulation. =A0The design is good > VHDL and should simulate OK. =A0Can you show us the > testbench code you used to simulate it? =A0I guess your > problem is related to timing of signals in the testbench. Thank you for your answer. You're right. I've changed my code and now it's work pretty well. I have to remember this for the next design. Here's my new code : library ieee; use ieee.std_logic_1164.all; --entity entity accushift32 is port ( e1 : in std_logic_vector(31 downto 0); rst : in std_logic; clk : in std_logic; load : in std_logic; s1 : out std_logic); end accushift32; --design architecture d_accushift32 of accushift32 is signal internal : std_logic_vector(31 downto 0) :=3D (others =3D> '0'); begin -- d_accushift32 s1 <=3D internal(0); process (clk, rst, load) begin -- process if rst =3D '0' then -- asynchronous reset (active low) internal <=3D (others =3D> '0'); elsif clk'event and clk =3D '1' then -- rising clock edge if load =3D '1' then internal <=3D e1; else internal <=3D '0' & internal(31 downto 1); end if; end if; end process; end d_accushift32; Thanks. From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!s20g2000vbp.googlegroups.com!not-for-mail From: philippe.faes@gmail.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Sigasi Public Beta: future of VHDL design Date: Tue, 19 May 2009 03:33:38 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242729219 11695 127.0.0.1 (19 May 2009 10:33:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 10:33:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000vbp.googlegroups.com; posting-host=195.144.71.15; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.8.1.19) Gecko/20081216 Fedora/2.0.0.19-1.fc8 Firefox/2.0.0.19 pango-text,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1170 comp.arch.fpga:3463 Today, Sigasi proudly announces the Public Beta program for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL (http:// www.sigasi.com/publicbeta). Sigasi HDT (Hardware Development Toolkit) is a powerful VHDL development tool that assists designers in reading, writing and modifying VHDL more accurately and faster. It differs from other development tools in that it contains an ultra-fast VHDL parser and compiler that runs transparently in the background (http:// www.sigasi.com/product). Through the Public Beta program, VHDL designers join a community that takes advantage of modern development techniques. To participate in the program, please visit http://www.sigasi.com/start. From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!f28g2000pra.googlegroups.com!not-for-mail From: move Newsgroups: comp.lang.vhdl Subject: ADSP TS101 Linkport implementation Date: Tue, 19 May 2009 04:52:57 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <3d3ec383-a84a-402e-bd44-17f5ca8aebe9@f28g2000pra.googlegroups.com> NNTP-Posting-Host: 61.187.2.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242733977 26178 127.0.0.1 (19 May 2009 11:52:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 11:52:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f28g2000pra.googlegroups.com; posting-host=61.187.2.211; posting-account=WOMbEwoAAABSmbQhJFsLtz_F527uyH75 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.8) Gecko/2009032609 Firefox/3.0.8,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1171 Hi all: have anybody use the ts101 link port interface to communicate with FPGA? i have been using one that Xilinx provided (Xapp634), but it is huge and not easy to understood. From newsfish@newsfish Wed Aug 19 13:24:43 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Standard library packages for bit and strings? Date: Tue, 19 May 2009 05:04:19 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <1c608402-81dc-42de-aa54-36ec4500d9be@b6g2000pre.googlegroups.com> References: <4a112dd5$0$90274$14726298@news.sunsite.dk> NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242734659 12239 127.0.0.1 (19 May 2009 12:04:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 12:04:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1172 See link below for some C type functions. http://bear.ces.cwru.edu/VHDL/index.html Also see this thread that discusses some issues I found with the packages. http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/9bc060881f29ed78/cca9dbaded3bbbcd?hl=en#cca9dbaded3bbbcd From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n4g2000vba.googlegroups.com!not-for-mail From: Kenneth Brun Nielsen Newsgroups: comp.lang.vhdl Subject: Re: Lazy man's testbench Date: Tue, 19 May 2009 05:20:01 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <6fa4aa06-fe5d-405f-aa91-8330541a6cb4@n4g2000vba.googlegroups.com> References: <18afdcd6-64ca-4915-8490-236ad9cc3ef8@m24g2000vbp.googlegroups.com> <7733a6F1fg6jlU1@mid.individual.net> NNTP-Posting-Host: 80.196.98.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242735601 31224 127.0.0.1 (19 May 2009 12:20:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 12:20:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n4g2000vba.googlegroups.com; posting-host=80.196.98.142; posting-account=Y2qrgwkAAACbbT37NX8gk-aSqpI-3T6p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; SLCC1; .NET CLR 2.0.50727; InfoPath.2; .NET CLR 3.5.30729; .NET CLR 3.0.30618; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1173 On 14 Maj, 19:39, Mike Treseler wrote: > Kenneth Brun Nielsen wrote: > > A testbench, that reads input levels from columns in an input file, > > and writes outputs to another file, must be a widely used block(?). > > If I already have a device model, > and an appropriate testbench, I could collect > such files from my simulator. > Writing the model and testbench is the problem, > and there is no generic solution. > > Unless I am feeding a device tester, > I have no need of such "test vector" files. > If you do, google a bit:http://www.actel.com/documents/TestVector_AN.pdf Thanks. I'm actually using this for device test vector generation, so the link is highly relevant. Best regards, Kenneth From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u10g2000vbd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: modulo function Date: Tue, 19 May 2009 05:52:37 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <8fa65807-5eff-4478-a987-859f4639c4af@u10g2000vbd.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242737557 4788 127.0.0.1 (19 May 2009 12:52:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 12:52:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u10g2000vbd.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1174 On May 18, 4:39=A0pm, "qharz" wrote: > Hi > I am quite fresh with vhdl and i have a problem. How to realize modulo > function using signals not variables? > For example: modulo_signal <=3D sample_signal mod 65536; > > Best regards, > qharz As long as the signal data types are either integer, numeric_std.signed or .unsigned, your example will work just fine. Numeric_std defines the modulo operator with .unsigned, .signed or integer RH operands. It is also directly synthesizable so long as the RH operand is a static (i.e. value is known at synthesis time), integral power of two, which simplifies to simply a slice operation. For the purposes of synthesis, "static" also includes such things as for-loop indices, since loops are unrolled anyway. Andy From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 19 May 2009 07:55:56 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 13:53:19 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <19fbf9ed-744c-4396-befc-0cea8b8d8fbd@n8g2000vbb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 47 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-NEeb+Hw7yHv9SQHrjO64vjsaBwSK/5fqveV/1XtA7ciPy7M+NRwBJrpo04UVZ4miLY9jn2tKQsCQcOB!atJKLqgz8SgbTYFTHbJio/jCyvqutrpxgSV0f5qehoC7mfdC/u871BuaqItqob5HJvYhTjNxqFue!CMeTKcfhGwbH+9zu X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2627 Xref: news.eternal-september.org comp.lang.vhdl:1175 On Tue, 19 May 2009 03:21:50 -0700 (PDT), Beware wrote: >Here's my new code : [...] > process (clk, rst, load) > begin -- process > if rst = '0' then > internal <= (others => '0'); > elsif clk'event and clk = '1' then > if load = '1' then > internal <= e1; > else > internal <= '0' & internal(31 downto 1); > end if; > end if; > end process; Cool. Two points to look at: (1) Get into the habit of using "rising_edge(clk)" in place of "clk'event and clk='1'". It's easier to write and easier to read. (2) The process sensitivity list should be process(clk, rst) You do NOT need "load" in the sensitivity list, because it is sampled only on the active clock edge. In VHDL it will not break your simulation, but it will waste simulation time and it may give synthesis warnings. Never include synchronous inputs in the sensitivity list; it should have ONLY clock and asynchronous reset. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!l32g2000vba.googlegroups.com!not-for-mail From: VIPS Newsgroups: comp.lang.vhdl Subject: Re: i2c Start and stop detection Date: Tue, 19 May 2009 06:19:43 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: References: <77e8acF1d11hlU1@mid.individual.net> NNTP-Posting-Host: 70.108.245.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242739184 26176 127.0.0.1 (19 May 2009 13:19:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 13:19:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000vba.googlegroups.com; posting-host=70.108.245.211; posting-account=WPnTdQoAAADxtUw2WpFzf9cv-eCysaC_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 GTB5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1176 On May 18, 7:12=A0pm, Mike Treseler wrote: > VIPS wrote: > > I am implementing the I2C Slave and I am using the I2C clock SCL for > > detecting the start and stop condition . I am detecting the start and > > stop successfully in simulation but i am not able to do the same in > > the post synthesis scenario. > > That scenario requires a synchronous process > something like this: > ... > begin > =A0 if reset =3D '1' then > =A0 =A0 =A0init_regs; > =A0 elsif rising_edge(clock) then > =A0 =A0 =A0update_regs; > =A0 end if; > =A0 update_ports; > end process; > > > Help will be appreciated. > > An i2c controller is a complex shift register > with case statements for bit and byte control. > A working design will require several > hundred lines of code. > > Google a bit. This has been done. > > =A0 =A0 =A0 -- Mike Treseler Thanks Mike for the reply . I have implemented the I2C slave as a state machine and the start and stop condition in data going from high to low when the clock is high . It is working fine in simulation but i am stuck up in the start and stop detection condition as it is asynchronous and on synthesis itis giving a setup time violation in synthesis in quartus. This is the main issue as to design a ckt for start and stop condition with I2C clock . I am not using oversampled clock as it is desired to use the I2C clock From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!news2.euro.net!82.197.223.103.MISMATCH!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 07:29:55 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <053af38c-cb4f-4134-8418-cf63dc08ff07@r34g2000vba.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <19fbf9ed-744c-4396-befc-0cea8b8d8fbd@n8g2000vbb.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242743396 7432 127.0.0.1 (19 May 2009 14:29:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 14:29:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1177 On 19 mai, 14:53, Jonathan Bromley wrote: hi, > Cool. =A0Two points to look at: > > (1) > Get into the habit of using "rising_edge(clk)" > in place of "clk'event and clk=3D'1'". =A0It's > easier to write and easier to read. > Ok, i'll remember it. In fact, i use Emacs and its VHDL-mode to write my files. So i use the shortcuts for write the vhdl and i don't rewrite it (i'm wrong i know). > (2) > The process sensitivity list should be > =A0 process(clk, rst) > You do NOT need "load" in the sensitivity list, because > it is sampled only on the active clock edge. =A0In VHDL > it will not break your simulation, but it will waste > simulation time and it may give synthesis warnings. > Never include synchronous inputs in the sensitivity list; > it should have ONLY clock and asynchronous reset. > -- > Jonathan Bromley, Consultant Allright, i delete the 'load' entry in the sensitive list. Thanks for all. From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r34g2000vba.googlegroups.com!not-for-mail From: philippe.faes@gmail.com Newsgroups: comp.lang.vhdl Subject: Re: Standard library packages for bit and strings? Date: Tue, 19 May 2009 09:00:53 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <4a112dd5$0$90274$14726298@news.sunsite.dk> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242748853 24586 127.0.0.1 (19 May 2009 16:00:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 16:00:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r34g2000vba.googlegroups.com; posting-host=195.144.71.15; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.8.1.19) Gecko/20081216 Fedora/2.0.0.19-1.fc8 Firefox/2.0.0.19 pango-text,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1178 On May 18, 3:08 pm, Alan Fitch wrote: > Also the company Easics used to have a package PCK_FIO which emulated > some printf-like behaviour. > This package can be found at: http://www.easics.com/webtools/freesics -- Philippe Faes http://www.sigasi.com From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: modulo function Date: Tue, 19 May 2009 16:20:12 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 30 Sender: mdhicks2@outside.world Message-ID: <6004390c20e718cba68ae97bdf56@news.acm.uiuc.edu> References: <8400e056-536e-4bf8-a96a-3a61d62d45cd@z7g2000vbh.googlegroups.com> NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1242750013 11312 98.220.249.110 (19 May 2009 16:20:13 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 19 May 2009 16:20:13 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1179 > On May 18, 11:39 pm, "qharz" wrote: > >> Hi >> I am quite fresh with vhdl and i have a problem. How to realize >> modulo >> function using signals not variables? >> For example: modulo_signal <= sample_signal mod 65536; >> Best regards, >> qharz > If you need to calculate mod 2^n it is as simple as just using the > array slice containing the data you seek. > You know x mod m gives you the rest of the division of x/m. If m is > 2^n, you simply need to take the lower n bits of the array to get your > result. > x / m for m = 2^n is x >> m, the rest is then the part shifted away, > or x - (( x >> m ) << m), or if x is an std_logic_vector( ? downto 0), > result <= x( n - 1 downto 0); > > Hope that helps, > Andreas Wallner Note that the solution above is true for positive x and m only. In this case the MOD and REM operators produce the same result, but they both can accept negative numbers, where they differ. Since the OP didn't explicitly limit the input, I thought I'd give a heads-up. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!h23g2000vbc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Quartus Inference Challenge Date: Tue, 19 May 2009 10:15:00 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242753300 21131 127.0.0.1 (19 May 2009 17:15:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 17:15:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h23g2000vbc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1180 Im trying to replace an altsyncram instatiation with an implied version, and I cant figure it out atm - thought Id put it out as a little challenge. Heres the altsyncram (dual clocked, in and out port width difference): alt_ram : altsyncram generic map ( Width_a => 64, width_b => 16, widthad_a => 7, widthad_b => 9 ) port map ( clock0 => clka, clock1 => clkb, data_a => data_a, address_a => std_logic_vector(to_unsigned(addr_a, 7) ), address_b => std_logic_vector(to_unsigned(addr_b, 9) ), q_b => q_b ); Its easy to infer it when A and B ports are identical widths, bit how to do it now there is a width mismatch? From newsfish@newsfish Wed Aug 19 13:24:44 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi069.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> Subject: Re: Version Control for VHDL Project Lines: 30 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi069.nbdc.sbc.com 1242754235 ST000 75.57.64.202 (Tue, 19 May 2009 13:30:35 EDT) NNTP-Posting-Date: Tue, 19 May 2009 13:30:35 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PGWXCD^JW]CRLZN[O@_WH@YR_B@EXLLBWLOOAFQATJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Tue, 19 May 2009 12:30:35 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1181 "KJ" wrote in message news:ljKPl.33384$ZP4.6385@nlpi067.nbdc.sbc.com... > > 3. Have the new design reference the new widget as in #2. But when you > get to the point of releasing something and want to be able to create a > tag that you can use as a real archive so that you go back and pull the > design as it really existed at some prior time, but still have the > benefits of referencing a single widget design when you're in development > mode, then you need to use 'svncopy.pl' > (http://svn.collab.net/repos/svn/trunk/contrib/client-side/svncopy/svncopy.README). > > This is one particular area of source control where MS Source Safe beats > Subversion hands down. The fact that you can't reference a widget in some > repository and be able to later tag it down to a specific revision at > design complete without a lot of effort (#2) or having to use scripts to > help along the source control tool's weakness (#3) is a major weakness, > 'specially considering that this is after all a source control tool. Unless I missed the full import of the context, for it to work in VSS, it has to all reside in the one repository, and so works even better in SVN. SVN doesn't need tags or labels. A single revision number refers to the entire state of the repository, including branches. You run into trouble only if your work spans different branches, but that's a problematic workflow issue regardless of the version control tool. For example, your project is in the trunk, but you branched the libraries to support your local work. The better solution is to branch lower so they have a common root. If they span repositories, ... you might want to reconsider the repository schema. From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi069.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> Subject: Re: Version Control for VHDL Project Lines: 40 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi069.nbdc.sbc.com 1242755108 ST000 75.57.64.202 (Tue, 19 May 2009 13:45:08 EDT) NNTP-Posting-Date: Tue, 19 May 2009 13:45:08 EDT Organization: at&t http://my.att.net/ X-UserInfo1: O@ZAR[SEBBTACFD[LZKJOPHAWB\^PBQLGPQRZ_MHEQR@ETUCCNSKQFCY@TXDX_WHSVB]ZEJLSNY\^J[CUVSA_QLFC^RQHUPH[P[NRWCCMLSNPOD_ESALHUK@TDFUZHBLJ\XGKL^NXA\EVHSP[D_C^B_^JCX^W]CHBAX]POG@SSAZQ\LE[DCNMUPG_VSC@VJM Date: Tue, 19 May 2009 12:45:08 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1182 "MikeWhy" wrote in message news:%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com... > "KJ" wrote in message > news:ljKPl.33384$ZP4.6385@nlpi067.nbdc.sbc.com... >> >> 3. Have the new design reference the new widget as in #2. But when you >> get to the point of releasing something and want to be able to create a >> tag that you can use as a real archive so that you go back and pull the >> design as it really existed at some prior time, but still have the >> benefits of referencing a single widget design when you're in development >> mode, then you need to use 'svncopy.pl' >> (http://svn.collab.net/repos/svn/trunk/contrib/client-side/svncopy/svncopy.README). >> >> This is one particular area of source control where MS Source Safe beats >> Subversion hands down. The fact that you can't reference a widget in >> some repository and be able to later tag it down to a specific revision >> at design complete without a lot of effort (#2) or having to use scripts >> to help along the source control tool's weakness (#3) is a major >> weakness, 'specially considering that this is after all a source control >> tool. > > Unless I missed the full import of the context, for it to work in VSS, it > has to all reside in the one repository, and so works even better in SVN. > SVN doesn't need tags or labels. A single revision number refers to the > entire state of the repository, including branches. You run into trouble > only if your work spans different branches, but that's a problematic > workflow issue regardless of the version control tool. For example, your > project is in the trunk, but you branched the libraries to support your > local work. The better solution is to branch lower so they have a common > root. If they span repositories, ... you might want to reconsider the > repository schema. [ps] Oops. Scratch that. I've successfully avoided needing SVN externals altogether, but they solve the problem of cross branches or repositories. Thought I'd save everyone the trouble of correcting me. Once the externals are setup, the project can always be reverted to the right state for a given revision. From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 19 May 2009 12:45:54 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Quartus Inference Challenge Date: Tue, 19 May 2009 18:43:16 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <1dq515hcs28nf6trmukj4m8eaoaqjplhfq@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 25 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-qACha+dZ+iIRZMXqaQ4xhEQsQcbC0NefZVsoIPy8OBgQUpsiSQFuc/0ar3vbz4tQrwE5iRMVth1muSY!2S2SquUggX+LoTKe1iTxsoJwv5bv5fN2G8jO0STndUglfTGGhZx9HmMh4DnBVdEydK+kLLCgMY4p!y2yDyyxhOr44EmwV X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2077 Xref: news.eternal-september.org comp.lang.vhdl:1183 On Tue, 19 May 2009 10:15:00 -0700 (PDT), Tricky wrote: >Its easy to infer it when A and B ports are identical widths, bit how >to do it now there is a width mismatch? In a recent thread on comp.arch.fpga, various posts pointed out that this can't currently be done for Xilinx BRAMs using any of the usual synthesis tools. I strongly suspect it can't be done for Altera either. I tried resizing "by hand" in the VHDL but couldn't make it work properly. Might try again later in Verilog, where it's easier to do the shared-variable thing. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!q14g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Tue, 19 May 2009 11:03:55 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <905cdccf-936c-453b-86b5-e76be7889160@q14g2000vbn.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <19fbf9ed-744c-4396-befc-0cea8b8d8fbd@n8g2000vbb.googlegroups.com> <053af38c-cb4f-4134-8418-cf63dc08ff07@r34g2000vba.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242756236 15762 127.0.0.1 (19 May 2009 18:03:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 18:03:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q14g2000vbn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1184 A few more recommendations for your code: If you have a reset function, you should not initialize the register signal in its declaration. The initialization makes it harder to test whether your reset is working. You can use the 'range attribute when declaring a signal that needs to be the same range as a port: signal internal : std_logic_vector(e1'range); -- same range as e1 Given your shift logic, this works because the port has the correct range (direction & bounds) too. Sometimes the port may not have the correct index bounds and/or direction (it may be an unconstrained port, which take's its range from the signal bound to the port for that instance): signal internal : std_logic_vector(e1'length-1 downto 0); -- normalized range Andy From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi069.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> Subject: Re: Version Control for VHDL Project Lines: 15 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi069.nbdc.sbc.com 1242756374 ST000 75.57.64.202 (Tue, 19 May 2009 14:06:14 EDT) NNTP-Posting-Date: Tue, 19 May 2009 14:06:14 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PAPDCA[S@IRRDXKZNT_ZTDFZ\@@FXLM@TDOCQDJ@_@FNXACNVOPCWZBL[\YUWHANGYZEFNHFZPNLOBUNSS^_LGEVWEY\PHO@YJSSWBBDT\PFD^ESBTXVCCMTD]JCJLE\_IJMFNRY]SWE[S[D_CNB__ZK^VGVCKHA[S@COB^[@ZQSDFQ\BPMS@DZVUKQTJL Date: Tue, 19 May 2009 13:06:14 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1185 "KJ" wrote in message news:Hg%Pl.22530$as4.8241@nlpi069.nbdc.sbc.com... > > Creating tags using 'svn copy' though doesn't lock down the revision of > externals when creating the tag so when you go back later to get the tag > and check it out, anything from an 'svn_external' will return the 'head' > revision of the referenced folder, not the revision that existed at the > time that you created the tag... The externals property takes an optional revision number: fooPath -rNnnn URL Since properies are versioned, the externals will track properly when you manually track the external revision. From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!t10g2000vbg.googlegroups.com!not-for-mail From: Aiken Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design Date: Tue, 19 May 2009 11:23:55 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <679b3afd-a0dd-494f-acd7-c1737fa3d231@t10g2000vbg.googlegroups.com> References: NNTP-Posting-Host: 199.10.150.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242757435 1511 127.0.0.1 (19 May 2009 18:23:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 18:23:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t10g2000vbg.googlegroups.com; posting-host=199.10.150.153; posting-account=o1NIRQoAAACD94UsAWOsHscwtNA8hiam User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.65 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1186 comp.arch.fpga:3471 How can I setup for running modelsim? Aiken On May 19, 6:33=A0am, philippe.f...@gmail.com wrote: > Today, Sigasi proudly announces the Public Beta program for Sigasi > HDT, an Intelligent Development Environment (IDE) for VHDL (http://www.si= gasi.com/publicbeta). > > Sigasi HDT (Hardware Development Toolkit) is a powerful VHDL > development tool that assists designers in reading, writing and > modifying VHDL more accurately and faster. It differs from other > development tools in that it contains an ultra-fast VHDL parser and > compiler that runs transparently in the background (http://www.sigasi.com= /product). > > Through the Public Beta program, VHDL designers join a community that > takes advantage of modern development techniques. To participate in > the program, please visithttp://www.sigasi.com/start. From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e24g2000vbe.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Tue, 19 May 2009 11:37:15 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <369ffaa6-d92f-4119-9432-23c377b2fef0@e24g2000vbe.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242758235 4106 127.0.0.1 (19 May 2009 18:37:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 18:37:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e24g2000vbe.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1187 On May 19, 2:06=A0pm, "MikeWhy" wrote: > "KJ" wrote in message > > news:Hg%Pl.22530$as4.8241@nlpi069.nbdc.sbc.com... > > > > > Creating tags using 'svn copy' though doesn't lock down the revision of > > externals when creating the tag so when you go back later to get the ta= g > > and check it out, anything from an 'svn_external' will return the 'head= ' > > revision of the referenced folder, not the revision that existed at the > > time that you created the tag... > > The externals property takes an optional revision number: > fooPath -rNnnn URL > > Since properies are versioned, the externals will track properly when you > manually track the external revision. That's good if you really like *manually* setting revisions on all svn_externals. When you're getting ready to release and really lock down on a final version, the last thing you want is some manual process like this to be in the loop. >From a 'two years down the road' support perspective of being able to exactly recreate all source files as they really were at the time of release, the last thing you want is to have to hope and pray that someone manually did this to each and every svn_external (on each and every release) when you know that they were under the gun to get the thing released and out the door. Neither scenario is a good one, which is why if you use svn_external you really need to use something like svncopy.pl to create the tags for release and not rely on 'svn copy' or TortoiseSVN or the methods discussed by the Subversion folks to create a tag. KJ From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!t10g2000vbg.googlegroups.com!not-for-mail From: philippe.faes@gmail.com Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design Date: Tue, 19 May 2009 11:55:15 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <679b3afd-a0dd-494f-acd7-c1737fa3d231@t10g2000vbg.googlegroups.com> NNTP-Posting-Host: 81.11.160.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242759315 7403 127.0.0.1 (19 May 2009 18:55:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 May 2009 18:55:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t10g2000vbg.googlegroups.com; posting-host=81.11.160.189; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X; en-US; rv:1.8.1.12) Gecko/20080201 Firefox/2.0.0.12,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1188 comp.arch.fpga:3473 On May 19, 8:23 pm, Aiken wrote: > How can I setup for running modelsim? > > Aiken Hi Aiken, To set up external tools, please check the user manual: "help->help contents" and then "Sigasi HDT -> User Manual -> External Tools" I suggest further support requests can be handled on the Sigasi website, in order not to overload this list with off-topic questions: http://www.sigasi.com/userforum kind regards Philippe From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design Date: Tue, 19 May 2009 12:00:38 -0700 Lines: 14 Message-ID: <77gdunF1ghd5hU1@mid.individual.net> References: <679b3afd-a0dd-494f-acd7-c1737fa3d231@t10g2000vbg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net e0+AODvFwIrTxJ+MFjG7kAeYXtV9AGaKk2i1Do+gQrC5eRpD/L Cancel-Lock: sha1:K8oTVVxD8tFDZj+aWfoPrv4h/cQ= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1189 comp.arch.fpga:3474 philippe.faes@gmail.com wrote: > On May 19, 8:23 pm, Aiken wrote: >> How can I setup for running modelsim? >> >> Aiken > > Hi Aiken, > > To set up external tools, please check the user manual: "help->help > contents" and then "Sigasi HDT -> User Manual -> External Tools" The editor does seem to cover syntax checking without needing vcom. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:45 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Sigasi Public Beta: future of VHDL design Date: Tue, 19 May 2009 22:33:15 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 24 Sender: mdhicks2@outside.world Message-ID: <6004390c20f6a8cba6bf06beb514@news.acm.uiuc.edu> References: <77gdunF1ghd5hU1@mid.individual.net> NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1242772396 20762 98.220.249.110 (19 May 2009 22:33:16 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Tue, 19 May 2009 22:33:16 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.arch.fpga:3475 comp.lang.vhdl:1190 > philippe.faes@gmail.com wrote: > >> On May 19, 8:23 pm, Aiken wrote: >> >>> How can I setup for running modelsim? >>> >>> Aiken >>> >> Hi Aiken, >> >> To set up external tools, please check the user manual: "help->help >> contents" and then "Sigasi HDT -> User Manual -> External Tools" >> > The editor does seem to cover syntax checking without needing vcom. > > -- Mike Treseler > That's because they use their own VHDL front end. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi149.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> Subject: Re: Version Control for VHDL Project Lines: 160 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi149.ffdc.sbc.com 1242796930 ST000 99.184.242.197 (Wed, 20 May 2009 01:22:10 EDT) NNTP-Posting-Date: Wed, 20 May 2009 01:22:10 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[R_@SJD^RTYBQPXGRHJ__TDFZ\@@FXLM@TDOCQDJ@_@FN\CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 20 May 2009 01:15:04 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1191 "MikeWhy" wrote in message news:EeCQl.22637>> Unless I missed the full import of the context, for it to work in VSS, it >> SVN doesn't need tags or labels. A single revision number refers to the >> entire state of the repository, including branches. But the labels in VSS actually allow one to easily mark everything so that you can come back years later and recover it exactly. I'm not pushing VSS, actually I like Subversion and Tortoise better than VSS, I just happen to use both. > Once the externals are setup, the project can always be reverted to the > right state for a given revision. > Try the following experiment (or just read along and trust that it really turns out the way that I say it does...the ending has quite the twist for those who think that Subversion tags actually do anything useful from an archival standpoint) 1. Setup a new repository 2. Add new folders called 'Project1' and 'Project2' to the repo. 3. Export 'Project1' to some folder 4. Add the svn_external property to the working copy of 'Project1' to reference 'Project2'. 5. Do an update to get Project2 into the working copy. 6. Create a new text file called 'Project2_File.txt' in the Project2 folder. 7. Edit Project2_File.txt so it has the single line of text 'This is line #1' 8. Add Project2_File.txt into 'Project2' and commit the changes to both 'Project1' and 'Project2'. At this point, what you've emulated is the creation of a new design called 'Project1' that refers to some presumably reusable module called 'Project2'. Consider for the moment that reusable modules always begin life somewhere and many times this begining is during the development of some bigger thing. So in this case 'Project1' is the *bigger* thing, and 'Project2' is the newly created (but intended to be reusable) module. In this scenario both projects are likely both being developed concurrently and, for the most part, up until towards the end of the development cycle 'Project1' will most likely always want to be referring to the latest/greatest (i.e. the 'head' revision in Subversion-speak). For that scenario then, one would most likely want to leave the revision off of the 'svn_external' reference thereby defaulting to the 'head'. You might not want to, but indulge me. Anyway, so far, so good. 9. Create your tag of 'Project1' using 'svn copy' or TortoiseSVN so that you get the warm fuzzy feeling that you've successfully archived away the current state of 'Project1' at this moment in time confident that you can come back at any time to recover this entire project exactly as it was left after step #8. To do so you will of course be specifying the exact revision of 'Project1' to use to create the tag. Lets say this tagged version of 'Project1' is put into the archive at 'Tags/Project1_1.0' Step 9 emulates what one would be doing when you've completed development and are getting ready to release. The purpose of the tag 'Tags/Project1_1.0' is to permanently archive away the 'Project1' design and any of its subprojects for posterity so that they can be recreated at any point in the future regardless of any future changes to either 'Project1' or 'Project2'. 10. Checkout 'Tags/Project1_1.0' to a folder 'Project1_1.0_Step10' 11. Open up the file ''Project1_1.0_Step10\Project2\Project2_File.txt' and it will of course have one line of text "This is line #1"...again all is well and good 12. Go back to the original working copy where you created 'Project1', or better yet delete all of the folders so there are no working copies. Then check out 'Project1' (not the archived tag, but the original) to create a working copy in 'Project1-NEW' 13. Edit the file 'Project1-NEW\Project2\Project2_File.txt' by adding a new line "This is line #2" and commit it to the repository. Steps 12 and 13 emulate entering design changes into the 'trunk', perhaps to add new functionality, bug fixes, documenation, whatever. You've dutifully avoided changing the 'tag' branch, you've made modifications only to the trunk as per all the Subversion recommended procedures (actually I've skipped over the creating of a branch and the merge back into the trunk just for simplicity). 14. Now let's checkout 'Tags/Project1_1.0' again, this time to the folder 'Project1_1.0_Step_14' Step 14 is emulating the attempted recovery of the tag of 'Project1' as it was archived back on step 9. This would be a normal support activity, the re-creation of all of the source files as they existed at some previous time to investigate some odd customer reported activity. 15. Open the file 'Project1_1.0_Step_14\Project2\Project2_File.txt' 16. Pick your jaw up, wipe the sweat off your brow, or do whatever it is that you think is appropriate when you see that this file (checked out from the safely and dutifully archived 'tag' remember) now has two lines of text This is line #1 This is line #2 17. Explain to me how you think you've archived the actual source files and can re-create any of your released builds because you've 'tagged' them. --- Now this story could have had a happier ending. You could vehemently object and say that in step #4 when the 'svn_external' was first added that by golly you would never have let this go, you would always have specified a particular revision. Fair enough, and if 'Project2' is always some locked down, well debugged, never ever going to change thing and that's the only type of thing you would ever reference via 'svn_external' you might have a point. But remember the scenario I was painting, both 'Project1' and 'Project2' were being developed simultaneously, both subject to change. I'll boldly make the following claims about such an approach - Very, very little is ever likely to meet the standard of "locked down, well debugged, never ever going to change" - You're creating a lot more needless work for yourself by manually specifying revisions for every 'svn_external'...and when you think about it, this extra work is because the version control system you're using has trouble recreating a specific revision. - You haven't considered that others might not be quite as diligent as you about always manually adding revisions, so then what? A few questions come to mind: How much effort do you think is worth expending to cover the omissions of others? Ask yourself why a highly regarded version control system should have such a glaring deficiency in actually being able to recover archived versions properly? Don't work yourself into a dither though, help may be on the way. The method to recover from all the bad things that you realized in step #16 might be are (but beware the bogey on step 22): 18. Google for svncopy.pl. Download it, it's a PERL script 19. Google for and download and install some version of PERL if necessary. 20. Go to your repository log and figure out which revision of your repository created the tag that you did in Step #9. I'm sure you added a log message entry during your commit to facilitate this ;) 21. Type in the following (replacing xxxx with the revision you determined in #20, and of course replacing the repo links as appropriate for the source and destination of the copy perl svncopy.pl --tag --revision xxxx file:///C:/Mysvn/Project1 file:///C:/Mysvn/Tags/Project1_1.0-Svncopy 22. Hope that you don't get the error message: Can't call method "temp_dir" on an undefined value at \program files\subversion\svncopy.pl line 221. 23. If you're lucky with step #22, you should now have a correctly tagged 'Project1' that has really archived the entire revision. Repeat steps 12 and 13 and see if it really sticks. If so, then exhale. If you're not so lucky on step #22 and get the error message, please post the solution to this problem. Even Google failed to come up with the solution although it appears many have run across this problem. If you're stuck having this problem, exhale anyway, holding your breath doesn't really help. Kevin Jennings P.S. I am looking for the solution to the error message in a Windows environment if anyone can provide it. P.P.S. Obviously this post has more to do with Subversion then VHDL so I apologize but there do seem to be some misconceptions among this group about just how useful a 'tag' really is from an archival perspective when using 'svn_external' to reference reusable widgets. From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Wed, 20 May 2009 09:04:20 +0100 Organization: TRW Conekt Lines: 36 Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <19fbf9ed-744c-4396-befc-0cea8b8d8fbd@n8g2000vbb.googlegroups.com> <053af38c-cb4f-4134-8418-cf63dc08ff07@r34g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net RYHS4Lx8T+6cngfI73d5Fw0MZ7NebGSVf1cf0vjUZ94yJw9os= Cancel-Lock: sha1:Sdtr/TUtuRbFDYEDTCrHVo0pmag= sha1:LJqcjbbuDS088ySAHOM+e9ODhNs= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:1192 Beware writes: > On 19 mai, 14:53, Jonathan Bromley > wrote: > > hi, >> Cool.  Two points to look at: >> >> (1) >> Get into the habit of using "rising_edge(clk)" >> in place of "clk'event and clk='1'".  It's >> easier to write and easier to read. >> > > Ok, i'll remember it. > In fact, i use Emacs and its VHDL-mode to write my files. So i use the > shortcuts for write the vhdl and i don't rewrite it (i'm wrong i > know). You can change a setting in VHDL-mode to tell it to use rising_edge() as well: Click VHDL..Options..Template..Sequential Process..Clock Edge Condition Don't forget to save it to your .emacs file as well. VHDL..Options..Save Options While you're in there there's loads of other customisations as well :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Wed, 20 May 2009 01:59:56 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242809996 21641 127.0.0.1 (20 May 2009 08:59:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 08:59:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1193 Thanks all for your answer. @Andy : I didn't knew the 'range' option to describe a signal, it's very usefull. Can i use them for describe all my internal signal? The code will not become harder to read? @Martin : Thanks for the option. You're are right, there's a lot of options to customize emacs for the VHDL. From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r13g2000vbr.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Wed, 20 May 2009 05:54:43 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <1eb63a60-fa98-4626-b3d6-29e754889558@r13g2000vbr.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242824084 392 127.0.0.1 (20 May 2009 12:54:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 12:54:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000vbr.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1194 On May 20, 3:59=A0am, Beware wrote: > Thanks all for your answer. > > @Andy : I didn't knew the 'range' option to describe a signal, it's > very usefull. Can i use them for describe all my internal signal? The > code will not become harder to read? > > @Martin : Thanks for the option. You're are right, there's a lot of > options to customize emacs for the VHDL. I use range/length attributes to make it clear that one signal/ variable's size needs to be related to another. If it just happens that they are the same size, but do not need to be, I do not use those attributes. It's just another hint about the code for when I'm reading it weeks/months/years after I wrote it. Use of those attributes also makes it easier to modify later on, since I can change the size of one or a few signals/variables, and others will automatically adjust as needed. Thinking about maintaining a piece of code, even while you are writing it the first time, will pay for itself eventually. Another example of this would be to change the shift assignment to something like: internal <=3D '0' & internal(internal'left downto 1); There are other ways to accomplish the shift, but this is closest to what you originally wrote. This way, all you need to do to change the length of the shift register is to change the length of the e1 port. Andy From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b1g2000vbc.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Wed, 20 May 2009 08:02:59 -0700 (PDT) Organization: http://groups.google.com Lines: 122 Message-ID: <0aa866d0-a3e7-421a-9a03-be1de70bff55@b1g2000vbc.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <1eb63a60-fa98-4626-b3d6-29e754889558@r13g2000vbr.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242831779 25073 127.0.0.1 (20 May 2009 15:02:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 15:02:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b1g2000vbc.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1195 On 20 mai, 14:54, Andy wrote: > On May 20, 3:59=A0am, Beware wrote: > > > Thanks all for your answer. > > > @Andy : I didn't knew the 'range' option to describe a signal, it's > > very usefull. Can i use them for describe all my internal signal? The > > code will not become harder to read? > > > @Martin : Thanks for the option. You're are right, there's a lot of > > options to customize emacs for the VHDL. > > I use range/length attributes to make it clear that one signal/ > variable's size needs to be related to another. If it just happens > that they are the same size, but do not need to be, I do not use those > attributes. It's just another hint about the code for when I'm reading > it weeks/months/years after I wrote it. Use of those attributes also > makes it easier to modify later on, since I can change the size of one > or a few signals/variables, and others will automatically adjust as > needed. Thinking about maintaining a piece of code, even while you are > writing it the first time, will pay for itself eventually. > > Another example of this would be to change the shift assignment to > something like: > > =A0 internal <=3D '0' & internal(internal'left downto 1); > > There are other ways to accomplish the shift, but this is closest to > what you originally wrote. > > This way, all you need to do to change the length of the shift > register is to change the length of the e1 port. > > Andy Hi Andy, Thank you for all your hints and your eplications. It's now easy to modify the length of an input by using 'length, 'range or 'left options for internals signals. I've one another question. I'm using GHDL for compilation and simulation add to Gkwave. For compilation GHDL use the ieee libraries and VHDL-1993(c) standard, i have no errors or warning. But if i user VHDL-2000 standard, i have one error in my testbench file in the declaration of my component. The error : testbench/tb_multi.vhd:36:3:warning: component instance "multiplieur1" is not bound testbench/tb_multi.vhd:11:14:warning: (in default configuration of tb_multiplieur(d_tb_multiplieur)) The code : library ieee; use ieee.std_logic_1164.all; --entity entity tb_multiplieur is end tb_multiplieur; --design architecture d_tb_multiplieur of tb_multiplieur is component multiplieur port ( op1 : in std_logic_vector(31 downto 0); op2 : in std_logic_vector(31 downto 0); res : out std_logic_vector(63 downto 0); h : in std_logic; raz : in std_logic; load : in std_logic); end component; signal sortie : std_logic_vector(res'range) :=3D (others =3D> '0'); signal A : std_logic_vector(op1'range) :=3D (others =3D> '0'); signal B : std_logic_vector(op2'range) :=3D (others =3D> '0'); signal clk : std_logic :=3D '0'; signal rst : std_logic :=3D '0'; signal ld : std_logic :=3D '0'; begin -- d_tb_multiplieur multiplieur1:multiplieur port map ( op1 =3D> A, op2 =3D> B, res =3D> sortie, h =3D> clk, load =3D> ld, raz =3D> rst); reset:process begin -- process reset wait for 10 ns; rst <=3D not rst; wait for 1000 ms; end process reset; horloge: process begin -- process horloge wait for 10 ns; clk <=3D not clk; end process horloge; inputs: process begin -- process inputs A <=3D x"A5A5A5A5"; B <=3D x"5A5A5A5A"; wait for 15 ns; ld <=3D '1'; wait for 20 ns; ld <=3D not ld; wait for 900 ns; end process inputs; end d_tb_multiplieur; But i don't know if the error is due to GHDL or to my code. From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: Quartus Inference Challenge Date: Wed, 20 May 2009 08:15:08 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <014d146b-b8d0-4351-813d-2b074733af4b@z5g2000vba.googlegroups.com> References: NNTP-Posting-Host: 217.171.129.69 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242832508 27380 127.0.0.1 (20 May 2009 15:15:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 15:15:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=217.171.129.69; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.65 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1196 On May 19, 6:15=A0pm, Tricky wrote: > Im trying to replace an altsyncram instatiation with an implied > version, and I cant figure it out atm - thought Id put it out as a > little challenge. > Heres the altsyncram (dual clocked, in and out port width difference): > > alt_ram : altsyncram > =A0 generic map ( > =A0 =A0 Width_a =A0 =A0=3D> 64, > =A0 =A0 width_b =A0 =A0=3D> 16, > > =A0 =A0 widthad_a =A0=3D> 7, > =A0 =A0 widthad_b =A0=3D> 9 > > =A0 ) > =A0 port map ( > > =A0 =A0 clock0 =A0 =A0 =A0 =A0 =3D> clka, > =A0 =A0 clock1 =A0 =A0 =A0 =A0 =3D> clkb, > > =A0 =A0 data_a =A0 =A0 =A0 =A0 =3D> data_a, > =A0 =A0 address_a =A0 =A0 =A0=3D> std_logic_vector(to_unsigned(addr_a, 7)= ), > > =A0 =A0 address_b =A0 =A0 =A0=3D> std_logic_vector(to_unsigned(addr_b, 9)= ), > =A0 =A0 q_b =A0 =A0 =A0 =A0 =A0 =A0=3D> q_b > > =A0 ); > > Its easy to infer it when A and B ports are identical widths, bit how > to do it now there is a width mismatch? Try multiplexing a 64 bit output port into 4*16 using two address bits. This makes the same port widths. cheers jacko From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Sigasi Public Beta: future of VHDL design Date: Wed, 20 May 2009 08:48:44 -0700 Lines: 15 Message-ID: <77in2uF1i105oU1@mid.individual.net> References: <77gdunF1ghd5hU1@mid.individual.net> <6004390c20f6a8cba6bf06beb514@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net j9UVBiD2Vw8GiMg9ejQkzAp9a4MU4UyRTDQg5BB8BlPfUjyGqF Cancel-Lock: sha1:NXcX+TvKKxSptRvLgqsv7Jpd3Sc= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <6004390c20f6a8cba6bf06beb514@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.arch.fpga:3498 comp.lang.vhdl:1197 >>> Aiken wrote: >>> >>>> How can I setup for running modelsim? > Mike Treseler wrote: >> The editor does seem to cover syntax checking without needing vcom. Matthew Hicks wrote: > That's because they use their own VHDL front end. Yes, and for that reason Aiken might not need to hook up modelsim to jump to syntax errors. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000vba.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Quartus Inference Challenge Date: Wed, 20 May 2009 09:06:34 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <68b15058-d193-4a9c-ac73-fdb70bf1d2c2@l32g2000vba.googlegroups.com> References: <014d146b-b8d0-4351-813d-2b074733af4b@z5g2000vba.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242835594 13653 127.0.0.1 (20 May 2009 16:06:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 16:06:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000vba.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1198 On 20 May, 16:15, Jacko wrote: > On May 19, 6:15=A0pm, Tricky wrote: > > > > > Im trying to replace an altsyncram instatiation with an implied > > version, and I cant figure it out atm - thought Id put it out as a > > little challenge. > > Heres the altsyncram (dual clocked, in and out port width difference): > > > alt_ram : altsyncram > > =A0 generic map ( > > =A0 =A0 Width_a =A0 =A0=3D> 64, > > =A0 =A0 width_b =A0 =A0=3D> 16, > > > =A0 =A0 widthad_a =A0=3D> 7, > > =A0 =A0 widthad_b =A0=3D> 9 > > > =A0 ) > > =A0 port map ( > > > =A0 =A0 clock0 =A0 =A0 =A0 =A0 =3D> clka, > > =A0 =A0 clock1 =A0 =A0 =A0 =A0 =3D> clkb, > > > =A0 =A0 data_a =A0 =A0 =A0 =A0 =3D> data_a, > > =A0 =A0 address_a =A0 =A0 =A0=3D> std_logic_vector(to_unsigned(addr_a, = 7) ), > > > =A0 =A0 address_b =A0 =A0 =A0=3D> std_logic_vector(to_unsigned(addr_b, = 9) ), > > =A0 =A0 q_b =A0 =A0 =A0 =A0 =A0 =A0=3D> q_b > > > =A0 ); > > > Its easy to infer it when A and B ports are identical widths, bit how > > to do it now there is a width mismatch? > > Try multiplexing a 64 bit output port into 4*16 using two address > bits. This makes the same port widths. > > cheers jacko Yup, I can do that, but its not as efficient as the direct instantiation. Altera have come back saying they dont support it - I shall put in an enhancement request. From newsfish@newsfish Wed Aug 19 13:24:46 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Quartus Inference Challenge Date: Wed, 20 May 2009 11:18:27 -0700 Lines: 9 Message-ID: <77ivrkF1hbdiiU1@mid.individual.net> References: <014d146b-b8d0-4351-813d-2b074733af4b@z5g2000vba.googlegroups.com> <68b15058-d193-4a9c-ac73-fdb70bf1d2c2@l32g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net fXxkOG4Q3gdeE4hX6yMoGQLO7WnEwftthF15W3/pq+brz9tGv1 Cancel-Lock: sha1:nVEWb+JCHfhJfYF45AkxbvzodRk= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <68b15058-d193-4a9c-ac73-fdb70bf1d2c2@l32g2000vba.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1199 Tricky wrote: > Yup, I can do that, but its not as efficient as the direct > instantiation. But it is portable. Does the instance use zero LUTs for the mux? -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!transit3.readnews.com!news-out.readnews.com!transit4.readnews.com!postnews.google.com!v17g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Wed, 20 May 2009 12:09:02 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <1eb63a60-fa98-4626-b3d6-29e754889558@r13g2000vbr.googlegroups.com> <0aa866d0-a3e7-421a-9a03-be1de70bff55@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242846542 7363 127.0.0.1 (20 May 2009 19:09:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 May 2009 19:09:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v17g2000vbb.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1200 GHDL is just complaining that you have not compiled anything for the multiplier component to bind to. Compile the entity/arch for multiplier with the same signature (name and port list) and it should get rid of the warning. If the entity signature is not the same as that of the component, then you will have to use a configuration to bind the entity/arch to the component instantiation. You can also directly instantiate entity/architectures under vhdl'93 and later: label: entity work.entity_name(architecture_name)... The architecture name is optional. Beware, this will result in errors (not warnings) if you have not already compiled the entity (and architecture if the instantiation specified it). I use entity instantiation for stuff that I write, but components for primitives from other libraries, especially when synthesis recognizes the component automatically, but simulation needs to compile/link the model for the primitive. Andy From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi064.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> Subject: Re: Version Control for VHDL Project Lines: 50 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi064.nbdc.sbc.com 1242851280 ST000 75.57.64.202 (Wed, 20 May 2009 16:28:00 EDT) NNTP-Posting-Date: Wed, 20 May 2009 16:28:00 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PAPDCA[S@IRRDXKZNT_ZTDFZ\@@FXLM@TDOCQDJ@_@FNXACNVOPCWZBL[\YUWHANGYZEFNHFZPNLOBUNSS^_LGEVWEY\PHO@YJSSWBBDT\PFD^ESBTXVCCMTD]JCJLE\_IJMFNRY]SWE[S[D_CNB__ZK^VGVCKHA[S@COB^[@ZQSDFQ\BPMS@DZVUKQTJL Date: Wed, 20 May 2009 15:28:05 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1201 I wish I had sent the Me too! earlier rather than deleting it. It might have saved you a lot of typing. Fundamentally, I agree with your observation, that svn:externals have archival problems. But I come to a different conclusion. If you need to use them, the externals must all have explicit revision references. Otherwise, they are little more useful than `ln -s` soft links to a local working copy of the foreign repository. In fact, they are worse in some respects. You get the worst of both worlds: archival issues, AND continual integration issues as you blindly track their updates. The soft-link at least allows you control over when you update the foreign source. My day job is software. The revision id is post-processed into the binaries and debug symbols so the toolchain can pull the right source versions for autopsies. With unrestrained externals in the tree, traceability is already compromised without talking about archiving. It isn't completely broken, as the externals version can be narrowed _manually_ by approximate time and date. But you should know that anything that interferes with a smooth workflow on a 02:00 server outage brings painful wrath immediately. The problem with SVN externals is not so much their implementation, but their visibility. They're essentially hidden without tools that show clearly the state, that they're external, and to which revision they are locked if it is or isn't. I don't believe that Tortoise does this, but I have no experience with externals. It was a wise rule: NO FREAKING EXTERNALS. I've reaffirmed it with the thought exercise. An additional comment below... "KJ" wrote in message news:6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com... ... > 21. Type in the following (replacing xxxx with the revision you determined > in #20, and of course replacing the repo links as appropriate for the > source and destination of the copy > perl svncopy.pl --tag --revision xxxx file:///C:/Mysvn/Project1 > file:///C:/Mysvn/Tags/Project1_1.0-Svncopy > 22. Hope that you don't get the error message: > Can't call method "temp_dir" on an undefined value at \program > files\subversion\svncopy.pl line 221. ... > > P.S. I am looking for the solution to the error message in a Windows > environment if anyone can provide it. Many tools have a problem with spaces in the path name. Have you tried simply moving the script to a directory with a simpler name? E:\tools and E:\apps became my local convention after being bitten too many times by cross-platform packages. From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Wed, 20 May 2009 14:13:16 -0700 Lines: 22 Message-ID: <77ja3cF1i4fh2U1@mid.individual.net> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net NWhZVzjlaeEvX2AtMV32/gsDbHjo0jIMaw2wC2f+fV1/38VXqz Cancel-Lock: sha1:y0VlaYdJN1B5vHEpVyfGa3eLhM0= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1202 MikeWhy wrote: > I wish I had sent the Me too! earlier rather than deleting > it. It might have saved you a lot of typing. Yes, thanks to KJ for sharing the hard knocks. > ... You get the worst > of both worlds: archival issues, AND continual integration issues as you > blindly track their updates. The soft-link at least allows you control > over when you update the foreign source. Since an svn copy is essentially free, and since almost anything might be reused, what is the downside to keeping all of an organization's vhdl code in the same repository? > It was a wise rule: NO FREAKING > EXTERNALS. I've reaffirmed it with the thought exercise. *Me too*, at least until I understand their upside. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi065.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <77ja3cF1i4fh2U1@mid.individual.net> Subject: Re: Version Control for VHDL Project Lines: 39 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi065.nbdc.sbc.com 1242856087 ST000 75.57.64.202 (Wed, 20 May 2009 17:48:07 EDT) NNTP-Posting-Date: Wed, 20 May 2009 17:48:07 EDT Organization: at&t http://my.att.net/ X-UserInfo1: TSU[@IONXJTERTT[FJMD]_\@VR]^@B@MCPWZKB]MPXHJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 20 May 2009 16:48:07 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1203 "Mike Treseler" wrote in message news:77ja3cF1i4fh2U1@mid.individual.net... > MikeWhy wrote: >> I wish I had sent the Me too! earlier rather than deleting >> it. It might have saved you a lot of typing. > > Yes, thanks to KJ for sharing the hard knocks. > >> ... You get the worst >> of both worlds: archival issues, AND continual integration issues as you >> blindly track their updates. The soft-link at least allows you control >> over when you update the foreign source. > > Since an svn copy is essentially free, > and since almost anything might be reused, > what is the downside to keeping all of > an organization's vhdl code in the same repository? > >> It was a wise rule: NO FREAKING >> EXTERNALS. I've reaffirmed it with the thought exercise. > > *Me too*, at least until I understand their upside. So... what are the benefits? If it's a single repository, I can see building a virtual view of the tree, with just the parts I want, and arranged more meaningfully in my local project. It makes sense sometimes to lift libraries, say, so they are more accessible and visible, below the project itself. That's not a problem for archiving, since they are snapped from the same repository, with the same revision ids. In this case, you wouldn't lock down the revisions unless you had a specific need for a particular revision. Referencing a branch with the external probably makes as much or more sense than explicitly tagging the external revision. What about foreign repositories? The choices there are to import them into your own repository. Leaving it as a foreign external, I would think you want to lock down the revision. From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi065.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <77ja3cF1i4fh2U1@mid.individual.net> Subject: Re: Version Control for VHDL Project Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi065.nbdc.sbc.com 1242865037 ST000 99.184.242.197 (Wed, 20 May 2009 20:17:17 EDT) NNTP-Posting-Date: Wed, 20 May 2009 20:17:17 EDT Organization: at&t http://my.att.net/ X-UserInfo1: T[OER[ODPRUORRPXIZOD]_\@VR]^@B@MCPWZKB]MPXHJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 20 May 2009 20:17:14 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1204 "Mike Treseler" wrote in message news:77ja3cF1i4fh2U1@mid.individual.net... >> It was a wise rule: NO FREAKING >> EXTERNALS. I've reaffirmed it with the thought exercise. > > *Me too*, at least until I understand their upside. > One upside is that you don't have to try to remember on which project you used 'widget' where you had made some improvement over the last time you used 'widget'. All the reusable components would be in one place, a new design project would simply svn_external reference them to get them into the new design and then add new code for whatever is unique to the new design. That way you don't have multiple similar (or the same) versions of 'widget' around, just one, presumably the 'best' in that it has been refined over time with various improvements. The huge archive downside though makes svn_external something to be extremely careful about ever using. The headache of manual revision specification (and the potential to overlook at least one of them) is just stupid. KJ From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!v23g2000pro.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Are all these claims in VHDL correct? Date: Wed, 20 May 2009 18:50:56 -0700 (PDT) Organization: http://groups.google.com Lines: 109 Message-ID: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242870656 18044 127.0.0.1 (21 May 2009 01:50:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 01:50:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v23g2000pro.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3515 comp.lang.vhdl:1205 Hi, I am trying to claim the following things in VHDL in some written materials, and want to know if they are absolute correct practically based on Xilinx FPGA implementations, not theoretically on ModelSim simulations. signal X : unsigned(63 downto 0); signal X0 : unsigned(63 downto 0); signal X1 : unsigned(63 downto 0); signal X2 : unsigned(63 downto 0); signal X3 : unsigned(63 downto 0); signal A1 : std_logic; signal A2 : std_logic; signal A3 : std_logic; 1. The following M1 and M2 process code implementations are the same: M1 : process(..) begin X <= X0; if A1 = '1' then X <= X1; if A2 = '1' then X <= X2; elsif A3 = '1' then X <= X3; end if; end if; end process; M2 : process(..) begin if A1 = '1' then if A2 = '1' then X <= X2; elsif A3 = '1' then X <= X3; else X <= X1; end if; else X <= X0; end if; end process; 2. The following M3 to M5 process code implementations are the same: M3 : process(A1) begin if A1 = '1' then X <= X1; else null; end if; end process; M4 : process(A1) begin if A1 = '1' then X <= X1; end if; end process; M5 : process(A1) begin if A1 = '1' then X <= X1; else X <= X; end if; end process; 3. The following M6 to M8 process code implementations are the same: M6 : process(CLK) begin if CLK'event and CLK = '1' then if A1 = '1' then X <= X1; else null; end if; end if; end process; M7 : process(CLK) begin if CLK'event and CLK = '1' then if A1 = '1' then X <= X1; end if; end if; end process; M8 : process(CLK) begin if CLK'event and CLK = '1' then if A1 = '1' then X <= X1; else X <= X; end if; end if; end process; Thank you. Weng From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi147.ffdc.sbc.com.POSTED!857c7983!not-for-mail From: Muzaffer Kal Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: GTKWave 3.2.1 for Windows is available Organization: DSPIA INC. http://www.dspia.com Message-ID: References: X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 11 NNTP-Posting-Host: 75.101.94.80 X-Complaints-To: abuse@prodigy.net X-Trace: flpi147.ffdc.sbc.com 1242872924 ST000 75.101.94.80 (Wed, 20 May 2009 22:28:44 EDT) NNTP-Posting-Date: Wed, 20 May 2009 22:28:44 EDT X-UserInfo1: Q[R_PJSCOHU[ST@[@JK@NFXBWR\HPCTL@XT^OBPLAH[\BPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Wed, 20 May 2009 19:35:55 -0700 Xref: news.eternal-september.org comp.arch.fpga:3517 comp.lang.verilog:426 comp.lang.vhdl:1206 Hi everyone, the latest version of GTKWave (3.2.1) windows binary is available at here: http://www.dspia.com/gtkwave.html Thanks to Tony now we have a way to start GTKWave without a file and open one later. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 21 May 2009 02:43:34 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 08:40:55 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 170 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-M0gf/P9+Kamh38kNZo4cr0s1Tqkjj6f8+BvSEu8BSsU/m+ieKxYuzUYSF3amRl8FmfI62VAPWNfWB3Y!DHeFQS9w7IghicS068ITNDNq59KwYN6b0+/d0qagiHqkpgNqDdeKt4aKxgKpJkNP6Y+mmFxNaelf!2yzu1/SoCstSUowA X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 5508 Xref: news.eternal-september.org comp.arch.fpga:3528 comp.lang.vhdl:1207 On Wed, 20 May 2009 18:50:56 -0700 (PDT), Weng Tianxiang wrote: >I am trying to claim the following things in VHDL in >some written materials, and want to know if they are absolute >correct practically based on Xilinx FPGA implementations, not >theoretically on ModelSim simulations. That's a very strange way to look at it. The VHDL language is defined by its simulation semantics. Synthesis creates hardware that conforms to a certain (very useful) subset of those behaviours. It makes no sense to say that your understanding of VHDL is "absolutely correct... based on FPGA implementations". On the other hand, you CAN reasonably ask "do these two pieces of VHDL code imply identical synthesised hardware?". >signal X : unsigned(63 downto 0); >signal X0 : unsigned(63 downto 0); >signal X1 : unsigned(63 downto 0); >signal X2 : unsigned(63 downto 0); >signal X3 : unsigned(63 downto 0); >signal A1 : std_logic; >signal A2 : std_logic; >signal A3 : std_logic; > >1. The following M1 and M2 process code implementations are the same: > >M1 : process(..) >begin > X <= X0; > if A1 = '1' then > X <= X1; > if A2 = '1' then > X <= X2; > elsif A3 = '1' then > X <= X3; > end if; > end if; >end process; > >M2 : process(..) >begin > if A1 = '1' then > if A2 = '1' then > X <= X2; > elsif A3 = '1' then > X <= X3; > else > X <= X1; > end if; > else > X <= X0; > end if; >end process; Well... single-stepping through the two pieces of code in a simulator will of course show slightly different sequences of activity, but I agree that the externally-visible results of the two processes should be identical. It is impossible to tell the difference between Y <= A; Y <= B; -- completely replaces assignment Y<=A and Y <= B; (unless the evaluation of expression A has side-effects, of course). ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >2. The following M3 to M5 process code implementations are the same: > >M3 : process(A1) >begin > if A1 = '1' then > X <= X1; > else > null; > end if; >end process; > >M4 : process(A1) >begin > if A1 = '1' then > X <= X1; > end if; >end process; I agree that these two are identical in every meaningful way. "null;" really does nothing. >M5 : process(A1) >begin > if A1 = '1' then > X <= X1; > else > X <= X; > end if; >end process; No, this is not the same. In M5 but not in M4, when A1 transitions to a value that is not '1', signal X is written; there will be no value-change on X as a result, for sure, but there *is* a transaction on X and that could be detected, outside the process, with the 'transaction, 'active or 'quiet attributes. None of the processes M3 to M5 follow any conventional synthesis template. If you had included X1 in the sensitivity list, they would all be perfectly good descriptions of a transparent latch. If you had rewritten the condition as "if rising_edge(A1)" they would all be perfectly good descriptions of a register. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >3. The following M6 to M8 process code implementations are the same: > >M6 : process(CLK) >begin > if CLK'event and CLK = '1' then > if A1 = '1' then > X <= X1; > else > null; > end if; > end if; >end process; > >M7 : process(CLK) >begin > if CLK'event and CLK = '1' then > if A1 = '1' then > X <= X1; > end if; > end if; >end process; M6 and M7 are completely identical in behaviour, yes. >M8 : process(CLK) >begin > if CLK'event and CLK = '1' then > if A1 = '1' then > X <= X1; > else > X <= X; > end if; > end if; >end process; Same discussion as for M5, above. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:47 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000vba.googlegroups.com!not-for-mail From: "colin_toogood@yahoo.com" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design Date: Thu, 21 May 2009 01:15:55 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: NNTP-Posting-Host: 81.149.223.5 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242893755 25553 127.0.0.1 (21 May 2009 08:15:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 08:15:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000vba.googlegroups.com; posting-host=81.149.223.5; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.65 Safari/525.19,gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Clearswift Web Policy Engine Xref: news.eternal-september.org comp.lang.vhdl:1208 comp.arch.fpga:3529 I created an account and downloaded it. Then I noticed the one month license and no pricing. Perhaps you might post again when you have decided whether I can afford it at which point I will try it. Your website promises many of the things I've always wanted from an editor. Colin From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 09:46:57 +0100 Organization: A noiseless patient Spider Lines: 81 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Trace: news.eternal-september.org U2FsdGVkX1+wjXSPkNKo3rnMPHbgaIvr7RdWTjYwzdWzvc0E7kxH8bM0oY9EqPXRLvcQkvyelBeBJv8uNAQcsnB6Ythcevrs46JueNdQPCeQLZrFruUQYPldn8BXsaO4zUJF3zix6TkkHcICcXk8aA== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Thu, 21 May 2009 08:47:23 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1/u59eSqVwWvQZsVNAbCj2flk5j4qRVIyQ= Cancel-Lock: sha1:9Y7mLBbNGaXOzissgzGXYO126B4= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.arch.fpga:3532 comp.lang.vhdl:1209 "Jonathan Bromley" wrote in message news:ri0a15dqak38clq3j8uuvb2tl6lusob9lu@4ax.com... >> >>M4 : process(A1) >>begin >> if A1 = '1' then >> X <= X1; >> end if; >>end process; > > I agree that these two are identical in every meaningful way. > "null;" really does nothing. > >>M5 : process(A1) >>begin >> if A1 = '1' then >> X <= X1; >> else >> X <= X; >> end if; >>end process; > > No, this is not the same. In M5 but not in M4, when > A1 transitions to a value that is not '1', signal X > is written; there will be no value-change on X as a > result, for sure, but there *is* a transaction on X > and that could be detected, outside the process, > with the 'transaction, 'active or 'quiet attributes. > > None of the processes M3 to M5 follow any conventional > synthesis template. If you had included X1 in the > sensitivity list, they would all be perfectly good > descriptions of a transparent latch. If you had > rewritten the condition as "if rising_edge(A1)" they > would all be perfectly good descriptions of a register. > >> >>M7 : process(CLK) >>begin >> if CLK'event and CLK = '1' then >> if A1 = '1' then >> X <= X1; >> end if; >> end if; >>end process; > > M6 and M7 are completely identical in behaviour, yes. > >>M8 : process(CLK) >>begin >> if CLK'event and CLK = '1' then >> if A1 = '1' then >> X <= X1; >> else >> X <= X; >> end if; >> end if; >>end process; > > Same discussion as for M5, above. > I'm missing the point here. The sensitivity list for M4 and M5 only includes A1, so any change in X1 doesn't propagate through to X in either case. Also, are you suggesting that an X <= X; would be seen as a transaction within a sensitivity list? M9: process (X) begin if X = '1' then Y <= Y1; end if; end process; where Y will take on the value of Y1, despite no change in X? From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 21 May 2009 03:58:52 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 09:56:13 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 56 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rHEooxmt3vFNPWTgylX6Fyw02GuN9+GJldQFHWOsDrOxVy/QzCrFnhm1oSu67VX1XKgq8Bn6/Cj56uI!bF5HnaR5/m5B1/DErQ6fLM0pxkkTji0eJlutR5DoRfsP/ZU0zX2k5mAaLO80czxCYia0tgwzpCZY!RUOWXLJpVTtUFiD5 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3506 Xref: news.eternal-september.org comp.arch.fpga:3533 comp.lang.vhdl:1210 On Thu, 21 May 2009 09:46:57 +0100, "Fredxx" wrote: >> None of the processes M3 to M5 follow any conventional >> synthesis template. If you had included X1 in the >> sensitivity list, they would all be perfectly good >> descriptions of a transparent latch. If you had >> rewritten the condition as "if rising_edge(A1)" they >> would all be perfectly good descriptions of a register. [...] >I'm missing the point here. The sensitivity list for M4 and M5 only >includes A1, so any change in X1 doesn't propagate through to X in either Right. So the description is not a piece of synthesisable hardware; it's neither a latch, nor a register, nor a combinational function. I agree that the externally observable simulation behaviour would be the same for all those examples, apart from the 'transaction thing I mentioned. But it's not very useful. >Also, are you suggesting that an X <= X; would be seen as a transaction >within a sensitivity list? No. Be careful about the terminology; sensitivity lists see EVENTS, i.e. value-changes, on a signal; there is of course no such event as a result of X<=X. However, there is a TRANSACTION, an attempt to update X. You can't ordinarily see transactions in VHDL, but you can detect them using the built-in attributes I mentioned. >M9: process (X) >begin > if X = '1' then > Y <= Y1; > end if; >end process; > >where Y will take on the value of Y1, despite no change in X? Sorry, I don't see what you're asking here. If there's no change in X's value then the process won't run and Y won't update. In a real hardware transparent latch, you DO expect Y to follow the input Y1 if the enable X is asserted; you can easily get this by including both X and Y1 in the sensitivity list, and that gives you a good synthesisable description of a transparent latch. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 10:09:26 +0100 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Trace: news.eternal-september.org U2FsdGVkX18ATnanb2sX6pBmIkQo89QDgtDMVjRGoAvCnxNIshFs3eTqbAPbeVJfox49P//02U8ybDurhETxq7idrsycZQno6ugVl2aS4sRrZaE2Sf9BOlCL9elxeQlENFp37zHc2q9KBSpMGek0CA== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Thu, 21 May 2009 09:09:48 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX19TcKmsLorQ19p1mfPGN4NDAwbAE6jc54I= Cancel-Lock: sha1:9IngcgbLRXNdHEMLK9MYgbvo9/o= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.arch.fpga:3534 comp.lang.vhdl:1211 "Jonathan Bromley" wrote in message news:g85a15lp0jd5kap4u0n5rlbq82k2l3mbh1@4ax.com... > On Thu, 21 May 2009 09:46:57 +0100, "Fredxx" wrote: > >>> None of the processes M3 to M5 follow any conventional >>> synthesis template. If you had included X1 in the >>> sensitivity list, they would all be perfectly good >>> descriptions of a transparent latch. If you had >>> rewritten the condition as "if rising_edge(A1)" they >>> would all be perfectly good descriptions of a register. > [...] >>I'm missing the point here. The sensitivity list for M4 and M5 only >>includes A1, so any change in X1 doesn't propagate through to X in either > > Right. So the description is not a piece of synthesisable > hardware; it's neither a latch, nor a register, nor a > combinational function. I agree that the externally > observable simulation behaviour would be the same for > all those examples, apart from the 'transaction thing > I mentioned. But it's not very useful. > >>Also, are you suggesting that an X <= X; would be seen as a transaction >>within a sensitivity list? > > No. Be careful about the terminology; sensitivity lists see > EVENTS, i.e. value-changes, on a signal; there is of course > no such event as a result of X<=X. However, there is a > TRANSACTION, an attempt to update X. You can't ordinarily > see transactions in VHDL, but you can detect them using > the built-in attributes I mentioned. > It is synthsisable but perhaps not tgive the intended result. In essence an event on A1 and A1 = 1, would cause the value X1 to be latched into X. In both cases? >>M9: process (X) >>begin >> if X = '1' then >> Y <= Y1; >> end if; >>end process; >> >>where Y will take on the value of Y1, despite no change in X? > > Sorry, I don't see what you're asking here. If there's no change > in X's value then the process won't run and Y won't update. > In a real hardware transparent latch, you DO expect Y to follow > the input Y1 if the enable X is asserted; you can easily get this > by including both X and Y1 in the sensitivity list, and that gives > you a good synthesisable description of a transparent latch. That was my point, how would a transaction on X be "seen"? I thought VHDL was all about events. From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!21g2000vbk.googlegroups.com!not-for-mail From: Beware Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Thu, 21 May 2009 02:17:17 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <84d739ed-5ef5-4bff-b150-18ad72ae5490@21g2000vbk.googlegroups.com> References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <1eb63a60-fa98-4626-b3d6-29e754889558@r13g2000vbr.googlegroups.com> <0aa866d0-a3e7-421a-9a03-be1de70bff55@b1g2000vbc.googlegroups.com> NNTP-Posting-Host: 88.160.144.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242897437 9006 127.0.0.1 (21 May 2009 09:17:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 09:17:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 21g2000vbk.googlegroups.com; posting-host=88.160.144.1; posting-account=vEyO1woAAACo2vvLkqB78k2NdTQCDYAm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042523 Ubuntu/9.04 (jaunty) Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1212 On May 20, 9:09=A0pm, Andy wrote: > GHDL is just complaining that you have not compiled anything for the > multiplier component to bind to. Compile the entity/arch for > multiplier with the same signature (name and port list) and it should > get rid of the warning. If the entity signature is not the same as > that of the component, then you will have to use a configuration to > bind the entity/arch to the component instantiation. > > You can also directly instantiate entity/architectures under vhdl'93 > and later: > > label: entity work.entity_name(architecture_name)... > > The architecture name is optional. > > Beware, this will result in errors (not warnings) if you have not > already compiled the entity (and architecture if the instantiation > specified it). > > I use entity instantiation for stuff that I write, but components for > primitives from other libraries, especially when synthesis recognizes > the component automatically, but simulation needs to compile/link the > model for the primitive. > > Andy Hi, Sorry but i still don't understand what i do wrong. When i write the instancation of "multiplieur" in my testbench file, i use the same name of the "multiplieur" entity and the same list port. From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 21 May 2009 11:22:24 +0200 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: <4a151d23$0$2850$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: d0c56027.news.skynet.be X-Trace: 1242897700 news.skynet.be 2850 81.240.3.28:59361 X-Complaints-To: usenet-abuse@skynet.be Xref: news.eternal-september.org comp.lang.vhdl:1213 comp.arch.fpga:3535 colin_toogood@yahoo.com wrote: > I created an account and downloaded it. Then I noticed the one month > license and no pricing. Perhaps you might post again when you have > decided whether I can afford it at which point I will try it. Your > website promises many of the things I've always wanted from an editor. The beta program conditions are explained here: http://www.sigasi.com/betaconditions Jan From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.mixmin.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "Nial Stewart" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Sigasi Public Beta: future of VHDL design Date: Thu, 21 May 2009 10:37:10 +0100 Lines: 19 Message-ID: <77klmmF1h9gfqU1@mid.individual.net> References: X-Trace: individual.net 8IeNGELr0S63D9RCogod4wOC3wIw3J/z1LvIM5k5bnyYpHlV/J Cancel-Lock: sha1:p6zQv1y8SgoOCGVQqutPflbl0Rs= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-RFC2646: Format=Flowed; Original Xref: news.eternal-september.org comp.lang.vhdl:1214 comp.arch.fpga:3538 wrote in message news:ab4b2e35-883a-4ae3-bd3d-e7e8bddae345@l32g2000vba.googlegroups.com... >I created an account and downloaded it. Then I noticed the one month > license and no pricing. Perhaps you might post again when you have > decided whether I can afford it at which point I will try it. Your > website promises many of the things I've always wanted from an editor. > Colin Colin, If you email them they'll give you an outline of what they're thinking about pricing wise. I think they should publish this. Niall From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!news.motzarella.org!eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 21 May 2009 06:23:45 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 12:21:06 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 66 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Onjn90ae3yS+5sfhX+09O8T15yHo0/7kfFEwVPY1rvg4Vl8BGWOZ/DK9LEPKU/LwW/ha0CtrrGi64WI!+sYDaoBBXAELXpRnamYXbNv8goYKe3O4nZ5Hu5v1uSxR/hiyv2tUMJY1ZHtfPzEodE2esOvxjoE+!fCjPqX1Wg4hsmnCz X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3640 Xref: news.eternal-september.org comp.arch.fpga:3542 comp.lang.vhdl:1215 On Thu, 21 May 2009 10:09:26 +0100, "Fredxx" wrote: [regarding this example] M4 : process(A1) begin if A1 = '1' then X <= X1; end if; end process; >It is synthsisable but perhaps not tgive the intended result. >In essence an event on A1 and A1 = 1, would cause the value >X1 to be latched into X. I'm confused. I already explained, with justification, why it's not correctly synthesisable, and then you tell me it is... Here's why that is BAD code for synthesis: - The description, as you say, implies latching only on the rising edge of A1. Like a D flop. - But there is no "if A1'event" or "if rising_edge(A1)" in the process. So it doesn't match the standard clocked synthesis template. In the synth tool I tried just now (Mentor Precision) I got a warning about precisely this, telling me that there might be synthesis/simulation mismatches (there will). And it created a transparent latch, because - as usual - for any non-clocked process, synthesis will assume a complete sensitivity list. Personally I would prefer it if synthesis tools were to reject the code as an error, but that's not what happens; instead you get hardware whose behaviour doesn't match the simulation. I'm fairly sure that almost all mainstream synthesis tools behave in a similar way on this example, but I can't be bothered trying them all because it's code that should not be synthesised. >In both cases? I already stated, correctly and with explanation, that Weng's processes M4 and M5 have identical behaviour in simulation. Both of them are inappropriate for synthesis. >how would a transaction on X be "seen"? I thought VHDL >was all about events. As I already pointed out, you can sense transactions in simulation by using the 'transaction, 'active and 'quiet built-in attributes. VHDL transactions have no use in synthesis. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j12g2000vbl.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Vhdl beginner - Signal assignment doesn't work Date: Thu, 21 May 2009 06:15:22 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: References: <07936bec-9098-4fe7-afb8-992d1c0cd9dc@b1g2000vbc.googlegroups.com> <1eb63a60-fa98-4626-b3d6-29e754889558@r13g2000vbr.googlegroups.com> <0aa866d0-a3e7-421a-9a03-be1de70bff55@b1g2000vbc.googlegroups.com> <84d739ed-5ef5-4bff-b150-18ad72ae5490@21g2000vbk.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242911722 16877 127.0.0.1 (21 May 2009 13:15:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 13:15:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j12g2000vbl.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1216 On May 21, 4:17=A0am, Beware wrote: > On May 20, 9:09=A0pm, Andy wrote: > > > > > > > GHDL is just complaining that you have not compiled anything for the > > multiplier component to bind to. Compile the entity/arch for > > multiplier with the same signature (name and port list) and it should > > get rid of the warning. If the entity signature is not the same as > > that of the component, then you will have to use a configuration to > > bind the entity/arch to the component instantiation. > > > You can also directly instantiate entity/architectures under vhdl'93 > > and later: > > > label: entity work.entity_name(architecture_name)... > > > The architecture name is optional. > > > Beware, this will result in errors (not warnings) if you have not > > already compiled the entity (and architecture if the instantiation > > specified it). > > > I use entity instantiation for stuff that I write, but components for > > primitives from other libraries, especially when synthesis recognizes > > the component automatically, but simulation needs to compile/link the > > model for the primitive. > > > Andy > > Hi, > > Sorry but i still don't understand what i do wrong. > When i write the instancation of "multiplieur" in my testbench file, i > use the same name of the "multiplieur" entity and the same list port.- Hi= de quoted text - > > - Show quoted text - I think your instantiation is correct, you just have not yet compiled an entity and/or architecture for the multiplier itself. There isn't a model for multiplier yet that the simulator can bind to your component instance. Andy From newsfish@newsfish Wed Aug 19 13:24:48 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!gegeweb.org!news.glorb.com!postnews.google.com!o20g2000vbh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 06:49:50 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1242913790 26296 127.0.0.1 (21 May 2009 13:49:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 13:49:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o20g2000vbh.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3545 comp.lang.vhdl:1217 I think we can summarize... M1 and M2 will synthesize to identical combinatorial circuits. There may be warnings about synthesis/simulations mis-matches if the sensitivity lists are not complete. M3, M4 and M5 will synthesize to identical combinatorial circuits, with a warning on the incomplete sensitivity list. M6 and M7 will synthesize to identical sequential circuits (D-flop with clk enable). M8 will synthesize to a sequential circuit with identical behavior (on a clock cycle basis) to that of M6 and M7, but the synthesis tool may try to build a feedback mux instead of using the built-in clk enable on the register. Different synthesis tools may handle this differently. It should be noted that if X were a port of mode OUT (or an alias thereof), then the processes that attempt to read X (M5 & M8) would not synthesize at all. It should also be noted that of M1 and M2, M1 is preferable for one significant reason: The default assignemnt to X up front makes it very easy to verify that M1 will not result in a latch. It is more difficult to verify that M2 will not result in a latch. Andy From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 08:56:15 -0700 (PDT) Organization: http://groups.google.com Lines: 254 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242921376 14890 127.0.0.1 (21 May 2009 15:56:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 15:56:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3555 comp.lang.vhdl:1218 On May 21, 12:40=A0am, Jonathan Bromley wrote: > On Wed, 20 May 2009 18:50:56 -0700 (PDT), Weng Tianxiang wrote: > >I am trying to claim the following things in VHDL in > >some written materials, and want to know if they are absolute > >correct practically based on Xilinx FPGA implementations, not > >theoretically on ModelSim simulations. > > That's a very strange way to look at it. =A0The VHDL language > is defined by its simulation semantics. =A0Synthesis creates > hardware that conforms to a certain (very useful) subset > of those behaviours. =A0It makes no sense to say that your > understanding of VHDL is "absolutely correct... based on > FPGA implementations". > > On the other hand, you CAN reasonably ask "do these two > pieces of VHDL code imply identical synthesised hardware?". > > > > > > >signal =A0 X =A0: unsigned(63 downto 0); > >signal =A0 X0 : unsigned(63 downto 0); > >signal =A0 X1 : unsigned(63 downto 0); > >signal =A0 X2 : unsigned(63 downto 0); > >signal =A0 X3 : unsigned(63 downto 0); > >signal =A0 A1 : std_logic; > >signal =A0 A2 : std_logic; > >signal =A0 A3 : std_logic; > > >1. The following M1 and M2 process code implementations are the same: > > >M1 : process(..) > >begin > > =A0 X <=3D X0; > > =A0 if A1 =3D '1' then > > =A0 =A0 =A0X <=3D X1; > > =A0 =A0 =A0if A2 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X2; > > =A0 =A0 =A0elsif A3 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X3; > > =A0 =A0 =A0end if; > > =A0 end if; > >end process; > > >M2 : process(..) > >begin > > =A0 if A1 =3D '1' then > > =A0 =A0 =A0if A2 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X2; > > =A0 =A0 =A0elsif A3 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X3; > > =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 X <=3D X1; > > =A0 =A0 =A0end if; > > =A0 else > > =A0 =A0 =A0X <=3D X0; > > =A0 end if; > >end process; > > Well... single-stepping through the two pieces of > code in a simulator will of course show slightly > different sequences of activity, but I agree that > the externally-visible results of the two processes > should be identical. =A0It is impossible to tell the > difference between > > =A0 Y <=3D A; > =A0 Y <=3D B; -- completely replaces assignment Y<=3DA > > and > > =A0 Y <=3D B; > > (unless the evaluation of expression A has side-effects, > of course). > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > >2. The following M3 to M5 process code implementations are the same: > > >M3 : process(A1) > >begin > > =A0 if A1 =3D '1' then > > =A0 =A0 =A0X <=3D X1; > > =A0 else > > =A0 =A0 =A0null; > > =A0 end if; > >end process; > > >M4 : process(A1) > >begin > > =A0 if A1 =3D '1' then > > =A0 =A0 =A0X <=3D X1; > > =A0 end if; > >end process; > > I agree that these two are identical in every meaningful way. > "null;" really does nothing. > > >M5 : process(A1) > >begin > > =A0 if A1 =3D '1' then > > =A0 =A0 =A0X <=3D X1; > > =A0 else > > =A0 =A0 =A0X <=3D X; > > =A0 end if; > >end process; > > No, this is not the same. =A0In M5 but not in M4, when > A1 transitions to a value that is not '1', signal X > is written; there will be no value-change on X as a > result, for sure, but there *is* a transaction on X > and that could be detected, outside the process, > with the 'transaction, 'active or 'quiet attributes. > > None of the processes M3 to M5 follow any conventional > synthesis template. =A0If you had included X1 in the > sensitivity list, they would all be perfectly good > descriptions of a transparent latch. =A0If you had > rewritten the condition as "if rising_edge(A1)" they > would all be perfectly good descriptions of a register. > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > >3. The following M6 to M8 process code implementations are the same: > > >M6 : process(CLK) > >begin > > =A0 if CLK'event and CLK =3D '1' then > > =A0 =A0 =A0if A1 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X1; > > =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 null; > > =A0 =A0 =A0end if; > > =A0 end if; > >end process; > > >M7 : process(CLK) > >begin > > =A0 if CLK'event and CLK =3D '1' then > > =A0 =A0 =A0if A1 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X1; > > =A0 =A0 =A0end if; > > =A0 end if; > >end process; > > M6 and M7 are completely identical in behaviour, yes. > > >M8 : process(CLK) > >begin > > =A0 if CLK'event and CLK =3D '1' then > > =A0 =A0 =A0if A1 =3D '1' then > > =A0 =A0 =A0 =A0 X <=3D X1; > > =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 X <=3D X; > > =A0 =A0 =A0end if; > > =A0 end if; > >end process; > > Same discussion as for M5, above. > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.- Hide quote= d text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Hi Jonathan, Once again I get your valuable comments. 1. "On the other hand, you CAN reasonably ask "do these two pieces of VHDL code imply identical synthesised hardware?". " Yes, you are right and I accept it. 2. >M5 : process(A1) >begin > if A1 =3D '1' then > X <=3D X1; > else > X <=3D X; > end if; >end process; No, this is not the same. In M5 but not in M4, when A1 transitions to a value that is not '1', signal X is written; there will be no value-change on X as a result, for sure, but there *is* a transaction on X and that could be detected, outside the process, with the 'transaction, 'active or 'quiet attributes. If M5 Xilinx implementation were carried out for M3 or M4, you couldn't tell there was a transaction on X, because it didn't generate a transaction information except it really happend internally. It may violate the true spirit of coding, but it doesn't hurt anybody and always gives the correct result. 3. I have to frankly admit that I have no hardware transparent latch in my mind. In all my designs, there are only two data signal types: register or combinational signal. Your comments bring me back some ideas about transparent latch: M9: process (X, Y1) begin if X =3D '1' then Y <=3D Y1; end if; end process; Does it mean: X is connected to the latch enable terminal and Y1 to data input terminal and Y is configured as a transparent latch? Thank you. Weng From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!postnews.google.com!q2g2000vbr.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.lang.vhdl Subject: Re: Quartus Inference Challenge Date: Thu, 21 May 2009 09:01:09 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: References: <014d146b-b8d0-4351-813d-2b074733af4b@z5g2000vba.googlegroups.com> <68b15058-d193-4a9c-ac73-fdb70bf1d2c2@l32g2000vba.googlegroups.com> <77ivrkF1hbdiiU1@mid.individual.net> NNTP-Posting-Host: 217.171.129.72 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1242921669 16059 127.0.0.1 (21 May 2009 16:01:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 May 2009 16:01:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbr.googlegroups.com; posting-host=217.171.129.72; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.65 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1219 On May 20, 7:18=A0pm, Mike Treseler wrote: > Tricky wrote: > > Yup, I can do that, but its not as efficient as the direct > > instantiation. > > But it is portable. > Does the instance use zero LUTs for the mux? > > =A0 =A0 =A0-- Mike Treseler Probly not. Good job he didn't want the write bus smaller width, and write before read! cheers jacko http://nibz.googlecode.com version G-spot From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 21 May 2009 11:47:04 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Thu, 21 May 2009 17:44:25 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-MBer3JvqNhDUKAFSKZTPUJlf+yjc/3l4FvptSTavK1QgOFu90RPzKwkq4kcrJawkkHKljRr6lu9/2oR!liIKy2L1dchgUjA7IaFTplwkfIhxcIUBdl1tPNGv09EFDDIGJeAsL0rGm1BoDyuB4vhjQJPZV1iv!JCO9jE3fyjVh0Mv2 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.arch.fpga:3562 comp.lang.vhdl:1220 On Thu, 21 May 2009 08:56:15 -0700 (PDT), Weng Tianxiang wrote: >If M5 Xilinx implementation were carried out for M3 or M4, you >couldn't tell there was a transaction on X, >because it didn't generate a transaction information except it really >happend internally. >It may violate the true spirit of coding, but it doesn't hurt anybody >and always gives the correct result. Yes, I completely agree. They are the same for synthesis, in every tool I have tried. >M9: process (X, Y1) >begin > if X = '1' then > Y <= Y1; > end if; >end process; > >Does it mean: >X is connected to the latch enable terminal and Y1 to data input >terminal and Y is configured as a transparent latch? Yes, exactly. It is a good description both for simulation and for synthesis. The problem, of course, is that many FPGAs do not have good latch primitives (except, maybe, on their I/O pads) and so you can get very strange hardware implementations that will cause trouble with static timing analysis. Regards -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!newsfeed.kpn.net!pfeed08.wxs.nl!plix.pl!newsfeed1.plix.pl!217.153.128.51.MISMATCH!nf1.ipartners.pl!ipartners.pl!news.internetia.pl!not-for-mail From: donald Newsgroups: comp.lang.vhdl Subject: Re: "Independent" Simulation of Xilinx Project Date: Fri, 22 May 2009 10:13:52 +0200 Organization: tuskin Lines: 38 Message-ID: References: <57569307-db64-42bd-9357-50bf82df46df@o11g2000yql.googlegroups.com> NNTP-Posting-Host: 87-205-226-123.adsl.inetia.pl Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Trace: mx1.internetia.pl 1242980646 15227 87.205.226.123 (22 May 2009 08:24:06 GMT) X-Complaints-To: abuse@inetia.pl NNTP-Posting-Date: Fri, 22 May 2009 08:24:06 +0000 (UTC) X-Tech-Contact: usenet@internetia.pl User-Agent: MicroPlanet-Gravity/2.80.0 X-Server-Info: http://www.internetia.pl/news/ Xref: news.eternal-september.org comp.lang.vhdl:1221 In article <57569307-db64-42bd-9357- 50bf82df46df@o11g2000yql.googlegroups.com>, goouse@twinmail.de says... test > > On 12 Mrz., 16:33, russ wrote: > > We are doing a simple pld using Xilinx ISE 9.2i. The project began with > > 9.2i and must be finished with 9.2i. > > > > We are working under DO-254 and need to do either tool qualification or > > independent verification and validation with another tool set. GHDL and > > GTKWave have been chosen as the second tool set. But the customer > > objects that we are still using the Xilinx VITAL, primsim, etc., libraries. > > > > Is there an independent implementation of these libraries for GHDL? > > I've googled and got lots of links, but sorting through them hasn't > > revealed much yet. > > > > Thanks > > Hi russ, > maybe you can point out to your customer, that libraries are part of > the source code, not of the simulator tools. > The mentioned libs are a description of the hardware you are using, > and therefore as unique as your own source code. > Or do you have multiple versions of your sources (e.g. one in vhdl, > and another in verilog)? > Well, the libs are also available in two HDLs, so you could do > multilingual cross-simulation. > e.g. vhdl soure with vhdl lib , > verilog source with vhdl lib, > vhdl source with verilog lib, > verilog source with verilog lib > > > Have a nice simulation > Eilert From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!pe1.news.blueyonder.co.uk!blueyonder!text.news.virginmedia.com!53ab2750!not-for-mail From: Dave Farrance Newsgroups: comp.lang.vhdl Subject: Re: SPAM: Why are we getting all the spam ?? Organization: Farry's Pad Message-ID: References: X-Newsreader: Forte Agent on Wine 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 14 Date: Fri, 22 May 2009 08:46:10 GMT NNTP-Posting-Host: 92.233.40.23 X-Complaints-To: http://netreport.virginmedia.com X-Trace: text.news.virginmedia.com 1242981970 92.233.40.23 (Fri, 22 May 2009 09:46:10 BST) NNTP-Posting-Date: Fri, 22 May 2009 09:46:10 BST Xref: news.eternal-september.org comp.lang.vhdl:1222 "David Binnie" wrote: > Google groups seem to have let a captcha-cracking spam-botnet slip beyond their control for the moment since it hits them from multiple IPs. Also readnews.com is spammer friendly due to rubbish security which allows a forged NNTP-Posting-Host, forged preloaded path, and forged abuse address (it's not really Usenet Monster) -- and their claims to have fixed the problem are demonstrably false for now. -- Dave Farrance From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Followup-To: comp.arch.fpga Date: Fri, 22 May 2009 11:57:36 +0100 Organization: TRW Conekt Lines: 25 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 5y65PGq3M1z3dhEwH4Z+2QOfluEah/yQgdcAmD/MhLoB4zx0s= Cancel-Lock: sha1:IWEti9ftkgN4sb+wV00VV5BA/zY= sha1:H2McuA4AywxuDrvg5NCkoqwPH/w= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: news.eternal-september.org comp.arch.fpga:3580 comp.lang.vhdl:1223 Jonathan Bromley writes: > Yes, exactly. It is a good description both for simulation > and for synthesis. The problem, of course, is that many > FPGAs do not have good latch primitives (except, maybe, on > their I/O pads) and so you can get very strange hardware > implementations that will cause trouble with static > timing analysis. Hi Jonathan, I noticed whilst delving with FPGA editor into Xilinx devices that there is a latch option within the flipflop block - have you ever used them? Will synth tools map to them do you know? As an aside - the Virtex-5 version of Microblaze has 3 latches buried deep inside it... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!aioe.org!news.glorb.com!news2.glorb.com!news-in-01.newsfeed.easynews.com!easynews!core-easynews-01!easynews.com!en-nntp-03.dc1.easynews.com.POSTED!not-for-mail From: Rich Webb Newsgroups: comp.lang.vhdl Subject: Re: SPAM: Why are we getting all the spam ?? Organization: Line Eater Memorial Fund Message-ID: References: X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hamster-Pg/1.25.2.0 X-Antivirus: avast! (VPS 090521-0, 05/21/2009), Outbound message X-Antivirus-Status: Clean Lines: 35 X-Complaints-To: abuse@easynews.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 22 May 2009 08:28:06 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1224 On Fri, 22 May 2009 08:46:10 GMT, Dave Farrance wrote: >"David Binnie" wrote: > >> > >Google groups seem to have let a captcha-cracking spam-botnet slip beyond >their control for the moment since it hits them from multiple IPs. > >Also readnews.com is spammer friendly due to rubbish security which allows >a forged NNTP-Posting-Host, forged preloaded path, and forged abuse >address (it's not really Usenet Monster) -- and their claims to have fixed >the problem are demonstrably false for now. One option to de-spam your feed is to run your own feed. There are several free apps out there that can be setup as mini-newsservers on your PC, to which you then connect via the loopback IP (127.0.0.1:119). The benefit of this is that the local server has access to all header lines and the entire body, so it's easy to set rules that drop any posts with an HTTP link to the site the spammer is flogging. Dropping by body content means that it doesn't matter which IP they come in from or what account they use; it all goes into the bit-bucket. On the downside, that does mean that one's machine is downloading all traffic in the groups that one follows. That's not so much of an issue for most text groups but is something to be aware of. http://improve-usenet.org/ has info on several local servers. I use Hamster but mostly because it was the one I tried first and it meets my needs. NewsProxy also seems to be pretty popular. -- Rich Webb Norfolk, VA From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!postnews.google.com!e23g2000vbe.googlegroups.com!not-for-mail From: Amal Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Subject: SPAM? Date: Fri, 22 May 2009 06:47:03 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 142.46.198.27 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243000023 2723 127.0.0.1 (22 May 2009 13:47:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 May 2009 13:47:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e23g2000vbe.googlegroups.com; posting-host=142.46.198.27; posting-account=aaW8HAkAAABqrMdJYSf-acWh2T9ofAYm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.verilog:433 comp.lang.vhdl:1225 comp.arch.fpga:3583 It is weird that these newsgroups are getting swamped with SPAM recently!? I wonder if Google or whoever takes care of these newsgroups can do a better job of filtering or deleting them? -- Amal From newsfish@newsfish Wed Aug 19 13:24:49 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!g22g2000pra.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Fri, 22 May 2009 06:52:40 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243000360 32568 127.0.0.1 (22 May 2009 13:52:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 May 2009 13:52:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g22g2000pra.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3584 comp.lang.vhdl:1226 On May 21, 9:44=A0am, Jonathan Bromley wrote: > On Thu, 21 May 2009 08:56:15 -0700 (PDT), Weng Tianxiang wrote: > >If M5 Xilinx implementation were carried out for M3 or M4, you > >couldn't tell there was a transaction on X, > >because it didn't generate a transaction information except it really > >happend internally. > >It may violate the true spirit of coding, but it doesn't hurt anybody > >and always gives the correct result. > > Yes, I completely agree. =A0They are the same for synthesis, > in every tool I have tried. > > >M9: process (X, Y1) > >begin > > =A0 =A0if X =3D '1' then > > =A0 =A0 =A0 =A0Y <=3D Y1; > > =A0 =A0end if; > >end process; > > >Does it mean: > >X is connected to the latch enable terminal and Y1 to data input > >terminal and Y is configured as a transparent latch? > > Yes, exactly. =A0It is a good description both for simulation > and for synthesis. =A0The problem, of course, is that many > FPGAs do not have good latch primitives (except, maybe, on > their I/O pads) and so you can get very strange hardware > implementations that will cause trouble with static > timing analysis. > > Regards > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, Thank you for your answer. Have you received my email? Weng From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 22 May 2009 09:11:56 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Are all these claims in VHDL correct? Date: Fri, 22 May 2009 15:09:17 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <04c03556-0c1f-444a-93d5-17075513b5f7@v23g2000pro.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 18 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gDJSZZ530qFM6uVAw1B45TT8DrV4StdOrhR6PHGhOCG1KhGayrY4T3n3hNMcHxZot+RcfM1t1aBzNLH!Hap8p0Nu6wp7HyATXF3fO+Y1q8O3qSiPbh1rB8MV0mFaTfGrEVKqBSCpBwEWnFV/FuhkHjG7wWbu!gCVERwpSCPX901H1 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.arch.fpga:3585 comp.lang.vhdl:1227 On Fri, 22 May 2009 06:52:40 -0700 (PDT), Weng Tianxiang wrote: >Have you received my email? no, not yet. Just put the six-letter name of my company in place of MYCOMPANY in the email address. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Fri, 22 May 2009 16:47:18 +0200 Lines: 77 Message-ID: <87ab55xki1.fsf@harnisch.dyndns.org> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 8z1yiFUMTF2QA4JktADqCwhmOrJFXlNVAnXkGvpVJuCv/rOAhM Cancel-Lock: sha1:yGjvnWWT08bKGvNEzqOzbLuFhyI= sha1:5Ssc82fr2twlzuvak5eSVr78LPA= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:1228 Hi KJ Your "how-things-can-go-wrong" example is purely based on a work flow that the inventors of SVN explicitly advise against.[1] It isn't as hard as you make it look like. Here's my interpretation of what you really want: Rather than having to explicitly specifying revisions, Subversion ought to automatically remember the current(?) state of any externally referenced workspace. All metadata for doing this is available. How's the system supposed to behave in different scenarios and how do you specify the different behavior in each case? Project1 -+- src | +- data | `-- Project2 [external reference] 1. Update Project1 workspace without also updating Project2 workspace, because you really want to stick to one version of Project2 for the time being. 2. Update Project1 workspace including updating Project2 workspace to HEAD. 3. Update Project1 workspace including updating Project2 workspace to a specific revision. 4. When you checkout a new working copy of Project1, which version of Project2 will be used? HEAD, the one that was in the Project1 workspace that was last checked in or a specific revision? How much work is involved tracking the actual changes (not just looking at revision numbers) in Project2 since you last touched Project1? This would be necessary to gain confidence you actually want that release. Neither approach saves you from having to do this, but the argument that having to explicitly specify a revision number makes things considerably worse just doesn't hold any water. Staying on top of all this involves much more work than adding an explicit revision number to some text entry field. OIW, the extra effort you complain about is neglectible in projects big enough to make it worthwhile thinking about externals to begin with. At least the Subversion externals mechanism lets everyone have her way. I prefer that over tools that are trying to outsmart developers. Lastly, you had doubts about your fellow co-workers being able to properly maintain an externals property with revision numbers: > How much effort do you think is worth expending to cover the > omissions of others? How about a trivial pre-commit hook checking that all externals have explicit revision numbers. Which, BTW, could be -rHEAD, too. Which shows another benefit: When I check out a working copy and get Project2@HEAD I know that this is because sbdy explicitly wanted me to get this and not because the tool happens to behave this way by default. Best regards Marcus Footnotes: [1] "You should seriously consider using explicit revision numbers in all of your externals definitions. [...]" http://svnbook.red-bean.com/en/1.5/svn.advanced.externals.html -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi070.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <87ab55xki1.fsf@harnisch.dyndns.org> Subject: Re: Version Control for VHDL Project Lines: 139 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi070.nbdc.sbc.com 1243007891 ST000 99.184.242.197 (Fri, 22 May 2009 11:58:11 EDT) NNTP-Posting-Date: Fri, 22 May 2009 11:58:11 EDT Organization: at&t http://my.att.net/ X-UserInfo1: SCSYQN_@FS@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WHUQBKZQLYJX\_ITFD_KFVLUN[DOM_A_NSYNWPFWNS[XV\I]PZ@BQ[@CDQDPCL^FKCBIPC@KLGEZEFNMDYMKHRL_YYYGDSSODXYN@[\BK[LVTWI@AXGQCOA_SAH@TPD^\AL\RLGRFWEARBM Date: Fri, 22 May 2009 11:58:07 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1229 "Marcus Harnisch" wrote in message news:87ab55xki1.fsf@harnisch.dyndns.org... > Hi KJ > > Your "how-things-can-go-wrong" example is purely based on a work flow > that the inventors of SVN explicitly advise against.[1] Marcus, The workflow I suggested is an appropriate workflow if you have the following goals in mind: - You create modules intended to be reused, and... - Those reusable modules get enhanced or changed over time, and... - You need to be able to accurately reproduce all of the source files for a particular build sometime in the future, and... - You don't want to burden developers with a task that is easy to get wrong or be incomplete That SVN explicitly advises against it, simply indicates that those developers do not have the above list of criteria in mind when they use SVN. That's fine, they don't have to, others do though and other tools do support that workflow. One simple reason a supposedly 'reusable' module would change would simply be because when it was first created and used, not necessarily every optimization (or perhaps assertion checking) was put in. When you go to reuse the module in some later design, you might improve it. That improvement should propogate to all new users (i.e. checkouts from 'head') but should never propogate to archival tags, ever. Many developers don't meet the above criteria because - They don't create reusable modules, they start from scratch or copy paste snippets from here and there for every new design - They create perfect reusable modules that can not possibly be improved on - Never have to go back to investigate a problem peculiar to a particular design that is not the current head revision. - They have the time to burn having developers type in specific revision numbers for each and every module (hoping they get every one of them) THEN produce the final build for qualification testing. And have even more time to do this whole exercise again for the next build that occurs the next day... > It isn't as hard as you make it look like. > In what way did I make it look harder than it is? I think I described the steps accurately as well as describing the scenario and pressures that the developers would be under at the particular time and the repercussions down the road for making a bad move. > Here's my interpretation of what you really want: Rather than having > to explicitly specifying revisions, Subversion ought to automatically > remember the current(?) state of any externally referenced > workspace. No, Subversion doesn't need to remember anything. It just needs to be able to have a way to create a real archival tag. A reader of the Subversion manual can be led to believe that doing the 'svn copy' thing to create a tag does this, but in fact it doesn't if there is an svn_external with an unspecified revision anywhere in the design. I'm not saying that what Subversion has it wrong, just saying that it is missing a key piece if you meet the criteria I outlined above. Google for svncopy.pl, find their readme for more info on why you should be using that to create your archival tags and not the native 'svn copy' > All metadata for doing this is available. > That's possibly how svncopy.pl can perform it's magic. > How's the system supposed to behave in different scenarios and how do > you specify the different behavior in each case? > I think I described the different scenarios adequately in the previous postings. > > Neither approach saves you from having to do this, but the argument > that having to explicitly specify a revision number makes things > considerably worse just doesn't hold any water. > Unless there is some very good reason (and there can be), I don't think there should be any specific revision numbers called out for any svn_externals that are referenced in the trunk or any code intended to be merged back into the trunk in the future (i.e. any time you create new code). The time when specific revision numbers should be added is when you're creating an archival tag (i.e. a new build that will be tested). The adding of those specific revision numbers during the creation of the tag should be an automated process that replaces all unspecified revisions with the current (head) revision of whatever thing is being referenced by that svn_external (regardless of whether that thing is in the same physical repo or not). It should not be manual and subject to errors. If you have only one svn_external reference in your design, you can probably handle this without much trouble. If you're really reusing modules though, I'd wager that you have a lot more than that. Whether you think that is 'considerably worse' or not probably depends directly on whether or not you've ever been on the back end and had to recreate the source to investigate some problem on an old design. > Staying on top of all this involves much more work than adding an > explicit revision number to some text entry field. OIW, the extra > effort you complain about is neglectible in projects big enough to > make it worthwhile thinking about externals to begin with. > We'll just have to disagree on this point, 'specially when you're talking about big projects. > At least the Subversion externals mechanism lets everyone have her > way. I prefer that over tools that are trying to outsmart developers. > Again, I never asked SVN to outsmart anyone. I'm just saying that it doesn't natively provide a way to handle the workflow I mentioned (which is OK) but it also tends to mislead one into thinking that it is correctly archiving (which is not OK). The fact that svncopy.pl picks up the slack is great...now if someone could fix svncopy.pl so that IT always worked. > Lastly, you had doubts about your fellow co-workers being able to > properly maintain an externals property with revision numbers: > >> How much effort do you think is worth expending to cover the >> omissions of others? > > How about a trivial pre-commit hook checking that all externals have > explicit revision numbers. Which, BTW, could be -rHEAD, too. As I said, specific revision numbers for the most part should not be commited. It's when you want to create an archival copy (i.e. a new build to test) that they are needed. As for the pre-commit hook...so, if the tool can't do what it should be capable of doing, then create a nag message? We think differently on that point I guess. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 22 May 2009 11:52:35 -0500 Date: Fri, 22 May 2009 09:52:33 -0700 From: Rob Gaddi Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Subject: Re: SPAM? Message-ID: <20090522095233.00000a2a@unknown> References: Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 17 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-wKPJHDcNeyql/NNMp+MSV6tdtxBOwCTFB/IxhF+MXjK9YklHL3yPNoDrqB0KkM4eBE5saR5XuWVSAQu!HnAIPTI7ypGzd2l5zJCRF1Bv5esGaddgzYeuPuog7bId2E8cpoQebfEcSYcyvfnECA== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.verilog:434 comp.lang.vhdl:1230 comp.arch.fpga:3592 On Fri, 22 May 2009 06:47:03 -0700 (PDT) Amal wrote: > It is weird that these newsgroups are getting swamped with SPAM > recently!? I wonder if Google or whoever takes care of these > newsgroups can do a better job of filtering or deleting them? > > -- Amal The real problem at the moment seems to coming through usenetmonster. I tried using their X-Complaints-To, but they seem to not give a damn. So instead I now killfile anything coming through on their Message-ID. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!x29g2000prf.googlegroups.com!not-for-mail From: MadHatter7@myself.com Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Subject: Re: SPAM? Date: Fri, 22 May 2009 09:53:08 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: References: NNTP-Posting-Host: 132.190.112.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243011188 1273 127.0.0.1 (22 May 2009 16:53:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 May 2009 16:53:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x29g2000prf.googlegroups.com; posting-host=132.190.112.111; posting-account=C78jzQoAAACBtxZAbMWmM-rIg3SLw0qU User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.verilog:435 comp.lang.vhdl:1231 comp.arch.fpga:3593 On May 22, 6:47 am, Amal wrote: > It is weird that these newsgroups are getting swamped with SPAM > recently!? I wonder if Google or whoever takes care of these > newsgroups can do a better job of filtering or deleting them? > > -- Amal We will have peace in the Middle East before Google does anything about SPAM. There were a number of people that were manually shutting it off (by changing the subject line to minimize its annoyance), but the format fascists complained too much, and Google turned off their ability to shut it down. So long as we're all bottom-posting, all is good, right? From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: James Harris Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Subject: Re: SPAM? Date: Fri, 22 May 2009 10:27:15 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 87.113.208.92 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243013235 7685 127.0.0.1 (22 May 2009 17:27:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 May 2009 17:27:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=87.113.208.92; posting-account=Ss8wVAkAAADjaLf6nhKZFuysJxWaHI9Z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.8.1.20) Gecko/20081217 Firefox/2.0.0.20 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.verilog:436 comp.lang.vhdl:1232 comp.arch.fpga:3597 On 22 May, 17:53, MadHatt...@myself.com wrote: > On May 22, 6:47 am, Amal wrote: > > > It is weird that these newsgroups are getting swamped with SPAM > > recently!? I wonder if Google or whoever takes care of these > > newsgroups can do a better job of filtering or deleting them? > > > -- Amal > > We will have peace in the Middle East before Google does anything > about SPAM. Not so. I sent complaints to Google about the spam in alt.os.development and it appears that they have not just removed the sending accounts but also deleted the spam posts sent. Maybe their responsiveness is a per-newsgroup thing. Encouraged by their apparent response I have been reporting spams in other groups to them for the last couple of months. I can't say I've seen any definite response yet but I've not been checking for specific messages and ids. Reporting spam consumes a bit of time but I presume the reason why some groups are heavily hit with spam is that spammers have been allowed to get away with it. They tell their friends and before you know it the spam levels drown out the legitimate posts. The delay was about 6 weeks for alt.os.development. It may be worth many folks reporting spam posts for a while to see if that encourages a faster response. James From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newshub.sdsu.edu!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi061.nbdc.sbc.com.POSTED!7b20fae2!not-for-mail From: "MikeWhy" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <87ab55xki1.fsf@harnisch.dyndns.org> Subject: Re: Version Control for VHDL Project Lines: 22 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Message-ID: NNTP-Posting-Host: 75.57.64.202 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi061.nbdc.sbc.com 1243046921 ST000 75.57.64.202 (Fri, 22 May 2009 22:48:41 EDT) NNTP-Posting-Date: Fri, 22 May 2009 22:48:41 EDT Organization: at&t http://my.att.net/ X-UserInfo1: SCSYQNONXJTERTT[FJMD]_\@VR]^@B@MCPWZKB]MPXHZUYICD^RAQBKZQTZTX\_I[^G_KGFNON[ZOE_AZNVO^\XGGNTCIRPIJH[@RQKBXLRZ@CD^HKANYVW@RLGEZEJN@\_WZJBNZYYKVIOR]T]MNMG_Z[YVWSCH_Q[GPC_A@CARQVXDSDA^M]@DRVUM@RBM Date: Fri, 22 May 2009 21:48:41 -0500 Xref: news.eternal-september.org comp.lang.vhdl:1233 "KJ" wrote in message news:nYzRl.17415$%54.17034@nlpi070.nbdc.sbc.com... > > Many developers don't meet the above criteria because > - They don't create reusable modules, they start from scratch or copy > paste snippets from here and there for every new design > - They create perfect reusable modules that can not possibly be improved > on > - Never have to go back to investigate a problem peculiar to a particular > design that is not the current head revision. > - They have the time to burn having developers type in specific revision > numbers for each and every module (hoping they get every one of them) THEN > produce the final build for qualification testing. And have even more > time to do this whole exercise again for the next build that occurs the > next day... Wow. That's a mouthful of disdain. How about: I don't have time for externals and have successfully avoided needing them. Not because we don't reuse modules. The opposite is true. We've learned to reference them in place. From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!bigfeed2.bellsouth.net!bignumber.bellsouth.net!news.bellsouth.net!bignews6.bellsouth.net.POSTED!b90561f0!not-for-mail Reply-To: "Robert Miles" From: "Robert Miles" Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga References: In-Reply-To: Subject: Re: SPAM? Lines: 50 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Windows Mail 6.0.6001.18000 X-MimeOLE: Produced By Microsoft MimeOLE V6.0.6001.18049 X-RFC2646: Format=Flowed; Original Message-ID: X-Complaints-To: abuse@bellsouth.net X-Abuse-Info: Please forward a copy of all headers for proper handling X-Trace: ofjmidbaofeaohdodbdpiflmbcekedmfhojhikkbagflhcbogfmodalpihndkfnhiokpjbkjjejoddklfgfpagpngcfbimppaahihelibegjblkbpjogimejokdcbfpcbjdonbajiphnmbbhckapaibaobfmmfhn NNTP-Posting-Date: Sat, 23 May 2009 02:53:22 EDT Organization: BellSouth Internet Group Date: Sat, 23 May 2009 01:56:44 -0500 Xref: news.eternal-september.org comp.lang.verilog:442 comp.lang.vhdl:1234 comp.arch.fpga:3617 "James Harris" wrote in message news:b7987197-158d-4333-8e8f-ce7621292579@s28g2000vbp.googlegroups.com... > On 22 May, 17:53, MadHatt...@myself.com wrote: >> On May 22, 6:47 am, Amal wrote: >> >> > It is weird that these newsgroups are getting swamped with SPAM >> > recently!? I wonder if Google or whoever takes care of these >> > newsgroups can do a better job of filtering or deleting them? >> >> > -- Amal >> >> We will have peace in the Middle East before Google does anything >> about SPAM. > > Not so. I sent complaints to Google about the spam in > alt.os.development and it appears that they have not just removed the > sending accounts but also deleted the spam posts sent. > > Maybe their responsiveness is a per-newsgroup thing. Encouraged by > their apparent response I have been reporting spams in other groups to > them for the last couple of months. I can't say I've seen any definite > response yet but I've not been checking for specific messages and ids. > > Reporting spam consumes a bit of time but I presume the reason why > some groups are heavily hit with spam is that spammers have been > allowed to get away with it. They tell their friends and before you > know it the spam levels drown out the legitimate posts. > > The delay was about 6 weeks for alt.os.development. It may be worth > many folks reporting spam posts for a while to see if that encourages > a faster response. > > James . I finally got Google Groups to do something about the spam reports I sent them, but slowly enough that it looks like you then needed to wait a month from the time you start reporting each post by a certain spammer to the time you should expect any action, and you should not expect that action to include sending any email back to you. However, most of the spam I've seen for the last few days was not posted through Google Groups, and is from a very active spammer who's been able fake enough of the header lines to lie about just where it was posted. The readnews.com site (a little upsteam from that spammer) seems to be doing much of the work for handling that spammer. Robert Miles From newsfish@newsfish Wed Aug 19 13:24:50 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 23 May 2009 14:51:48 -0700 Lines: 34 Message-ID: <4A186FF4.5020803@gmail.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <77ja3cF1i4fh2U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 7tAG/Rtfiub7/pxfB7KQGAzXYnZJfVKrqkHwA/oBIc2gaO0uFp Cancel-Lock: sha1:i7iS1VgP88xyiJMjeFawflqN7yw= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1235 KJ wrote: > One upside is that you don't have to try to remember on which project you > used 'widget' where you had made some improvement over the last time you > used 'widget'. All the reusable components would be in one place, a new > design project would simply svn_external reference them to get them into the > new design and then add new code for whatever is unique to the new design. > That way you don't have multiple similar (or the same) versions of 'widget' > around, just one, presumably the 'best' in that it has been refined over > time with various improvements. > > The huge archive downside though makes svn_external something to be > extremely careful about ever using. The headache of manual revision > specification (and the potential to overlook at least one of them) is just > stupid. I will stick with tagging my own reusable vhdl library units and keeping all vhdl code in one repos. The svn users know not to update a tags directory even if they don't bother with formal reuse. If a tag update does happen, there is an audit trail. Upsides: -If I update a library unit, I just copy a new tag. -All changes are observable. -No fussing with externals. -Disinterested developers are not burdened by my reuse. Downsides: -No formal reuse enforcement or marketing. -Interested developers might reinvent the wheel. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!postnews.google.com!e24g2000vbe.googlegroups.com!not-for-mail From: "Juan A. Gomez-Pulido" Newsgroups: comp.lang.vhdl Subject: 2nd. CFP - Journal of Systems Architecture - Embedded Software Design (Elsevier) - Special Issue on HARDWARE/SOFTWARE CO-DESIGN Date: Sun, 24 May 2009 08:14:41 -0700 (PDT) Organization: http://groups.google.com Lines: 90 Message-ID: <08250aef-3055-41cc-bfdd-6be1d98aacf9@e24g2000vbe.googlegroups.com> NNTP-Posting-Host: 85.53.243.38 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243178081 3795 127.0.0.1 (24 May 2009 15:14:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 24 May 2009 15:14:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e24g2000vbe.googlegroups.com; posting-host=85.53.243.38; posting-account=B2VzRwoAAACpyxnJB68ISKVHsSaSttV- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1238 Dear researchers, =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Second Call for Papers Journal of Systems Architecture - Embedded Software Design (Elsevier) Special Issue on HARDWARE/SOFTWARE CO-DESIGN =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D General Information =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Design of embedded systems is an extended activity for different markets such as aeronautics, telecommunications, consumer electronics, audiovisual, automotive, etc. The strong requirements for many applications in these areas (real-time, power consumption, cost and many others) do necessary the simultaneous use of both hardware and software to design and implement in a successful product. Besides this, the more and more complex systems would need to be designed by engineers with deep knowledge in computer architecture if the software is not taken advantage of as powerful tool that facilitates the work of designing. Traditional methodologies for designing embedded systems distinguish hardware and software separately, avoiding the relationship of both during the first phases of the design cycle. Nowadays, fortunately Hardware/Software co-design involves many technologies and methods, making easier the electronic engineer=92s work. Nevertheless, there are still many challenges, trends and open possibilities in this area that it is necessary to know. According to the above-mentioned, this special issue seeks to explore the last advances in the Hardware/Software co-design. In this special issue, we seek original, high quality articles, clearly focused on theoretical or practical aspects of the Hardware/Software co-design of embedded systems, including but not limited to the topics shown below: * Frameworks for Hardware/Software co-design. * Architectures: - Embedded processors and Systems on Chip (SoC). - DSPs and systems for real-time. - Reconfigurable processors and FPGAs. - Multiprocessors and Multiprocessor System-on-Chip (MPSoC). - Networks on Chip (NoC). * Methodologies and tools for designing: - CAD tools. - Modelling HW/SW systems with hardware description languages. - Compilers, interfaces and protocols. - Operating system support. - Concurrency and parallel programming. * Co-verification and co-simulation. * Performance analysis. * Applications and case studies. Submission Information =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D All manuscripts and any supplementary material should be submitted via the online submission and peer review systems at http://ees.elsevier.com/js= a. Follow the submission instructions given on this site. Please select the article type as "Special Issue: Hardware/Software Co- Design". All manuscripts should comply with the journal's Guide for Authors. Please refer to the following site: http://www.elsevier.com/wps/find/journaldescription.cws_home/505616/authori= nstructions. Important Dates =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Submission Deadline: 30 Sep 2009 Acceptation Notification: 30 Dec 2009 Final Papers: 15 Jan 2010 Publication: Spring of 2010 (subject to JSA editorial calendar) JSA Editor-in-Chief =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Dr. Iain Bate Guest Editor for the JSA Special Issue on Hardware/Software Co-Design =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Dr. Juan A. G=F3mez-Pulido Associate professor Department of Technologies of Computers and Communications University of Extremadura Escuela Politecnica. Campus Universitario s/n 10071 =96 Caceres - Spain e-mail: jangomez@unex.es web: http://arco.unex.es/jangomez From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!b6g2000pre.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: When is it to generate transparent latch or usual combinational logic? Date: Mon, 25 May 2009 12:52:08 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243281128 9579 127.0.0.1 (25 May 2009 19:52:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 May 2009 19:52:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000pre.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3653 comp.lang.vhdl:1242 Hi, Through discussions of last problem title "Are all these claims in VHDL correct?" I understand how to recognize a transparent latch from a register. Here I gave an example to show what I am puzzled. State1_A : process(CLK) begin if CLK'event and CLK = '1' then if SINI = '1' then State1 <= Idle_S; else State1 <= State1_NS; end if; end if; end if; State1_B : process(State1, A1, A2) begin case State1 is when Idle_S => if A1 = '1' then State1_NS <= X_S; else State1_NS <= Idle_S; end if; when X_S => if A2 = '1' then State1_NS <= Idle_S; else State1_NS <= X_S; end if; end case; end process; State2_A : process(SINI, CLK) begin if CLK'event and CLK = '1' then if SINI = '1' then State2 <= Idle_S; else State2 <= State2_NS; end if; end if; end if; State2_B : process(State2, A1, A2) begin case State2 is when Idle_S => if A1 = '1' then State2_NS <= X_S; -- else <-- key difference -- State2_NS <= Idle_S; end if; when X_S => if A2 = '1' then State2_NS <= Idle_S; else State2_NS <= X_S; end if; end case; end process; >From my experiences with state machine, VHDL compiler would generate warning for state2: "state machine state2 will be implemented as latches". Once It took me one week to have found the similar situation with the above state2 in my a long state machine. I don't know why VHDL compiler generate latches for state2. Thank you. Weng From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!m17g2000vbi.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Mon, 25 May 2009 14:10:52 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243285852 16286 127.0.0.1 (25 May 2009 21:10:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 May 2009 21:10:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m17g2000vbi.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3655 comp.lang.vhdl:1243 On May 25, 3:52=A0pm, Weng Tianxiang wrote: > Hi, > Through discussions of last problem title "Are all these claims in > VHDL correct?" I understand how to recognize a transparent latch from > a register. > > Here I gave an example to show what I am puzzled. > > State1_A : process(CLK) > begin > =A0 =A0if CLK'event and CLK =3D '1' then > =A0 =A0 =A0 if SINI =3D '1' then > =A0 =A0 =A0 =A0 =A0State1 <=3D Idle_S; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0State1 <=3D State1_NS; > =A0 =A0 =A0 end if; > =A0 =A0end if; > end if; > > State1_B : process(State1, A1, A2) > begin > =A0 =A0case State1 is > =A0 =A0 =A0 when Idle_S =3D> > =A0 =A0 =A0 =A0 =A0if A1 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State1_NS <=3D X_S; > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0 State1_NS <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 when X_S =3D> > =A0 =A0 =A0 =A0 =A0if A2 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State1_NS <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0 State1_NS <=3D X_S; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0end case; > end process; > > State2_A : process(SINI, CLK) > begin > =A0 =A0if CLK'event and CLK =3D '1' then > =A0 =A0 =A0 if SINI =3D '1' then > =A0 =A0 =A0 =A0 =A0State2 <=3D Idle_S; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0State2 <=3D State2_NS; > =A0 =A0 =A0 end if; > =A0 =A0end if; > end if; > > State2_B : process(State2, A1, A2) > begin > =A0 =A0case State2 is > =A0 =A0 =A0 when Idle_S =3D> > =A0 =A0 =A0 =A0 =A0if A1 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State2_NS <=3D X_S; > -- =A0 =A0 =A0 =A0 else =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 <-- key d= ifference > -- =A0 =A0 =A0 =A0 =A0 =A0State2_NS <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 when X_S =3D> > =A0 =A0 =A0 =A0 =A0if A2 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State2_NS <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0 State2_NS <=3D X_S; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0end case; > end process; > > From my experiences with state machine, VHDL compiler would generate > warning for state2: "state machine state2 will be implemented as > latches". > > Once It took me one week to have found the similar situation with the > above state2 in my a long state machine. > > I don't know why VHDL compiler generate latches for state2. > > Thank you. > > Weng Are you sure the latch isn't being created for State2_NS? You may want to put a "when others =3D>" clause at the end of the case statement to make sure State2_NS gets assigned something en every case. A default assignment at the top of the process would give similar effects. Also, SINI doesn't need to be in the sensitivity list for the State2 process, but it shouldn't hurt anything other than simulation time. Dave From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!postnews.google.com!s28g2000vbp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Mon, 25 May 2009 14:28:23 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243286903 19352 127.0.0.1 (25 May 2009 21:28:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 May 2009 21:28:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000vbp.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3656 comp.lang.vhdl:1244 Weng, You've told the synthesizer that state2_ns (the combinatorial signal, not the register) has to remember its previous value under certain circumstances, so it generates a latch to remember the value. Your choices to avoid the latch include a) avoiding combinatorial processes, b) including a default assignment (perhaps from the output of the associated register) in combinatorial processes, or c) making sure every possible execution path through the process results in all driven signals being assigned a value (and not just to themselves). I always choose (a). If you just have to use a combinatorial process, then (b) is much easier to read/write/verify/review than is(c). Andy From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y34g2000prb.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Mon, 25 May 2009 16:44:28 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243295068 19548 127.0.0.1 (25 May 2009 23:44:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 May 2009 23:44:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y34g2000prb.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3664 comp.lang.vhdl:1245 On May 25, 2:28=A0pm, Andy wrote: > Weng, > > You've told the synthesizer that state2_ns (the combinatorial signal, > not the register) has to remember its previous value under certain > circumstances, so it generates a latch to remember the value. > > Your choices to avoid the latch include a) avoiding combinatorial > processes, b) including a default assignment (perhaps from the output > of the associated register) in combinatorial processes, or c) making > sure every possible execution path through the process results in all > driven signals being assigned a value (and not just to themselves). > > I always choose (a). If you just have to use a combinatorial process, > then (b) is much easier to read/write/verify/review than is(c). > > Andy Hi Andy, "You've told the synthesizer that state2_ns (the combinatorial signal, not the register) has to remember its previous value under certain circumstances, so it generates a latch to remember the value." You are right and I understand it. I am interested in your method a. Could you give me an example on how to use your method a. in the above situation. Thank you. Weng From newsfish@newsfish Wed Aug 19 13:24:51 2009 From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Tue, 26 May 2009 09:15:38 +0200 Lines: 99 Message-ID: <87prdwpc6d.fsf@harnisch.dyndns.org> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <87ab55xki1.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net VyyqMCaWWx+0EfDO9p0a4w0oVZPF32Q15J95zpsnXbN+4+4WF0 Cancel-Lock: sha1:9I0w3NlLG0SLArm3jnZ+/bXJ/yM= sha1:NpjzRHU/BkpaNuAbLRZkM839UvQ= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news4us.nl!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail Xref: news.eternal-september.org comp.lang.vhdl:1246 "KJ" writes: > "Marcus Harnisch" wrote in message > news:87ab55xki1.fsf@harnisch.dyndns.org... >> >> Your "how-things-can-go-wrong" example is purely based on a work flow >> that the inventors of SVN explicitly advise against.[1] > > That SVN explicitly advises against it, simply indicates that those > developers do not have the above list of criteria in mind when they use SVN. > That's fine, they don't have to, others do though and other tools do support > that workflow. Sorry, my mistake. What I meant was not your workflow per se, but the fact that externals references be used without explicit version number. >> It isn't as hard as you make it look like. >> > In what way did I make it look harder than it is? I think I described the > steps accurately as well as describing the scenario and pressures that the > developers would be under at the particular time and the repercussions down > the road for making a bad move. Sure you did. But as you wrote in that same message, you chose not to put a revision number in the externals property, despite the fact that you were aware of the issue. I guess you could say that your provoked the result. > No, Subversion doesn't need to remember anything. It just needs to be able > to have a way to create a real archival tag. But it would help you, I think. First of all, in SVN there is no such thing as an archival tag. *Every* revision is one implicitly. I know that other tools treat archiving specially but SVN doesn't. That's one reason why it is so simple. If Subversion automatically remembered the current revision of a checked out sub-project Project2 when you commit Project1, you would be able to restore the exact state of Project1 at any time, no? Thinking about it, I suppose you could come up with a pre-commit (or perhaps start-commit) script, that scans your externals property and updates revision tags for all sub-projects. > A reader of the Subversion manual can be led to believe that doing > the 'svn copy' thing to create a tag does this. Hardly. > Google for svncopy.pl, find their readme for more info on why you > should be using that to create your archival tags and not the native > 'svn copy'. Hmm, half of the job of svncopy.pl (absolute paths) has been obsoleted by changes in SVN's externals syntax. This wouldn't apply to me personally anyway, since I prefer using separate repositories for projects. The other half (maintaining the externals revisions) could be handled by a hook (see above), so that users don't even have to worry about this. > Unless there is some very good reason (and there can be), I don't think > there should be any specific revision numbers called out for any > svn_externals that are referenced in the trunk or any code intended to be > merged back into the trunk in the future (i.e. any time you create new > code). The time when specific revision numbers should be added is when > you're creating an archival tag (i.e. a new build that will be tested). The > adding of those specific revision numbers during the creation of the tag > should be an automated process that replaces all unspecified revisions with > the current (head) revision of whatever thing is being referenced by that > svn_external (regardless of whether that thing is in the same physical repo > or not). It should not be manual and subject to errors. Since "archival tags" are not part of the SVN concept, here is how it might work. Given a hook script as described above, you may settle on a repository structure similar to the quasi standard "trunk, branches, tags". The proposed hook could fix the externals revisions whenever you are about to commit something into "tags". Commiting to other directories would not touch your revision-less externals property. > As I said, specific revision numbers for the most part should not be > commited. The revisions information about your "archival tag" has to be stored somwhere. Whether automatically managed or not, it *has* to be committed. Regards Marcus -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:51 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 26 May 2009 05:47:54 -0500 From: Brian Drummond Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 11:50:45 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 24 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-AABG0YP6l1OOiZ+B7V5rwzhuppxn+bgYk/lS8hSTx0+B6ZeK6grakqisvkWNJkUYgKRFvy0pQK+qF3T!Wi3lsUFNBkWK2hPcmGiYtWjHl/UjozbozwJlQ1fC/K5GKbJBdNg3NTYV+sa+C2UHnjwuODTPIHzO!stwK7aTaWO6WewLO X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2238 Xref: news.eternal-september.org comp.arch.fpga:3676 comp.lang.vhdl:1247 On Mon, 25 May 2009 16:44:28 -0700 (PDT), Weng Tianxiang wrote: >On May 25, 2:28 pm, Andy wrote: >> Weng, >> >> You've told the synthesizer that state2_ns (the combinatorial signal, >> not the register) has to remember its previous value under certain >> circumstances, so it generates a latch to remember the value. >> >> Your choices to avoid the latch include a) avoiding combinatorial >> processes, >Hi Andy, >You are right and I understand it. I am interested in your method a. >Could you give me an example on how to use your method a. in the above >situation. Search for "Single Process State Machine" - it has been described many times on this group and it is the usual way to avoid combinatorial processes in your example - to avoid precisely the problem that you took a week to find. - Brian From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!h23g2000vbc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 05:58:39 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243342719 2540 127.0.0.1 (26 May 2009 12:58:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 May 2009 12:58:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h23g2000vbc.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3681 comp.lang.vhdl:1248 Here ya go... State2 : process(CLK) begin if rising_edge(CLK) then if SINI = '1' then State2 <= Idle_S; else case State2 is when Idle_S => if A1 = '1' then State2 <= X_S; end if; when X_S => if A2 = '1' then State2 <= Idle_S; end if; end case; end if; -- sini end if; -- clk end process; Unless you know that SINI is initially asserted (to initialize the state machine), you will need a reset for the state machine too. Andy From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j18g2000prm.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 08:40:23 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: <7839f8ec-6fa7-4c7f-8b40-8d9e4aecb9cf@j18g2000prm.googlegroups.com> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243352424 29775 127.0.0.1 (26 May 2009 15:40:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 May 2009 15:40:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prm.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3693 comp.lang.vhdl:1249 On May 26, 5:58=A0am, Andy wrote: > Here ya go... > > State2 : process(CLK) > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 =A0 if SINI =3D '1' then > =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 case State2 is > =A0 =A0 =A0 =A0 when Idle_S =3D> > =A0 =A0 =A0 =A0 =A0 if A1 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D X_S; > =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 when X_S =3D> > =A0 =A0 =A0 =A0 =A0 if A2 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end case; > =A0 =A0 =A0 end if; -- sini > =A0 =A0end if; -- clk > end process; > > Unless you know that SINI is initially asserted (to initialize the > state machine), you will need a reset for the state machine too. > > Andy Hi Andy and Brian, 1. Good point: use one process state machine. 2. How do you handle turn-on signals in a state machine? State2_B : process(State2, A1, A2) begin Turn_On <=3D '0'; case State2 is when Idle_S =3D> if A1 =3D '1' then Turn_On <=3D '1'; State2_NS <=3D X_S; -- else <-- key difference -- State2_NS <=3D Idle_S; end if; when X_S =3D> if A2 =3D '1' then State2_NS <=3D Idle_S; else State2_NS <=3D X_S; end if; end case; end process; 3. I don't like one process state machine writing type and Xilinx and Altera all recommend using 2 process method. I have a state machine that has 3000 lines and 30 turn-on signals. One process method is hard to handle my situation. 4. I say VHDL synthesizer should be SMARTER to avoid generating transparent latch in the exact my situations: Locally State2_NS is described as transparent latches, but globally, they are only used in one statement: State2 <=3D State2_NS; or they are assigned to registers: State2 which is the case signal in the case process so that generating transparent latches for State2_NS is OVER-REACTING and State2_NS should be generated as a combinational logic !!! That is what I want to say and highlight !!! Global optimization rule for VHDL synthesizers: if a type signal (as State2_NS) is specified in a case process (case process is a process that contains only one case statement as State2_B shows) as a latch type, and it is only used to be assigned to the case signal in the case process, the latch signal can be reduced to combinational logic without any harm, because the case register keeps the data unchanged for the latch signal. Weng From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 09:51:11 -0700 Lines: 31 Message-ID: <782l00F1k9ajiU1@mid.individual.net> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 7apHIBRIm9f40JtsEV64fgvyAD9KD21LpQMxRcNf1p44CYSpqh Cancel-Lock: sha1:rx+IyB0ImmxjvYgAF365iz1eB8I= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.arch.fpga:3698 comp.lang.vhdl:1250 Andy wrote: > Here ya go... > > State2 : process(CLK) > begin > if rising_edge(CLK) then > if SINI = '1' then > State2 <= Idle_S; > else > case State2 is > when Idle_S => > if A1 = '1' then > State2 <= X_S; > end if; > when X_S => > if A2 = '1' then > State2 <= Idle_S; > end if; > end case; > end if; -- sini > end if; -- clk > end process; Thanks for taking the time to post this simplified solution. This thread demonstrates the clarity provided by minimizing the number of processes in a design entity. More importantly, it shows the downside of using an asynchronous process for synthesis. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!w31g2000prd.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Tue, 26 May 2009 13:02:12 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243368132 16804 127.0.0.1 (26 May 2009 20:02:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 May 2009 20:02:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w31g2000prd.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1251 On May 20, 1:28=A0pm, "MikeWhy" wrote: > I wish I had sent the Me too! earlier rather than deleting it.= It > might have saved you a lot of typing. Fundamentally, I agree with your > observation, that svn:externals have archival problems. But I come to a > different conclusion. If you need to use them, the externals must all hav= e > explicit revision references. Otherwise, they are little more useful than > `ln -s` soft links to a local working copy of the foreign repository. In > fact, they are worse in some respects. You get the worst of both worlds: > archival issues, AND continual integration issues as you blindly track th= eir > updates. The soft-link at least allows you control over when you update t= he > foreign source. If you consider that your subproject modules -- the things you would include in a larger design using externals -- can be tagged, then simply adopt the paradigm that tags are immutable. For released designs you should always use a tagged version of the module, never the trunk. It's really pretty simple, and it works. There's no need to keep track of which revision of the submodule (no need to deal with pinned revisions), and as noted, the svn copy you do to make the tag is "cheap." Really -- it works. -a From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g19g2000yql.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Tue, 26 May 2009 14:22:54 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> NNTP-Posting-Host: 192.62.143.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243372974 30443 127.0.0.1 (26 May 2009 21:22:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 May 2009 21:22:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000yql.googlegroups.com; posting-host=192.62.143.126; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1252 On May 26, 4:02 pm, Andy Peters wrote: > > If you consider that your subproject modules -- the things you would > include in a larger design using externals -- can be tagged, then > simply adopt the paradigm that tags are immutable. I'm not sure I follow what you're saying. Creating a tag does not make the tag immutable, nor do I get how one would "adopt a pardigm" that it is (although I absolutely agree that the thing that is tagged, and all of the things it references, if any, 'should' not be changable). The tag simply indicates the revision level of the repository of a particular project (i.e. the top level of the design) > For released > designs you should always use a tagged version of the module, never > the trunk. I agree, create the tag and build from that. But if you have an svn_external with an unspecified revision anywhere then when you go to retrieve the tagged item one year from now, you won't get the same thing that you get if you retrieve it today if the thing that is referenced via the svn_external happens to change between those two times. > It's really pretty simple, and it works. There's no need to > keep track of which revision of the submodule (no need to deal with > pinned revisions), and as noted, the svn copy you do to make the tag > is "cheap." > > Really -- it works. > If so, then you should be able to complete steps 1 thru 16 from my May 20 post and then have an explanation as requested for step #17. So far nobody has. If there is some method to use Subversion to meet the following goals (from the May 22 post) I'd like to hear it. - You create modules intended to be reused, and... - Those reusable modules get enhanced or changed over time, and... - You need to be able to accurately reproduce all of the source files for a particular build sometime in the future, and... - You don't want to burden developers with a task that is easy to get wrong or be incomplete KJ From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s31g2000vbp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 15:21:53 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> <7839f8ec-6fa7-4c7f-8b40-8d9e4aecb9cf@j18g2000prm.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243376513 10329 127.0.0.1 (26 May 2009 22:21:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 May 2009 22:21:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s31g2000vbp.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3709 comp.lang.vhdl:1253 This example shows one way to handle outputs, but inserts a one clock delay on the output. State2 : process(CLK) begin if rising_edge(CLK) then turn_on <= '0'; if SINI = '1' then State2 <= Idle_S; else case State2 is when Idle_S => if A1 = '1' then turn_on <= '1'; State2 <= X_S; end if; when X_S => if A2 = '1' then State2 <= Idle_S; end if; end case; end if; -- sini end if; -- clk end process; If you want to avoid the delay, just assert the output when you transition into the states in which you want it on. I think it was Jonathan Bromley that demonstrated a method, using variables, to describe state machine outputs more easily in a single clocked process. It's not that hard to do, and you don't get latches, ever! If you really prefer dual-process state machines, there are proven, easy ways to avoid latches in them (like default "State <= State_NS" assignments). Quite frankly, I'd prefer the synthesis vendors work on other optimizations that are more important to quality of results, than avoiding inferring latches from poorly written RTL code. Andy From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Wed, 27 May 2009 00:47:38 +0200 Organization: T-Online Lines: 48 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1243378059 01 n14125 zYyUQnh1gqpyx00 090526 22:47:39 X-Complaints-To: usenet-abuse@t-online.de X-ID: Ty4fsyZX8e11B6NGoYo8b1DAWKqtjPdAFDSnXfrwXTsQV+fCsm-eUc User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1254 KJ schrieb: > On May 26, 4:02 pm, Andy Peters wrote: > If so, then you should be able to complete steps 1 thru 16 from my May > 20 post and then have an explanation as requested for step #17. So > far nobody has. > > If there is some method to use Subversion to meet the following goals > (from the May 22 post) I'd like to hear it. > - You create modules intended to be reused, and... > - Those reusable modules get enhanced or changed over time, and... > - You need to be able to accurately reproduce all of the source files > for a > particular build sometime in the future, and... > - You don't want to burden developers with a task that is easy to get > wrong > or be incomplete > > KJ Hi KJ, I completely agree with Andy. It does work. The 'paradigm change' is in step 4 of your May 20 post. The steps are 1. Setup a new repository 2. Add new folders called 'Project1' and 'Project2' to the repo. 3. Export 'Project1' to some folder 4. Add the svn_external property to the working copy of 'Project1' to reference 'Project2'. 4+ Do not use the working copy of Project2. Tag (svn copy) Project2 first. Reference this tagged version of Project2 in Project1. Any further development to Project2 is done on the trunk. If you ever find you have to change the version of Project2 in Project1, make a new tagged version of Project2 first and change the svn:externals to reference this. Never ever import the _trunk_ of a sub project into a super-project. The trunk is for development, tags are for releases. I extracted one of my archived projects (about a year old) a few days ago and it worked just as expected. Regards, Charles From newsfish@newsfish Wed Aug 19 13:24:52 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!weretis.net!feeder2.news.weretis.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!o18g2000pra.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Tue, 26 May 2009 17:22:40 -0700 (PDT) Organization: http://groups.google.com Lines: 62 Message-ID: <93d63151-1244-41e3-a818-3c8e9851cfe5@o18g2000pra.googlegroups.com> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> <7839f8ec-6fa7-4c7f-8b40-8d9e4aecb9cf@j18g2000prm.googlegroups.com> NNTP-Posting-Host: 68.126.127.103 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243383761 32760 127.0.0.1 (27 May 2009 00:22:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 May 2009 00:22:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000pra.googlegroups.com; posting-host=68.126.127.103; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3712 comp.lang.vhdl:1255 On May 26, 3:21=A0pm, Andy wrote: > This example shows one way to handle outputs, but inserts a one clock > delay on the output. > > State2 : process(CLK) > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 =A0 turn_on <=3D '0'; > =A0 =A0 =A0 if SINI =3D '1' then > =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 case State2 is > =A0 =A0 =A0 =A0 when Idle_S =3D> > =A0 =A0 =A0 =A0 =A0 if A1 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 turn_on <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D X_S; > =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 when X_S =3D> > =A0 =A0 =A0 =A0 =A0 if A2 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end case; > =A0 =A0 =A0 end if; -- sini > =A0 =A0end if; -- clk > end process; > > If you want to avoid the delay, just assert the output when you > transition into the states in which you want it on. I think it was > Jonathan Bromley that demonstrated a method, using variables, to > describe state machine outputs more easily in a single clocked > process. > > It's not that hard to do, and you don't get latches, ever! > > If you really prefer dual-process state machines, there are proven, > easy ways to avoid latches in them (like default "State <=3D State_NS" > assignments). Quite frankly, I'd prefer the synthesis vendors work on > other optimizations that are more important to quality of results, > than avoiding inferring latches from poorly written RTL code. > > Andy Hi Andy, "If you really prefer dual-process state machines, there are proven, easy ways to avoid latches in them (like default "State <=3D State_NS" assignments)." Very good suggestions !!! I will follow it in all my designs starting today. Actually I give a default value at head of each of important states, not for full state machine. But your method of one process with turn-on signal delayed by 1 clock is not acceptable to me. That is the fatal fault of one process and the main reason for me to use dual-process method. One may like vegetables and others may like beef and pork. There is no need to compare between two methods, I know, it is a long crusade in VHDL industry. Weng From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!feeder.news-service.com!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!newsfeed2.telusplanet.net!newsfeed.telus.net!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!nlpi066.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> Subject: Re: Version Control for VHDL Project Lines: 42 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi066.nbdc.sbc.com 1243424152 ST000 99.184.242.197 (Wed, 27 May 2009 07:35:52 EDT) NNTP-Posting-Date: Wed, 27 May 2009 07:35:52 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PAPDCAOXTEBS\Y@RHVOQH@FJT@QDDMEPWXODMMHXMTWA]EPMVOPCWZBL[\YUWHANGYZEFNHFZPNLOBUNSS^_LGEVWEY\PHO@YJSSWBBDT\PFD^ESBTXVCCMTD]JCJLE\_IJMFNRY]SWE[S[D_CNB__ZK^VGVCKHA[S@COB^[@ZQSDFQ\BPMS@DZVUKQTJL Date: Wed, 27 May 2009 07:35:46 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1257 "Charles Gardiner" wrote in message news:gvhrib$dpd$01$1@news.t-online.com... > 1. Setup a new repository > 2. Add new folders called 'Project1' and 'Project2' to the repo. > 3. Export 'Project1' to some folder > 4. Add the svn_external property to the working copy of 'Project1' to > reference 'Project2'. > > 4+ Do not use the working copy of Project2. Tag (svn copy) Project2 > first. Reference this tagged version of Project2 in Project1. > Step 4+ is essentially the same thing as referencing a specific revision of Project2 in Project1. Either way, in order to prepare for a release candidate build of Project1, one would have to manually make sure that each and every revision reference points to the latest/greatest (or per your suggestion, make sure that each sub-project tag is a copy of the latest/greatest). I'm not saying that this method doesn't work, but (in my opinion) violates the goal of >> - You don't want to burden developers with a task that is easy to get >> wrong or be incomplete Compare this with VSS, in which the equivalent to the busy work of manual revision checking is to simply label Project1, and then export it. Maybe we just don't agree that the manual task of making sure that each and every revision is up to date at the time when you need to create a release candidate build is a burden, or that it could ever be done incorrectly (like missing the last update to some module) I had listed several goals, all of which *should* be achievable by a revision control tool, but do not appear to be possible using SVN but can with other tools. I'm not a big fan of creating extra manual tasks that can be done wrong when working concurrently on a project. Thanks for your input on how you do things. KJ From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!f16g2000vbf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Wed, 27 May 2009 07:23:56 -0700 (PDT) Organization: http://groups.google.com Lines: 100 Message-ID: <5da1c27a-ff80-4ee7-a2ec-98d30c500229@f16g2000vbf.googlegroups.com> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> <7839f8ec-6fa7-4c7f-8b40-8d9e4aecb9cf@j18g2000prm.googlegroups.com> <93d63151-1244-41e3-a818-3c8e9851cfe5@o18g2000pra.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243434236 28839 127.0.0.1 (27 May 2009 14:23:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 May 2009 14:23:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f16g2000vbf.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3734 comp.lang.vhdl:1258 On May 26, 7:22=A0pm, Weng Tianxiang wrote: > On May 26, 3:21=A0pm, Andy wrote: > > > > > > > This example shows one way to handle outputs, but inserts a one clock > > delay on the output. > > > State2 : process(CLK) > > begin > > =A0 =A0if rising_edge(CLK) then > > =A0 =A0 =A0 turn_on <=3D '0'; > > =A0 =A0 =A0 if SINI =3D '1' then > > =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > > =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 case State2 is > > =A0 =A0 =A0 =A0 when Idle_S =3D> > > =A0 =A0 =A0 =A0 =A0 if A1 =3D '1' then > > =A0 =A0 =A0 =A0 =A0 =A0 turn_on <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D X_S; > > =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 when X_S =3D> > > =A0 =A0 =A0 =A0 =A0 if A2 =3D '1' then > > =A0 =A0 =A0 =A0 =A0 =A0 State2 <=3D Idle_S; > > =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end case; > > =A0 =A0 =A0 end if; -- sini > > =A0 =A0end if; -- clk > > end process; > > > If you want to avoid the delay, just assert the output when you > > transition into the states in which you want it on. I think it was > > Jonathan Bromley that demonstrated a method, using variables, to > > describe state machine outputs more easily in a single clocked > > process. > > > It's not that hard to do, and you don't get latches, ever! > > > If you really prefer dual-process state machines, there are proven, > > easy ways to avoid latches in them (like default "State <=3D State_NS" > > assignments). Quite frankly, I'd prefer the synthesis vendors work on > > other optimizations that are more important to quality of results, > > than avoiding inferring latches from poorly written RTL code. > > > Andy > > Hi Andy, > "If you really prefer dual-process state machines, there are proven, > easy ways to avoid latches in them (like default "State <=3D State_NS" > assignments)." > > Very good suggestions !!! I will follow it in all my designs starting > today. Actually I give a default value at head of each of important > states, not for full state machine. > > But your method of one process with turn-on signal delayed by 1 clock > is not acceptable to me. > > That is the fatal fault of one process and the main reason for me to > use dual-process method. > > One may like vegetables and others may like beef and pork. There is no > need to compare between two methods, I know, it is a long crusade in > VHDL industry. > > Weng- Hide quoted text - > > - Show quoted text - I agree there are multiple valid ways to design a state machine, each with their trade-offs (e.g. latches vs output timing issues). I prefer to deal with the former, and gain the other benefits of single, clocked process descriptions, others (yourself included) may not. Single, clocked process descriptions also allow the flexibility of using VHDL variables for specifying both combinatorial and registered behavior in a compact, straight-forward manner (the circuit behaves just like the code sequential code reads). One of the primary benefits of assigning default values in combinatorial processes, right up front, for every signal driven by that process, is that this is the most easily remembered/verified/ reviewed place to do it. You can default the state variable to the current registered value, but choose to default outputs either to the "off" state or to the current registered value, depending on how you want to describe the output in the state machine. For example, do you want to describe when the output changes, or do you just want to describe when it should be on? Judicious choice of the default value can greatly simplify the coding of the state machine and outputs themselves (i.e. state machines only need to describe transitions to other states, letting the default assignment take care of waiting in the same state). If you try to make decisions about this signal or that signal being "important" enough to include or exclude a default, you are more likely to forget to properly handle something, and get a latch, and it is much harder to verify/review that each signal is properly handled. Andy From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d19g2000prh.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Wed, 27 May 2009 10:06:10 -0700 (PDT) Organization: http://groups.google.com Lines: 74 Message-ID: <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243443971 23619 127.0.0.1 (27 May 2009 17:06:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 May 2009 17:06:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000prh.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1259 On May 26, 2:22=A0pm, KJ wrote: > On May 26, 4:02 pm, Andy Peters wrote: > > > > > If you consider that your subproject modules -- the things you would > > include in a larger design using externals -- can be tagged, then > > simply adopt the paradigm that tags are immutable. > > I'm not sure I follow what you're saying. =A0Creating a tag does not > make the tag immutable, nor do I get how one would "adopt a pardigm" > that it is (although I absolutely agree that the thing that is tagged, > and all of the things it references, if any, 'should' not be > changable). =A0The tag simply indicates the revision level of the > repository of a particular project (i.e. the top level of the design) By "paradigm" I suppose I really mean "common practice." And the common practice with Subversion is that you never modify tags. If you use TortoiseSVN, and you try to commit a change to a tag, TSVN will complain. It's a kind of gentle reminder. > > For released > > designs you should always use a tagged version of the module, never > > the trunk. > > I agree, create the tag and build from that. =A0But if you have an > svn_external with an unspecified revision anywhere then when you go to > retrieve the tagged item one year from now, you won't get the same > thing that you get if you retrieve it today if the thing that is > referenced via the svn_external happens to change between those two > times. That is NOT true. If no changes are committed to the tagged branch (sorry for mixing svn metaphors here), and the whole point of keeping tags is that you do NOT change them -- then you WILL get exactly what you expect. Think of the tag as a mnemonic that refers to the state of the repository at the time at which the tag was made. Why remember - r45677 when instead you can remember tag\Release-v1.0.0? > > It's really pretty simple, and it works. There's no need to > > keep track of which revision of the submodule (no need to deal with > > pinned revisions), and as noted, the svn copy you do to make the tag > > is "cheap." > > > Really -- it works. > > If so, then you should be able to complete steps 1 thru 16 from my May > 20 post and then have an explanation as requested for step #17. =A0So > far nobody has. > > If there is some method to use Subversion to meet the following goals > (from the May 22 post) I'd like to hear it. > - You create modules intended to be reused, and... > - Those reusable modules get enhanced or changed over time, and... > - You need to be able to accurately reproduce all of the source files > for a > particular build sometime in the future, and... > - You don't want to burden developers with a task that is easy to get > wrong > or be incomplete Tags do that! The changes to the reusable modules get made to those modules' TRUNKS, never the tags. And if you decide that you like a newer version of your foo module, tag it as tags\Release-v2.0.0. If you check out any previous designs that depended on Release-v1.0.0, you will in fact get the state of all of that module's files as of the Release-v1.0.0 tag! The old tag is never removed and never changed, and you can use either version as you see fit. I am not sure if I can explain this any better. -a From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Date: Wed, 27 May 2009 23:15:16 +0200 From: Peter Soerensen User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Standard library packages for bit and strings? References: <4a112dd5$0$90274$14726298@news.sunsite.dk> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 16 Message-ID: <4a1dad11$0$90271$14726298@news.sunsite.dk> Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 91.143.113.214 X-Trace: news.sunsite.dk DXC=H64<_NC2d_Ic5QH[6O^X]LYSB=nbEKnkKebg1>^?UCAJ_hN;Vo;0KjHZPcL;PaZCSES^2KnhMoT`IGNR17K7IN>D0?lC=; On May 18, 3:08 pm, Alan Fitch wrote: >> Also the company Easics used to have a package PCK_FIO which emulated >> some printf-like behaviour. >> > This package can be found at: > http://www.easics.com/webtools/freesics > > -- > Philippe Faes > http://www.sigasi.com Thank you Philippe and everyone else for your inputs. best regards Peter Sørensen From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!ecngs!feeder2.ecngs.de!94.232.116.16.MISMATCH!feeder.xsnews.nl!feed.xsnews.nl!border-4.ams.xsnews.nl!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi144.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> Subject: Re: Version Control for VHDL Project Lines: 183 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi144.ffdc.sbc.com 1243476017 ST000 99.184.242.197 (Wed, 27 May 2009 22:00:17 EDT) NNTP-Posting-Date: Wed, 27 May 2009 22:00:17 EDT Organization: at&t http://my.att.net/ X-UserInfo1: [[PAPDCA[S@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WH[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 27 May 2009 22:00:10 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1261 "Andy Peters" wrote in message news:8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com... On May 26, 2:22 pm, KJ wrote: > On May 26, 4:02 pm, Andy Peters wrote: > > > > If you consider that your subproject modules -- the things you would > > > include in a larger design using externals -- can be tagged, then > > > simply adopt the paradigm that tags are immutable. > > > > I'm not sure I follow what you're saying. Creating a tag does not > > make the tag immutable, nor do I get how one would "adopt a pardigm" > > that it is (although I absolutely agree that the thing that is tagged, > > and all of the things it references, if any, 'should' not be > > changable). The tag simply indicates the revision level of the > > repository of a particular project (i.e. the top level of the design) > > By "paradigm" I suppose I really mean "common practice." And the > common practice with Subversion is that you never modify tags. I agree, never modify tags...and if you look at my simple example of a usage of svn_externals in my posting from May 20, in step 9 I said to create a tag. In steps 10 thru 15 I made a change to the 'trunk' of 'Project2' and when I re-exported the tag in step #15, I didn't get what was originally tagged, 'Project2' had stuff from the trunk. It's not totally clear to me why somebody would prefer such behaviour, and I don't begrudge them having it if they so choose, but saying that you can recover exactly what you originally tagged, just because you created a tag and did not modify the tag is not really correct. You can only make that statement if there are either no externals or every external is explicitly revision specified. > > > > I agree, create the tag and build from that. But if you have an > > svn_external with an unspecified revision anywhere then when you go to > > retrieve the tagged item one year from now, you won't get the same > > thing that you get if you retrieve it today if the thing that is > > referenced via the svn_external happens to change between those two > > times. > > That is NOT true. If no changes are committed to the tagged branch > (sorry for mixing svn metaphors here), and the whole point of keeping > tags is that you do NOT change them -- then you WILL get exactly what > you expect. If you really believe that then you should be able to explain why in my May 20 posting, I got different results from exporting the tag after modifying only the trunk. The answer, quite simply, (and I knew this going in and you probably do too) is that the different results from exporting an unmodified tag are a result of the lack of a revision being specified...OK, so what mechanism exists to lock down revisions at the time of tag creation? svncopy.pl is the only mechanism I've run across, but it has problems as well. The other mechanism is to explicitly declare revision levels. If done during concurrent development this task will hinder development since every user of a widget will have to manually change the revision level in order to get the latest/greatest from something that has already been tested and commited by the developer. When it gets near time for product release, this manual step is something again that can get in the way at a time when developers are under pressure to get their last fixes in. Charles, in his reply, suggested another step that gets around the problem, but is essentially the same as simply locking down a revision (actually a slight bit more work). Whether or not somebody thinks this cost is 'worth it' or 'not a big deal', is totally up to that person. It certainly appears though to be extra effort needed so that you can use SVN, but with no real upside (other than so you can continue to use SVN, or Tortoise...I do by the way). I don't mind that SVN has 'cheap copies' that cut down on disk usage, but I think it's an oversight on SVN's part that it doesn't also support a mechanism to simply take a snapshot of a project (and it's sub-projects) and lock down any revisions that are not specified. When I do a checkout or an export, it tells me the revision of each external so it's not like it can't be done. The fact that svncopy.pl exists at all suggests I'm not alone in seeing this as something important (although I seem to be almost alone in this particular newsgroup). I've posted to the Subversion group a (as have others) and either nothing comes back, or in one case the repliers got somewhat hostile for suggesting that SVN might be missing something. The Tortoise newsgroup though seems to agree that this would be a good thing, but basically thought that it is up to SVN to first provide the capability so that Tortoise can take advantage of it. > Think of the tag as a mnemonic that refers to the state of > the repository at the time at which the tag was made. Why remember - > r45677 when instead you can remember tag\Release-v1.0.0? > I agree. > > > > If there is some method to use Subversion to meet the following goals > > (from the May 22 post) I'd like to hear it. > > - You create modules intended to be reused, and... > > - Those reusable modules get enhanced or changed over time, and... > > - You need to be able to accurately reproduce all of the source files > > for a > > particular build sometime in the future, and... > > - You don't want to burden developers with a task that is easy to get > > wrong > > or be incomplete > > Tags do that! The changes to the reusable modules get made to those > modules' TRUNKS, never the tags. > I guess we disagree on this point. But if you can list a process that really does meet all of the above mentioned goals I'd like to hear it. > And if you decide that you like a newer version of your foo module, > tag it as tags\Release-v2.0.0. If you check out any previous designs > that depended on Release-v1.0.0, you will in fact get the state of all > of that module's files as of the Release-v1.0.0 tag! The old tag is > never removed and never changed, and you can use either version as you > see fit. > I understand that and agree that the v1.0.0 tag will be retrieved under the conditions you describe...but only if module 'foo' doesn't happen to have any svn_externals in it. Now stand back for a moment and view your process from the point of view of doing concurrent development where both the new widget is being developed as well as the widget being integrated into a design and evaluate it against these two particular points (which you've already stated are handled by tags) - Those reusable modules get enhanced or changed over time, and... - You don't want to burden developers with a task that is easy to get wrong or be incomplete The time period over which the module changes can be short (it's under development remember, we're not talking about the integration of a stable, static design). What happens is the integrator is burdened with having to update his links to point to a new tag, just so he can get the latest/greatest. Before updating though, he is also burdened with simply discovering that there is an updated version even available. Multiply that effort by say 10 modules and again by 4 designs and several changes to modules and the whole mess has to be released at the end of the month. Is that really how you want your integrator spending their time? How about the delay that is created because the integrator has to do this process for each build...or does this get shortcut because the integrator 'knows' what things have changed? How do you 'know' that he/she 'knows' and didn't miss something? The integrator is also burdened with insuring that there are no unspecified revisions on any externals that may be lurking in all modules (on every build). The developer has the additional burden of creating a new tag, as opposed to simply committing his change. How do you insure that happens every time? How do you check to see that the repo is in that state prior to a build? I'm not necessarily expecting answers here to all this, just potential holes that I see in your process that can only be fixed by manual intervention...all because SVN doesn't natively support a method of capturing a snapshot of the repo and being able to truly recreate it later except under special conditions...conditions that cause more work. >From a more fundamental standpoint, you should always be able to answer 'yes' to the following questions: - Is your build built from an unchangable tag? (I agree that your method gets a yes) - Is your tag built from a snapshot of the trunk? Given your process, you would have to manually verify this by checking that the tag for each module reflects what is in the trunk and then verify that the integration of each module also points to this latest tag. Maybe you can automate this...if it's not, you can't really guarantee this...you can only hope that mistakes don't get made by mere mortals. With my method of unspecified versions on externals, it exposes me only on the archival front and none of the others. If some Perl wizard would fix svncopy.pl, the archival hole could be closed as well (or of course, if SVN added a new form of copy that locked down revisions to whatever they are at the time that the copy is performed). > I am not sure if I can explain this any better. You don't have to, thanks for your explanation. I think you're overstating a bit what tags really do because of the way you happen to choose to use them. But because of the way you use them, you're exposed on a couple of the points. You're maybe aware of them anyway, but it was a good discussion...even if it really had no place in comp.lang.vhdl in the first place. Apologies to those clv readers that found this boring and off topic. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Thu, 28 May 2009 10:49:24 -0700 Lines: 27 Message-ID: <788155F1l0ipkU1@mid.individual.net> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net UeI0oBY/3tsmfoRFDiHZvAeySLzDcOuxVmKtEB9XgtrOXfYYHM Cancel-Lock: sha1:1JbQYDEqsNLrRrFWbWQYf+vPgqc= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1262 KJ wrote: > You can only make that > statement if there are either no externals or every external is explicitly > revision specified. And that is why I keep all referenced code in the same repository and use no externals. For me, externals are not worth all the brain cycles. svn isn't perfect, but it works real good for free. Andy Peters wrote: >> Think of the tag as a mnemonic that refers to the state of >> the repository at the time at which the tag was made. Why remember - >> r45677 when instead you can remember tag\Release-v1.0.0? KJ wrote: > I agree. Me too > Apologies to those clv readers that found this boring and off topic. I think the discussion is on-topic as lack of proper version control is a significant problem in vhdl projects with multiple developers. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w31g2000prd.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Thu, 28 May 2009 13:02:45 -0700 (PDT) Organization: http://groups.google.com Lines: 125 Message-ID: <6acc113a-c9c4-4455-a04f-fb1c59f2e4b7@w31g2000prd.googlegroups.com> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243540966 8081 127.0.0.1 (28 May 2009 20:02:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 May 2009 20:02:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w31g2000prd.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1266 On May 27, 7:00=A0pm, "KJ" wrote: > "Andy Peters" wrote in message > > That is NOT true. If no changes are committed to the tagged branch > > (sorry for mixing svn metaphors here), and the whole point of keeping > > tags is that you do NOT change them -- then you WILL get exactly what > > you expect. > > If you really believe that then you should be able to explain why in my M= ay > 20 posting, I got different results from exporting the tag after modifyin= g > only the trunk. =A0The answer, quite simply, (and I knew this going in an= d you > probably do too) is that the different results from exporting an unmodifi= ed > tag are a result of the lack of a revision being specified...OK, so what > mechanism exists to lock down revisions at the time of tag creation? > svncopy.pl is the only mechanism I've run across, but it has problems as > well. So you are saying that you: a) Tagged a submodule, b) Added the submodule tag to the main project's source directory, c) Did an svn update on the main project's source directory, d) Committed the change to the main project's source directory. e) Later checked out or exported the main project and discovered that the submodule had the wrong stuff in it? OK, I went back and found the 19 May post that describes your issue: > 1. Setup a new repository > 2. Add new folders called 'Project1' and 'Project2' to the repo. > 3. Export 'Project1' to some folder > 4. Add the svn_external property to the working copy of 'Project1' to ref= erence 'Project2'. By "reference 'Project2'" here, I assume that you mean you are referencing Project2's TRUNK and not a TAG? > 5. Do an update to get Project2 into the working copy. > 6. Create a new text file called 'Project2_File.txt' in the Project2 fold= er. > 7. Edit Project2_File.txt so it has the single line of text 'This is line= #1' > 8. Add Project2_File.txt into 'Project2' and commit the changes to both '= Project1' and 'Project2'. At this point, Project2's __trunk__ now has the file Project2_File.txt. You point out that it is likely that you will be simultaneously working on both Project1 and its submodule Project2, and so the external pointing to Project2's __trunk__ is correct. > 9. Create your tag of 'Project1' using 'svn copy' or TortoiseSVN so that = you > get the warm fuzzy feeling that you've successfully archived away the > current state of 'Project1' at this moment in time confident that you can > come back at any time to recover this entire project exactly as it was le= ft > after step #8. To do so you will of course be specifying the exact revis= ion > of 'Project1' to use to create the tag. Lets say this tagged version of > 'Project1' is put into the archive at 'Tags/Project1_1.0' ******************************** And here is the problem: You never created a tag for Project2. ******************************** The svn:externals property on Project1 probably looks like Project2 svn://myrepo/Project2 So even though you created a tag for Project1, that tag still refers to the head of Project2, and as such, if someone later modifies Project2, you get those modifications, even though you checked out the tagged version of Project1. Project2 is its own project within the repo. So you will have to create tags for it. If you create a tag for Project2 (for example, Project2-v1.0), and change the svn:externals property on Project1 to look like: Project2 svn://myrepo/Project2/tags/Project2-v1.0/ then I __guarantee__ that this will work the way you want it to work. --------------------------------------------- Assume that Project1 has two files, foo.txt and bar.txt, as well as requiring the stuff in Project2. To ensure that we always get the correct version of Project2, we've set the svn:externals property on Project1 as noted above. Now we tag Project1 as Project1-v1.0. That tag, which is a copy of Project1, also has the svn:externals property referencing the tag Project2-v1.0. So say we wish to check out the the Project1-v1.0 tag into the directory /devel/Project1. Your working copy will look like: /devel/Project1/ <- top of working copy /devel/Project1/foo.txt <- a file in Project1 /devel/Project1/bar.txt <- another file in Project1 /devel/Project1/Project2/ <- brought in by externals /devel/Project1/Project2/Project2_File.txt <- the file in Project2 -------------------------------------------------------------------------- So your repo should be structured essentially like: //myrepo/Project1/trunk <- working trunk for Project1 //myrepo/Project1/tags <- tags here //myrepo/Project1/tags/Project1-v1.0 <- tag for 1st release //myrepo/Project1/tags/Project1-v2.0 <- tag for 2nd release //myrepo/Project2/trunk <- working trunk for Project2 //myrepo/Project2/tags <- tags here //myrepo/Project2/tags/Project2-v1.0 <- tag for 1st release of Project2 //myrepo/Project2/tags/Project2-v2.0 <- tag for 2nd release of Project2 Does this help??? -a From newsfish@newsfish Wed Aug 19 13:24:53 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!feeder.news-service.com!feeder.news-service.com!postnews.google.com!h23g2000vbc.googlegroups.com!not-for-mail From: Jacko Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Thu, 28 May 2009 18:32:54 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <1df327cf-67a3-4250-819f-6baf5bb59b11@h23g2000vbc.googlegroups.com> References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> <782l00F1k9ajiU1@mid.individual.net> NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243560775 5499 127.0.0.1 (29 May 2009 01:32:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 May 2009 01:32:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h23g2000vbc.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/525.19 (KHTML, like Gecko) Chrome/1.0.154.65 Safari/525.19,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3795 comp.lang.vhdl:1267 Sound advice. Processes should be separate only for separate functional parts. Splitting action into multiple case statements also causes errors of logic. 'Inferred latches for signal' is quite a strange phrase, maybe 'possible forgotten signal assignment' would be better. It only seems to be if ... then ... else ... end if; which generates inferred latches. case and if ... then ... end if; does not seem to. I guess this is because no else is definite latch/register, and case can contain many places of non assignment and so could flood the message display. It's not that strange really. cheers jacko http://nibz.googlecode.com version T much easier to read code. final version for a while. From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Fri, 29 May 2009 15:05:07 +0200 Lines: 67 Message-ID: <871vq8cb5o.fsf@harnisch.dyndns.org> References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> <6acc113a-c9c4-4455-a04f-fb1c59f2e4b7@w31g2000prd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net F2+m5LgbK7/G14SffKRObAZcZhhJs/kww2bvHiCJhWaYraRKNc Cancel-Lock: sha1:tV0desRJoWaiWuz6uhuBNBYxvtE= sha1:YH3U/hmZH8moz3JZxn7I3XUJeXI= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b28 (linux) Xref: news.eternal-september.org comp.lang.vhdl:1268 Andy Peters writes: > So even though you created a tag for Project1, that tag still refers > to the head of Project2, and as such, if someone later modifies > Project2, you get those modifications, even though you checked out the > tagged version of Project1. > > Project2 is its own project within the repo. So you will have to > create tags for it. > > If you create a tag for Project2 (for example, Project2-v1.0), and > change the svn:externals property on Project1 to look like: > > Project2 svn://myrepo/Project2/tags/Project2-v1.0/ > > then I __guarantee__ that this will work the way you want it to > work. No. Because that is not the way KJ wants it to work as far as I understand it. While this is not my development style, I think this is a perfectly valid request. 1. KJ wants to be able to check out Project1, which refers Project2. Whenever Project1 is checked out, the most recent revision of Project2 should be checked out into the subdirectory of Project1. 2. While he is working on Project1, he occasionally updates the Project2 subdirectory to stay up-to-date. At some point KJ wants to take a snapshot of his Project1 workspace *including* the current state of all externals (i.e. Project2). In order to do that, Subversion requires you to put explicit revision numbers into externals property, which means that upon the next check out of Project1, that same revision of Project2 is checked ut as well. But that's not what he wants (see 1.). He doesn't want to be bothered with revision numbers just to create a (recreatable) snapshot of the current state of his workspace. To (sort of) support KJ's development style, Subversion gives you two basic options: *Don't* fix the externals revision number in main-line. Whenever you are about to create a snapshot, you'd create a branch of Project1, switch your workspace over to that branch, add the current revision number of Project2 to the externals property and commit again. Create a tag for that revision. *Do* fix the externals revision number in main-line. Whenever you check out Project1, you will get the same revision of Project2 that was current last time Project1 was checked in[1]. In order to track the latest releases of externals, go into each sub directory and do 'svn update'. Take note of the new revisions and keep the externals property of Project1 in sync. This could easily be wrapped into a script, I reckon. Regards Marcus Footnotes: [1] Or rather: last time you *didn't forget* to update the externals property. -- note that "property" can also be used as syntaxtic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n21g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: When is it to generate transparent latch or usual combinational logic? Date: Fri, 29 May 2009 07:25:34 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <09d4c3ca-6a20-4986-b3e5-e3c4fc64fddd@m17g2000vbi.googlegroups.com> <79a3cd31-2f79-44f4-8a00-a47ceb46eaee@s28g2000vbp.googlegroups.com> <782l00F1k9ajiU1@mid.individual.net> <1df327cf-67a3-4250-819f-6baf5bb59b11@h23g2000vbc.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1243607134 20486 127.0.0.1 (29 May 2009 14:25:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 May 2009 14:25:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n21g2000vba.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:3810 comp.lang.vhdl:1269 On May 28, 8:32=A0pm, Jacko wrote: >'Inferred latches for signal' is quite a > strange phrase, maybe 'possible forgotten signal assignment' would be > better. It only seems to be if ... then ... else ... end if; which > generates inferred latches. case and if ... then ... end if; does not > seem to. I guess this is because no else is definite latch/register, > and case can contain many places of non assignment and so could flood > the message display. It's not that strange really. I agree, it is not that strange... But it really has nothing to do with missing "else" statements. It only has to do with missed assignments. Complex if/elsif or case statements just make it much easier to miss an assignment. Unfortunately, simply adding an "else" for every "if" is not guaranteed to catch every missed assignment. If combinatorial processes are needed/desired, the best coding mechanism to ensure a latch-free implementation is to include a default assignment for every driven signal, right up front in the process. This is the simplest coding method to write, review, audit and maintain, because then it simply does not matter whether you have an "else" for every "if", or an assignment in every branch of a case statement. Andy From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!newsfeed.datemas.de!weretis.net!feeder2.news.weretis.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Version Control for VHDL Project Date: Sat, 30 May 2009 10:10:07 +0200 Organization: T-Online Lines: 53 Message-ID: References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> <6acc113a-c9c4-4455-a04f-fb1c59f2e4b7@w31g2000prd.googlegroups.com> <871vq8cb5o.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1243671007 02 n19065 lM5FQ7UvyE3AcB4 090530 08:10:07 X-Complaints-To: usenet-abuse@t-online.de X-ID: bcI7YcZereBMioU+16z3qu9zZQ27WD01vhMFOGFZz2b2w0IRckct8L User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <871vq8cb5o.fsf@harnisch.dyndns.org> Xref: news.eternal-september.org comp.lang.vhdl:1270 Marcus Harnisch schrieb: > > No. Because that is not the way KJ wants it to work as far as I > understand it. While this is not my development style, I think this is > a perfectly valid request. > > 1. KJ wants to be able to check out Project1, which refers > Project2. Whenever Project1 is checked out, the most recent > revision of Project2 should be checked out into the subdirectory of > Project1. > > 2. While he is working on Project1, he occasionally updates the > Project2 subdirectory to stay up-to-date. At some point KJ wants to > take a snapshot of his Project1 workspace *including* the current > state of all externals (i.e. Project2). In order to do that, > Subversion requires you to put explicit revision numbers into > externals property, which means that upon the next check out of > Project1, that same revision of Project2 is checked ut as well. But > that's not what he wants (see 1.). He doesn't want to be bothered > with revision numbers just to create a (recreatable) snapshot of > the current state of his workspace. > Hi, from a work-flow view point, I see at least one major problem with this methodology. If you are designing everything yourself in the course of personal multi-tasking then it's fine, but as soon as a team is involved I regard it as highly risky. The head should really carry the tag 'under development'. I know several companies where the head is also used as a sort of 'light-weight back-up'. A check-in is done on fridays, before the developer goes on a course, holidays etc. and of course in larger companies whenever the administrator needs to migrate the archive to a different server (even if this is a seldom occurence). Also, it's very useful to be able to check into the head from a workstation and pick it up again from a lap-top when on the road and continue working. Of course you could argue that the developer should make a branch first and work there, merging back to trunk when he is finished. But this is only forcing the responsibility on the developer of the reusable. The flow is basically the same. You still need two 'streams' trunk/tags or branches/trunk. I prefer the trunk/tags because it usually makes the developer think of a tag name when he does the 'svn copy' even if it is only 20090529a. But even that is better than simply 'r8080' or whatever. An 'svn copy' to a tags or releases directory could be regarded as a 'contract'. The developer should be implicitly saying he has fixed/improved/extended something, tested it and now makes it generally available. IMHO, only reusables carrying this stamp should ever be incorporated into a super-project. Charles From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!nlpi057.nbdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi147.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <2eb4ac53-c176-4a13-80aa-1aed8e2f522b@p4g2000vba.googlegroups.com> <4A0F4D22.5010907@gmail.com> <80a11091-0540-43da-832a-38980c3a8b55@o30g2000vbc.googlegroups.com> <4A0F68F4.7080608@gmail.com> <%0CQl.22636$as4.22440@nlpi069.nbdc.sbc.com> <6sMQl.16871$pr6.7745@flpi149.ffdc.sbc.com> <226476e8-e93d-4d13-aa3a-20ab644b0b9e@g19g2000yql.googlegroups.com> <8e00787a-9a21-40d4-b565-03d0f7148bcd@d19g2000prh.googlegroups.com> <6acc113a-c9c4-4455-a04f-fb1c59f2e4b7@w31g2000prd.googlegroups.com> <871vq8cb5o.fsf@harnisch.dyndns.org> Subject: Re: Version Control for VHDL Project Lines: 168 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi147.ffdc.sbc.com 1243705300 ST000 99.184.242.197 (Sat, 30 May 2009 13:41:40 EDT) NNTP-Posting-Date: Sat, 30 May 2009 13:41:40 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[R_PJSCOXTEBS\Y@RHVOQH@FJT@QDDMEPWXODMMHXMTWA]EPUW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Sat, 30 May 2009 13:48:57 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1271 "Charles Gardiner" wrote in message news:gvqpkv$ijp$02$1@news.t-online.com... > Marcus Harnisch schrieb: > >> >> No. Because that is not the way KJ wants it to work as far as I >> understand it. While this is not my development style, I think this is >> a perfectly valid request. >> >> 1. KJ wants to be able to check out Project1, which refers >> Project2. Whenever Project1 is checked out, the most recent >> revision of Project2 should be checked out into the subdirectory of >> Project1. >> >> 2. While he is working on Project1, he occasionally updates the >> Project2 subdirectory to stay up-to-date. At some point KJ wants to >> take a snapshot of his Project1 workspace *including* the current >> state of all externals (i.e. Project2). In order to do that, >> Subversion requires you to put explicit revision numbers into >> externals property, which means that upon the next check out of >> Project1, that same revision of Project2 is checked ut as well. But >> that's not what he wants (see 1.). He doesn't want to be bothered >> with revision numbers just to create a (recreatable) snapshot of >> the current state of his workspace. >> > > Hi, > > from a work-flow view point, I see at least one major problem with this > methodology. If you are designing everything yourself in the course of > personal multi-tasking then it's fine, but as soon as a team is involved > I regard it as highly risky. Whether it's risky would depend on several other "usage-of-the-tool" factors (more later), but I can say our software group has multiple people all working concurrently and this is not an issue. However, they're also using SourceSafe which then dictates a different type of work flow anyway, but the bottom line is that when the integrator/builder person needs to create a build they simply add a label to the top level project like "xyz_Ver_1.0.10", then they check out that labelled version out and do their build. I'm not trying to get into the relative merits/demerits of SourceSafe versus Subversion here, my only points are: - It is simple for the builder to create a new version that can then be built - There are no manual steps or checks that must be done to create the labelled version, so there are no chances for mistakes when the those steps get skipped. During crunch time, near product release, when time is very valuable and scarce, the value of this probably should not be underestimated. - The build and test is a validation of what is in the trunk at a particular moment. [1] - That build can be recreated at any future time, regardless of what has happened in the repository > The head should really carry the tag 'under > development'. This seems to be an area where we differ somewhat. While I agree it is the 'under development' area, I don't think it should be used as scratch pad, commits to the trunk should be understood to be contributing to the development and should not 'break the build' or cause a test failure. > Also, it's very > useful to be able to check into the head from a workstation and pick it > up again from a lap-top when on the road and continue working. > That would be a misuse of commits in my opinion. It's just as easy to create a patch file and put the patch on the laptop, no commits are necessary to handle this situation. > Of course you could argue that the developer should make a branch first > and work there, merging back to trunk when he is finished. That would be the other way to do it. For the 'pick it up on the laptop later' scenario that you just described, the branch/merge would probably not be a very good way for the developer to handle the situation, that's one thing that patches are good for. For an extended development branch/merge makes more sense. The point of creating the branch in the first place is to totally decouple the widget from the trunk for the time being. It creates a private work area for the developer...for now. > But this is > only forcing the responsibility on the developer of the reusable. Since the developer is making the changes, this is where the responsibility belongs. Shoving the responsibility to each integrator to discern when the changes are completed (what notifies them to do this) and then make possibly numerous changes (i.e. to update all of his references to any newly changed things) and putting this task on the critical path to the build (since the task of updating those references can not even be started until after all the developers creates their new tags) at a time of high stress (getting the new build to fix the last problem/problems) is potentially error prone. > > An 'svn copy' to a tags or releases directory could be regarded as a > 'contract'. The developer should be implicitly saying he has > fixed/improved/extended something, tested it and now makes it generally > available. IMHO, only reusables carrying this stamp should ever be > incorporated into a super-project. > Contracts involve agreement between at least two parties and in this instance (the creation of a new tag by a developer) there appears to be only one, the developer. The creation of the new tag by a developer is not anything the integrator would willingly agree to (but it is something that can of course be imposed on them by local custom on how the version control tool should be used). What it means to the integrator is that they must now go in and update any references to the old thing that the developer made and have it now point to the new thing. Multiply this task by having several developers working on their own widgets and the integrator being responsible for producing several different product builds and you quickly have a potential mess...and ticked off integrator(s) who will greet each change as an onerous burden rather than a relatively straight forward thing to handle. Instead if the contract between integrator and developers is that things are only committed to the trunk when they are "fixed/improved/extended" then the integrator's work is straight forward, create a snapshot of the trunk (i.e. create a release tag) and build it. Doing so has the following benefits: - You haven't burdened the integrator to make changes in their stuff simply to accomodate a new commit by a developer. - You lessened the burden on the developer, there is no need for them to create a new tag to follow the commit that they just did. - You've lessened the need for problematic communication by the developer announcing the availability of their new widget since now the developer does not need to keep track of who all the integrators that might choose to use their widget. - The trunk then is the one place where one needs to go in order to get the absolute latest/greatest/believed-to-be-best Now of course the usual objection to this approach is that if the trunk is the 'golden code' and a developer commits something that has some problem with it then they've created a problem that needs to be fixed. OK, but the problem exists, it is checked in, it needs to be fixed. With the approach that you subscribe to, the developer has announced his new widget, the integrator(s) cheerfully updates all of their references to the new widget, does the builds and low and behold you're in the same spot, there is a problem that needs fixing. The only way you avoid having the problem appear is because of a breakdown in communication between developer and integrator where the integrator was unaware of the new widget and didn't update their references. Counting on a breakdown in your system is probably not a 'good' thing to rely on. Finding problems in the trunk early is better than finding them later. At crunch time, if the problem can not be easily fixed, the integrator can choose to roll back to the previous version by updating the references to widget to point to the earlier working version. The solution and effort for this work around is the same whether you follow my approach or yours, in my case though this effort is the exception rather than standard operating procedure. Thanks again for explaining how you go about doing things, it's always good to hear about different ways of approaching the same basic problem. Kevin Jennings [1] The assumption heres are that - Trunk code that references reusable components does so via references to components that do NOT specify specific revision levels (this would have to be manually checked by the integrator, but also can be automated somewhat and does not need to be a critical path thing to do) - The creation of the tag or labelled version locks down specific revision levels for that tag, but not to references that may be the trunk From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.news-service.com!goblin3!goblin.stu.neva.ru!lon-transit.news.telstra.net!pit-in1.telstra.net!news.telstra.net!news-south.connect.com.au!bunyip2.cc.uq.edu.au!not-for-mail From: Sarah Li Newsgroups: comp.lang.vhdl Subject: Constraint File Error: vhdl_bl3_ram8d_1.vhd Date: Sun, 31 May 2009 09:07:22 +0000 (UTC) Organization: UQ News Server Lines: 20 Message-ID: NNTP-Posting-Host: schizo.soe.uq.edu.au Mime-Version: 1.0 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: 8bit X-Trace: air.soe.uq.edu.au 1243760842 20853 130.102.6.144 (31 May 2009 09:07:22 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: Sun, 31 May 2009 09:07:22 +0000 (UTC) X-User-Real-E-Mail: s4177081@student.uq.edu.au User-Agent: PHP News Reader v2.6.4 (CDSHEEN) X-HTTP-Posting-Host: 172.20.200.222 Xref: news.eternal-september.org comp.lang.vhdl:1274 Hi, According to the solution to the following error, the file vhdl_bl3_ram8d_1.vhd is needed. ERROR:ConstraintSystem:59 - Constraint [vhdl_bl4.ucf(590)]: INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit4" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. However, I cannot find the file in any of my directories and online sites. So can anyone send me the file if they have it? Sorry if this has been posted before. Many thanks. Sarah Li From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: "eram.shaikh272@gmail.com" Newsgroups: comp.lang.vhdl Subject: Work at Home - Make $ 50 Per Hour , 100% Guaranteed Date: Mon, 1 Jun 2009 01:42:26 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <4efaa270-a93f-4479-9c9c-d784e0d88ec4@k2g2000yql.googlegroups.com> NNTP-Posting-Host: 117.98.108.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243845746 16587 127.0.0.1 (1 Jun 2009 08:42:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Jun 2009 08:42:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=117.98.108.151; posting-account=I-4vAQoAAAC5QtBmo24TZmdG2R6KPAYX User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/530.5 (KHTML, like Gecko) Chrome/2.0.172.2 Safari/530.5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1275 Work at Home - Make $ 50 Per Hour , 100% Guaranteed and for more details please logon http//:www.mulitilinesolutions.blogspot.com/ From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e20g2000vbc.googlegroups.com!not-for-mail From: "halwits23@gmail.com" Newsgroups: comp.lang.vhdl Subject: A Complete Web Development Solution | Halwasiya Infosys Date: Mon, 1 Jun 2009 03:28:49 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <04b2bd3a-15fd-476d-94b7-701b16da793c@e20g2000vbc.googlegroups.com> NNTP-Posting-Host: 122.161.81.110 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243852129 2631 127.0.0.1 (1 Jun 2009 10:28:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Jun 2009 10:28:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbc.googlegroups.com; posting-host=122.161.81.110; posting-account=nVruDQoAAABJiG7W5J6AOp-sTjekre_m User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.12) Gecko/20080201 Firefox/2.0.0.12,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1276 Dear Sir/Madam At last you found us! Halwasiya Infosys is the one-stop shop you have been looking for to fill all of your Web Development needs. From Logos to Web Sites to Facebook Applications to Iphone Applications to promoting your company on the web, we do it all and at very competitive prices. We use only the latest technologies and every project is completely customized to your needs. No templates are ever used. This is why more and more people are coming to us than anywhere else. We invite you to come inside to learn more about us and to view our work. When you are done looking around please visit our contact page to send us an email with your questions and so we can formally introduce ourselves. Some of the Services we provide:- 1) Website Design 2) Custom Web Solutions & Database Driven Websites 3) Facebook Application & Facebook Connect 4) MySpace Application 5) Offshore Development 6) Ecommerce Development 7) IPhone Application 8) Search Engine Marketing 9) Search Engine Optimisation Visit us at: www.halwasiyainfosys.com and get 20% Discount using the E- coupon code: XY78S Thanks & Regards Admin From newsfish@newsfish Wed Aug 19 13:24:54 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Constraint File Error: vhdl_bl3_ram8d_1.vhd Date: Mon, 01 Jun 2009 12:35:15 -0700 Lines: 12 Message-ID: <78iorlF1m7nioU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=Big5 Content-Transfer-Encoding: 7bit X-Trace: individual.net Tl7F2Jwx0XVrIJaFCKijdAwCndNus6UCnPopEJhTkuMbio+NGd Cancel-Lock: sha1:MqFECHfNhSjqpDr2Z4BB5cGYokU= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1277 Sarah Li wrote: > According to the solution to the following error, the file > vhdl_bl3_ram8d_1.vhd is needed. What do you mean? The reference in the error message is: vhdl_bl4.ucf Note that bl4 could be confused with b14. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!p4g2000vba.googlegroups.com!not-for-mail From: s Newsgroups: comp.lang.vhdl Subject: Islam Date: Tue, 2 Jun 2009 15:47:24 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <336e160c-0c28-4740-8923-47f3b57763b9@p4g2000vba.googlegroups.com> NNTP-Posting-Host: 79.172.174.179 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1243982845 14221 127.0.0.1 (2 Jun 2009 22:47:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Jun 2009 22:47:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p4g2000vba.googlegroups.com; posting-host=79.172.174.179; posting-account=DDacxgoAAACFgYOROa0bMJ7-olwBlig0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; GTB5; SLCC1; .NET CLR 2.0.50727; Media Center PC 5.0; .NET CLR 3.0.04506; InfoPath.2),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1278 Excuse me!! Would you stop for a moment?! O...man...Haven't you thought-one day- about yourself ? Who has made it? Have you seen a design which hasn't a designer ?! Have you seen a wonderful,delicate work without a worker ?! It's you and the whole universe!.. Who has made them all ?!! You know who ?.. It's "ALLAH",prise be to him. Just think for a moment. How are you going to be after death ?! Can you believe that this exact system of the universe and all of these great creation will end in in nothing...just after death! Have you thought, for a second, How to save your soul from Allah's punishment?! Haven't you thought about what is the right religion?! Read ... and think deeply before you answer.. It is religion of Islam. It is the religion that Mohammad-peace upon him- the last prophet, had been sent by. It is the religion that the right Bible- which is not distorted-has preached. Just have a look at The Bible of (Bernaba). Don't be emstional. Be rational and judge.. Just look..listen...compare..and then judge and say your word. We advise you visiting : http://www.islam-guide.com http://www.thetruereligion.org http://www.beconvinced.com http://www.plaintruth.org http://english.islamway.com http://www.todayislam.com http://www.prophetmuhammed.org http://www.islamtoday.net/english/ http://www.islamunveiled.org http://www.islamic-knowledge.com From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!j32g2000yqh.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: So, they started synthesizing shared variables? Date: Wed, 3 Jun 2009 01:17:15 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244017035 21548 127.0.0.1 (3 Jun 2009 08:17:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 3 Jun 2009 08:17:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j32g2000yqh.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1279 Ive always been told categorically that "Shared variables cannot be synthesized, Use signals for communication between processes" But now it appears at least Quartus does. I have infered a ram using one, plus also this interesting setup. shared variable C : std_logic; begin process(clk) begin if rising_edge(clk) then C := data_a; end if; end process; process(clk) begin if rising_edge(clk) then --c := data_b; q_b <= C; end if; end process; >From synthesis, this gives me 2 registers, source from data_a. If I uncomment the C assignment in the 2nd process, I only get 1 register driven from data_b, with no warning about multiple constant drivers, like you would if C was a signal. So, is this an interesting and potentially dangerous precident Altera are setting, or is this happening with other synthesisors too? would shared variables actually have any use anywhere? From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 03 Jun 2009 04:12:26 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 03 Jun 2009 10:09:37 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 58 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Hlxwt4kIv9fCcUiZ43U5mcFFnu8l8c4J7Ozs0E22TSWH/uc5r38wtJOBrnm1cg5d61Yoa9ruCyNh6/7!0cRXZ2Zc2RUp2bORlMokaY/c0OYOGmoeUJNhQiKfBByXXeiq8RQ5P+MgH6wXn3S2zi2Q5yhLHaeX!/SaHSZGS5NXkcApe X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3244 Xref: news.eternal-september.org comp.lang.vhdl:1280 On Wed, 3 Jun 2009 01:17:15 -0700 (PDT), Tricky wrote: >Ive always been told categorically that "Shared variables cannot be >synthesized, Use signals for communication between processes" yeah, I thought that too... >But now it appears at least Quartus does. I have infered a ram using >one, I speculate that it's RAM inference that led them to support shared variables. It provides a straightforward way to do dual-port RAM with read-before-write, which is otherwise rather hard to do in VHDL. > plus also this interesting setup. [...] Yes, I first saw this (unnecessary) use of shared variables at a customer where I was doing some design work - I nearly spilt my coffee over the keyboard :-) >So, is this an interesting and potentially dangerous precident Altera >are setting I think it is, yes. Unfortunately it's a precedent that has *already* been set by Verilog, where shared variables are a (largely undesirable) fact of life. So it is not a big step for a synthesis tool. But it is a sure-fire way for VHDL programmers to get all the same dreadful race conditions that plague careless Verilog users. Note that this form of shared variable is, properly speaking, illegal now in VHDL; you should be using protected types. However, all tools still support the VHDL-93 hooligan form of shared variable (equivalent to Verilog's shared variables using blocking assignment). >shared variables actually have any use anywhere? To the best of my understanding, their only use in synthesisable code would be the modeling of dual-port RAM with different write clocks on the two ports. They have many interesting uses in testbenches, of course. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.erje.net!xlned.com!feeder3.xlned.com!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!pe1.news.blueyonder.co.uk!blueyonder!text.news.virginmedia.com!53ab2750!not-for-mail From: Dave Farrance Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Organization: Farry's Pad Message-ID: References: X-Newsreader: Forte Agent on Wine 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 15 Date: Wed, 03 Jun 2009 09:56:49 GMT NNTP-Posting-Host: 92.233.40.23 X-Complaints-To: http://netreport.virginmedia.com X-Trace: text.news.virginmedia.com 1244023009 92.233.40.23 (Wed, 03 Jun 2009 10:56:49 BST) NNTP-Posting-Date: Wed, 03 Jun 2009 10:56:49 BST Xref: news.eternal-september.org comp.lang.vhdl:1281 Tricky wrote: >Ive always been told categorically that "Shared variables cannot be >synthesized, Use signals for communication between processes" > >But now it appears at least Quartus does. I have infered a ram using >one, plus also this interesting setup. > ... Maybe the synthesiser has grouped the processes together because they are both triggered on the same rising_edge(clk), making C absorb unambiguously into q_b? I don't know how other synthesisers would handle it. -- Dave Farrance From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k2g2000yql.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 3 Jun 2009 03:03:13 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244023393 8479 127.0.0.1 (3 Jun 2009 10:03:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 3 Jun 2009 10:03:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k2g2000yql.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1282 On 3 June, 10:56, Dave Farrance wrote: > Tricky wrote: > >Ive always been told categorically that "Shared variables cannot be > >synthesized, Use signals for communication between processes" > > >But now it appears at least Quartus does. I have infered a ram using > >one, plus also this interesting setup. > > ... > > Maybe the synthesiser has grouped the processes together because they are > both triggered on the same rising_edge(clk), making C absorb unambiguousl= y > into q_b? =A0I don't know how other synthesisers would handle it. > > -- > Dave Farrance If it did that then the same would apply if C was a signal - when C is declared as a signal, it throws an error saying multiple constant drivers on C. If it combined the 2 processes, it wouldnt complain and just take the last assignment to C. From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!h18g2000yqj.googlegroups.com!not-for-mail From: HT-Lab Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 3 Jun 2009 03:57:02 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> References: NNTP-Posting-Host: 86.16.123.60 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244026622 18264 127.0.0.1 (3 Jun 2009 10:57:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 3 Jun 2009 10:57:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h18g2000yqj.googlegroups.com; posting-host=86.16.123.60; posting-account=6NNIQAkAAAAJrC4b290k1fuKOv2yco5N User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1283 On Jun 3, 9:17=A0am, Tricky wrote: "Tricky" wrote in message news:d3545c34-d074-41b5- b565-71da45810fae@j32g2000yqh.googlegroups.com... > Ive always been told categorically that "Shared variables cannot be > synthesized, Use signals for communication between processes" > > But now it appears at least Quartus does. Precision seems to support it as well although it does give a warning: [43156]: Shared variables must be of a protected type. It gives the same results as you describe below. Hans www.ht-lab.com >I have infered a ram using > one, plus also this interesting setup. > > shared variable C : std_logic; > > begin > > process(clk) > begin > if rising_edge(clk) then > C :=3D data_a; > end if; > end process; > > process(clk) > begin > if rising_edge(clk) then > --c :=3D data_b; > > q_b <=3D C; > end if; > end process; > > From synthesis, this gives me 2 registers, source from data_a. If I > uncomment the C assignment in the 2nd process, I only get 1 register > driven from data_b, with no warning about multiple constant drivers, > like you would if C was a signal. > > So, is this an interesting and potentially dangerous precident Altera > are setting, or is this happening with other synthesisors too? would > shared variables actually have any use anywhere? From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!pe1.news.blueyonder.co.uk!blueyonder!text.news.virginmedia.com!53ab2750!not-for-mail From: Dave Farrance Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Organization: Farry's Pad Message-ID: References: X-Newsreader: Forte Agent on Wine 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 14 Date: Wed, 03 Jun 2009 11:22:10 GMT NNTP-Posting-Host: 92.233.40.23 X-Complaints-To: http://netreport.virginmedia.com X-Trace: text.news.virginmedia.com 1244028130 92.233.40.23 (Wed, 03 Jun 2009 12:22:10 BST) NNTP-Posting-Date: Wed, 03 Jun 2009 12:22:10 BST Xref: news.eternal-september.org comp.lang.vhdl:1284 Tricky wrote: >If it did that then the same would apply if C was a signal - when C is >declared as a signal, it throws an error saying multiple constant >drivers on C. If it combined the 2 processes, it wouldnt complain and >just take the last assignment to C. I see. The shared variable assignments are computed sequentially within the scope of the shared variable, so I guess that the behaviour that you describe would be correct for simulation. I agree that allowing synthesis, just because it can in this case, is very questionable. -- Dave Farrance From newsfish@newsfish Wed Aug 19 13:24:55 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!pe1.news.blueyonder.co.uk!blueyonder!text.news.virginmedia.com!53ab2750!not-for-mail From: Dave Farrance Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Organization: Farry's Pad Message-ID: References: X-Newsreader: Forte Agent on Wine 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 12 Date: Wed, 03 Jun 2009 12:27:26 GMT NNTP-Posting-Host: 92.233.40.23 X-Complaints-To: http://netreport.virginmedia.com X-Trace: text.news.virginmedia.com 1244032046 92.233.40.23 (Wed, 03 Jun 2009 13:27:26 BST) NNTP-Posting-Date: Wed, 03 Jun 2009 13:27:26 BST Xref: news.eternal-september.org comp.lang.vhdl:1285 Dave Farrance wrote: >I see. The shared variable assignments are computed sequentially within >the scope of the shared variable, so I guess that the behaviour that you >describe would be correct for simulation. Ah. I see that the Std 1076-1993 spec says it's not. Para 225: "... A description is erroneous if it depends on whether or how an implementation sequentializes access to shared variables." -- Dave Farrance From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 03 Jun 2009 09:26:30 -0700 Lines: 14 Message-ID: <78nmhnF1lohc1U1@mid.individual.net> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qY29Lzu/wIGuiKkskcP+rgQ6kWKeB4mcuNOYcmakttTvzSo5ys Cancel-Lock: sha1:FseqTcKAXoPHJCqrka5nlskrzuM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1287 HT-Lab wrote: > Precision seems to support it as well although it does give a warning: > [43156]: Shared variables must be of a protected type. > It gives the same results as you describe below. It might be possible to rewrite Tricky's model using protected types. That would eliminate the modelsim warnings, but I don't know if quartus and precision would still buy it. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 03 Jun 2009 11:39:31 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 03 Jun 2009 17:36:45 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-f0XXCdaVneGEPTDBgMmRfQJnq7VkQQhD51zW3XafuCEJmo0u14F+4HVxKO77/4srMBL7D2WneAXKU5z!8kckPi60FxulPqvREzkG6sD4amEwy6TjiNqu5UeEfiXgi8ClSuK4n9bs9b2zoydPIWybDodctyvF!VtjpMe2z4v4cvhUV X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2417 Xref: news.eternal-september.org comp.lang.vhdl:1288 On Wed, 03 Jun 2009 09:26:30 -0700, Mike Treseler wrote: >HT-Lab wrote: > >> Precision seems to support it as well although it does give a warning: >> [43156]: Shared variables must be of a protected type. >> It gives the same results as you describe below. > >It might be possible to rewrite Tricky's >model using protected types. >That would eliminate the modelsim warnings, >but I don't know if quartus and precision >would still buy it. I'm not entirely sure I understand what a protected type method would look like in hardware, but I'm happy to be educated if anyone can explain. Note that some simulators are not yet supporting VHDL protected types, so you need to be a little circumspect when using shared variables. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 03 Jun 2009 10:49:37 -0700 Lines: 17 Message-ID: <78nrdiF1kpvloU1@mid.individual.net> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net srI8kvNAnsos8s2Yn9v0ZgI/AB67ab+Cf/VImcvj5ASysQ8Oi9 Cancel-Lock: sha1:qRH7IxI4R5QJQ7Chh8JoiL6XKYk= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1289 Jonathan Bromley wrote: > I'm not entirely sure I understand what a protected > type method would look like in hardware, but I'm > happy to be educated if anyone can explain. It is not necessary to employ a shared variable for a single port ram because a plain variable works fine. http://mysite.verizon.net/miketreseler/block_ram.vhd For a dual-port ram, two processes are needed to match the given hardware. I would declare the protected types/bodies in architecture scope, rather than in a package, so that the procedures have full access to the shared array. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 3 Jun 2009 21:26:06 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 25 Sender: mdhicks2@outside.world Message-ID: <6004390c229b58cbb27f2171932e@news.acm.uiuc.edu> References: NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1244064361 9421 98.220.249.110 (3 Jun 2009 21:26:01 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Wed, 3 Jun 2009 21:26:01 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1290 > > Unfortunately it's a precedent that has *already* been set > by Verilog, where shared variables are a (largely undesirable) > fact of life. So it is not a big step for a synthesis tool. > But it is a sure-fire way for VHDL programmers to get all > the same dreadful race conditions that plague careless > Verilog users. > Note that this form of shared variable is, properly speaking, > illegal now in VHDL; you should be using protected types. > However, all tools still support the VHDL-93 hooligan form > of shared variable (equivalent to Verilog's shared variables > using blocking assignment). In my verilog experience, no synthesizer will allow the type of behavior you speak of. Can you give me an example that is synthesizable? By the way, if you look at the synthesis standards for VHDL (IEEE 1076.6-2004) it clearly says shared variables aren't supported. So a designer shouldn't be using them even if tool support is there. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.84.MISMATCH!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Date: Thu, 04 Jun 2009 08:43:57 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Islam References: <336e160c-0c28-4740-8923-47f3b57763b9@p4g2000vba.googlegroups.com> In-Reply-To: <336e160c-0c28-4740-8923-47f3b57763b9@p4g2000vba.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 2 Message-ID: <4a276d2e$0$194$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 80.127.156.245 X-Trace: 1244097839 news.xs4all.nl 194 [::ffff:80.127.156.245]:51369 X-Complaints-To: abuse@xs4all.nl Xref: news.eternal-september.org comp.lang.vhdl:1291 Please make sure your code compiles before putting it on the mailinglist. Written like this, we honestly can't help you. From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!news.eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Jun 2009 02:41:42 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 08:38:54 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <6004390c229b58cbb27f2171932e@news.acm.uiuc.edu> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 49 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-6QfBuZEgYh4RwkfJwDrMI7JJ1oiXB5hG5V/tO+v3IgY8tFlmZBc79e4FkQm+O7kbGcca+GxOFC1/6Af!2rx2jUmq62k7wNOahJP36Z5ENz8hyNI4lMUlwsPjI5Of3xIFk8fIHyV0LAs5CLnP8SsehMynKr9j!OreOVDzYK0hARP9W X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2951 Xref: news.eternal-september.org comp.lang.vhdl:1292 On Wed, 3 Jun 2009 21:26:06 +0000 (UTC), Matthew Hicks wrote: >> However, all tools still support the VHDL-93 hooligan form >> of shared variable (equivalent to Verilog's shared variables >> using blocking assignment). > >In my verilog experience, no synthesizer will allow the type of behavior >you speak of. My bad; when I said "all tools" I intended to say "all simulators". Apologies. > Can you give me an example that is synthesizable? I agree that Verilog variables *written by more than one process* are not generally synthesizable. However, synthesis tools DO support this (very, very bad) Verilog: reg q; // shared variable, because it's written by = assignment reg r; // like a VHDL signal, because written by <= always @(posedge clock) q = d; always @(posedge clock) r <= q; // read/write race on q because it's a shared var Of course, sensible Verilog users would immediately point out that I should have used <= assignment to q. But the fact remains that synthesis tools support what I wrote above, giving rise to sim/synth mismatch just as you would get with a VHDL shared variable. >By the way, if you look at the synthesis standards for VHDL (IEEE 1076.6-2004) >it clearly says shared variables aren't supported. So a designer shouldn't >be using them even if tool support is there. I agree. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!postnews.google.com!q16g2000yqg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 03:10:41 -0700 (PDT) Organization: http://groups.google.com Lines: 122 Message-ID: <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244110241 15820 127.0.0.1 (4 Jun 2009 10:10:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 10:10:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q16g2000yqg.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1293 On 3 June, 17:36, Jonathan Bromley wrote: > On Wed, 03 Jun 2009 09:26:30 -0700, Mike Treseler > > wrote: > >HT-Lab wrote: > > >> Precision seems to support it as well although it does give a warning: > >> [43156]: Shared variables must be of a protected type. > >> It gives the same results as you describe below. > > >It might be possible to rewrite Tricky's > >model using protected types. > >That would eliminate the modelsim warnings, > >but I don't know if quartus and precision > >would still buy it. > > I'm not entirely sure I understand what a protected > type method would look like in hardware, but I'm > happy to be educated if anyone can explain. > > Note that some simulators are not yet supporting > VHDL protected types, so you need to be a little > circumspect when using shared variables. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Having a quick play, Quartus doesnt even want to know about protected types, so I assume they havent gone beyond VHDL 93 (93/87 are the only two settings). But what was iteresting was it said it was expecting other stuff, including access, instead of protected. So I tried infering a ram via an access type and shared variable. Quartus just ploughed on, didnt throw a warning about access, but seemed to ignore that it existed (therefore, just assumed everything was connected to thin air - not really a surprise). Not even a warning saying access types are not synthesizable. Heres what I tried to synthesize(be interesting to see what other synth tools do): entity test_build is port( clk : in std_logic; addr_a : in natural range 0 to 127; addr_b : in natural range 0 to 127; data_a : in std_logic_vector(7 downto 0); q_b : out std_logic_vector(7 downto 0) ); end entity test_build; architecture syn of test_build is type ram_t; type ram_t_p is access ram_t; type ram_t is array(0 to 127) of std_logic_vector(7 downto 0); --type ram_t is protected -- function read(a : natural) return std_logic_vector; -- procedure write(a : natural; d : std_logic_vector); --end protected type ram_t; -- --type ram_t is protected body -- type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); -- variable ram_array : ram_array_t; -- -- function read(a : natural) return std_logic_vector is -- begin -- return ram_array(a); -- end function read; -- -- procedure write(a : natural; d : std_logic_vector) is -- begin -- ram_array(a) := d; -- end procedure write; -- --end protected type ram_t; shared variable ram : ram_t_p := new ram_t; signal addr_b_r : natural range 0 to 127; begin process(clk) begin if rising_edge(clk) then ram(addr_a) := data_a; end if; end process; process(clk) begin if rising_edge(clk) then addr_b_r <= addr_b; end if; end process; q_b <= ram(addr_b_r); end architecture syn; From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.z74.net!news.z74.net!goblin1!goblin2!goblin.stu.neva.ru!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe10.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> Subject: Re: So, they started synthesizing shared variables? Lines: 92 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <_ONVl.1117$h21.294@newsfe10.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe10.ams2 1244113210 86.16.123.60 (Thu, 04 Jun 2009 11:00:10 UTC) NNTP-Posting-Date: Thu, 04 Jun 2009 11:00:10 UTC Organization: virginmedia.com Date: Thu, 4 Jun 2009 12:00:04 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1294 "Tricky" wrote in message news:924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com... > On 3 June, 17:36, Jonathan Bromley > wrote: >> On Wed, 03 Jun 2009 09:26:30 -0700, Mike Treseler >> >> wrote: >> >HT-Lab wrote: >> >> >> Precision seems to support it as well although it does give a warning: >> >> [43156]: Shared variables must be of a protected type. >> >> It gives the same results as you describe below. >> >> >It might be possible to rewrite Tricky's >> >model using protected types. >> >That would eliminate the modelsim warnings, >> >but I don't know if quartus and precision >> >would still buy it. >> >> I'm not entirely sure I understand what a protected >> type method would look like in hardware, but I'm >> happy to be educated if anyone can explain. >> >> Note that some simulators are not yet supporting >> VHDL protected types, so you need to be a little >> circumspect when using shared variables. >> -- >> Jonathan Bromley, Consultant >> >> DOULOS - Developing Design Know-how >> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services >> >> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK >> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com >> >> The contents of this message may contain personal views which >> are not the views of Doulos Ltd., unless specifically stated. > > Having a quick play, Quartus doesnt even want to know about protected > types, so I assume they havent gone beyond VHDL 93 (93/87 are the only > two settings). But what was iteresting was it said it was expecting > other stuff, including access, instead of protected. > > So I tried infering a ram via an access type and shared variable. > Quartus just ploughed on, didnt throw a warning about access, but > seemed to ignore that it existed (therefore, just assumed everything > was connected to thin air - not really a surprise). Not even a warning > saying access types are not synthesizable. > > Heres what I tried to synthesize(be interesting to see what other > synth tools do): Not much luck in Precision either... [40000]: vhdlorder, Release 2009a.15 [40000]: Files sorted successfully. [40000]: hdl-analyze, Release RTLC-Precision 2009a.15 [42502]: Analyzing input file "D:/test/shared_var/test2.vhd" ... [43156]: Shared variables must be of a protected type. [651]: Top module of the design is set to: test_build. [649]: Current working directory: <...>/shared_var/project_2_impl_1. [40000]: RTLC-Driver, Release RTLC-Precision 2009a.15 [40000]: Last compiled on Mar 18 2009 18:40:36 [44512]: Initializing... [44504]: Partitioning design .... [40000]: RTLCompiler, Release RTLC-Precision 2009a.15 [40000]: Last compiled on Mar 18 2009 19:20:03 [44512]: Initializing... [44522]: Root Module work.test_build(syn): Pre-processing... [45258]: Object ram is of Non-Rtl type ram_t_p. Declaration wont be compiled. [46831]: Object ram of Non-Rtl type ram_t_p not handled. Continuing ... [46292]: Module work.test_build(syn) cannot be compiled because it contains non-rtl constructs. Please check the log for warnings or errors about non-synthesizable constructs in this module. [44536]: No modules were compiled in this run of RTLC, please check the logs for blackboxes or non-rtl constructs in the design. [44856]: Total lines of RTL compiled: 68. [47002]: RTLCompiler error... aborting compilation. [44513]: Overall running time 3.0 secs. [46259]: Design compilation failed, unsupported or non-rtl constructs detected in the following modules : [40000]: work.test_build(syn) [40000]: Please check the log for details pertaining to unsupported or non-rtl construct(s) [666]: Unable to elaborate design work.test_build in vhdl. Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:24:56 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!j18g2000yql.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 07:11:44 -0700 (PDT) Organization: http://groups.google.com Lines: 97 Message-ID: References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244124704 27785 127.0.0.1 (4 Jun 2009 14:11:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 14:11:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000yql.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1295 On 4 June, 12:00, "HT-Lab" wrote: > "Tricky" wrote in message > > news:924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com... > > > > > On 3 June, 17:36, Jonathan Bromley > > wrote: > >> On Wed, 03 Jun 2009 09:26:30 -0700, Mike Treseler > > >> wrote: > >> >HT-Lab wrote: > > >> >> Precision seems to support it as well although it does give a warning: > >> >> [43156]: Shared variables must be of a protected type. > >> >> It gives the same results as you describe below. > > >> >It might be possible to rewrite Tricky's > >> >model using protected types. > >> >That would eliminate the modelsim warnings, > >> >but I don't know if quartus and precision > >> >would still buy it. > > >> I'm not entirely sure I understand what a protected > >> type method would look like in hardware, but I'm > >> happy to be educated if anyone can explain. > > >> Note that some simulators are not yet supporting > >> VHDL protected types, so you need to be a little > >> circumspect when using shared variables. > >> -- > >> Jonathan Bromley, Consultant > > >> DOULOS - Developing Design Know-how > >> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > >> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > >> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > >> The contents of this message may contain personal views which > >> are not the views of Doulos Ltd., unless specifically stated. > > > Having a quick play, Quartus doesnt even want to know about protected > > types, so I assume they havent gone beyond VHDL 93 (93/87 are the only > > two settings). But what was iteresting was it said it was expecting > > other stuff, including access, instead of protected. > > > So I tried infering a ram via an access type and shared variable. > > Quartus just ploughed on, didnt throw a warning about access, but > > seemed to ignore that it existed (therefore, just assumed everything > > was connected to thin air - not really a surprise). Not even a warning > > saying access types are not synthesizable. > > > Heres what I tried to synthesize(be interesting to see what other > > synth tools do): > > Not much luck in Precision either... > > [40000]: vhdlorder, Release 2009a.15 > [40000]: Files sorted successfully. > [40000]: hdl-analyze, Release RTLC-Precision 2009a.15 > [42502]: Analyzing input file "D:/test/shared_var/test2.vhd" ... > [43156]: Shared variables must be of a protected type. > [651]: Top module of the design is set to: test_build. > [649]: Current working directory: <...>/shared_var/project_2_impl_1. > [40000]: RTLC-Driver, Release RTLC-Precision 2009a.15 > [40000]: Last compiled on Mar 18 2009 18:40:36 > [44512]: Initializing... > [44504]: Partitioning design .... > [40000]: RTLCompiler, Release RTLC-Precision 2009a.15 > [40000]: Last compiled on Mar 18 2009 19:20:03 > [44512]: Initializing... > [44522]: Root Module work.test_build(syn): Pre-processing... > [45258]: Object ram is of Non-Rtl type ram_t_p. Declaration wont be > compiled. > [46831]: Object ram of Non-Rtl type ram_t_p not handled. Continuing ... > [46292]: Module work.test_build(syn) cannot be compiled because it contains > non-rtl constructs. Please check the log for warnings or errors about > non-synthesizable constructs in this module. > [44536]: No modules were compiled in this run of RTLC, please check the logs > for blackboxes or non-rtl constructs in the design. > [44856]: Total lines of RTL compiled: 68. > [47002]: RTLCompiler error... aborting compilation. > [44513]: Overall running time 3.0 secs. > [46259]: Design compilation failed, unsupported or non-rtl constructs > detected in the following modules : > [40000]: work.test_build(syn) > [40000]: Please check the log for details pertaining to unsupported or > non-rtl construct(s) > [666]: Unable to elaborate design work.test_build in vhdl. > > Hanswww.ht-lab.com Well that is interesting, the fact that it recognises protected types. Any chance you could take the code I posted and use the protected type instead of the pointer? see what it does what that? From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r13g2000vbr.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 07:38:19 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <6004390c229b58cbb27f2171932e@news.acm.uiuc.edu> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244126299 22163 127.0.0.1 (4 Jun 2009 14:38:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 14:38:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000vbr.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1296 On Jun 4, 2:38=A0am, Jonathan Bromley wrote: > On Wed, 3 Jun 2009 21:26:06 +0000 (UTC), Matthew Hicks wrote: > >By the way, if you look at the synthesis standards for VHDL (IEEE 1076.6= -2004) > >it clearly says shared variables aren't supported. =A0So a designer shou= ldn't > >be using them even if tool support is there. > > I agree. It is my understanding (perhaps flawed) that the VHDL Synthesis Standard sets the minimum set of the language to be supported by synthesis. Shared variables are not required to be supported by a compliant synthesis tool. If it sets limits on which VHDL constructs/ features CAN be supported, then it becomes a tremendous detriment to the advancement of synthesis capabilities in general, since no vendor will support it until it becomes part of the standard, and no vendor will spend their money to develop a new capability if they cannot use it any sooner than their competition. We should seriously consider the adverse effects on the development of synthesis technology before we advise ourselves and others to avoid anything not already documented in "the" synthesis standard. Various individuals and their employers have differing needs WRT portability across multiple synthesis tools. As it is, we have an agreement that synthesis results' behavior must be consistent with simulation (or else at least warnings are issued), and market competitiveness drives innovation (e.g. multiple clock-edge processes, handling of signal assignments after the clocked clause, etc.) In this case of shared variables, there are serious potential issues with simulation mismatch, but none that could not be handled by limiting the synthesizeable subset of shared variables such that simulation and synthesis will agree. In the bargain, we get the ability to store more abstract and/or efficient data types(enumerated types, integers, records, etc.) in an inferred dual port memory than is possible with instantiated primitives. Andy From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 16:38:45 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 81 Sender: mdhicks2@outside.world Message-ID: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> References: NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1244133525 8415 98.220.249.110 (4 Jun 2009 16:38:45 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Thu, 4 Jun 2009 16:38:45 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1297 > On Jun 4, 2:38 am, Jonathan Bromley > wrote: > >> On Wed, 3 Jun 2009 21:26:06 +0000 (UTC), Matthew Hicks wrote: >> >>> By the way, if you look at the synthesis standards for VHDL (IEEE >>> 1076.6-2004) >>> it clearly says shared variables aren't supported. So a designer >>> shouldn't >>> be using them even if tool support is there. >> I agree. >> > It is my understanding (perhaps flawed) that the VHDL Synthesis > Standard sets the minimum set of the language to be supported by > synthesis. Shared variables are not required to be supported by a > compliant synthesis tool. IEEE 1076.6 states, "The intent of this version was to include a maximum subset of VHDL that could be used to describe synthesizable RTL logic." The standard does include MAY rules which leave open to interpretation how certain constructs can be handled by synthesis tools. Shared is not one of those. > If it sets limits on which VHDL constructs > features CAN be supported, then it becomes a tremendous detriment to > the advancement of synthesis capabilities in general, since no vendor > will support it until it becomes part of the standard, and no vendor > will spend their money to develop a new capability if they cannot use > it any sooner than their competition. Since no synthesis tool currently meets the requirements, I don't think your logic holds. It seems most vendors use the standards as a guide and make language support decisions based upon what the majority of customers want. Remember that vendors can do what they want, the IEEE isn't going to stop them, they just can claim IEEE 1076.6 conformance. > > We should seriously consider the adverse effects on the development of > synthesis technology before we advise ourselves and others to avoid > anything not already documented in "the" synthesis standard. Various > individuals and their employers have differing needs WRT portability > across multiple synthesis tools. We should also think of the adverse affect of adding features and bloat to the tools/language just to meet the needs of a few. But, this is a religious argument akin to RISC vs CISC (<--- computer architectures). > > As it is, we have an agreement that synthesis results' behavior must > be consistent with simulation (or else at least warnings are issued), > and market competitiveness drives innovation (e.g. multiple clock-edge > processes, handling of signal assignments after the clocked clause, > etc.) I wish this were the case. I have had plenty of experiences with both Verilog and VHDL where synthesis differed from simulation, but the tool didn't care to inform me of the potential difference, when it could have. Maybe tool vendors should work on perfecting features before adding new, possibly buggy, ones. > > In this case of shared variables, there are serious potential issues > with simulation mismatch, but none that could not be handled by > limiting the synthesizeable subset of shared variables such that > simulation and synthesis will agree. In the bargain, we get the > ability to store more abstract and/or efficient data types(enumerated > types, integers, records, etc.) in an inferred dual port memory than > is possible with instantiated primitives. > > Andy > In this thread, I've seen no mention/proof of some unique utility provided by shared variables, but lots of problems. Dual-port ram isn't a good example as it is just a case of using search-and-replace on a highly constrained version of shared variables. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o20g2000vbh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 10:22:32 -0700 (PDT) Organization: http://groups.google.com Lines: 104 Message-ID: <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244136153 21059 127.0.0.1 (4 Jun 2009 17:22:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 17:22:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o20g2000vbh.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1298 On Jun 4, 11:38=A0am, Matthew Hicks wrote: > IEEE 1076.6 states, "The intent of this version was to include a maximum > subset of VHDL that could be used to describe synthesizable RTL logic." = =A0 > The standard does include MAY rules which leave open to interpretation ho= w > certain constructs can be handled by synthesis tools. =A0Shared is not on= e > of those. Like I said, my understanding of the intent of the standard could be flawed... :) > > If it sets limits on which VHDL constructs > > features CAN be supported, then it becomes a tremendous detriment to > > the advancement of synthesis capabilities in general, since no vendor > > will support it until it becomes part of the standard, and no vendor > > will spend their money to develop a new capability if they cannot use > > it any sooner than their competition. > > Since no synthesis tool currently meets the requirements, I don't think y= our > logic holds. =A0It seems most vendors use the standards as a guide and ma= ke > language support decisions based upon what the majority of customers want= . > =A0Remember that vendors can do what they want, the IEEE isn't going to s= top > them, they just can claim IEEE 1076.6 conformance. So we have a standard that no tool can or does correctly claim compliance to? How good a standard is that? My logic is that because the standard is what it is, no one follows it verbatim. In turn, because no one follows it verbatim, the standard must be flawed. > > We should seriously consider the adverse effects on the development of > > synthesis technology before we advise ourselves and others to avoid > > anything not already documented in "the" synthesis standard. Various > > individuals and their employers have differing needs WRT portability > > across multiple synthesis tools. > > We should also think of the adverse affect of adding features and bloat t= o > the tools/language just to meet the needs of a few. =A0But, this is a rel= igious > argument akin to RISC vs CISC (<--- computer architectures). Features sell, but bloat does not (usually); let the market decide. Standards are there to coax interoperability to the maximum extent practical. Vendors support and adhere to standards to the extent that those standards create/support a market, but in the end, the vendors support the market, as it should be. What discerns features from bloat in the standard? > > As it is, we have an agreement that synthesis results' behavior must > > be consistent with simulation (or else at least warnings are issued), > > and market competitiveness drives innovation (e.g. multiple clock-edge > > processes, handling of signal assignments after the clocked clause, > > etc.) > > I wish this were the case. =A0I have had plenty of experiences with both = Verilog > and VHDL where synthesis differed from simulation, but the tool didn't ca= re > to inform me of the potential difference, when it could have. =A0Maybe to= ol > vendors should work on perfecting features before adding new, possibly bu= ggy, > ones. Bugs exist, and most synthesis vendors will fix bugs related to simulation mismatch (except in traditional "accepted" ways like sensitivity lists, etc.) when they are brought to their attention. I think we can agree on perfecting existing features for sure! > > In this thread, I've seen no mention/proof of some unique utility provide= d > by shared variables, but lots of problems. =A0Dual-port ram isn't a good = example > as it is just a case of using search-and-replace on a highly constrained > version of shared variables. Shared variables allow inferring dual port rams with different clocks from arrays of any data type you want. Inferred memories allow storage of data not easily (if at all) described by SLV, and in a target- independent manner. Just because you say it is not a good example does not make it so. There may be flaws in the allowed use of shared variables (e.g. unprotected access), but the proof of unique utility is there nevertheless. I applaud vendors that try to advance the state of the art in synthesis. It is certainly more than the synthesis standard has accomplished lately (merely listing the existing capabilities that vendors had already come up with on their own). Andy From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!pfeed09.wxs.nl!newsfeed.kpn.net!pfeed08.wxs.nl!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 10:35:35 -0700 Lines: 17 Message-ID: <78qev8F1nepkuU1@mid.individual.net> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 3bRMGWMtrV8xoazAvQuN6A3vbynVpvOZM0i09YcePeQ/aQV6mQ Cancel-Lock: sha1:yHVcptq9WbZBRpTLdememBpA8Bo= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:1299 Matthew Hicks wrote: > I wish this were the case. I have had plenty of experiences with both > Verilog and VHDL where synthesis differed from simulation, but the tool > didn't care to inform me of the potential difference, when it could > have. As a counterpoint, I have coded vhdl and verilog on the edge for years using modelsim, quartus and ise. I found only one such bug, and none since. http://groups.google.com/groups/search?q=update_regs_bug What did you find? -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.velia.net!news.tu-darmstadt.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 10:47:29 -0700 Lines: 12 Message-ID: <78qfliF1mt04cU1@mid.individual.net> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <78qev8F1nepkuU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net YHcIDnPqBcyWYbb0meUQGglTgj84tVndMvhjzPSsp8I1Xwek8i Cancel-Lock: sha1:fVe+601aWfqaX0oCBfALTD6M6Lc= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <78qev8F1nepkuU1@mid.individual.net> Xref: news.eternal-september.org comp.lang.vhdl:1300 Mike Treseler wrote: > As a counterpoint, I have coded vhdl and verilog on the edge > for years using modelsim, quartus and ise. > I found only one such bug, and none since. > http://groups.google.com/groups/search?q=update_regs_bug After rereading that thread, there was a synthesis warning, so my total of cases breaking Andy's rule is still zero. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!b1g2000vbc.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 11:28:05 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <27990ef1-6264-4d36-b898-6cd5578d72c0@b1g2000vbc.googlegroups.com> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <78qev8F1nepkuU1@mid.individual.net> <78qfliF1mt04cU1@mid.individual.net> NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244140085 10446 127.0.0.1 (4 Jun 2009 18:28:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 18:28:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b1g2000vbc.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1301 On Jun 4, 1:47=A0pm, Mike Treseler wrote: > Mike Treseler wrote: > > As a counterpoint, I have coded vhdl and verilog on the edge > > for years using modelsim, quartus and ise. > > I found only one such bug, and none since. > >http://groups.google.com/groups/search?q=3Dupdate_regs_bug > > After rereading that thread, there was a synthesis > warning, so my total of cases breaking > Andy's rule is still zero. > > =A0 =A0 =A0 =A0 =A0 =A0 -- Mike Treseler I've recently been having a back-and-forth with Xilinx about what XST does when there's a top-level inout port with a VHDL init value of 'Z'. XST makes such a signal init to '0' - in other words, it doesn't set the INIT value of the tristate-enable register correctly. When they said they weren't going to fix it, I said that they should at least throw a warning or error about a sim/synth mismatch. This was the reply: I have reviewed the notes for case XXXXXX and understand the situation. In regards to adding a "mismatch" warning in XST, here are some thoughts: 1) Following synthesis, we expect customers to review the functionality of the generated netlist by looking at the post- synthesis netlist simulation, not the behavioral (RTL) simulation. 2) In several circumstances, XST already issues "potential simulation mismatch" where the post-synthesis netlist simulation can potentially show a mismatch on actual hardware behavior. As such, a "mismatch warning" is only applicable against the post-synthesis simulation, not the behavioral (RTL) simulation. Please let me know if the information in this e-mail explains the conclusion to this case. I guess their definition of a mismatch is different from mine. Dave From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!n4g2000vba.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 12:39:28 -0700 (PDT) Organization: http://groups.google.com Lines: 68 Message-ID: <89e7ad94-7a2b-425f-899d-23068dfeacbe@n4g2000vba.googlegroups.com> References: NNTP-Posting-Host: 98.246.136.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244144368 14722 127.0.0.1 (4 Jun 2009 19:39:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 19:39:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n4g2000vba.googlegroups.com; posting-host=98.246.136.75; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1302 Tricky, > Ive always been told categorically that "Shared variables cannot be > synthesized, Use signals for communication between processes" > > But now it appears at least Quartus does. I have infered a ram using > one, plus also this interesting setup. > > =A0 shared variable C : std_logic; > > begin > > =A0 Proc1: process(clk) > =A0 begin > =A0 =A0 if rising_edge(clk) then > =A0 =A0 =A0 C :=3D data_a; > =A0 =A0 end if; > =A0 end process; > > =A0 Proc2: process(clk) > =A0 begin > =A0 =A0 if rising_edge(clk) then > =A0 =A0 =A0 --c :=3D data_b; > > =A0 =A0 =A0 q_b <=3D C; > =A0 =A0 end if; > =A0 end process; > > From synthesis, this gives me 2 registers, source from data_a. If I > uncomment the C assignment in the 2nd process, I only get 1 register > driven from data_b, with no warning about multiple constant drivers, > like you would if C was a signal. Usage of shared variables in this example - independent of using either a protected type (only correct usage in 1076-2002 and beyond) or regular types (as temporarily defined in 1076-1993) - is always going to lead to quirky behavior in simulation. Either process can be executed first. If Proc2 runs first, there are two registers. If Proc1 runs first, there is only one register. Adding protected types only ensures that the access to the object is not interrupted in the middle - which really does not help or hurt this pair of processes. To be correct, synthesis results must match RTL simulation results. Since the RTL simulation is ambiguous for this example, there is no correct synthesis result for this problem. > So, is this an interesting and potentially dangerous precident Altera > are setting, or is this happening with other synthesisors too? would > shared variables actually have any use anywhere? I agree with your assessment and would consider it a bad investment on their part - unless they got it for free. Even then it is still a liability. I primarily use shared variables in testbenches where they are great for data structures and randomization. See http://www.synthworks.com/downloads= / for the randomziation packages we use. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 20:36:23 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 32 Sender: mdhicks2@outside.world Message-ID: <6004390c22c0a8cbb34159d58729@news.acm.uiuc.edu> References: <78qev8F1nepkuU1@mid.individual.net> NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1244147782 14479 98.220.249.110 (4 Jun 2009 20:36:22 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Thu, 4 Jun 2009 20:36:22 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1303 > Matthew Hicks wrote: > >> I wish this were the case. I have had plenty of experiences with >> both Verilog and VHDL where synthesis differed from simulation, but >> the tool didn't care to inform me of the potential difference, when >> it could have. >> > As a counterpoint, I have coded vhdl and verilog on the edge > for years using modelsim, quartus and ise. > I found only one such bug, and none since. > http://groups.google.com/groups/search?q=update_regs_bug > What did you find? > > -- Mike Treseler > I don't remember which tool I was using ModelSim or Active-HDL, but the problem centered around concatenating two signals together and switching on the result. I had to instead use an intermediate signal to hold the result of the operation, then switch on it, otherwise the code was optimized away during synthesis. This was a few years ago and may count as a bug, but I'm sure I have had the fun of hunting mismatch bugs before, but can't remember the situation. I just know that these bugs are the hardest (for me) to fix as I don't like playing around with post-synthesis simulations. Speaking of which, does anyone know of an automated tool that will equivalence check the behavior pre and post synthesis designs? ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:24:57 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!21g2000vbk.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 13:42:15 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> NNTP-Posting-Host: 98.246.136.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244148135 2954 127.0.0.1 (4 Jun 2009 20:42:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 20:42:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 21g2000vbk.googlegroups.com; posting-host=98.246.136.75; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1304 Andy, > I applaud vendors that try to advance the state of the art in > synthesis. It is certainly more than the synthesis standard has > accomplished lately (merely listing the existing capabilities that > vendors had already come up with on their own). Your ignorance is both insulting and part of the problem with getting the standards implemented. Among other things, 1076.6-2004 has coding styles for implementing dual port rams with different clocks. For a quick start on this standard, see the paper or slides on "IEEE 1076.6-2004: VHDL Synthesis Coding Styles for the Future" that is at: http://www.synthworks.com/papers/ If a vendor implements an inferior alternative to what is in 1076.6-2004 (and do not implement what is in 1076.6-2004), I would not call that advancing the state of the art. I would call it a bad investment. Please educate yourself on what is current and make sure your vendors are implementing the parts you need. Vendors are market driven and if you fail to do this, they will not implement it. If you need something that is not in 1076.6-2004, quit whining and get involved. There are quite a few of you here who are senior enough that you ought to be participating in standards development - if not driving the standards development. Participation is volunteer work. A typical committee will let anyone with a vested interested participate - ie: a VHDL user - after all free labor is free. Typically issues are resolved by consensus. Only when the group is polarized does an official membership vote come up. If you want to participate in those you will need to be a member of the appropriate groups (typically IEEE and DASC). 1076.6-1999 did as you said, listed a baseline set of existing capabilities that intellectual property developers could depend on all synthesis tools implementing. Its purpose was not to push the state of the art - its intent is allow model developers to claim compliance, and hence, if you purchased a compliant model you could count an a synthesis tool creating a good implementation. If not you then who? Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 14:06:54 -0700 Lines: 10 Message-ID: <78qrbfF1nfljiU1@mid.individual.net> References: <78qev8F1nepkuU1@mid.individual.net> <6004390c22c0a8cbb34159d58729@news.acm.uiuc.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net bumAHyjk8NjKFXg0s3SEfQ8My8PCwtOA8bjg30bwwBaotBsPJH Cancel-Lock: sha1:AuGB5Bv7+uRDFt3tKccXcKTzBrs= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <6004390c22c0a8cbb34159d58729@news.acm.uiuc.edu> Xref: news.eternal-september.org comp.lang.vhdl:1305 Matthew Hicks wrote: > Speaking of which, does anyone know of an automated tool that will > equivalence check the behavior pre and post synthesis designs? I rarely check post-synthesis, but when I do, I just compile the gate architecture over the rtl and rerun the testbench. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.pimp.lart.info!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!z7g2000vbh.googlegroups.com!not-for-mail From: VIPS Newsgroups: comp.lang.vhdl Subject: I2C SDA LINE Date: Thu, 4 Jun 2009 14:21:52 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: NNTP-Posting-Host: 70.108.245.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244150513 10386 127.0.0.1 (4 Jun 2009 21:21:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 21:21:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z7g2000vbh.googlegroups.com; posting-host=70.108.245.211; posting-account=WPnTdQoAAADxtUw2WpFzf9cv-eCysaC_ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 GTB5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1306 Hi All I am implementing the I2C Slave and i am using two data lines for sda input and sda output. MY question is that shall I expect from I2C bus to give me Z as input in place of 1 Shall I drive output 1 as Z to the sda_out Secondly We cannot synthesize Z as an input but can drive the output as Z any reason I have used an interal sda signal and sampled the SDA_input as SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the output /input to gnd and vcc in synthesis Pls specify Thanks Vipul From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 14:36:16 -0700 Lines: 21 Message-ID: <78qt2hF1ns04rU1@mid.individual.net> References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Wi8b6MJ8jxdnaBFNYQAGuwQ4/xcVAWzar9Kr77SyAHkp6flyQk Cancel-Lock: sha1:e/MhxiP/v8fNKobyj882zS9ftfM= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1307 JimLewis wrote: > If a vendor implements an inferior alternative to what is in > 1076.6-2004 (and do not implement what is in 1076.6-2004), I would > not call that advancing the state of the art. I would call it a bad > investment. Nevertheless, the fact is interesting to a least one reader of this newsgroup. > Please educate yourself on what is current and make sure your vendors > are implementing the parts you need. Vendors are market driven and > if you fail to do this, they will not implement it. I hear what you are saying, but consider the designer's point of view. I live in the moment with tightly budgeted time and money. I would like like nothing better than to work on logic description and synthesis all day, but that does not pay the bills. A few lines of text in the newsgroup is all I can afford. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!j20g2000vbp.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 14:59:05 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> NNTP-Posting-Host: 98.246.136.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244152745 17126 127.0.0.1 (4 Jun 2009 21:59:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 21:59:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j20g2000vbp.googlegroups.com; posting-host=98.246.136.75; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1308 Jon, > Note that some simulators are not yet supporting > VHDL protected types, so you need to be a little > circumspect when using shared variables. Care to name names? I have used protected types on both ModelSim and Aldec for quite some time now. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Jun 2009 17:02:29 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 22:59:41 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 57 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-9jNwfTcCRyADEteYJJcY/v3fjFWP8S9HqrBz6uQGVRbA3Q8ujNeGVs5ofxz23Epvbsv0JJFDYEIN1SR!owaBlt1MzFv/o3N9CQTD5vaK1ECuBrcIOPhSC/wVadMMyMag2NBJ8pErgHiHYfPOEOwtGucHX3oI!NIjIKTb15MASGk4b X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3887 Xref: news.eternal-september.org comp.lang.vhdl:1309 On Thu, 4 Jun 2009 13:42:15 -0700 (PDT), JimLewis wrote: >Among other things, 1076.6-2004 has coding styles for implementing >dual port rams with different clocks. I don't have access to the published standard just now, but I do have draft 8 which does not explicitly specify a scheme for multiple-clocked memory; instead, one can assume that the multiple-clocked storage style could also be used for memory. Unfortunately, I'm not aware of any synthesis tools that support multiple-clock storage elements (with the single exception of DDR flops clocked on both edges of the same clock). Consequently, the real practical situation today is that if you want to model dual-clock dual-port RAM for synthesis you must do one of the following: - model the storage as a VHDL-93 shared variable and have two clocked processes both writing to it - this is supported by some but not all tools; - model the storage as a signal and have two clocked processes both writing to it; this is simply flat-out wrong, and won't simulate correctly, but I've found FPGA synthesis tools that not only accept it for synthesis of DPRAM but actually recommend it as the "correct" coding style! - use Verilog, where you can do nonblocking assignment (roughly, signal-like update) on a shared variable. I share your frustration about lack of contribution to standards efforts but, when the real situation on the ground is so widely different from what the standard says, it's hardly surprising that many people have given up or don't even try. You and I have the luxury (and, indeed, the duty) of trying to get these things right; many working engineers must, as their first and only priority, get the results they need with the tools and techniques they can get today. I shall be filing bug reports against the tools that do last-write-wins resolution of writes to VHDL signals from multiple processes, a poisonous hack to make it possible to get DPRAM from VHDL source code whilst using the same algorithms they use to handle Verilog source. But there's little else I can reasonably do to push things forward. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!feed.news.qwest.net!mpls-nntp-08.inet.qwest.net!216.196.98.141.MISMATCH!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Jun 2009 17:11:20 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: I2C SDA LINE Date: Thu, 04 Jun 2009 23:08:32 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <62hg25tkfp7n3u6n8jrmkk1i308qsnpa9o@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 66 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-7D4WFewL1dqtu2fwoLtLnX4FQNteUl2z2maYhg+Jh+o3jvSX+GQL4boZ49qcT+IKhUfZOmCxLZbk4na!AvhUFaOeD41qMiTMVw4XImHSxBINz1bn8KbiPYLAj2fEW8lG0JP/TpU99Lt5C8BmpkiOHv/jEmAj!N9R+suLYdjm1tYkY X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1310 On Thu, 4 Jun 2009 14:21:52 -0700 (PDT), VIPS wrote: >I am implementing the I2C Slave and i am using two data lines for sda >input and sda output. > >MY question is that shall I expect from I2C bus to give me Z as input >in place of 1 > >Shall I drive output 1 as Z to the sda_out > >Secondly We cannot synthesize Z as an input but can drive the output >as Z any reason > >I have used an interal sda signal and sampled the SDA_input as > >SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the >output /input to gnd and vcc in synthesis Here's what I usually do: entity I2C_widget is port (...; SDA: inout std_logic; ... architecture RTL of I2C_widget is signal drive_to_SDA: std_logic; -- the value I'm trying to drive signal read_from_SDA: std_logic; -- the value seen as an input begin -- Drive the SDA output pin: SDA <= '0' when drive_to_SDA = '0' else 'H'; -- pull-up -- Receive the input read_from_SDA <= to_X01(SDA); The 'H' drive to SDA puts a weak high level on the line when you are not driving it to '0'. Since '0' is stronger than 'H', a single '0' will win even if many connected modules are trying to drive 'H'. But if no module is driving '0', then the line will float to 'H'. On input, the to_X01 strength stripper function converts 'H' to '1'. In synthesis, the to_X01 function is ignored and becomes simply a wire, which is OK because a pulled-up line is a perfectly good '1' level. The idiom '0' when drive_to_SDA = '0' else 'H' should synthesise correctly to a driver with strong pull-down and weak pull-up (open-drain with pullup). Of course, this kind of pull-up arrangement is possible only on PINS of the FPGA. Don't try to do it on internal signals. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.albasani.net!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Jun 2009 17:13:22 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 04 Jun 2009 23:10:35 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <0ghg25p7l6jplae15nq7hf05loesdel3up@4ax.com> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-r2KZhUIzedbjYC/xHF4xjFFjbU4966euEIkQAhosy0D7+CTaX68RovNVm/a5eGjvQCKgQr/KWetQ5Qd!vMOOO438t5kVpgW6lbvoQFjyyEuHglG3y59J1O6DBApyjvFgl17XYNY+tT846tJAHpAN9QL/XFAE!l5BAsmwnI3nCTeOa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1311 On Thu, 4 Jun 2009 14:59:05 -0700 (PDT), JimLewis wrote: >Jon, >> Note that some simulators are not yet supporting >> VHDL protected types, so you need to be a little >> circumspect when using shared variables. > >Care to name names? >I have used protected types on both ModelSim and >Aldec for quite some time now. Yup, me too. Tried any others recently? ;-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!grolier!v.t-online.fr!t-online.fr!not-for-mail Subject: Anyone can check if XST v11 has fixed this bug ? From: Bert_Paris Newsgroups: comp.lang.vhdl X-Newsreader: MesNews/1.08.03.00-gb Date: Fri, 05 Jun 2009 00:56:24 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 60 Message-ID: <4a285116$0$294$7a628cd7@news.club-internet.fr> Organization: Club-Internet / T-Online France NNTP-Posting-Date: 04 Jun 2009 22:56:22 GMT NNTP-Posting-Host: 86.69.86.247 X-Trace: 1244156182 news.club-internet.fr 294 86.69.86.247 X-Complaints-To: abuse@club-internet.fr Xref: news.eternal-september.org comp.lang.vhdl:1312 Hello, I stumbled on yet another XST VHDL bug in v 10.1, & haven't had time to install the new v11. I would appreciate if someone could tell me if this bug is still there (I would have to modify our obfuscator just for XST, something I'd prefer not do). Thanx. Bert Here is the (correct) code : -- XST_TESTCASE.vhd -- --------------------------------------------------------------- -- another XST Issue :-( (tested on version 10.1) -- --------------------------------------------------------------- -- Author : Bert CUZEAU -- Contact : info@alse-fr.com -- Web : http://www.alse-fr.com -- ----------------------------------------------------------------- -- Bug : XST fails when an extended Identifier -- is used in an enumeration -- ----------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; -- ---------------------------------------------- Entity TEST is -- ---------------------------------------------- Port ( CLK : in std_logic; -- System Clock at Fqxtal RST : in std_logic; -- Asynchronous Reset active high Dout : out std_logic );-- end entity TEST; -- --------------------------------------------------------------- Architecture RTL of TEST is -- --------------------------------------------------------------- Type State_t is (Idle,\Shift__TX\); signal State : State_t; -----\ Begin -- -----/ Dout <= '1' when State=\Shift__TX\ else '0'; -- -------------------------- -- State Machine -- -------------------------- process (RST, CLK) begin if RST='1' then State <= Idle; elsif rising_edge(CLK) then case State is when Idle => State <= \Shift__TX\; when \Shift__TX\ => State <= Idle; end case; end if; end process; end RTL; From newsfish@newsfish Wed Aug 19 13:24:58 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe12.iad.POSTED!57094676!not-for-mail From: "Brad Smallridge" Newsgroups: comp.lang.vhdl References: Subject: Re: I2C SDA LINE Lines: 16 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: X-Complaints-To: abuse2@dslextreme.com NNTP-Posting-Date: Thu, 04 Jun 2009 23:06:19 UTC Organization: DSL Extreme Date: Thu, 4 Jun 2009 16:06:08 -0700 Xref: news.eternal-september.org comp.lang.vhdl:1313 > SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the > output /input to gnd and vcc in synthesis If you are using a Xilinx device you can use an IO primitive with a tristate output. This is the same kind of primitive you would use on a memory data bus, for example. The trick is to connect the SDA output to the IO Tristate, and connect '0' to the IO Output. Then when your SDA output goes low the tristate turns off and drives the output to '0'. When your SDA output goes high, the tristate turns on and effectivly outputs a 'Z', the '0' at the IO Output is ignored. Brad Smallridge AiVision From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!u10g2000vbd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Thu, 4 Jun 2009 16:43:16 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244158996 3885 127.0.0.1 (4 Jun 2009 23:43:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Jun 2009 23:43:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u10g2000vbd.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1314 On Jun 4, 3:42=A0pm, JimLewis wrote: > Andy, > > > I applaud vendors that try to advance the state of the art in > > synthesis. It is certainly more than the synthesis standard has > > accomplished lately (merely listing the existing capabilities that > > vendors had already come up with on their own). > > Your ignorance is both insulting and part of the problem with > getting the standards implemented. > > Among other things, 1076.6-2004 has coding styles for implementing > dual port rams with different clocks. =A0For a quick start on this > standard, see the paper or slides on "IEEE 1076.6-2004: VHDL > Synthesis > Coding Styles for the Future" that is at:http://www.synthworks.com/papers= / > > If a vendor implements an inferior alternative to what is in > 1076.6-2004 (and do not implement what is in 1076.6-2004), I would > not call that advancing the state of the art. =A0I would call it a bad > investment. > > Please educate yourself on what is current and make sure your vendors > are implementing the parts you need. =A0Vendors are market driven and > if you fail to do this, they will not implement it. > > If you need something that is not in 1076.6-2004, quit whining > and get involved. =A0There are quite a few of you here > who are senior enough that you ought to be participating in standards > development - if not driving the standards development. > Participation is volunteer work. =A0A typical committee > will let anyone with a vested interested participate - ie: a VHDL > user - after all free labor is free. =A0Typically issues are resolved > by consensus. =A0Only when the group is polarized does an official > membership vote come up. =A0If you want to participate in those > you will need to be a member of the appropriate groups (typically > IEEE and DASC). > > 1076.6-1999 did as you said, listed a baseline set of existing > capabilities that intellectual property developers could depend > on all synthesis tools implementing. =A0Its purpose was not to push > the state of the art - its intent is allow model developers to > claim compliance, and hence, if you purchased a compliant model > you could count an a synthesis tool creating a good implementation. > > If not you then who? > > Cheers, > Jim I do not have access to the latest non-draft revision either, but would add that there is a huge difference between a dual port ram that operates with two independent, asynchronous clocks, and a dual-edge/ clock device such as a DDR flip-flop which requires constrained timing between clocks for proper operation. I also read your related paper. Your model in section 6.1 of the behavior of a dual edged flop is flawed. An asynchronous reset should be the highest priority (not an elsif to the clock conditions), as is correctly mentioned in section 2.1. Also, with two simultaneous clocks, it is a bit pessimistic. The output should not assume 'X' unless the two data inputs are different and reset is not asserted. Just like set and hold violations, RTL models need not faithfully describe clock skew related behavior either. But relax, I'm not insulted by your ignorance... :^) Seriously, I truly enjoy and respect your fervent advocation of VHDL, whether I agree with all of it or not. I believe the 1999 approach (not the content) of the standard is more useful than apparently that of the 2004 standard. By implementing a minimum set of common capabilities, the 1999 standard allows both model writers, consumers, and tool vendors to ascertain compatibility, while not restricting progress in the state of the art until the next version of the standard is published. You seem to believe it is the standard that sets the state of the art, yet I know there were synthesis vendors that implemented some if not all of the features in your paper prior to 2004. Had the 1999 standard prohibited capabilities in excess of the standards, those vendors would have had to choose between providing the advanced capabilities desired by their customers, or claiming compliance with the standard in order to ensure compatibility with their users. Thankfully, the 1999 standard let them do both. Andy From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!q16g2000yqg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Fri, 5 Jun 2009 00:53:48 -0700 (PDT) Organization: http://groups.google.com Lines: 83 Message-ID: <186e4f9e-cf50-4f8d-9db9-299a49d1f3f9@q16g2000yqg.googlegroups.com> References: <89e7ad94-7a2b-425f-899d-23068dfeacbe@n4g2000vba.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244188428 23498 127.0.0.1 (5 Jun 2009 07:53:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Jun 2009 07:53:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q16g2000yqg.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1315 On 4 June, 20:39, JimLewis wrote: > Tricky, > > > > > Ive always been told categorically that "Shared variables cannot be > > synthesized, Use signals for communication between processes" > > > But now it appears at least Quartus does. I have infered a ram using > > one, plus also this interesting setup. > > > =A0 shared variable C : std_logic; > > > begin > > > =A0 Proc1: process(clk) > > =A0 begin > > =A0 =A0 if rising_edge(clk) then > > =A0 =A0 =A0 C :=3D data_a; > > =A0 =A0 end if; > > =A0 end process; > > > =A0 Proc2: process(clk) > > =A0 begin > > =A0 =A0 if rising_edge(clk) then > > =A0 =A0 =A0 --c :=3D data_b; > > > =A0 =A0 =A0 q_b <=3D C; > > =A0 =A0 end if; > > =A0 end process; > > > From synthesis, this gives me 2 registers, source from data_a. If I > > uncomment the C assignment in the 2nd process, I only get 1 register > > driven from data_b, with no warning about multiple constant drivers, > > like you would if C was a signal. > > Usage of shared variables in this example - independent of using > either a > protected type (only correct usage in 1076-2002 and beyond) or > regular > types (as temporarily defined in 1076-1993) - is always going to lead > to > quirky behavior in simulation. =A0Either process can be executed > first. > If Proc2 runs first, there are two registers. If Proc1 runs first, > there > is only one register. =A0Adding protected types only ensures that the > access > to the object is not interrupted in the middle - which really does not > help > or hurt this pair of processes. > > To be correct, synthesis results must match RTL simulation results. > Since the RTL simulation is ambiguous for this example, there is no > correct synthesis result for this problem. > > > So, is this an interesting and potentially dangerous precident Altera > > are setting, or is this happening with other synthesisors too? would > > shared variables actually have any use anywhere? > > I agree with your assessment and would consider it a bad investment on > their part - unless they got it for free. =A0Even then it is still a > liability. > > I primarily use shared variables in testbenches where they are great > for > data structures and randomization. =A0Seehttp://www.synthworks.com/downlo= ads/ > for the randomziation packages we use. > > Cheers, > Jim Thanks Jim. I am not really interested in simulation results - I was just surprised such features were supported by at least 1 synth tool (I only have access to Quartus), not something I intend to use at all for synth. Like you, I only use shared variables in testbenches (as should anyones else, IMO, though being able to get the correct behaviour for a Dual-port ram may be considered a bonus). I just dont want people falling into traps, like I think I have demonstrated, because synth tools allow shared variables but dont warn against their use. Who knows what a VHDL beginner might do when he finds out about this magical device that is updated instantly across many processes. From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Jun 2009 07:11:58 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Fri, 05 Jun 2009 13:15:04 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <78qev8F1nepkuU1@mid.individual.net> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 22 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-VnynRYqEmgbwSDBUZh+vCDLg0SrmQ+BTu8PSlqke7ttKOfim0Y9ZOVu3d/PeQbGSw88rnVeyrHqJqFs!fXaDsE8qZU6fZtwE9kT1Qg+4t4iuloWXJenUS4BJZkandrD0Uz2f+PWqveqnrSQmu41MAmzQdcjo!Q4rN X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2134 Xref: news.eternal-september.org comp.lang.vhdl:1316 On Thu, 04 Jun 2009 10:35:35 -0700, Mike Treseler wrote: >Matthew Hicks wrote: > >> I wish this were the case. I have had plenty of experiences with both >> Verilog and VHDL where synthesis differed from simulation, but the tool >> didn't care to inform me of the potential difference, when it could >> have. > >As a counterpoint, I have coded vhdl and verilog on the edge >for years using modelsim, quartus and ise. >I found only one such bug, and none since. >http://groups.google.com/groups/search?q=update_regs_bug > >What did you find? I have seen XST using variable assignment rules (immediate not postponed) on signals, when the assignments were in a procedure, with the signal passed as an inout parameter. Eventually acknowledged as a bug; I don't know if it's fixed in ISE11. - Brian From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed4-a.proxad.net!nnrp15-2.free.fr!not-for-mail Date: Fri, 05 Jun 2009 22:09:46 +0200 From: Nicolas Matringe User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: I2C SDA LINE References: <62hg25tkfp7n3u6n8jrmkk1i308qsnpa9o@4ax.com> In-Reply-To: <62hg25tkfp7n3u6n8jrmkk1i308qsnpa9o@4ax.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 14 Message-ID: <4a297b8b$0$7251$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 05 Jun 2009 22:09:47 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1244232587 news-1.free.fr 7251 82.246.229.10:1465 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:1317 Jonathan Bromley a écrit : > [...] The idiom > '0' when drive_to_SDA = '0' else 'H' > should synthesise correctly to a driver with strong pull-down > and weak pull-up (open-drain with pullup). Does this synthesize ok? I stick to the good old tri-state driver (assign 'Z' to the output) and add the pull-ups in the constraint file but if the tools can handle this syntax I will probably change my ways. Why maintain two files when one is enough? Nicolas From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Jun 2009 15:45:01 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: I2C SDA LINE Date: Fri, 05 Jun 2009 21:42:13 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <62hg25tkfp7n3u6n8jrmkk1i308qsnpa9o@4ax.com> <4a297b8b$0$7251$426a74cc@news.free.fr> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-zmSDRXtJ08M00fxRrYTt//Y1siyw+UGhqNMqJrXdT7TLxnW4Ujvzd6jXs+UftYGdVsPqbkD3N4gh7U/!MATArZ/cxCYS3mJ66/FbEg2X/roxn5PQYPJHOXDq1caUqWt4Ay3SsDeD6TqjbYpsG533B5bIZpgl!wYaakgeunYVlKaFz X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1318 On Fri, 05 Jun 2009 22:09:46 +0200, Nicolas Matringe wrote: >Jonathan Bromley a menti : >> [...] The idiom >> '0' when drive_to_SDA = '0' else 'H' >> should synthesise correctly to a driver with strong pull-down >> and weak pull-up (open-drain with pullup). > > >Does this synthesize ok? No, it certainly does not. Apologies are due. When I responded to the original post, I looked back through some old code and got completely confused - I was looking at a behavioural model, not at synthesisable code. >I stick to the good old tri-state driver (assign 'Z' to the output) and >add the pull-ups in the constraint file I think that is the right choice. I tried the 'H' driver in several synthesis tools, and they all got it wrong (in various ways). Once again, apologies for the red herring. It's sad that the synth tools don't support this, though. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeds.phibee-telecom.net!de-l.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!oleane.net!oleane!grolier!v.t-online.fr!t-online.fr!not-for-mail Subject: Re: I2C SDA LINE From: Bert_Paris References: Newsgroups: comp.lang.vhdl X-Newsreader: MesNews/1.08.03.00-gb Date: Fri, 05 Jun 2009 23:43:48 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 36 Message-ID: <4a299192$0$292$7a628cd7@news.club-internet.fr> Organization: Club-Internet / T-Online France NNTP-Posting-Date: 05 Jun 2009 21:43:47 GMT NNTP-Posting-Host: 86.69.86.247 X-Trace: 1244238227 news.club-internet.fr 292 86.69.86.247 X-Complaints-To: abuse@club-internet.fr Xref: news.eternal-september.org comp.lang.vhdl:1319 Hello, I do things a bit differently : 1. In the FPGA : SDA in inout, SDA <= '0' when SDAout ='0' else 'Z'; Because : * most synthesis tools I used at this time did NOT infer internal pullups using 'H', you need a constraint on the IO pin. * Internal pullups in all technologies I used were way too week for the purpose (slew rate too low, -> glitches after input). * there should always be an external pull up resistor on the i2c signals anyway. 2. In the FPGA : SDA_in <= SDA or SDA; (as an alternative to To_X01, which is more academic) 3. In the FPGA : I insert a simple digital filter (especially recommended on SCL). This allowed me to have a working system with only an internal pull up (not recommended though). 5. In the _Test bench_ : SDA <= 'H'; to model the external pull up resistor and get an H when neither Master nor Slave(s) are driving. Most applies to SCL (though the slave won't drive it) Hope this helps, Bert From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!feeder.news-service.com!publishnet.news-service.com!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: I2C SDA LINE References: <4a299192$0$292$7a628cd7@news.club-internet.fr> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: X-Complaints-To: abuse@news-service.com Organization: Publishnet Date: Sat, 06 Jun 2009 00:26:19 +0200 Lines: 20 NNTP-Posting-Host: 84.246.49.113 (84.246.49.113) NNTP-Posting-Date: Sat, 06 Jun 2009 00:26:19 +0200 X-Trace: b535a4a299b8bf15394d416877 Xref: news.eternal-september.org comp.lang.vhdl:1320 In comp.lang.vhdl, Bert_Paris wrote: > > 5. In the _Test bench_ : > SDA <= 'H'; > to model the external pull up resistor and get an H > when neither Master nor Slave(s) are driving. > > Most applies to SCL (though the slave won't drive it) > That's not entirely correct. A slave may hold SCL low when its is busy and releasy it when ready. So a master must always check if SCL has returned high before proceeding. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Home on the Range was originally written in beef-flat. From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe20.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4a285116$0$294$7a628cd7@news.club-internet.fr> Subject: Re: Anyone can check if XST v11 has fixed this bug ? Lines: 87 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: <78qWl.96766$X77.8071@newsfe20.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe20.ams2 1244278403 86.16.123.60 (Sat, 06 Jun 2009 08:53:23 UTC) NNTP-Posting-Date: Sat, 06 Jun 2009 08:53:23 UTC Organization: virginmedia.com Date: Sat, 6 Jun 2009 09:53:19 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1321 "Bert_Paris" wrote in message news:4a285116$0$294$7a628cd7@news.club-internet.fr... > Hello, > > I stumbled on yet another XST VHDL bug in v 10.1, & haven't had time to > install the new v11. I would appreciate if someone could tell me if this > bug is still there (I would have to modify our obfuscator just for XST, > something I'd prefer not do). Thanx. > Bert > > Here is the (correct) code : > > -- XST_TESTCASE.vhd > -- --------------------------------------------------------------- > -- another XST Issue :-( (tested on version 10.1) > -- --------------------------------------------------------------- > -- Author : Bert CUZEAU > -- Contact : info@alse-fr.com > -- Web : http://www.alse-fr.com > -- ----------------------------------------------------------------- > -- Bug : XST fails when an extended Identifier > -- is used in an enumeration > -- ----------------------------------------------------------------- > Library IEEE; > use IEEE.std_logic_1164.all; > > -- ---------------------------------------------- > Entity TEST is > -- ---------------------------------------------- > Port ( CLK : in std_logic; -- System Clock at Fqxtal > RST : in std_logic; -- Asynchronous Reset active high > Dout : out std_logic );-- > end entity TEST; > > -- --------------------------------------------------------------- > Architecture RTL of TEST is > -- --------------------------------------------------------------- > Type State_t is (Idle,\Shift__TX\); > signal State : State_t; > -----\ > Begin -- > -----/ > Dout <= '1' when State=\Shift__TX\ else '0'; > -- -------------------------- > -- State Machine > -- -------------------------- > process (RST, CLK) > begin > if RST='1' then > State <= Idle; > elsif rising_edge(CLK) then > case State is > when Idle => > State <= \Shift__TX\; > when \Shift__TX\ => > State <= Idle; > end case; > end if; > end process; > end RTL; > I will have a go at it give that it is raining again in the UK :-( Using 11.1 I get: ERROR:HDLParsers:3312 - "D:/test_lib/x.vhd" Line 31. Undefined symbol '\Shift__TX\'. ERROR:HDLParsers:1209 - "D:/test_lib/x.vhd" Line 31. \Shift__TX\: Undefined symbol (last report in this block) ERROR:HDLParsers:813 - "D:/test_lib/x.vhd" Line 41. Enumerated value \shift__tx\ is missing in case. --> Total memory usage is 126028 kilobytes Number of errors : 3 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:24:59 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe20.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> Subject: Re: So, they started synthesizing shared variables? Lines: 41 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <3bqWl.96767$X77.12615@newsfe20.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe20.ams2 1244278591 86.16.123.60 (Sat, 06 Jun 2009 08:56:31 UTC) NNTP-Posting-Date: Sat, 06 Jun 2009 08:56:31 UTC Organization: virginmedia.com Date: Sat, 6 Jun 2009 09:56:23 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1322 "Tricky" wrote in message news:fb2b24a3-8eb3-41a9-88ce-debe737a4c0c@j18g2000yql.googlegroups.com... > On 4 June, 12:00, "HT-Lab" wrote: >> "Tricky" wrote in message .. >> >> > So I tried infering a ram via an access type and shared variable. >> > Quartus just ploughed on, didnt throw a warning about access, but >> > seemed to ignore that it existed (therefore, just assumed everything >> > was connected to thin air - not really a surprise). Not even a warning >> > saying access types are not synthesizable. >> >> > Heres what I tried to synthesize(be interesting to see what other >> > synth tools do): >> >> Not much luck in Precision either... >> >> [40000]: vhdlorder, Release 2009a.15 >> [40000]: Files sorted successfully. >> [40000]: hdl-analyze, Release RTLC-Precision 2009a.15 .. >> detected in the following modules : >> [40000]: work.test_build(syn) >> [40000]: Please check the log for details pertaining to unsupported or >> non-rtl construct(s) >> [666]: Unable to elaborate design work.test_build in vhdl. >> >> Hanswww.ht-lab.com > > Well that is interesting, the fact that it recognises protected types. > Any chance you could take the code I posted and use the protected type > instead of the pointer? see what it does what that? Sure, send/or post a version that doesn't annoy Modelsim and I will run it through Precision, Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 06 Jun 2009 04:01:00 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Anyone can check if XST v11 has fixed this bug ? Date: Sat, 06 Jun 2009 09:58:13 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <4a285116$0$294$7a628cd7@news.club-internet.fr> <78qWl.96766$X77.8071@newsfe20.ams2> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 35 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-606MsvwicfT9pW1N8TKuGw1AP0YvPsgffU4nJYP33smf4SID8z6WWQme7KhZUJLBOkhDJ6xD0Fu7sEf!KBu+jWJzm71NLh47iZImMNPwUmXMMSPVErwBwk3pzcHJzjqcMnbD8aM84nK0aCNv0HqH1XOFNOaI!K9sR8oehMCL0ajma X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2493 Xref: news.eternal-september.org comp.lang.vhdl:1323 On Sat, 6 Jun 2009 09:53:19 +0100, "HT-Lab" wrote: >I will have a go at it give that it is raining again in the UK :-( And because of the rain, I'm supposed to be tidying the filing cabinet; and because of that, I'm reading Usenet :-) >Using 11.1 I get: > >ERROR:HDLParsers:3312 - "D:/test_lib/x.vhd" Line 31. Undefined symbol >'\Shift__TX\'. >ERROR:HDLParsers:1209 - "D:/test_lib/x.vhd" Line 31. \Shift__TX\: Undefined >symbol (last report in this block) >ERROR:HDLParsers:813 - "D:/test_lib/x.vhd" Line 41. Enumerated value >\shift__tx\ is missing in case. Ahah. So it seems that XST is flattening uppercase letters in the escaped-identifier to lowercase, but not everywhere. It would be interesting to try the same testcase with the identifier name changed to \shift__tx\ (all lowercase). Sorry, I don't yet have ISE11 installed at home; it will need a *very* long spell of rain before I do that :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe08.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4a285116$0$294$7a628cd7@news.club-internet.fr> <78qWl.96766$X77.8071@newsfe20.ams2> Subject: Re: Anyone can check if XST v11 has fixed this bug ? Lines: 60 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <%OrWl.13391$c74.8363@newsfe08.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe08.ams2 1244285243 86.16.123.60 (Sat, 06 Jun 2009 10:47:23 UTC) NNTP-Posting-Date: Sat, 06 Jun 2009 10:47:23 UTC Organization: virginmedia.com Date: Sat, 6 Jun 2009 11:47:15 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1324 "Jonathan Bromley" wrote in message news:nmbk25t3v4odsdbs6ua8l93dlgckaaadv5@4ax.com... > On Sat, 6 Jun 2009 09:53:19 +0100, "HT-Lab" wrote: > >>I will have a go at it give that it is raining again in the UK :-( > > And because of the rain, I'm supposed to be tidying the > filing cabinet; and because of that, I'm reading Usenet :-) > >>Using 11.1 I get: >> >>ERROR:HDLParsers:3312 - "D:/test_lib/x.vhd" Line 31. Undefined symbol >>'\Shift__TX\'. >>ERROR:HDLParsers:1209 - "D:/test_lib/x.vhd" Line 31. \Shift__TX\: >>Undefined >>symbol (last report in this block) >>ERROR:HDLParsers:813 - "D:/test_lib/x.vhd" Line 41. Enumerated value >>\shift__tx\ is missing in case. > > Ahah. So it seems that XST is flattening uppercase letters > in the escaped-identifier to lowercase, but not everywhere. > It would be interesting to try the same testcase with the > identifier name changed to \shift__tx\ (all lowercase). You are right! ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "D:/test_lib/x.vhd" in Library test_lib. Architecture rtl of Entity test is up to date. Reading constraint file D:/test_lib/TEST.xcf. XCF parsing done. ... Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) www.ht-lab.com Hans > > Sorry, I don't yet have ISE11 installed at home; > it will need a *very* long spell of rain before I do that :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!grolier!v.t-online.fr!t-online.fr!not-for-mail Subject: Re: Anyone can check if XST v11 has fixed this bug ? From: Bert_Paris References: <4a285116$0$294$7a628cd7@news.club-internet.fr> <78qWl.96766$X77.8071@newsfe20.ams2> <%OrWl.13391$c74.8363@newsfe08.ams2> Newsgroups: comp.lang.vhdl X-Newsreader: MesNews/1.08.03.00-gb Date: Sat, 06 Jun 2009 13:42:37 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 7 Message-ID: <4a2a562d$0$296$7a628cd7@news.club-internet.fr> Organization: Club-Internet / T-Online France NNTP-Posting-Date: 06 Jun 2009 11:42:37 GMT NNTP-Posting-Host: 86.69.86.247 X-Trace: 1244288557 news.club-internet.fr 296 86.69.86.247 X-Complaints-To: abuse@club-internet.fr Xref: news.eternal-september.org comp.lang.vhdl:1325 Thanks everyone ! FYI, it's raining in Paris too :-(, but sunny in Normandy ;-) This bug is bad news since our obfuscator produces "all-uppercased" code. I'll have to modify it... Bert From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.mixmin.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!grolier!v.t-online.fr!t-online.fr!not-for-mail Subject: Re: I2C SDA LINE From: Bert_Paris References: <4a299192$0$292$7a628cd7@news.club-internet.fr> Newsgroups: comp.lang.vhdl X-Newsreader: MesNews/1.08.03.00-gb Date: Sat, 06 Jun 2009 13:46:00 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 10 Message-ID: <4a2a56f8$0$291$7a628cd7@news.club-internet.fr> Organization: Club-Internet / T-Online France NNTP-Posting-Date: 06 Jun 2009 11:46:00 GMT NNTP-Posting-Host: 86.69.86.247 X-Trace: 1244288760 news.club-internet.fr 291 86.69.86.247 X-Complaints-To: abuse@club-internet.fr Xref: news.eternal-september.org comp.lang.vhdl:1326 > That's not entirely correct. A slave may hold SCL low when its is busy and > releasy it when ready. So a master must always check if SCL has returned > high before proceeding. Good remark ! My slaves were never busy so I coded SCL only as "in". Bert From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!e21g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Mon, 8 Jun 2009 00:43:06 -0700 (PDT) Organization: http://groups.google.com Lines: 115 Message-ID: <8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> <3bqWl.96767$X77.12615@newsfe20.ams2> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244446986 20678 127.0.0.1 (8 Jun 2009 07:43:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Jun 2009 07:43:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1327 On 6 June, 09:56, "HT-Lab" wrote: > "Tricky" wrote in message > > news:fb2b24a3-8eb3-41a9-88ce-debe737a4c0c@j18g2000yql.googlegroups.com... > > > > > On 4 June, 12:00, "HT-Lab" wrote: > >> "Tricky" wrote in message > .. > > >> > So I tried infering a ram via an access type and shared variable. > >> > Quartus just ploughed on, didnt throw a warning about access, but > >> > seemed to ignore that it existed (therefore, just assumed everything > >> > was connected to thin air - not really a surprise). Not even a warning > >> > saying access types are not synthesizable. > > >> > Heres what I tried to synthesize(be interesting to see what other > >> > synth tools do): > > >> Not much luck in Precision either... > > >> [40000]: vhdlorder, Release 2009a.15 > >> [40000]: Files sorted successfully. > >> [40000]: hdl-analyze, Release RTLC-Precision 2009a.15 > .. > >> detected in the following modules : > >> [40000]: work.test_build(syn) > >> [40000]: Please check the log for details pertaining to unsupported or > >> non-rtl construct(s) > >> [666]: Unable to elaborate design work.test_build in vhdl. > > >> Hanswww.ht-lab.com > > > Well that is interesting, the fact that it recognises protected types. > > Any chance you could take the code I posted and use the protected type > > instead of the pointer? see what it does what that? > > Sure, send/or post a version that doesn't annoy Modelsim and I will run it > through Precision, > > Hanswww.ht-lab.com entity test_build is port( clk : in std_logic; addr_a : in natural range 0 to 127; addr_b : in natural range 0 to 127; data_a : in std_logic_vector(7 downto 0); q_b : out std_logic_vector(7 downto 0) ); end entity test_build; architecture syn of test_build is --type ram_t; --type ram_t_p is access ram_t; -- --type ram_t is array(0 to 127) of std_logic_vector(7 downto 0); type ram_t is protected function read(a : natural) return std_logic_vector; procedure write(a : natural; d : std_logic_vector); end protected type ram_t; type ram_t is protected body type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); variable ram_array : ram_array_t; function read(a : natural) return std_logic_vector is begin return ram_array(a); end function read; procedure write(a : natural; d : std_logic_vector) is begin ram_array(a) := d; end procedure write; end protected type ram_t; shared variable ram : ram_t; signal addr_b_r : natural range 0 to 127; begin process(clk) begin if rising_edge(clk) then ram.write(addr_a, data_a); end if; end process; process(clk) begin if rising_edge(clk) then addr_b_r <= addr_b; end if; end process; q_b <= ram.read(addr_b_r); end architecture syn; From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe28.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> <3bqWl.96767$X77.12615@newsfe20.ams2> <8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com> Subject: Re: So, they started synthesizing shared variables? Lines: 84 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe28.ams2 1244449947 86.16.123.60 (Mon, 08 Jun 2009 08:32:27 UTC) NNTP-Posting-Date: Mon, 08 Jun 2009 08:32:27 UTC Organization: virginmedia.com Date: Mon, 8 Jun 2009 09:31:15 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1328 "Tricky" wrote in message news:8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com... > On 6 June, 09:56, "HT-Lab" wrote: >> "Tricky" wrote in message >> >> news:fb2b24a3-8eb3-41a9-88ce-debe737a4c0c@j18g2000yql.googlegroups.com... >> >> > On 4 June, 12:00, "HT-Lab" wrote: >> >> "Tricky" wrote in message .. >> > Well that is interesting, the fact that it recognises protected types. >> > Any chance you could take the code I posted and use the protected type >> > instead of the pointer? see what it does what that? >> >> Sure, send/or post a version that doesn't annoy Modelsim and I will run >> it >> through Precision, >> >> Hanswww.ht-lab.com > .. > > type ram_t is protected > function read(a : natural) return std_logic_vector; > procedure write(a : natural; d : std_logic_vector); > end protected type ram_t; > > type ram_t is protected body > type ram_array_t is array(0 to 127) of std_logic_vector(7 downto > 0); > variable ram_array : ram_array_t; > > function read(a : natural) return std_logic_vector is > begin > return ram_array(a); > end function read; > > procedure write(a : natural; d : std_logic_vector) is > begin > ram_array(a) := d; > end procedure write; > > end protected type ram_t; > > shared variable ram : ram_t; mmmm, not sure which version of Modelsim you are using but my 6.5b version complained bitterly and told me to get some more coffee.. After some quick hacking I changed the code into: type ram_t is protected -- Error in PS impure function read(a : natural) return std_logic_vector; procedure write(a : natural; d : std_logic_vector); end protected ram_t; type ram_t is protected body type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); variable ram_array : ram_array_t; impure function read(a : natural) return std_logic_vector is begin return ram_array(a); end function read; procedure write(a : natural; d : std_logic_vector) is begin ram_array(a) := d; end procedure write; end protected body ram_t; Unfortunately it didn't go through Precision although this might be due to me screwing up the code. [40000]: vhdlorder, Release 2009a.15 [40000]: Syntax error at or near "protected" [40000]: VHDL file ordering failed. Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Mon, 8 Jun 2009 03:28:10 -0700 (PDT) Organization: http://groups.google.com Lines: 110 Message-ID: <1adc2767-9f3b-47b4-9e85-9ec6df2501dd@k8g2000yqn.googlegroups.com> References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> <3bqWl.96767$X77.12615@newsfe20.ams2> <8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244456890 1981 127.0.0.1 (8 Jun 2009 10:28:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Jun 2009 10:28:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1329 On 8 June, 09:31, "HT-Lab" wrote: > "Tricky" wrote in message > > news:8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com... > > > > > On 6 June, 09:56, "HT-Lab" wrote: > >> "Tricky" wrote in message > > >>news:fb2b24a3-8eb3-41a9-88ce-debe737a4c0c@j18g2000yql.googlegroups.com.= .. > > >> > On 4 June, 12:00, "HT-Lab" wrote: > >> >> "Tricky" wrote in message > .. > >> > Well that is interesting, the fact that it recognises protected type= s. > >> > Any chance you could take the code I posted and use the protected ty= pe > >> > instead of the pointer? see what it does what that? > > >> Sure, send/or post a version that doesn't annoy Modelsim and I will ru= n > >> it > >> through Precision, > > >> Hanswww.ht-lab.com > > .. > > > =A0type ram_t is protected > > =A0 =A0function read(a : natural) return std_logic_vector; > > =A0 =A0procedure write(a : natural; d : std_logic_vector); > > =A0end protected type ram_t; > > > =A0type ram_t is protected body > > =A0 =A0type ram_array_t is array(0 to 127) of std_logic_vector(7 downto > > 0); > > =A0 =A0variable ram_array : ram_array_t; > > > =A0 =A0function read(a : natural) return std_logic_vector is > > =A0 =A0begin > > =A0 =A0 =A0return ram_array(a); > > =A0 =A0end function read; > > > =A0 =A0procedure write(a : natural; d : std_logic_vector) is > > =A0 =A0begin > > =A0 =A0 =A0ram_array(a) :=3D d; > > =A0 =A0end procedure write; > > > =A0end protected type ram_t; > > > =A0shared variable ram : ram_t; > > mmmm, not sure which version of Modelsim you are using but my 6.5b versio= n > complained bitterly and told me to get some more coffee.. > > After some quick hacking I changed the code into: > > type ram_t is protected -- Error in PS > impure function read(a : natural) return std_logic_vector; > procedure write(a : natural; d : std_logic_vector); > end protected ram_t; > > type ram_t is protected body > type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); > variable ram_array : ram_array_t; > > impure function read(a : natural) return std_logic_vector is > begin > return ram_array(a); > end function read; > > procedure write(a : natural; d : std_logic_vector) is > begin > ram_array(a) :=3D d; > end procedure write; > > end protected body ram_t; > > Unfortunately it didn't go through Precision although this might be due t= o > me screwing up the code. > > [40000]: vhdlorder, Release 2009a.15 > [40000]: Syntax error at or near "protected" > [40000]: VHDL file ordering failed. > > Hanswww.ht-lab.com You need to compile with the -2000 option, not -93. Protected types were not introduced until VHDL 2000 As for the protected type - I just realised I probably meant to find out what other synthesisors do with access types. So, in the origional code (without protected types), replace the type/ shared variable declaration with this: type ram_t; type ram_t_p is access ram_t; type ram_t is array(0 to 127) of std_logic_vector(7 downto 0); shared variable ram : ram_t_p :=3D new ram_t; Then run it through precision and see what it makes of it all - as I said quartus just ignored it - not even a warning that it's a bad idea. From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Use of 'simple_name/instance/path attributes - are they any use? Date: Tue, 9 Jun 2009 08:49:36 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244562577 2084 127.0.0.1 (9 Jun 2009 15:49:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Jun 2009 15:49:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1330 I cant think of any use for these attributes except in assertions, and even then there is no way of calling something like this: assert (generics_are_good) report this'path_name & ": Generics are bad" severity failure; So you could identify where the assert output came from. Is there any way of getting hold of the path of the entity/architecture you are currently in? From newsfish@newsfish Wed Aug 19 13:25:00 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000vbo.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Use of 'simple_name/instance/path attributes - are they any use? Date: Tue, 9 Jun 2009 08:51:49 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244562709 28361 127.0.0.1 (9 Jun 2009 15:51:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Jun 2009 15:51:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000vbo.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1331 On 9 June, 16:49, Tricky wrote: > I cant think of any use for these attributes except in assertions, and > even then there is no way of calling something =A0like this: > > assert (generics_are_good) > =A0 report this'path_name & ": Generics are bad" > =A0 =A0 severity failure; > > So you could identify where the assert output came from. Is there any > way of getting hold of the path of the entity/architecture you are > currently in? I mean 'instance_name, not path_name, but it still has the same problem. From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 09 Jun 2009 11:39:25 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Use of 'simple_name/instance/path attributes - are they any use? Date: Tue, 09 Jun 2009 17:36:32 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <1j3t25996lsef0r5qqfcdmvvvm9penlv1c@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 35 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-DrGosoCdLLlDr4hQihr3xv/w3FjloGm92KeL2O1d0kR7mfopGpgJen02UhQ/fineVtDXwXr0uMMSCIJ!kliiJwcUMhOXUjMsORauGGIn9DW7xiu3uQMI1Ui4lmFObHMvOhbxdJeV+xXlL52+h6Lx7yC1LQg4!mhD4u31UtNvgaHEi X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2400 Xref: news.eternal-september.org comp.lang.vhdl:1332 On Tue, 9 Jun 2009 08:51:49 -0700 (PDT), Tricky wrote: >On 9 June, 16:49, Tricky wrote: >> I cant think of any use for these attributes except in assertions, and >> even then there is no way of calling something  like this: >> >> assert (generics_are_good) >>   report this'path_name & ": Generics are bad" >>     severity failure; >> >> So you could identify where the assert output came from. Is there any >> way of getting hold of the path of the entity/architecture you are >> currently in? Use the architecture's name in place of your "this". You'll get The Right Answer (tm). entity foo is end; architecture bar of foo is begin assert FALSE report "I'm in " & bar'path_name severity note; end; -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Use of 'simple_name/instance/path attributes - are they any use? Date: Tue, 09 Jun 2009 10:08:02 -0700 Lines: 9 Message-ID: <797j7lF1pgsrrU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 5mpNnsdHlW7qL0tcyI+D+QW6o9LcErYWtKQLui8cW/Rxj6jnaw Cancel-Lock: sha1:D3ut6JjiVyrcrZ4Kg7Q30/+SHmk= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1333 Tricky wrote: > On 9 June, 16:49, Tricky wrote: >> I cant think of any use for these attributes except in assertions, Me neither. The scope is very limited. Not much use for a testbench message. I print custom messages for errors and warnings. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!newsfeed2.telusplanet.net!newsfeed.telus.net!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi149.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: Subject: Re: Use of 'simple_name/instance/path attributes - are they any use? Lines: 15 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi149.ffdc.sbc.com 1244612299 ST000 99.184.242.197 (Wed, 10 Jun 2009 01:38:19 EDT) NNTP-Posting-Date: Wed, 10 Jun 2009 01:38:19 EDT Organization: at&t http://my.att.net/ X-UserInfo1: OP[EB[SE[RUABQTY]BCBNWX@RJ_XPDLMN@GZ_GYO^BSZUSAANVUEAE[YETZPIWWI[FCIZA^NBFXZ_D[BFNTCNVPDTNTKHWXKB@X^B_OCJLPZ@ET_O[G\XSG@E\G[ZKVLBL^CJINM@I_KVIOR\T_M_AW_M[_BWU_HFA_]@A_A^SGFAUDE_DFTMQPFWVW[QPJN Date: Wed, 10 Jun 2009 01:30:48 -0400 Xref: news.eternal-september.org comp.lang.vhdl:1334 "Tricky" wrote in message news:a6b9c473-4fda-439a-bc7b-bb4151fc9085@o14g2000vbo.googlegroups.com... On 9 June, 16:49, Tricky wrote: > I cant think of any use for these attributes except in assertions, and > even then there is no way of calling something like this: > I've used 'path_name to create the name of a unique log file when the entity is something that gets reused in a design and where the sim model writes data to some output file for logging/debugging purposes. KJ From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!xlned.com!feeder3.xlned.com!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe16.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4eefc627-e2c2-4a8b-9c6f-0a44bca207a0@h18g2000yqj.googlegroups.com> <78nmhnF1lohc1U1@mid.individual.net> <924f64a6-74e4-44ec-b6f6-fa99e41cfe7a@q16g2000yqg.googlegroups.com> <_ONVl.1117$h21.294@newsfe10.ams2> <3bqWl.96767$X77.12615@newsfe20.ams2> <8ef9c5cf-faa1-4741-b54c-64d1acf05862@e21g2000yqb.googlegroups.com> <1adc2767-9f3b-47b4-9e85-9ec6df2501dd@k8g2000yqn.googlegroups.com> Subject: Re: So, they started synthesizing shared variables? Lines: 158 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <75KXl.36825$2t7.7209@newsfe16.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe16.ams2 1244622275 86.16.123.60 (Wed, 10 Jun 2009 08:24:35 UTC) NNTP-Posting-Date: Wed, 10 Jun 2009 08:24:35 UTC Organization: virginmedia.com Date: Wed, 10 Jun 2009 09:24:13 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1335 "Tricky" wrote in message news:1adc2767-9f3b-47b4-9e85-9ec6df2501dd@k8g2000yqn.googlegroups.com... On 8 June, 09:31, "HT-Lab" wrote: > "Tricky" wrote in message > .. > >> > Well that is interesting, the fact that it recognises protected types. > >> > Any chance you could take the code I posted and use the protected type > >> > instead of the pointer? see what it does what that? > > >> Sure, send/or post a version that doesn't annoy Modelsim and I will run > >> it > >> through Precision, > > >> Hanswww.ht-lab.com > > .. > > > type ram_t is protected > > function read(a : natural) return std_logic_vector; > > procedure write(a : natural; d : std_logic_vector); > > end protected type ram_t; > > > type ram_t is protected body > > type ram_array_t is array(0 to 127) of std_logic_vector(7 downto > > 0); > > variable ram_array : ram_array_t; > > > function read(a : natural) return std_logic_vector is > > begin > > return ram_array(a); > > end function read; > > > procedure write(a : natural; d : std_logic_vector) is > > begin > > ram_array(a) := d; > > end procedure write; > > > end protected type ram_t; > > > shared variable ram : ram_t; > > mmmm, not sure which version of Modelsim you are using but my 6.5b version > complained bitterly and told me to get some more coffee.. > > After some quick hacking I changed the code into: > > type ram_t is protected -- Error in PS > impure function read(a : natural) return std_logic_vector; > procedure write(a : natural; d : std_logic_vector); > end protected ram_t; > > type ram_t is protected body > type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); > variable ram_array : ram_array_t; > > impure function read(a : natural) return std_logic_vector is > begin > return ram_array(a); > end function read; > > procedure write(a : natural; d : std_logic_vector) is > begin > ram_array(a) := d; > end procedure write; > > end protected body ram_t; > > Unfortunately it didn't go through Precision although this might be due to > me screwing up the code. > > [40000]: vhdlorder, Release 2009a.15 > [40000]: Syntax error at or near "protected" > [40000]: VHDL file ordering failed. > > Hanswww.ht-lab.com > >You need to compile with the -2000 option, not -93. Protected types >were not introduced until VHDL 2000 I did and I get: D:\test\shared_var>vcom shared_tricky.vhd -2002 Model Technology ModelSim SE vcom 6.5b Compiler 2009.05 May 21 2009 -- Loading package standard -- Loading package std_logic_1164 -- Compiling entity test_build -- Compiling architecture syn of test_build ** Error: shared_tricky.vhd(28): near "type": expecting ';' ** Error: shared_tricky.vhd(30): Subprogram "read" parameter name "_impliedOperand_ram_t" does not conform bet ween subprogram declaration and subprogram body (declaration has "a"). ** Error: shared_tricky.vhd(30): Subprogram "read" parameter "_impliedOperand_ram_t" class does not conform be tween subprogram declaration and subprogram body. ** Error: shared_tricky.vhd(30): Subprogram "read" parameter "_impliedOperand_ram_t" mode INOUT does not confo rm between subprogram declaration and subprogram body (declaration has IN). ** Error: shared_tricky.vhd(30): Subprogram "read" parameter "_impliedOperand_ram_t" type does not conform bet ween subprogram declaration and subprogram body. ** Error: shared_tricky.vhd(34): VHDL Compiler exiting >As for the protected type - I just realised I probably meant to find >out what other synthesisors do with access types. >So, in the origional code (without protected types), replace the type/ >shared variable declaration with this: > >type ram_t; >type ram_t_p is access ram_t; >type ram_t is array(0 to 127) of std_logic_vector(7 downto 0); >shared variable ram : ram_t_p := new ram_t; >Then run it through precision and see what it makes of it all - as I >said quartus just ignored it - not even a warning that it's a bad idea. Precision doesn't seem to like it and reports: [40000]: vhdlorder, Release 2009a.15 [40000]: Files sorted successfully. [40000]: hdl-analyze, Release RTLC-Precision 2009a.15 [42502]: Analyzing input file "D:/hdl_designs/test/shared_var/shared_var3.vhd" ... [43156]: Shared variables must be of a protected type. [651]: Top module of the design is set to: test_build. [649]: Current working directory: <...>/shared_var/project_5_impl_1. [40000]: RTLC-Driver, Release RTLC-Precision 2009a.15 [40000]: Last compiled on Mar 18 2009 18:40:36 [44512]: Initializing... [44504]: Partitioning design .... [40000]: RTLCompiler, Release RTLC-Precision 2009a.15 [40000]: Last compiled on Mar 18 2009 19:20:03 [44512]: Initializing... [44522]: Root Module work.test_build(syn): Pre-processing... [45258]: Object ram is of Non-Rtl type ram_t_p. Declaration wont be compiled. [46831]: Object ram of Non-Rtl type ram_t_p not handled. Continuing ... [46292]: Module work.test_build(syn) cannot be compiled because it contains non-rtl constructs. Please check the log for warnings or errors about non-synthesizable constructs in this module. [44536]: No modules were compiled in this run of RTLC, please check the logs for blackboxes or non-rtl constructs in the design. [44856]: Total lines of RTL compiled: 70. [47002]: RTLCompiler error... aborting compilation. [44513]: Overall running time 1.0 secs. [46259]: Design compilation failed, unsupported or non-rtl constructs detected in the following modules : [40000]: work.test_build(syn) [40000]: Please check the log for details pertaining to unsupported or non-rtl construct(s) [666]: Unable to elaborate design work.test_build in vhdl. Regards, Hans. www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Use of 'simple_name/instance/path attributes - are they any use? Date: Wed, 10 Jun 2009 12:53:18 +0100 Organization: TRW Conekt Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net /yYsaj+Pk331ebK/LjQzCwXBX3Z/9cPnIQ1V48X9sjIVDWLMc= Cancel-Lock: sha1:2a4sq8DpFm146Wy22/OIMg7Ougg= sha1:G20vp0zZOwaM0OSVmkKDNarHzPw= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.3 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:1336 Tricky writes: > On 9 June, 16:49, Tricky wrote: >> I cant think of any use for these attributes except in assertions, and >> even then there is no way of calling something  like this: >> >> assert (generics_are_good) >>   report this'path_name & ": Generics are bad" >>     severity failure; >> >> So you could identify where the assert output came from. Is there any >> way of getting hold of the path of the entity/architecture you are >> currently in? > > I mean 'instance_name, not path_name, but it still has the same > problem. So long as "this" refers to something like an entity, you can do it. I've used it for logging msgs in the past. Unfortunately, when applied to a procedure, it just reports the procedure name, not back to the entity that called it :( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n19g2000vba.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: case statement concatenation condition Date: Wed, 10 Jun 2009 08:01:17 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: NNTP-Posting-Host: 208.12.121.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244646077 31211 127.0.0.1 (10 Jun 2009 15:01:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Jun 2009 15:01:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000vba.googlegroups.com; posting-host=208.12.121.254; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1337 One syntax I've favored in verilog for compactness (and to see that all variable conditions are covered) is to express logic in a truth table as: casez( {a,b,c} ) 3'b000: z <= ... 3'b001: z <= ... I'm trying to use a similar style in VHDL, and am wondering if there is an elegant way to do this. My first attempt was: case a & b & c is when "000" => z <= ... when "001" => z <= .. With the error, "Ambiguous type in infix expression; unsigned or signed." OK. Strong typing... doesn't know what type the concatenation should resolve to... so I write: case std_logic_vector'(a & b & c) is when "000" => z <= ... when "001" => z <= .. I get the model sim warning "Array type case expression must be of a locally static subtype." I could assign the concatenation first to a variable (verbose), or I could disabled the warning in modelsim (but it does seem to be a valid violation of the VHDL language), but does anyone have a suggestion on how to write this in both a terse and correct way? Thanks, Mark From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 10 Jun 2009 10:14:45 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: case statement concatenation condition Date: Wed, 10 Jun 2009 16:11:52 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 61 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-19ZV+M2xk1D/EZp4xTKpEDHjyRO0SKWJ98VSY0IdaeK3j0A4aRp5BgrEJS9TOdbGlZXzQklqJ7R85ok!3jTIkiD4IUXCd6Bek/fbQc8g/Ee7h1684M9sh2nWMV6FqZ3Aau+2lTrAcAWpAXRE2J1K9UZOR6Y7!sZ0lx/6z50Y4OTIB X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1338 On Wed, 10 Jun 2009 08:01:17 -0700 (PDT), Mark wrote: >One syntax I've favored in verilog for compactness (and to see that >all variable conditions are covered) is to express logic in a truth >table as: > >casez( {a,b,c} ) > 3'b000: z <= ... > 3'b001: z <= ... > >I'm trying to use a similar style in VHDL, and am wondering if there >is an elegant way to do this. My first attempt was: > >case a & b & c is > when "000" => z <= ... > when "001" => z <= .. > >With the error, "Ambiguous type in infix expression; unsigned or >signed." > >OK. Strong typing... doesn't know what type the concatenation should >resolve to... so I write: > >case std_logic_vector'(a & b & c) is You need to be even stronger... the *subtype* of the case expressions is still not "locally static". And yes, it's a pain and everyone agrees it's a pain. It just falls out of the language rules like that. Luckily there's a relatively simple fix. Declare a subtype of std_logic_vector (typically in the declarative region of your process): subtype slv3 is std_logic_vector(2 downto 0); And then you can qualify the case expression with the locally-static subtype: case slv3'(a & b & c) is when "000" => ... and all will be well. Of course, you may well need rather a lot of such subtype declarations, if you have numerous different case statements. Enjoy :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!z5g2000vba.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: Re: case statement concatenation condition Date: Wed, 10 Jun 2009 08:26:44 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244647604 3857 127.0.0.1 (10 Jun 2009 15:26:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Jun 2009 15:26:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z5g2000vba.googlegroups.com; posting-host=132.228.195.207; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1339 On Jun 10, 10:11=A0am, Jonathan Bromley wrote: > On Wed, 10 Jun 2009 08:01:17 -0700 (PDT), Mark wrote: > >One syntax I've favored in verilog for compactness (and to see that > >all variable conditions are covered) is to express logic in a truth > >table as: > > >casez( {a,b,c} ) > > =A0 3'b000: z <=3D ... > > =A0 3'b001: z <=3D ... > > >I'm trying to use a similar style in VHDL, and am wondering if there > >is an elegant way to do this. =A0My first attempt was: > > >case a & b & c is > > =A0 when "000" =3D> z <=3D ... > > =A0 when "001" =3D> z <=3D .. > > >With the error, "Ambiguous type in infix expression; unsigned or > >signed." > > >OK. Strong typing... doesn't know what type the concatenation should > >resolve to... so I write: > > >case std_logic_vector'(a & b & c) is > > You need to be even stronger... the *subtype* of the > case expressions is still not "locally static". =A0And > yes, it's a pain and everyone agrees it's a pain. =A0It > just falls out of the language rules like that. > > Luckily there's a relatively simple fix. =A0Declare > a subtype of std_logic_vector (typically in the > declarative region of your process): > > =A0 subtype slv3 is std_logic_vector(2 downto 0); > > And then you can qualify the case expression with > the locally-static subtype: > > =A0 case slv3'(a & b & c) is > =A0 =A0 when "000" =3D> ... > > and all will be well. > > Of course, you may well need rather a lot of such > subtype declarations, if you have numerous different > case statements. > > Enjoy :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.- Hide quote= d text - > > - Show quoted text - Jonathan, Thanks! Like that much better than the alternatives I was considering. Mark From newsfish@newsfish Wed Aug 19 13:25:01 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: case statement concatenation condition Date: Wed, 10 Jun 2009 17:47:04 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 64 Sender: mdhicks2@outside.world Message-ID: <6004390c236cf8cbb7e0b1366118@news.acm.uiuc.edu> References: NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1244656025 16322 98.220.249.110 (10 Jun 2009 17:47:05 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Wed, 10 Jun 2009 17:47:05 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1340 > On Wed, 10 Jun 2009 08:01:17 -0700 (PDT), Mark wrote: > >> One syntax I've favored in verilog for compactness (and to see that >> all variable conditions are covered) is to express logic in a truth >> table as: >> >> casez( {a,b,c} ) >> 3'b000: z <= ... >> 3'b001: z <= ... >> I'm trying to use a similar style in VHDL, and am wondering if there >> is an elegant way to do this. My first attempt was: >> >> case a & b & c is >> when "000" => z <= ... >> when "001" => z <= .. >> With the error, "Ambiguous type in infix expression; unsigned or >> signed." >> >> OK. Strong typing... doesn't know what type the concatenation should >> resolve to... so I write: >> >> case std_logic_vector'(a & b & c) is >> > You need to be even stronger... the *subtype* of the case expressions > is still not "locally static". And yes, it's a pain and everyone > agrees it's a pain. It just falls out of the language rules like > that. > > Luckily there's a relatively simple fix. Declare > a subtype of std_logic_vector (typically in the > declarative region of your process): > subtype slv3 is std_logic_vector(2 downto 0); > > And then you can qualify the case expression with the locally-static > subtype: > > case slv3'(a & b & c) is > when "000" => ... > and all will be well. > > Of course, you may well need rather a lot of such subtype > declarations, if you have numerous different case statements. > > Enjoy :-) > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com > > The contents of this message may contain personal views which are not > the views of Doulos Ltd., unless specifically stated. > You may not even need to create a named subtype for this. You can create an anonymous subtype of the range you need. I have tried to write this up in a case statement, but I have done similar things in type declarations. i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is... ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 10 Jun 2009 14:17:26 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: case statement concatenation condition Date: Wed, 10 Jun 2009 20:14:33 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <481035hecall89bq4osmjlq51clkgv8ghc@4ax.com> References: <6004390c236cf8cbb7e0b1366118@news.acm.uiuc.edu> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gfaKgOpdWqSMbgiduT+R/TSvAn6xwG4CnwyH8mBOt6Ckh2sJQNoP4/xlK5sJU/OtEtuI5GAhQusofcU!FwItQcZ/wuIMXpq+UL/ZZks2Yd2O5lMl/LMCFopQ+KDI9/CZGbuGIAcISebT4BluzOCwmhz7M52s!Xw1rHVqDsH1Iz//j X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1341 On Wed, 10 Jun 2009 17:47:04 +0000 (UTC), Matthew Hicks wrote: >You may not even need to create a named subtype for this. You can create >an anonymous subtype of the range you need. I have tried to write this up >in a case statement, but I have done similar things in type declarations. > >i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is... I can imagine that some tools may tolerate this, but it does not appear to be legal VHDL. The syntax of a qualified expression is type_mark'(expression) and a type_mark must be simply a type name or subtype name. A "subtype indication" won't do. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r13g2000vbr.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: So, they started synthesizing shared variables? Date: Wed, 10 Jun 2009 14:29:46 -0700 (PDT) Organization: http://groups.google.com Lines: 115 Message-ID: References: <6004390c22b768cbb320277cd753@news.acm.uiuc.edu> <9be5a467-1ce6-40be-8d16-ff33f8a6fb3e@o20g2000vbh.googlegroups.com> <15591ee6-48c3-4f85-a566-9a7c7ac55fcb@21g2000vbk.googlegroups.com> NNTP-Posting-Host: 98.246.136.75 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244669388 5811 127.0.0.1 (10 Jun 2009 21:29:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Jun 2009 21:29:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000vbr.googlegroups.com; posting-host=98.246.136.75; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1342 Andy, > I also read your related paper. Your model in section 6.1 of the > behavior of a dual edged flop is flawed. An asynchronous reset should > be the highest priority (not an elsif to the clock conditions), as is > correctly mentioned in section 2.1. The implementation you expected is in the slides. The one from the paper is still correct as it uses nReset as inactive as a condition to the clock statements - which is permitted in 1076.6-2004 - looking back I have no idea why I would have written the paper that way. > Also, with two simultaneous > clocks, it is a bit pessimistic. The output should not assume 'X' > unless the two data inputs are different and reset is not asserted. The example was intended to show that one can detect and flag simultaneous changes if it is problematic for the circuit being created, however, one is not obliged to do this. > But relax, I'm not insulted by your ignorance... :^) Seriously, I > truly enjoy and respect your fervent advocation of VHDL, whether I > agree with all of it or not. The standard gives users something to ask your vendor to implement. If you ignore it, then we get stuff that may solve the issue, however, in this case is not VHDL compliant. Not great, but like Mike T noted, one does have to get a job done. > I believe the 1999 approach (not the content) of the standard is more > useful than apparently that of the 2004 standard. ... WRT support and not support, the 2004 approach is identical to the 1999 approach. I think the selective quoting and confusion introduced since the standard is for both writing compliant models and writing compliant tools. The quote from, Matthew Hicks, which states: > IEEE 1076.6 states, "The intent of this version was to include a maximum > subset of VHDL that could be used to describe synthesizable RTL logic." This is correct, however, it was in the introduction which was noted as "not part of IEEE Std 1076.6-2004". Meaning it is non-binding. I find the word maximum easy to misunderstand here. I think the working group was trying to say that the goal was to maximize the variations of coding styles that would be accepted by a compliant synthesis tool. To do this, the 1999 templates for flip-flops were replaced by rules that included the templates and more. To further clarify this, the Scope of the 2004 specification states: ---------------------------------- Start of Quote of 2004 specification -------------------------- 1.1 Scope This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis tools may be compliant and yet have features beyond those required by this standard. This standard defines how the semantics of VHDL shall be used, for example, to model level- sensitive and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability. ---------------------------------- End of Quote of 2004 specification -------------------------- My interpretation is that a synthesis vendor is permitted to do more than the standard states. We also need to address what not supported means, so moving on to the next quote also from Matthew: >By the way, if you look at the synthesis standards for VHDL (IEEE 1076.6-2= 004) >it clearly says shared variables aren't supported. So a designer shouldn'= t >be using them even if tool support is there. While this is true, one has to review what "not supported" means: ---------------------------------- Start of Quote of 2004 specification -------------------------- Not Supported: RTL synthesis does not support the construct. RTL synthesis does not expect to encounter the construct, and the failure mode shall be undefined. RTL synthesis may fail upon encountering such a construct. Failure is not mandatory; more specifically, RTL synthesis is allowed to treat such a construct as ignored. NOTE=97A synthesis tool may interpret constructs that are identified as not supported in this standard. However a model that contains such unsupported constructs is not compliant with this standard. ---------------------------------- End of Quote of 2004 specification -------------------------- My interpretation is that a synthesis tool vendor is permitted to support anything it likes that is labeled as not supported and still be compliant, but a model that uses constructs marked as not supported is not compliant with the standard. Although I worked on both the 1999 and 2004 committees, this is not an official interpretation of the standard. If you need an official interpretation, you can request this by contacting the chair of the sponsoring committee of standard. The sponsoring committee for both 1076.6 and most IEEE EDA standards is DASC. You can find DASC on the web at: http://www.dasc.org/ Cheers, Jim From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: case statement concatenation condition Date: Wed, 10 Jun 2009 23:33:01 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 35 Sender: mdhicks2@outside.world Message-ID: <6004390c237558cbb81104f05220@news.acm.uiuc.edu> References: <481035hecall89bq4osmjlq51clkgv8ghc@4ax.com> NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1244676781 24977 98.220.249.110 (10 Jun 2009 23:33:01 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Wed, 10 Jun 2009 23:33:01 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: news.eternal-september.org comp.lang.vhdl:1343 > On Wed, 10 Jun 2009 17:47:04 +0000 (UTC), Matthew Hicks wrote: > >> You may not even need to create a named subtype for this. You can >> create an anonymous subtype of the range you need. I have tried to >> write this up in a case statement, but I have done similar things in >> type declarations. >> >> i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is... >> > I can imagine that some tools may tolerate this, but it does not > appear to be legal VHDL. The syntax of a qualified expression is > > type_mark'(expression) > > and a type_mark must be simply a type name or subtype name. A > "subtype indication" won't do. > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com > > The contents of this message may contain personal views which are not > the views of Doulos Ltd., unless specifically stated. > You are right, I took a quick glance at the LRM, saw that it took an expression and figured a subtype indication (which consists of a type_mark and a possible constraint) would work. It doesn't since, as you pointed out, a qualified expression is limited to type marks. ---Matthew Hicks From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!k19g2000prh.googlegroups.com!not-for-mail From: Tim Doyle Newsgroups: comp.lang.vhdl Subject: Do I have a race condition for clk33_div? Date: Fri, 12 Jun 2009 08:29:00 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: NNTP-Posting-Host: 97.66.123.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1244820540 28248 127.0.0.1 (12 Jun 2009 15:29:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Jun 2009 15:29:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k19g2000prh.googlegroups.com; posting-host=97.66.123.254; posting-account=yUcZTgoAAAAjC3_dY8-nCddtGf8mGAFd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1344 I am looking to determine if the following VHDL process block creates a race condition for clk33_div, given that it is a signal that is being updated seemingly at same time it is being evaluated if I understand VHDL constructs. Any thoughts or guidelines would be greatly appreciated. Regards, Tim Doyle Here is the code: CLOCK_DIV: process (clk33, resetn) begin if resetn = '0' then clk33_div <= (others =>'0'); clock_out <= '0'; elsif clk33'event and clk33 = '1' then if clk33_div = "11000" then clk33_div <= (others => '0'); clock_out <= not(clock_out); else clk33_div <= clk33_div + '1'; clock_out <= clock_out; end if; end if; end process; From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w9g2000pro.googlegroups.com!not-for-mail From: Barry Newsgroups: comp.lang.vhdl Subject: Re: Do I have a race condition for clk33_div? Date: Fri, 12 Jun 2009 08:38:09 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: References: NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1244821089 30008 127.0.0.1 (12 Jun 2009 15:38:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Jun 2009 15:38:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000pro.googlegroups.com; posting-host=192.25.142.225; posting-account=4NVzAQoAAAC-7jG90dquZ3NiXsf363Dd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; Agilent Technologies IE6 SP1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1345 On Jun 12, 8:29=A0am, Tim Doyle wrote: > I am looking to determine if the following VHDL process block creates > a race condition for clk33_div, given that it is a signal that is > being updated seemingly at same time it is being evaluated if I > understand VHDL constructs. > > Any thoughts or guidelines would be greatly appreciated. > > Regards, > > Tim Doyle > > Here is the code: > > CLOCK_DIV: process (clk33, resetn) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if resetn =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk33_div <=3D (others = =3D>'0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock_out <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif clk33'event and clk33 =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if clk33_div =3D "11000" = then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk33_div= <=3D (others =3D> '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock_out= <=3D not(clock_out); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk33_div= <=3D clk33_div + '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock_out= <=3D clock_out; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; Hi Tim, In VHDL, a signal is not assigned its new value until you reach the "end process" statement (or a wait statement). This is different from the behavior of a variable in a process. Barry From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Do I have a race condition for clk33_div? Date: Fri, 12 Jun 2009 09:04:58 -0700 Lines: 21 Message-ID: <79fclaF1q7n3uU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net YbxwlX2kwX4bWGIa61LnQwDmST5Bfw1/g9bhrca7bqU3jQqiTp Cancel-Lock: sha1:MIlXeBi8iC/E3JpzJN3WiTw3P7c= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1346 > On Jun 12, 8:29 am, Tim Doyle wrote: >> I am looking to determine if the following VHDL process block creates >> a race condition for clk33_div, given that it is a signal that is >> being updated seemingly at same time it is being evaluated As long as I use clk33 as the only clock and clk_div as an enable input for other logic on the same clock, there will be no timing problems. Think of the right side of an assignment as gates on the D side of the flop Barry wrote: > In VHDL, a signal is not assigned its new value until you reach the > "end process" statement Which happens once every clock tick in Tim's example. The code looks functional to me. clock_out <= clock_out; is not necessary. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!news.motzarella.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!weretis.net!feeder2.news.weretis.net!feeder.news-service.com!postnews.google.com!c18g2000prh.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Sun, 14 Jun 2009 10:21:33 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245000093 3688 127.0.0.1 (14 Jun 2009 17:21:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Jun 2009 17:21:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c18g2000prh.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4168 comp.lang.vhdl:1347 Hi, I recently read Altera Stratix II, III and IV device handbook and found its 3-bit addition circuit is really a genius invention. But I was surprised to find that Altera patent application "Logic Cell Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has not been approved to be a patent so far today, even though many Altera later patent applications based on the invention have been approved for U.S. patents. Is anyone knowledgable about the patent application willing to transfer the patent application context to me and disclose why it hasn't been approved as a U.S. patent. My guess is it may never be approved by U.S. Patent Office to be a patent, the reason is not its novelty violation, but its context didn't disclose enough information about the 3-bit addition circuit, a requirement for any patent application to be approved to be a U.S. patent. At least those skilled in the art cannot get the idea what is done within its circuit having an encircled '+' with 3 inputs and 2 outputs. Altera another sister patent application "Arithmetic Structure is for Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. Thank you. Weng From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!w35g2000prg.googlegroups.com!not-for-mail From: JSreeniv Newsgroups: comp.lang.vhdl Subject: Modelsim resulution info Date: Sun, 14 Jun 2009 21:01:18 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <25c7f22a-eb38-43bb-8292-8548d8a731bf@w35g2000prg.googlegroups.com> NNTP-Posting-Host: 125.99.249.124 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245038479 27449 127.0.0.1 (15 Jun 2009 04:01:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 04:01:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000prg.googlegroups.com; posting-host=125.99.249.124; posting-account=cCqSmQoAAAD72P5YVFrs1ZNFbeH4XiZ1 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1348 Hi all, My query is about Modelsim simulation,.. If we run any simulation under the defined resultions time it takes some time to finish the simulation. What i want is is there any equation to calculate the time period or days, if i increase the simulation time to 1 sec or more? Please give exposure on this knowledge! Sreeni Moog,Inc From newsfish@newsfish Wed Aug 19 13:25:02 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y7g2000yqa.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Modelsim resulution info Date: Sun, 14 Jun 2009 23:15:57 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <25c7f22a-eb38-43bb-8292-8548d8a731bf@w35g2000prg.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245046557 19123 127.0.0.1 (15 Jun 2009 06:15:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 06:15:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y7g2000yqa.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.9) Gecko/2009050519 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1349 On 15 Jun., 06:01, JSreeniv wrote: > Hi all, > > My query is about Modelsim simulation,.. > If we run any simulation under the defined resultions time it takes > some time to finish the simulation. > What i want is is there any equation to calculate the time period or > days, if i increase the simulation time to 1 sec or more? > > Please give exposure on this knowledge! > > Sreeni > Moog,Inc Hi Sreeni, if your simulated circuit performs repetitive tasks (e.g. video applications) you can multiply the time used for one picture by N to estimate the simulation time for N pictures. As always there's some limitation. If your circuit activates additional modules based on special conditions, your calculation will fail. Extra logic to simulate = extra transitions to calculate = increasing simulation time. >From my experience: I calculated the time for some picture frames to be a few days, but based on the simulation time before synchronisation lock. After synchronisation the DDR-module was activated. This slowed down simulation speed drastically. A recalculation based on the new simulation speed resulted in a new overall simulation times of half a month. So that's the variation of results you can have if it goes bad. But if you have enough knowledge about your design you can minimize such errors. Have a nice simulation. Eilert From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n7g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 04:36:52 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245065812 26302 127.0.0.1 (15 Jun 2009 11:36:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 11:36:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000prc.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4172 comp.lang.vhdl:1350 On Jun 14, 1:21=A0pm, Weng Tianxiang wrote: > Hi, > I recently read Altera Stratix II, III and IV device handbook and > found its 3-bit addition circuit is really a genius invention. But I > was surprised to find that Altera patent application "Logic Cell > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > not been approved to be a patent so far today, even though many Altera > later patent applications based on the invention have been approved > for U.S. patents. > > Is anyone knowledgable about the patent application willing to > transfer the patent application context to me and disclose why it > hasn't been approved as a U.S. patent. > > My guess is it may never be approved by U.S. Patent Office to be a > patent, the reason is not its novelty violation, but its context > didn't disclose enough information about the 3-bit addition circuit, a > requirement for any patent application to be approved to be a U.S. > patent. At least those skilled in the art cannot get the idea what is > done within its circuit having an encircled '+' with 3 inputs and 2 > outputs. > > Altera another sister patent application "Arithmetic Structure is for > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > Thank you. > > Weng I don't know why Altera wouldn't disclose info on the structure being used in a device. It is relatively inexpensive to reverse engineer a chip, so if it is not disclosed in a patent, it is not protected and is vulnerable to being copied. What exactly *does* the patent claim? Maybe the design inside the circled + is not really novel and only the design around the circle is novel enough to be patented? In general, I think a three in put adder is *very useful*. I've never seen such a circuit, I guess the carry chain has multiple bits, eh? Rick From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z8g2000prd.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 07:13:19 -0700 (PDT) Organization: http://groups.google.com Lines: 65 Message-ID: <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245075200 29534 127.0.0.1 (15 Jun 2009 14:13:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 14:13:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z8g2000prd.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4174 comp.lang.vhdl:1351 On Jun 15, 4:36=A0am, rickman wrote: > On Jun 14, 1:21=A0pm, Weng Tianxiang wrote: > > > > > > > Hi, > > I recently read Altera Stratix II, III and IV device handbook and > > found its 3-bit addition circuit is really a genius invention. But I > > was surprised to find that Altera patent application "Logic Cell > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > > not been approved to be a patent so far today, even though many Altera > > later patent applications based on the invention have been approved > > for U.S. patents. > > > Is anyone knowledgable about the patent application willing to > > transfer the patent application context to me and disclose why it > > hasn't been approved as a U.S. patent. > > > My guess is it may never be approved by U.S. Patent Office to be a > > patent, the reason is not its novelty violation, but its context > > didn't disclose enough information about the 3-bit addition circuit, a > > requirement for any patent application to be approved to be a U.S. > > patent. At least those skilled in the art cannot get the idea what is > > done within its circuit having an encircled '+' with 3 inputs and 2 > > outputs. > > > Altera another sister patent application "Arithmetic Structure is for > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > > Thank you. > > > Weng > > I don't know why Altera wouldn't disclose info on the structure being > used in a device. =A0It is relatively inexpensive to reverse engineer a > chip, so if it is not disclosed in a patent, it is not protected and > is vulnerable to being copied. > > What exactly *does* the patent claim? =A0Maybe the design inside the > circled + is not really novel and only the design around the circle is > novel enough to be patented? > > In general, I think a three in put adder is *very useful*. =A0I've never > seen such a circuit, I guess the carry chain has multiple bits, eh? > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 shows the invention circuit: http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it describes two applications: multiplication and correlation function. Any other applications? With multiplier hardware structure specially introduced in FPGA, is multiplication circuit still used for multiplication? Weng From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!u9g2000prd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 08:39:11 -0700 (PDT) Organization: http://groups.google.com Lines: 83 Message-ID: <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245080454 17371 127.0.0.1 (15 Jun 2009 15:40:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 15:40:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u9g2000prd.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4179 comp.lang.vhdl:1352 On Jun 15, 10:13 am, Weng Tianxiang wrote: > On Jun 15, 4:36 am, rickman wrote: > > > > > On Jun 14, 1:21 pm, Weng Tianxiang wrote: > > > > Hi, > > > I recently read Altera Stratix II, III and IV device handbook and > > > found its 3-bit addition circuit is really a genius invention. But I > > > was surprised to find that Altera patent application "Logic Cell > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > > > not been approved to be a patent so far today, even though many Altera > > > later patent applications based on the invention have been approved > > > for U.S. patents. > > > > Is anyone knowledgable about the patent application willing to > > > transfer the patent application context to me and disclose why it > > > hasn't been approved as a U.S. patent. > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > patent, the reason is not its novelty violation, but its context > > > didn't disclose enough information about the 3-bit addition circuit, a > > > requirement for any patent application to be approved to be a U.S. > > > patent. At least those skilled in the art cannot get the idea what is > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > outputs. > > > > Altera another sister patent application "Arithmetic Structure is for > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > > > Thank you. > > > > Weng > > > I don't know why Altera wouldn't disclose info on the structure being > > used in a device. It is relatively inexpensive to reverse engineer a > > chip, so if it is not disclosed in a patent, it is not protected and > > is vulnerable to being copied. > > > What exactly *does* the patent claim? Maybe the design inside the > > circled + is not really novel and only the design around the circle is > > novel enough to be patented? > > > In general, I think a three in put adder is *very useful*. I've never > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > describes two applications: multiplication and correlation function. > > Any other applications? With multiplier hardware structure specially > introduced in FPGA, is multiplication circuit still used for > multiplication? Although they show the interconnections being used, they don't show the logic implemented in the LUTs. The carry from one bit to the next is done with two signals each of which has the same weight. As far as I can tell, this is just a pair of cascaded adders, the first done in the LUTs and the second done in dedicated hardware. The only novelty is that instead of adding two inputs with one adder chain (the LUTs) and then adding the result to the third input with the dedicated hardware chain, they add all three input bits using the LUTs and feed both carry bits into the dedicated hardware chain which means the carry chain always uses the fast, dedicated hardware. Does that sound like a patent worthy invention to you? I don't really know what is and what is not worthy of a patent. But other patents "based" on this patent will not be affected by the validity of this patent. Even if this patent is upheld, ***I*** could patent some additional feature that uses this design as a starting point. I just can't build it without permission from the patent holder of the original design. Still, this means he/she couldn't use my idea without my permission either. Rick From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w35g2000prg.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 09:22:22 -0700 (PDT) Organization: http://groups.google.com Lines: 111 Message-ID: <09677e3d-4715-4926-9ac7-fd4cc7137a32@w35g2000prg.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245082942 26848 127.0.0.1 (15 Jun 2009 16:22:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 16:22:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000prg.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4180 comp.lang.vhdl:1353 On Jun 15, 8:39=A0am, rickman wrote: > On Jun 15, 10:13 am, Weng Tianxiang wrote: > > > > > > > On Jun 15, 4:36 am, rickman wrote: > > > > On Jun 14, 1:21 pm, Weng Tianxiang wrote: > > > > > Hi, > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > found its 3-bit addition circuit is really a genius invention. But = I > > > > was surprised to find that Altera patent application "Logic Cell > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 h= as > > > > not been approved to be a patent so far today, even though many Alt= era > > > > later patent applications based on the invention have been approved > > > > for U.S. patents. > > > > > Is anyone knowledgable about the patent application willing to > > > > transfer the patent application context to me and disclose why it > > > > hasn't been approved as a U.S. patent. > > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > > patent, the reason is not its novelty violation, but its context > > > > didn't disclose enough information about the 3-bit addition circuit= , a > > > > requirement for any patent application to be approved to be a U.S. > > > > patent. At least those skilled in the art cannot get the idea what = is > > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > > outputs. > > > > > Altera another sister patent application "Arithmetic Structure is f= or > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate= . > > > > > Thank you. > > > > > Weng > > > > I don't know why Altera wouldn't disclose info on the structure being > > > used in a device. =A0It is relatively inexpensive to reverse engineer= a > > > chip, so if it is not disclosed in a patent, it is not protected and > > > is vulnerable to being copied. > > > > What exactly *does* the patent claim? =A0Maybe the design inside the > > > circled + is not really novel and only the design around the circle i= s > > > novel enough to be patented? > > > > In general, I think a three in put adder is *very useful*. =A0I've ne= ver > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > shows the invention circuit:http://www.altera.com/literature/hb/stratix= -iv/stx4_5v1.pdf > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > describes two applications: multiplication and correlation function. > > > Any other applications? With multiplier hardware structure specially > > introduced in FPGA, is multiplication circuit still used for > > multiplication? > > Although they show the interconnections being used, they don't show > the logic implemented in the LUTs. =A0The carry from one bit to the next > is done with two signals each of which has the same weight. =A0As far as > I can tell, this is just a pair of cascaded adders, the first done in > the LUTs and the second done in dedicated hardware. =A0The only novelty > is that instead of adding two inputs with one adder chain (the LUTs) > and then adding the result to the third input with the dedicated > hardware chain, they add all three input bits using the LUTs and feed > both carry bits into the dedicated hardware chain which means the > carry chain always uses the fast, dedicated hardware. > > Does that sound like a patent worthy invention to you? =A0I don't really > know what is and what is not worthy of a patent. =A0But other patents > "based" on this patent will not be affected by the validity of this > patent. =A0Even if this patent is upheld, ***I*** could patent some > additional feature that uses this design as a starting point. =A0I just > can't build it without permission from the patent holder of the > original design. =A0Still, this means he/she couldn't use my idea > without my permission either. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, There are two novel points there: 1. It transfers 3 adders into 2 adders which was described very clear: nobody before had invented that point. 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose internal structure wasn't shown. 3. I am sure there may be more than 20 claims in the application as Altera patent claim trandition goes. Weng From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w9g2000pro.googlegroups.com!not-for-mail From: OutputLogic Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 09:23:45 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> NNTP-Posting-Host: 76.254.236.137 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245083144 21824 127.0.0.1 (15 Jun 2009 16:25:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 16:25:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000pro.googlegroups.com; posting-host=76.254.236.137; posting-account=SKCtowkAAAAV14AiC-uMfTe8gGDfZXe8 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/530.5 (KHTML, like Gecko) Chrome/2.0.172.31 Safari/530.5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4182 comp.lang.vhdl:1354 You can try to go to USPTO database and lookup the history of this patent application. It's not under the patent search, but under "http://www.uspto.gov" -> "Patents" -> "view in PAIR" -> "public PAIR". This database contains a complete history of the patent, including the correspondence with patent examiners, etc. Also, can you post the patent application number. - outputlogic http://outputlogic.com From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!d2g2000pra.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 10:27:34 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245086854 9501 127.0.0.1 (15 Jun 2009 17:27:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 17:27:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d2g2000pra.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4184 comp.lang.vhdl:1355 On Jun 15, 9:23=A0am, OutputLogic wrote: > You can try to go to USPTO database and lookup the history of this > patent application. > It's not under the patent search, but under "http://www.uspto.gov" -> > "Patents" -> "view in PAIR" -> "public PAIR". > This database contains a complete history of the patent, including the > correspondence with patent examiners, etc. > Also, can you post the patent application number. > > - outputlogic > > http://outputlogic.com Hi, Its application number is 10/718,968 filed on November 21, 2003. Weng From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!p21g2000prn.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 10:39:41 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245087581 6089 127.0.0.1 (15 Jun 2009 17:39:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 17:39:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p21g2000prn.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4186 comp.lang.vhdl:1356 On Jun 15, 9:23=A0am, OutputLogic wrote: > You can try to go to USPTO database and lookup the history of this > patent application. > It's not under the patent search, but under "http://www.uspto.gov" -> > "Patents" -> "view in PAIR" -> "public PAIR". > This database contains a complete history of the patent, including the > correspondence with patent examiners, etc. > Also, can you post the patent application number. > > - outputlogic > > http://outputlogic.com Hi OutputLogic, Thank you for your information. I had searched the website before I posed this message and got the error information: "Sorry, the entered Application Number "10/718968" is not available. The number may have been incorrectly typed, or assigned to an application that is not yet available for public inspection." I don't know why I got the error message. 10/718968 is available from reference literature in the invention: "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality", patent number 7,394,287, by Alera from following website: http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:7394287&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D Weng From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x31g2000prc.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Want flag to keep value through all states Date: Mon, 15 Jun 2009 13:34:04 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245098045 19899 127.0.0.1 (15 Jun 2009 20:34:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 20:34:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x31g2000prc.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1357 I am using a single-process state-machine style of coding. I have a flag that gets set or cleared in one state. I want it to keep whatever value that is throughout the rest of the state machine until the machine returns to that state. What is the correct way of doing this? Please note that I am not referring to a "default" state. That much I understand. I just want the flag to be set once and then stay that way regardless of the condition that set it changing later. Process (clk) begin if rising_edge(clk) then case state when one => flag <= input; ... when two => if flag = '1' then .... else .... etc... Thanks, Shannon From newsfish@newsfish Wed Aug 19 13:25:03 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d7g2000prl.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Mon, 15 Jun 2009 13:45:47 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <152f2f10-4e6a-4a93-865c-4a583f86c346@d7g2000prl.googlegroups.com> References: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245098748 15897 127.0.0.1 (15 Jun 2009 20:45:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 20:45:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000prl.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1358 On Jun 15, 1:34=A0pm, Shannon wrote: > I am using a single-process state-machine style of coding. =A0I have a > flag that gets set or cleared in one state. =A0I want it to keep > whatever value that is throughout the rest of the state machine until > the machine returns to that state. =A0What is the correct way of doing > this? > > Please note that I am not referring to a "default" state. =A0That much I > understand. =A0I just want the flag to be set once and then stay that > way regardless of the condition that set it changing later. > > Process (clk) > begin > =A0 if rising_edge(clk) then > =A0 =A0 case state > =A0 =A0 =A0 when one =3D> > =A0 =A0 =A0 =A0 =A0flag <=3D input; > =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 when two =3D> > =A0 =A0 =A0 =A0 =A0if flag =3D '1' then > =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0.... > etc... > > Thanks, > Shannon I'm suffering post traumatic "send" disorder.... I'm betting that I don't have to do anything since it is in a clocked process and will become a register. Shannon From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.kpn.net!pfeed09.wxs.nl!news.astraweb.com!border3.a.newsrouter.astraweb.com!multikabel.net!newsfeed10.multikabel.net!feeder.news-service.com!postnews.google.com!i28g2000prd.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Mon, 15 Jun 2009 13:47:42 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: <80777bf9-bf4e-41c0-a722-a9d595fb4812@i28g2000prd.googlegroups.com> References: NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245098862 23249 127.0.0.1 (15 Jun 2009 20:47:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 20:47:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000prd.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1359 On Jun 15, 4:34=A0pm, Shannon wrote: > I am using a single-process state-machine style of coding. =A0I have a > flag that gets set or cleared in one state. =A0I want it to keep > whatever value that is throughout the rest of the state machine until > the machine returns to that state. =A0What is the correct way of doing > this? > > Please note that I am not referring to a "default" state. =A0That much I > understand. =A0I just want the flag to be set once and then stay that > way regardless of the condition that set it changing later. > > Process (clk) > begin > =A0 if rising_edge(clk) then > =A0 =A0 case state > =A0 =A0 =A0 when one =3D> > =A0 =A0 =A0 =A0 =A0flag <=3D input; > =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 when two =3D> > =A0 =A0 =A0 =A0 =A0if flag =3D '1' then > =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0.... > etc... > > Thanks, > Shannon If you simply don't assign the signal's value in those states where the signal should remain unchanged, then the value will remain the same until the next clock tick. The synthesizer will implement this by making the clock enable for the signal's register '0' for those states where the signal is not assigned. This is one of the nice things about single-process state machines. Dave From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k17g2000prn.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 16:44:19 -0700 (PDT) Organization: http://groups.google.com Lines: 118 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245109459 7276 127.0.0.1 (15 Jun 2009 23:44:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Jun 2009 23:44:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k17g2000prn.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4187 comp.lang.vhdl:1360 On Jun 15, 8:39=A0am, rickman wrote: > On Jun 15, 10:13 am, Weng Tianxiang wrote: > > > > > > > On Jun 15, 4:36 am, rickman wrote: > > > > On Jun 14, 1:21 pm, Weng Tianxiang wrote: > > > > > Hi, > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > found its 3-bit addition circuit is really a genius invention. But = I > > > > was surprised to find that Altera patent application "Logic Cell > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 h= as > > > > not been approved to be a patent so far today, even though many Alt= era > > > > later patent applications based on the invention have been approved > > > > for U.S. patents. > > > > > Is anyone knowledgable about the patent application willing to > > > > transfer the patent application context to me and disclose why it > > > > hasn't been approved as a U.S. patent. > > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > > patent, the reason is not its novelty violation, but its context > > > > didn't disclose enough information about the 3-bit addition circuit= , a > > > > requirement for any patent application to be approved to be a U.S. > > > > patent. At least those skilled in the art cannot get the idea what = is > > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > > outputs. > > > > > Altera another sister patent application "Arithmetic Structure is f= or > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate= . > > > > > Thank you. > > > > > Weng > > > > I don't know why Altera wouldn't disclose info on the structure being > > > used in a device. =A0It is relatively inexpensive to reverse engineer= a > > > chip, so if it is not disclosed in a patent, it is not protected and > > > is vulnerable to being copied. > > > > What exactly *does* the patent claim? =A0Maybe the design inside the > > > circled + is not really novel and only the design around the circle i= s > > > novel enough to be patented? > > > > In general, I think a three in put adder is *very useful*. =A0I've ne= ver > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > shows the invention circuit:http://www.altera.com/literature/hb/stratix= -iv/stx4_5v1.pdf > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > describes two applications: multiplication and correlation function. > > > Any other applications? With multiplier hardware structure specially > > introduced in FPGA, is multiplication circuit still used for > > multiplication? > > Although they show the interconnections being used, they don't show > the logic implemented in the LUTs. =A0The carry from one bit to the next > is done with two signals each of which has the same weight. =A0As far as > I can tell, this is just a pair of cascaded adders, the first done in > the LUTs and the second done in dedicated hardware. =A0The only novelty > is that instead of adding two inputs with one adder chain (the LUTs) > and then adding the result to the third input with the dedicated > hardware chain, they add all three input bits using the LUTs and feed > both carry bits into the dedicated hardware chain which means the > carry chain always uses the fast, dedicated hardware. > > Does that sound like a patent worthy invention to you? =A0I don't really > know what is and what is not worthy of a patent. =A0But other patents > "based" on this patent will not be affected by the validity of this > patent. =A0Even if this patent is upheld, ***I*** could patent some > additional feature that uses this design as a starting point. =A0I just > can't build it without permission from the patent holder of the > original design. =A0Still, this means he/she couldn't use my idea > without my permission either. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, "The only novelty is that instead of adding two inputs with one adder chain (the LUTs) and then adding the result to the third input with the dedicated hardware chain, they add all three input bits using the LUTs and feed both carry bits into the dedicated hardware chain which means the carry chain always uses the fast, dedicated hardware. " The method I found was invented as early as 1963 by C.S. Wallace in paper "A suggestion for a Fast Multiplier" http://www.caip.rutgers.edu/~bushnell/dsmdesign/wallacepaper.pdf The circuit circled in '+' with 3 inputs and 2 outputs is novelty in my opinion, but they didn't disclose it. Weng From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!flpi107.ffdc.sbc.com!flpi144.ffdc.sbc.com.POSTED!857c7983!not-for-mail From: Muzaffer Kal Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Organization: DSPIA INC. http://www.dspia.com Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 16 NNTP-Posting-Host: 75.101.94.80 X-Complaints-To: abuse@prodigy.net X-Trace: flpi144.ffdc.sbc.com 1245110774 ST000 75.101.94.80 (Mon, 15 Jun 2009 20:06:14 EDT) NNTP-Posting-Date: Mon, 15 Jun 2009 20:06:14 EDT X-UserInfo1: Q[R_PJSCOHU[ST@[@JK@NFXBWR\HPCTL@XT^OBPLAH[\BQUBLNTC@AWZWDXZXQ[K\FFSKCVM@F_N_DOBWVWG__LG@VVOIPLIGX\\BU_B@\P\PFX\B[APHTWAHDCKJF^NHD[YJAZMCY_CWG[SX\Y]^KC\HSZRWSWKGAY_PC[BQ[BXAS\F\\@DMTLFZFUE@\VL Date: Mon, 15 Jun 2009 17:06:07 -0700 Xref: news.eternal-september.org comp.arch.fpga:4188 comp.lang.vhdl:1361 On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang wrote: >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in >my opinion, but they didn't disclose it. > It would be interesting to see if it's anything other than a 3:2 compressor. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y6g2000prf.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 18:41:51 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <9d211743-30a4-4541-8310-c8fe3d359d90@y6g2000prf.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245116512 28889 127.0.0.1 (16 Jun 2009 01:41:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 01:41:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y6g2000prf.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4190 comp.lang.vhdl:1362 On Jun 15, 5:06=A0pm, Muzaffer Kal wrote: > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang > > wrote: > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in > >my opinion, but they didn't disclose it. > > It would be interesting to see if it's anything other than a 3:2 > compressor. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Here is another good reference published in 1994 by Stanford Ph. D student Gary W. Bewick as his dissatation paper. ftp://reports.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf= , page 34 where a 3:2 compressor was shown graphically. Weng From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!g1g2000yqh.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 21:25:13 -0700 (PDT) Organization: http://groups.google.com Lines: 146 Message-ID: <48f24613-71f8-4dcb-bb8e-dbdd64ab4f0c@g1g2000yqh.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> <09677e3d-4715-4926-9ac7-fd4cc7137a32@w35g2000prg.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245126313 26446 127.0.0.1 (16 Jun 2009 04:25:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 04:25:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g1g2000yqh.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4192 comp.lang.vhdl:1363 On Jun 15, 12:22=A0pm, Weng Tianxiang wrote: > On Jun 15, 8:39=A0am, rickman wrote: > > > > > On Jun 15, 10:13 am, Weng Tianxiang wrote: > > > > On Jun 15, 4:36 am, rickman wrote: > > > > > On Jun 14, 1:21 pm, Weng Tianxiang wrote: > > > > > > Hi, > > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > > found its 3-bit addition circuit is really a genius invention. Bu= t I > > > > > was surprised to find that Altera patent application "Logic Cell > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003= has > > > > > not been approved to be a patent so far today, even though many A= ltera > > > > > later patent applications based on the invention have been approv= ed > > > > > for U.S. patents. > > > > > > Is anyone knowledgable about the patent application willing to > > > > > transfer the patent application context to me and disclose why it > > > > > hasn't been approved as a U.S. patent. > > > > > > My guess is it may never be approved by U.S. Patent Office to be = a > > > > > patent, the reason is not its novelty violation, but its context > > > > > didn't disclose enough information about the 3-bit addition circu= it, a > > > > > requirement for any patent application to be approved to be a U.S= . > > > > > patent. At least those skilled in the art cannot get the idea wha= t is > > > > > done within its circuit having an encircled '+' with 3 inputs and= 2 > > > > > outputs. > > > > > > Altera another sister patent application "Arithmetic Structure is= for > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fa= te. > > > > > > Thank you. > > > > > > Weng > > > > > I don't know why Altera wouldn't disclose info on the structure bei= ng > > > > used in a device. =A0It is relatively inexpensive to reverse engine= er a > > > > chip, so if it is not disclosed in a patent, it is not protected an= d > > > > is vulnerable to being copied. > > > > > What exactly *does* the patent claim? =A0Maybe the design inside th= e > > > > circled + is not really novel and only the design around the circle= is > > > > novel enough to be patented? > > > > > In general, I think a three in put adder is *very useful*. =A0I've = never > > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > > Rick- Hide quoted text - > > > > > - Show quoted text - > > > > Hi Rick, > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > > shows the invention circuit:http://www.altera.com/literature/hb/strat= ix-iv/stx4_5v1.pdf > > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > > describes two applications: multiplication and correlation function. > > > > Any other applications? With multiplier hardware structure specially > > > introduced in FPGA, is multiplication circuit still used for > > > multiplication? > > > Although they show the interconnections being used, they don't show > > the logic implemented in the LUTs. =A0The carry from one bit to the nex= t > > is done with two signals each of which has the same weight. =A0As far a= s > > I can tell, this is just a pair of cascaded adders, the first done in > > the LUTs and the second done in dedicated hardware. =A0The only novelty > > is that instead of adding two inputs with one adder chain (the LUTs) > > and then adding the result to the third input with the dedicated > > hardware chain, they add all three input bits using the LUTs and feed > > both carry bits into the dedicated hardware chain which means the > > carry chain always uses the fast, dedicated hardware. > > > Does that sound like a patent worthy invention to you? =A0I don't reall= y > > know what is and what is not worthy of a patent. =A0But other patents > > "based" on this patent will not be affected by the validity of this > > patent. =A0Even if this patent is upheld, ***I*** could patent some > > additional feature that uses this design as a starting point. =A0I just > > can't build it without permission from the patent holder of the > > original design. =A0Still, this means he/she couldn't use my idea > > without my permission either. > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > There are two novel points there: > 1. It transfers 3 adders into 2 adders which was described very clear: > nobody before had invented that point. No, it is not 3 adders using 2 adders, it is always just 2 adders. The only difference is that there is only one cascaded chain. There are two carries between each bit of the adder, sort of like a "Propagate/Generate" style of carry, only one results in a chained delay calculation. But I don't see any real advantage to that. I think the real advantage of this circuit is that it takes advantage of the large, 6 input LUT by breaking it into dual 4 input LUTs... but wait, that is still wasting half the 6 input LUTs. So it is really just an optimization of their particular architecture. The only possible novelty here is that they are doing this in an FPGA. > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose > internal structure wasn't shown. Yep, that is because that part is not very patentable, in my opinion. You don't put anything in a patent that is not patentable. Anything you don't explain in a patent is not part of it. > 3. I am sure there may be more than 20 claims in the application as > Altera patent claim trandition goes. Sure, any patent attorney worth his salt is going to put as many claims in as possible. If I understand correctly any claim can stand alone even if the others are struck down. Rick From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeds.phibee-telecom.net!feeder.news-service.com!postnews.google.com!h18g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 21:31:49 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <7a8c2ae5-18a3-4da2-bd03-e10c42eb132d@h18g2000yqj.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245126712 27736 127.0.0.1 (16 Jun 2009 04:31:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 04:31:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h18g2000yqj.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4193 comp.lang.vhdl:1364 On Jun 15, 8:06=A0pm, Muzaffer Kal wrote: > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang > > wrote: > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in > >my opinion, but they didn't disclose it. > > It would be interesting to see if it's anything other than a 3:2 > compressor. Someone is missing something. What is the three input, two output circuit? Each bit of the adder has five inputs and three outputs. The three addend inputs can add up to 3 and with the two carry inputs the total can be up to five requiring two carrie outputs of weight 2 and the sum output of weight 1. Of course, I am looking at the data sheet and I guess you are looking at the patent. Rick From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z14g2000yqa.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Mon, 15 Jun 2009 21:41:20 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245127280 6504 127.0.0.1 (16 Jun 2009 04:41:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 04:41:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqa.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4194 comp.lang.vhdl:1365 On Jun 15, 1:39=A0pm, Weng Tianxiang wrote: > On Jun 15, 9:23=A0am, OutputLogic wrote: > > > You can try to go to USPTO database and lookup the history of this > > patent application. > > It's not under the patent search, but under "http://www.uspto.gov" -> > > "Patents" -> "view in PAIR" -> "public PAIR". > > This database contains a complete history of the patent, including the > > correspondence with patent examiners, etc. > > Also, can you post the patent application number. > > > - outputlogic > > >http://outputlogic.com > > Hi OutputLogic, > Thank you for your information. > > I had searched the website before I posed this message and got the > error information: > "Sorry, the entered Application Number "10/718968" is not available. > The number may have been incorrectly typed, or assigned to an > application > that is not yet available for public inspection." > > I don't know why I got the error message. > > 10/718968 is available from reference literature in the invention: > "Programmable Logic Device Having Complex Logic Blocks with Improved > Logic Cell Functionality", patent number 7,394,287, by Alera from > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&d= q=3Dpatent:7394287... > > Weng 7,394,287 is the patent number. It works for me at the USPTO. What is the number you are searching for? Rick From newsfish@newsfish Wed Aug 19 13:25:04 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!d25g2000prn.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST) Date: Tue, 16 Jun 2009 06:25:05 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245158705 29011 127.0.0.1 (16 Jun 2009 13:25:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 13:25:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d25g2000prn.googlegroups.com; posting-host=132.228.195.207; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1368 I'm coding for the first time in 10 years in VHDL and am trying to find equivalents to my old verilog tool-box. One tool I found extremely useful was the AUTOINST features of the verilog-mode in emacs where it would automatically connect instance ports and where you could define per-instance naming rules via AUTO_TEMPLATE. I've discovered the port copy/port-paste as... feature in the emacs vhdl- mode, but am wondering if that's as close as I can get to the auto- instantiate feature of the verilog-mode? Thanks, Mark From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w35g2000prg.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Tue, 16 Jun 2009 06:25:46 -0700 (PDT) Organization: http://groups.google.com Lines: 183 Message-ID: <17307062-a43c-433d-987b-ce2c6c14490f@w35g2000prg.googlegroups.com> References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <7054e49c-55d3-4607-a604-a5214258ceb4@z8g2000prd.googlegroups.com> <964d691c-d9b5-43c7-8fa8-72b85c5b17f7@u9g2000prd.googlegroups.com> <09677e3d-4715-4926-9ac7-fd4cc7137a32@w35g2000prg.googlegroups.com> <48f24613-71f8-4dcb-bb8e-dbdd64ab4f0c@g1g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245158746 11485 127.0.0.1 (16 Jun 2009 13:25:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 13:25:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w35g2000prg.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4202 comp.lang.vhdl:1369 On Jun 15, 9:25=A0pm, rickman wrote: > On Jun 15, 12:22=A0pm, Weng Tianxiang wrote: > > > > > > > On Jun 15, 8:39=A0am, rickman wrote: > > > > On Jun 15, 10:13 am, Weng Tianxiang wrote: > > > > > On Jun 15, 4:36 am, rickman wrote: > > > > > > On Jun 14, 1:21 pm, Weng Tianxiang wrote: > > > > > > > Hi, > > > > > > I recently read Altera Stratix II, III and IV device handbook a= nd > > > > > > found its 3-bit addition circuit is really a genius invention. = But I > > > > > > was surprised to find that Altera patent application "Logic Cel= l > > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 20= 03 has > > > > > > not been approved to be a patent so far today, even though many= Altera > > > > > > later patent applications based on the invention have been appr= oved > > > > > > for U.S. patents. > > > > > > > Is anyone knowledgable about the patent application willing to > > > > > > transfer the patent application context to me and disclose why = it > > > > > > hasn't been approved as a U.S. patent. > > > > > > > My guess is it may never be approved by U.S. Patent Office to b= e a > > > > > > patent, the reason is not its novelty violation, but its contex= t > > > > > > didn't disclose enough information about the 3-bit addition cir= cuit, a > > > > > > requirement for any patent application to be approved to be a U= .S. > > > > > > patent. At least those skilled in the art cannot get the idea w= hat is > > > > > > done within its circuit having an encircled '+' with 3 inputs a= nd 2 > > > > > > outputs. > > > > > > > Altera another sister patent application "Arithmetic Structure = is for > > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same = fate. > > > > > > > Thank you. > > > > > > > Weng > > > > > > I don't know why Altera wouldn't disclose info on the structure b= eing > > > > > used in a device. =A0It is relatively inexpensive to reverse engi= neer a > > > > > chip, so if it is not disclosed in a patent, it is not protected = and > > > > > is vulnerable to being copied. > > > > > > What exactly *does* the patent claim? =A0Maybe the design inside = the > > > > > circled + is not really novel and only the design around the circ= le is > > > > > novel enough to be patented? > > > > > > In general, I think a three in put adder is *very useful*. =A0I'v= e never > > > > > seen such a circuit, I guess the carry chain has multiple bits, e= h? > > > > > > Rick- Hide quoted text - > > > > > > - Show quoted text - > > > > > Hi Rick, > > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > > > shows the invention circuit:http://www.altera.com/literature/hb/str= atix-iv/stx4_5v1.pdf > > > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, = it > > > > describes two applications: multiplication and correlation function= . > > > > > Any other applications? With multiplier hardware structure speciall= y > > > > introduced in FPGA, is multiplication circuit still used for > > > > multiplication? > > > > Although they show the interconnections being used, they don't show > > > the logic implemented in the LUTs. =A0The carry from one bit to the n= ext > > > is done with two signals each of which has the same weight. =A0As far= as > > > I can tell, this is just a pair of cascaded adders, the first done in > > > the LUTs and the second done in dedicated hardware. =A0The only novel= ty > > > is that instead of adding two inputs with one adder chain (the LUTs) > > > and then adding the result to the third input with the dedicated > > > hardware chain, they add all three input bits using the LUTs and feed > > > both carry bits into the dedicated hardware chain which means the > > > carry chain always uses the fast, dedicated hardware. > > > > Does that sound like a patent worthy invention to you? =A0I don't rea= lly > > > know what is and what is not worthy of a patent. =A0But other patents > > > "based" on this patent will not be affected by the validity of this > > > patent. =A0Even if this patent is upheld, ***I*** could patent some > > > additional feature that uses this design as a starting point. =A0I ju= st > > > can't build it without permission from the patent holder of the > > > original design. =A0Still, this means he/she couldn't use my idea > > > without my permission either. > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > There are two novel points there: > > 1. It transfers 3 adders into 2 adders which was described very clear: > > nobody before had invented that point. > > No, it is not 3 adders using 2 adders, it is always just 2 adders. > The only difference is that there is only one cascaded chain. =A0There > are two carries between each bit of the adder, sort of like a > "Propagate/Generate" style of carry, only one results in a chained > delay calculation. =A0But I don't see any real advantage to that. =A0I > think the real advantage of this circuit is that it takes advantage of > the large, 6 input LUT by breaking it into dual 4 input LUTs... but > wait, that is still wasting half the 6 input LUTs. =A0So it is really > just an optimization of their particular architecture. > > The only possible novelty here is that they are doing this in an > FPGA. > > > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose > > internal structure wasn't shown. > > Yep, that is because that part is not very patentable, in my opinion. > You don't put anything in a patent that is not patentable. =A0Anything > you don't explain in a patent is not part of it. > > > 3. I am sure there may be more than 20 claims in the application as > > Altera patent claim trandition goes. > > Sure, any patent attorney worth his salt is going to put as many > claims in as possible. =A0If I understand correctly any claim can stand > alone even if the others are struck down. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, "No, it is not 3 adders using 2 adders, it is always just 2 adders. The only difference is that there is only one cascaded chain. There are two carries between each bit of the adder, sort of like a "Propagate/Generate" style of carry, only one results in a chained delay calculation. But I don't see any real advantage to that. I think the real advantage of this circuit is that it takes advantage of the large, 6 input LUT by breaking it into dual 4 input LUTs... but wait, that is still wasting half the 6 input LUTs. So it is really just an optimization of their particular architecture. The only possible novelty here is that they are doing this in an FPGA. " Thank you for your comments. You are right. I realized it after I posed the message and re-read other papers about 3:2 compressor and I didn't correct it myself. From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!d38g2000prn.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Tue, 16 Jun 2009 06:34:09 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245159250 30707 127.0.0.1 (16 Jun 2009 13:34:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 13:34:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d38g2000prn.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4203 comp.lang.vhdl:1370 On Jun 15, 9:41=A0pm, rickman wrote: > On Jun 15, 1:39=A0pm, Weng Tianxiang wrote: > > > > > > > On Jun 15, 9:23=A0am, OutputLogic wrote: > > > > You can try to go to USPTO database and lookup the history of this > > > patent application. > > > It's not under the patent search, but under "http://www.uspto.gov" -> > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > This database contains a complete history of the patent, including th= e > > > correspondence with patent examiners, etc. > > > Also, can you post the patent application number. > > > > - outputlogic > > > >http://outputlogic.com > > > Hi OutputLogic, > > Thank you for your information. > > > I had searched the website before I posed this message and got the > > error information: > > "Sorry, the entered Application Number "10/718968" is not available. > > The number may have been incorrectly typed, or assigned to an > > application > > that is not yet available for public inspection." > > > I don't know why I got the error message. > > > 10/718968 is available from reference literature in the invention: > > "Programmable Logic Device Having Complex Logic Blocks with Improved > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ= &dq=3Dpatent:7394287... > > > Weng > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0What > is the number you are searching for? > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I have tried to find the text and its drawings of patent application "Logic Cell Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US application number 10/718968, but it must pay to get its context from USPTO, even though it was in public domain about 6 years ago. Can you help get the context and drawings from USPTO for me? Weng From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!s38g2000prg.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Tue, 16 Jun 2009 07:10:05 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245161405 5105 127.0.0.1 (16 Jun 2009 14:10:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 14:10:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s38g2000prg.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4205 comp.lang.vhdl:1371 Hi, Do you know how aggressive the patent fighting between Xilinx and Alters is going? I give you some tastes here. But I have to make a statement first: I don't have any internal personal relationships from neither companies and all information about the patent fighting is derived from the following patent I recently read: Patent number: 7,394, 287, "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality" filed on May 21, 2007, by Altera. Here is the patent website: http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= The patent contexts are all about Xilinx circuitry, but it was filed by Altera so that O5 and O6 must be in their current status: O5 and O6 must share 5 inputs, eliminating the chance O6 can be figured with the 6th input, an easy point to make for Xilinx. All inventions in the patent are trivial in its ideas, but important for Xilinx architecture to further improve its efficiency. What does it mean? It means Altera has occupied a strategic high point to prevent Xilinx from further improving its Virtex V cell structure without avoiding its patent violations. The working price paid by Altera is minimum and its benifits to Altera in market competition are huge and tremendous. In another words, it is not exaggeratory to say that Altera hit a Superlotto in the market competition. I think both companies, #1 and #2, would establish, or have already established, a division to specially research main opponent's technology and file aggressive patents to avoid its improvements in the future. It is right and normal for fighters in battlefield to use minimum of force to get superiority in the market. That is why I would like to say the patent fighting between Xilinx and Altera is so aggressive that anyone having read the patent 7394287 would smell the powder of the fighting hanging in the air without any internal messages leaked from both companied. Weng From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!y10g2000prc.googlegroups.com!not-for-mail From: JSreeniv Newsgroups: comp.lang.vhdl Subject: Pulse counter verification in vhdl Date: Tue, 16 Jun 2009 07:52:22 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: NNTP-Posting-Host: 125.99.249.124 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245163942 28444 127.0.0.1 (16 Jun 2009 14:52:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 14:52:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y10g2000prc.googlegroups.com; posting-host=125.99.249.124; posting-account=cCqSmQoAAAD72P5YVFrs1ZNFbeH4XiZ1 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1372 Hi all, I am presently working on verification and validation of pulse counter (where i am having such 8 counters) When i wrote a testbench in VHDL and checking the results in Modelsim i am not getting desired results. Here are the steps for vhdl code for simulation. 1.setting the por_n = 0 for 100 ns and release to por_n =1 (power on reset) 2. Setting up bit 20 of inhibit_1 register to which enables the functionality of Pulse_counter_0_results register/counter 3. checking the all registers before setting up the values: READ operation for ZERO values 4. wait for 10 ns 5.Set up register for software defined period for first two bits 6.set up same register for Time base 100 ns on other two bits 6.Load the count value to 10 in a register 7.set the register for start measurement 8. wait for 1000 ns 9. Read the pulse_counter_0_results register after waiting above time 10. As well read the loadable count register after this waiting time (where i am giving a continues pulse_din signal as a clock of 40 ns, so i need to get total pulse count in results register as : 1000 ns/40 ns = 25 = 19(Hex) 11 after waiting for 100 ns time also i should get same desired values which leads holding correct values in correspond results registers. 12. Stop measurement But i am not getting that desired value instead i am getting only 14 counts. The whole simulation also depends on two clocks : fpga_clk = 50 MHz, and dsp_clk = 100 MHz,.... So if anyone give me some exposure on this simulation desired results ....it will be very helpful. Sreenivas MITC - Bangalore From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w9g2000pro.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Pulse counter verification in vhdl Date: Tue, 16 Jun 2009 08:27:58 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <764d470e-060e-4779-9f89-74cefc0833db@w9g2000pro.googlegroups.com> References: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245166078 19390 127.0.0.1 (16 Jun 2009 15:27:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 15:27:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000pro.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1373 On Jun 16, 7:52=A0am, JSreeniv wrote: > Hi all, > > I am presently working on verification and validation of pulse counter > (where i am having such 8 counters) > When i wrote a testbench in VHDL and checking the results in Modelsim > i am not getting desired results. > Here are the steps for vhdl code for simulation. > > 1.setting the por_n =3D 0 for 100 ns and release to por_n =3D1 (power on > reset) > 2. Setting up bit 20 of inhibit_1 register to which enables the > functionality of Pulse_counter_0_results register/counter > 3. checking the all registers before setting up the values: READ > operation for ZERO values > 4. wait for 10 ns > 5.Set up register for software defined period for first two bits > 6.set up same register for Time base 100 ns on other two bits > 6.Load the count value to 10 in a register > 7.set the register for start measurement > 8. wait for 1000 ns > > 9. Read the pulse_counter_0_results register after waiting above time > 10. As well read the loadable count register after this waiting time > (where i am giving a continues pulse_din signal as a clock of 40 ns, > so i need to get total pulse count in results register as : 1000 ns/40 > ns =3D 25 =3D 19(Hex) > 11 after waiting for 100 ns time also i should get same desired values > which leads holding correct values in correspond results registers. > 12. Stop measurement > > But i am not getting that desired value instead i am getting only 14 > counts. > > The whole simulation also depends on two clocks : fpga_clk =3D 50 MHz, > and dsp_clk =3D 100 MHz,.... > > So if anyone give me some exposure on this simulation desired > results ....it will be very helpful. > > Sreenivas > > MITC - Bangalore My guess would be a thrown Johnson Rod or bad timing on the Spitzer Valve. But seriously, I think I can speak for the group. There is little chance we are going to be able to help with out some indication the problem code or something. We can't possibly guess at where the missing semicolon is otherwise. Shannon From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n7g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Tue, 16 Jun 2009 08:51:47 -0700 (PDT) Organization: http://groups.google.com Lines: 75 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245167508 23853 127.0.0.1 (16 Jun 2009 15:51:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 15:51:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000prc.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4207 comp.lang.vhdl:1374 On Jun 16, 9:34=A0am, Weng Tianxiang wrote: > On Jun 15, 9:41=A0pm, rickman wrote: > > > > > On Jun 15, 1:39=A0pm, Weng Tianxiang wrote: > > > > On Jun 15, 9:23=A0am, OutputLogic wrote: > > > > > You can try to go to USPTO database and lookup the history of this > > > > patent application. > > > > It's not under the patent search, but under "http://www.uspto.gov" = -> > > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > > This database contains a complete history of the patent, including = the > > > > correspondence with patent examiners, etc. > > > > Also, can you post the patent application number. > > > > > - outputlogic > > > > >http://outputlogic.com > > > > Hi OutputLogic, > > > Thank you for your information. > > > > I had searched the website before I posed this message and got the > > > error information: > > > "Sorry, the entered Application Number "10/718968" is not available. > > > The number may have been incorrectly typed, or assigned to an > > > application > > > that is not yet available for public inspection." > > > > I don't know why I got the error message. > > > > 10/718968 is available from reference literature in the invention: > > > "Programmable Logic Device Having Complex Logic Blocks with Improved > > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEB= AJ&dq=3Dpatent:7394287... > > > > Weng > > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0Wha= t > > is the number you are searching for? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > I have tried to find the text and its drawings of patent application > "Logic Cell > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > application number 10/718968, but it must pay to get its context from > USPTO, even though it was in public domain about 6 years ago. > > Can you help get the context and drawings from USPTO for me? > > Weng Where did you get the above info? That does not appear to be a valid document number. It needs to have 11 digits where the first four appear to be the year. I searched on "Three Binary Words" in the title and came up with nothing. I did search on this for patents and found this one which I think is interesting... maybe this is why the adder is just a plus sign with a circle... 4,783,757. Note that the owner is Intel, not Altera. Rick Rick From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Tue, 16 Jun 2009 10:22:58 -0700 Lines: 22 Message-ID: <79q2njF1rm924U1@mid.individual.net> References: <80777bf9-bf4e-41c0-a722-a9d595fb4812@i28g2000prd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net yVIwY/v3WBHSROco3Dkc5wdWQL7P1LQClh/DBKjkT3uSnS3B0t Cancel-Lock: sha1:tag33qErVDF0oLs98kxBuVFlb/o= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <80777bf9-bf4e-41c0-a722-a9d595fb4812@i28g2000prd.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1376 Dave wrote: > If you simply don't assign the signal's value in those states where > the signal should remain unchanged, then the value will remain the > same until the next clock tick. The synthesizer will implement this by > making the clock enable for the signal's register '0' for those states > where the signal is not assigned. This is one of the nice things about > single-process state machines. Yes. Describing changes takes less text than describing the full state and output. It is unfortunate that asynchronous processes and the default assignments they require, are so well covered in vhdl instruction. Some designers retain this verbose style in all cases, out of habit. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:05 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Tue, 16 Jun 2009 10:36:20 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <5fa7fb32-c215-4d67-bbd3-7174768b7414@z9g2000yqi.googlegroups.com> References: <80777bf9-bf4e-41c0-a722-a9d595fb4812@i28g2000prd.googlegroups.com> <79q2njF1rm924U1@mid.individual.net> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245173780 11136 127.0.0.1 (16 Jun 2009 17:36:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 17:36:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1377 On Jun 16, 12:22=A0pm, Mike Treseler wrote: > Dave wrote: > > If you simply don't assign the signal's value in those states where > > the signal should remain unchanged, then the value will remain the > > same until the next clock tick. The synthesizer will implement this by > > making the clock enable for the signal's register '0' for those states > > where the signal is not assigned. This is one of the nice things about > > single-process state machines. > > Yes. > Describing changes takes less text > than describing the full state and output. > > It is unfortunate that asynchronous processes > and the default assignments they require, > are so well covered in vhdl instruction. > > Some designers retain this verbose > style in all cases, out of habit. > > =A0 =A0 =A0 =A0 -- Mike Treseler What's worse, most texts that promote dual processes also don't promote the best way to avoid latches in the combinatorial processes: default assignments right up front in the process. With those, you have your choice of default signal behavior being unchanged, set or reset for each signal. Most texts try to focus on an else for every if, and complete assignment lists in every state, both of which are much harder to write, read and update/maintain. You still have all the default behavior choices with a single clocked process, which is much better in the first place. Andy From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w40g2000yqd.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Tue, 16 Jun 2009 10:46:20 -0700 (PDT) Organization: http://groups.google.com Lines: 117 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245174380 30142 127.0.0.1 (16 Jun 2009 17:46:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 17:46:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w40g2000yqd.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4213 comp.lang.vhdl:1378 On Jun 16, 8:51=A0am, rickman wrote: > On Jun 16, 9:34=A0am, Weng Tianxiang wrote: > > > > > > > On Jun 15, 9:41=A0pm, rickman wrote: > > > > On Jun 15, 1:39=A0pm, Weng Tianxiang wrote: > > > > > On Jun 15, 9:23=A0am, OutputLogic wrote: > > > > > > You can try to go to USPTO database and lookup the history of thi= s > > > > > patent application. > > > > > It's not under the patent search, but under "http://www.uspto.gov= " -> > > > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > > > This database contains a complete history of the patent, includin= g the > > > > > correspondence with patent examiners, etc. > > > > > Also, can you post the patent application number. > > > > > > - outputlogic > > > > > >http://outputlogic.com > > > > > Hi OutputLogic, > > > > Thank you for your information. > > > > > I had searched the website before I posed this message and got the > > > > error information: > > > > "Sorry, the entered Application Number "10/718968" is not available= . > > > > The number may have been incorrectly typed, or assigned to an > > > > application > > > > that is not yet available for public inspection." > > > > > I don't know why I got the error message. > > > > > 10/718968 is available from reference literature in the invention: > > > > "Programmable Logic Device Having Complex Logic Blocks with Improve= d > > > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > > > following website:http://www.google.com/patents/about?id=3D5yyrAAAA= EBAJ&dq=3Dpatent:7394287... > > > > > Weng > > > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0W= hat > > > is the number you are searching for? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > I have tried to find the text and its drawings of patent application > > "Logic Cell > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > > application number 10/718968, but it must pay to get its context from > > USPTO, even though it was in public domain about 6 years ago. > > > Can you help get the context and drawings from USPTO for me? > > > Weng > > Where did you get the above info? =A0That does not appear to be a valid > document number. =A0It needs to have 11 digits where the first four > appear to be the year. > I searched on "Three Binary Words" in the title and came up with > nothing. > > I did search on this for patents and found this one which I think is > interesting... maybe this is why the adder is just a plus sign with a > circle... 4,783,757. =A0Note that the owner is Intel, not Altera. > > Rick > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I got the number from the patent "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality" in its page 1 under "Other publications". http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:7394287&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D Here is an email I sent to USPTO for confirmation and its response: Hi, I want to research patent application"Logic Cell Supporting Addition of Three Binary Words." U.S. Application Number 10/718,968, filed November 21, 2003. It should have been published long ago and in public domain. Please tell how to find the patent application. Thank you. Weng Hello The status of the application is 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS. Thank you have a great day. Agent 31 I don't know what it means. Weng From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!pfeed09.wxs.nl!newsfeed.kpn.net!pfeed08.wxs.nl!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Modelsim resulution info Date: Tue, 16 Jun 2009 11:01:37 -0700 Lines: 16 Message-ID: <79q503F1qm28fU1@mid.individual.net> References: <25c7f22a-eb38-43bb-8292-8548d8a731bf@w35g2000prg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net SSIhRfGMTpDwbRe32wLrFAzkNSn8afRd7+VTbQwRtIvmI4KYXp Cancel-Lock: sha1:aIwpAp0gfpJMIqfscOxGMg2fV+0= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <25c7f22a-eb38-43bb-8292-8548d8a731bf@w35g2000prg.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1379 JSreeniv wrote: > If we run any simulation under the defined resultions time it takes > some time to finish the simulation. > What i want is is there any equation to calculate the time period or > days, if i increase the simulation time to 1 sec or more? Maybe you mean a resolution time of less than 1 nS? That can increase the simulation time. So can the use of asynchronous processes. > Please give exposure on this knowledge! Try a simple example and see for yourself. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST) Date: Tue, 16 Jun 2009 12:09:25 -0700 Lines: 17 Message-ID: <79q8v6F1r36pkU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net hJOWoXPQ8OTs9+vlPfQcRgF76hnKVgN9LU0vkhsRXnkW1Phm6u Cancel-Lock: sha1:BewIR4Ayy+1QVtmeYokUgNF0l5Y= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1380 Mark wrote: > I'm coding for the first time in 10 years in VHDL and am trying to > find equivalents to my old verilog tool-box. One tool I found > extremely useful was the AUTOINST features of the verilog-mode in > emacs where it would automatically connect instance ports and where > you could define per-instance naming rules via AUTO_TEMPLATE. I've > discovered the port copy/port-paste as... feature in the emacs vhdl- > mode, but am wondering if that's as close as I can get to the auto- > instantiate feature of the verilog-mode? That's it for vhdl-mode, unless you can tolerate functions and variables instead. VHDL,Port,Copy VHDL,Port,Paste as instance. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!goblin1!goblin2!goblin.stu.neva.ru!feed1.news.be.easynet.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 16 Jun 2009 23:08:24 +0200 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST) References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 21 Message-ID: <4a38098f$0$2853$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 865f165d.news.skynet.be X-Trace: 1245186447 news.skynet.be 2853 91.178.148.132:60950 X-Complaints-To: usenet-abuse@skynet.be Xref: news.eternal-september.org comp.lang.vhdl:1381 Mark wrote: > I'm coding for the first time in 10 years in VHDL and am trying to > find equivalents to my old verilog tool-box. One tool I found > extremely useful was the AUTOINST features of the verilog-mode in > emacs where it would automatically connect instance ports and where > you could define per-instance naming rules via AUTO_TEMPLATE. I've > discovered the port copy/port-paste as... feature in the emacs vhdl- > mode, but am wondering if that's as close as I can get to the auto- > instantiate feature of the verilog-mode? You may want to take a look at Sigasi HDT, a next generation (Eclipse-based) VHDL IDE. It makes instantiations much easier through intelligent autocompletes and by automatically generating missing signal declarations. It also has refactorings to add new connections quickly. http://www.sigasi.com -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com VHDL development, the modern way: http://www.sigasi.com From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!s12g2000yqi.googlegroups.com!not-for-mail From: Mohummadasif Newsgroups: comp.lang.vhdl Subject: Mlatestlaptop.blogspot.com Date: Tue, 16 Jun 2009 15:26:42 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <7f6cc5e9-7c73-49da-a96b-2e86cb88cdfa@s12g2000yqi.googlegroups.com> NNTP-Posting-Host: 210.2.140.194 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245191202 20261 127.0.0.1 (16 Jun 2009 22:26:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 22:26:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s12g2000yqi.googlegroups.com; posting-host=210.2.140.194; posting-account=NNguFQoAAAAMdxErqdAut9hAU8cf9Fn1 User-Agent: G2/1.0 X-HTTP-Via: 1.1 CITYSERVER, 1.1 DORKISHAHVAIS X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1382 Hi get information about latest laptop and pc and also free download latest software games and beautifull screen savar ,,,,,, and many more ,,,, get some fun......... God bless u From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!w3g2000yqf.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Tue, 16 Jun 2009 16:53:25 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <6751c90c-2218-47c7-b5a5-2f14e2db1255@w3g2000yqf.googlegroups.com> References: <80777bf9-bf4e-41c0-a722-a9d595fb4812@i28g2000prd.googlegroups.com> <79q2njF1rm924U1@mid.individual.net> <5fa7fb32-c215-4d67-bbd3-7174768b7414@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 75.36.160.135 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245196405 16205 127.0.0.1 (16 Jun 2009 23:53:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Jun 2009 23:53:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w3g2000yqf.googlegroups.com; posting-host=75.36.160.135; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1383 On Jun 16, 10:36=A0am, Andy wrote: > On Jun 16, 12:22=A0pm, Mike Treseler wrote: > > > > > Dave wrote: > > > If you simply don't assign the signal's value in those states where > > > the signal should remain unchanged, then the value will remain the > > > same until the next clock tick. The synthesizer will implement this b= y > > > making the clock enable for the signal's register '0' for those state= s > > > where the signal is not assigned. This is one of the nice things abou= t > > > single-process state machines. > > > Yes. > > Describing changes takes less text > > than describing the full state and output. > > > It is unfortunate that asynchronous processes > > and the default assignments they require, > > are so well covered in vhdl instruction. > > > Some designers retain this verbose > > style in all cases, out of habit. > > > =A0 =A0 =A0 =A0 -- Mike Treseler > > What's worse, most texts that promote dual processes also don't > promote the best way to avoid latches in the combinatorial processes: > default assignments right up front in the process. With those, you > have your choice of default signal behavior being unchanged, set or > reset for each signal. Most texts try to focus on an else for every > if, and complete assignment lists in every state, both of which are > much harder to write, read and update/maintain. > > You still have all the default behavior choices with a single clocked > process, which is much better in the first place. > > Andy thanks for the help. I suspected the answer moments after I pressed send. I used to be a two-process person but you guys convinced me otherwise. I never was a three-process person. Shannon From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!t-online.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.190.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: runtime arguments in VHDL (ala plusargs in Verilog) Date: Tue, 16 Jun 2009 18:49:29 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245203369 27390 127.0.0.1 (17 Jun 2009 01:49:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 01:49:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=132.228.195.207; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1384 Got another how do you things like in Verilog in VHDL question: what's the "best" way to pass runtime arguements to a compiled VHDL design? Write the test name to a file, and have the tb read the file, and execute a particular test procedure? I've seen a Modeltech example where the simulator force command was used to setup variables, but that seems rather clunky to me. Thanks, Mark From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 16 Jun 2009 21:03:52 -0500 Date: Tue, 16 Jun 2009 22:02:35 -0400 From: Chris Abele User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 99 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ozQb/RYhGt8swZdaBCKXhhSSjHxU/o5x2D3nJXF+h6KVtBGBJ6h9V4oa+V5OdcafDvdrfRPpARuJ+cc!S0FJ4ZLw3w4zaQtNvxuPa1F2GZlh35sjzh0eJxDQn0oIoB4jjAq4Uj4CQSVflDNDVsSGrGceKsg= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 5753 Xref: news.eternal-september.org comp.arch.fpga:4216 comp.lang.vhdl:1385 Weng Tianxiang wrote: > On Jun 16, 8:51 am, rickman wrote: >> On Jun 16, 9:34 am, Weng Tianxiang wrote: >> >> >> >> >> >>> On Jun 15, 9:41 pm, rickman wrote: >>>> On Jun 15, 1:39 pm, Weng Tianxiang wrote: >>>>> On Jun 15, 9:23 am, OutputLogic wrote: >>>>>> You can try to go to USPTO database and lookup the history of this >>>>>> patent application. >>>>>> It's not under the patent search, but under "http://www.uspto.gov" -> >>>>>> "Patents" -> "view in PAIR" -> "public PAIR". >>>>>> This database contains a complete history of the patent, including the >>>>>> correspondence with patent examiners, etc. >>>>>> Also, can you post the patent application number. >>>>>> - outputlogic >>>>>> http://outputlogic.com >>>>> Hi OutputLogic, >>>>> Thank you for your information. >>>>> I had searched the website before I posed this message and got the >>>>> error information: >>>>> "Sorry, the entered Application Number "10/718968" is not available. >>>>> The number may have been incorrectly typed, or assigned to an >>>>> application >>>>> that is not yet available for public inspection." >>>>> I don't know why I got the error message. >>>>> 10/718968 is available from reference literature in the invention: >>>>> "Programmable Logic Device Having Complex Logic Blocks with Improved >>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from >>>>> following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287... >>>>> Weng >>>> 7,394,287 is the patent number. It works for me at the USPTO. What >>>> is the number you are searching for? >>>> Rick- Hide quoted text - >>>> - Show quoted text - >>> Hi Rick, >>> I have tried to find the text and its drawings of patent application >>> "Logic Cell >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US >>> application number 10/718968, but it must pay to get its context from >>> USPTO, even though it was in public domain about 6 years ago. >>> Can you help get the context and drawings from USPTO for me? >>> Weng >> Where did you get the above info? That does not appear to be a valid >> document number. It needs to have 11 digits where the first four >> appear to be the year. >> I searched on "Three Binary Words" in the title and came up with >> nothing. >> >> I did search on this for patents and found this one which I think is >> interesting... maybe this is why the adder is just a plus sign with a >> circle... 4,783,757. Note that the owner is Intel, not Altera. >> >> Rick >> >> Rick- Hide quoted text - >> >> - Show quoted text - > > Hi Rick, > I got the number from the patent "Programmable Logic Device Having > Complex Logic Blocks with Improved Logic Cell Functionality" > in its page 1 under "Other publications". > http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= > > Here is an email I sent to USPTO for confirmation and its response: > Hi, > I want to research patent application"Logic Cell Supporting Addition > of Three Binary Words." U.S. Application Number 10/718,968, filed > November 21, 2003. > > It should have been published long ago and in public domain. > > Please tell how to find the patent application. > > Thank you. > > Weng > > Hello > > The status of the application is > 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF > PUBLICATIONS. > Thank you have a great day. Agent 31 > > I don't know what it means. > > Weng I'm confused: the Google page you linked to has a "Download PDF" button which gets you the full 19 page patient. There's also a link for "View patient at USPTO" which takes you directly to the page for patient number 7,394,287 at the USPTO site. So what is it that you're looking for? Chris From newsfish@newsfish Wed Aug 19 13:25:06 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 16 Jun 2009 21:21:27 -0500 Date: Tue, 16 Jun 2009 22:20:10 -0400 From: Chris Abele User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 109 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-cqhUavRkPROkkY7auX1oYVwtNbGbHY0+sgWprRUr50NoCuqm8cBE24J5uqMCWY6UQ+YE/jM5jY98Nz6!m2thUcQ0yyanSiT5il3BADKJ7RbtQnYfHlvVAqh8iN65uuLONE2NaLc8ktEQGmz6Ug62n+FZnbs= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 6121 Xref: news.eternal-september.org comp.arch.fpga:4217 comp.lang.vhdl:1386 Chris Abele wrote: > Weng Tianxiang wrote: >> On Jun 16, 8:51 am, rickman wrote: >>> On Jun 16, 9:34 am, Weng Tianxiang wrote: >>> >>> >>> >>> >>> >>>> On Jun 15, 9:41 pm, rickman wrote: >>>>> On Jun 15, 1:39 pm, Weng Tianxiang wrote: >>>>>> On Jun 15, 9:23 am, OutputLogic wrote: >>>>>>> You can try to go to USPTO database and lookup the history of this >>>>>>> patent application. >>>>>>> It's not under the patent search, but under >>>>>>> "http://www.uspto.gov" -> >>>>>>> "Patents" -> "view in PAIR" -> "public PAIR". >>>>>>> This database contains a complete history of the patent, >>>>>>> including the >>>>>>> correspondence with patent examiners, etc. >>>>>>> Also, can you post the patent application number. >>>>>>> - outputlogic >>>>>>> http://outputlogic.com >>>>>> Hi OutputLogic, >>>>>> Thank you for your information. >>>>>> I had searched the website before I posed this message and got the >>>>>> error information: >>>>>> "Sorry, the entered Application Number "10/718968" is not available. >>>>>> The number may have been incorrectly typed, or assigned to an >>>>>> application >>>>>> that is not yet available for public inspection." >>>>>> I don't know why I got the error message. >>>>>> 10/718968 is available from reference literature in the invention: >>>>>> "Programmable Logic Device Having Complex Logic Blocks with Improved >>>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from >>>>>> following >>>>>> website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287... >>>>>> >>>>>> Weng >>>>> 7,394,287 is the patent number. It works for me at the USPTO. What >>>>> is the number you are searching for? >>>>> Rick- Hide quoted text - >>>>> - Show quoted text - >>>> Hi Rick, >>>> I have tried to find the text and its drawings of patent application >>>> "Logic Cell >>>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US >>>> application number 10/718968, but it must pay to get its context from >>>> USPTO, even though it was in public domain about 6 years ago. >>>> Can you help get the context and drawings from USPTO for me? >>>> Weng >>> Where did you get the above info? That does not appear to be a valid >>> document number. It needs to have 11 digits where the first four >>> appear to be the year. >>> I searched on "Three Binary Words" in the title and came up with >>> nothing. >>> >>> I did search on this for patents and found this one which I think is >>> interesting... maybe this is why the adder is just a plus sign with a >>> circle... 4,783,757. Note that the owner is Intel, not Altera. >>> >>> Rick >>> >>> Rick- Hide quoted text - >>> >>> - Show quoted text - >> >> Hi Rick, >> I got the number from the patent "Programmable Logic Device Having >> Complex Logic Blocks with Improved Logic Cell Functionality" >> in its page 1 under "Other publications". >> http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= >> >> >> Here is an email I sent to USPTO for confirmation and its response: >> Hi, >> I want to research patent application"Logic Cell Supporting Addition >> of Three Binary Words." U.S. Application Number 10/718,968, filed >> November 21, 2003. >> >> It should have been published long ago and in public domain. >> >> Please tell how to find the patent application. >> >> Thank you. >> >> Weng >> >> Hello >> >> The status of the application is >> 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF >> PUBLICATIONS. >> Thank you have a great day. Agent 31 >> >> I don't know what it means. >> >> Weng > > I'm confused: the Google page you linked to has a "Download PDF" button > which gets you the full 19 page patient. There's also a link for "View > patient at USPTO" which takes you directly to the page for patient > number 7,394,287 at the USPTO site. So what is it that you're looking for? > > Chris Ignore that post - I see now. The patient application that you're looking for is referenced in the one you pointed to. (Note to self - engage brain before pushing send.) From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!m19g2000yqk.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words" Date: Tue, 16 Jun 2009 19:27:46 -0700 (PDT) Organization: http://groups.google.com Lines: 123 Message-ID: References: <1906456b-e3c5-4089-b79d-fd79c8a98b10@c18g2000prh.googlegroups.com> <2c0e4c4c-0577-49aa-b653-133fcb2937a3@w9g2000pro.googlegroups.com> <7398ef8a-40d3-4d8d-85c8-7ecc334aaa54@z14g2000yqa.googlegroups.com> NNTP-Posting-Host: 68.126.125.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245205666 12217 127.0.0.1 (17 Jun 2009 02:27:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 02:27:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m19g2000yqk.googlegroups.com; posting-host=68.126.125.180; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4218 comp.lang.vhdl:1387 On Jun 16, 7:02=A0pm, Chris Abele wrote: > Weng Tianxiang wrote: > > On Jun 16, 8:51 am, rickman wrote: > >> On Jun 16, 9:34 am, Weng Tianxiang wrote: > > >>> On Jun 15, 9:41 pm, rickman wrote: > >>>> On Jun 15, 1:39 pm, Weng Tianxiang wrote: > >>>>> On Jun 15, 9:23 am, OutputLogic wrote: > >>>>>> You can try to go to USPTO database and lookup the history of this > >>>>>> patent application. > >>>>>> It's not under the patent search, but under "http://www.uspto.gov"= -> > >>>>>> "Patents" -> "view in PAIR" -> "public PAIR". > >>>>>> This database contains a complete history of the patent, including= the > >>>>>> correspondence with patent examiners, etc. > >>>>>> Also, can you post the patent application number. > >>>>>> - outputlogic > >>>>>>http://outputlogic.com > >>>>> Hi OutputLogic, > >>>>> Thank you for your information. > >>>>> I had searched the website before I posed this message and got the > >>>>> error information: > >>>>> "Sorry, the entered Application Number "10/718968" is not available= . > >>>>> The number may have been incorrectly typed, or assigned to an > >>>>> application > >>>>> that is not yet available for public inspection." > >>>>> I don't know why I got the error message. > >>>>> 10/718968 is available from reference literature in the invention: > >>>>> "Programmable Logic Device Having Complex Logic Blocks with Improve= d > >>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from > >>>>> following website:http://www.google.com/patents/about?id=3D5yyrAAAA= EBAJ&dq=3Dpatent:7394287... > >>>>> Weng > >>>> 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0= What > >>>> is the number you are searching for? > >>>> Rick- Hide quoted text - > >>>> - Show quoted text - > >>> Hi Rick, > >>> I have tried to find the text and its drawings of patent application > >>> "Logic Cell > >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > >>> application number 10/718968, but it must pay to get its context from > >>> USPTO, even though it was in public domain about 6 years ago. > >>> Can you help get the context and drawings from USPTO for me? > >>> Weng > >> Where did you get the above info? =A0That does not appear to be a vali= d > >> document number. =A0It needs to have 11 digits where the first four > >> appear to be the year. > >> I searched on "Three Binary Words" in the title and came up with > >> nothing. > > >> I did search on this for patents and found this one which I think is > >> interesting... maybe this is why the adder is just a plus sign with a > >> circle... 4,783,757. =A0Note that the owner is Intel, not Altera. > > >> Rick > > >> Rick- Hide quoted text - > > >> - Show quoted text - > > > Hi Rick, > > I got the number from the patent "Programmable Logic Device Having > > Complex Logic Blocks with Improved Logic Cell Functionality" > > in its page 1 under "Other publications". > >http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:739428= 7... > > > Here is an email I sent to USPTO for confirmation and its response: > > Hi, > > I want to research patent application"Logic Cell Supporting Addition > > of Three Binary Words." U.S. Application Number 10/718,968, filed > > November 21, 2003. > > > It should have been published long ago and in public domain. > > > Please tell how to find the patent application. > > > Thank you. > > > Weng > > > Hello > > > The status of the application is > > 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF > > PUBLICATIONS. > > Thank you have a great day. Agent 31 > > > I don't know what it means. > > > Weng > > I'm confused: the Google page you linked to has a "Download PDF" button > which gets you the full 19 page patient. =A0There's also a link for "View > patient at USPTO" which takes you directly to the page for patient > number 7,394,287 at the USPTO site. =A0So what is it that you're looking = for? > > Chris- Hide quoted text - > > - Show quoted text - Hi Chris, You have to download full patent papers to get the idea that the patent application "Logic Cell Supproting Addition of Three Binary Words" has not been approved for last 6.5 years. In the link I listed there is no the reference about the patent application. When you download the patent 7,394,287, in its page 1 there is an item named "OTHER PUBLICATION". The first paper listed under the item is the patent application "Logic Cell Supproting Addition of Three Binary Words" which applied on November 21, 2003 from where I've learned that the "Logic Cell Supproting Addition of Three Binary Words" has not been approved for last 6.5 years after I searched for the patent application name through USPTO patent website. Weng From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: runtime arguments in VHDL (ala plusargs in Verilog) Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.132 (Waxed in Black) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 17 Jun 2009 02:54:25 GMT Lines: 23 Message-ID: <02484cf7$0$9594$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4660f31b.news.astraweb.com X-Trace: DXC=?E1kZ7a;62@jEc;hW[JGKHL?0kYOcDh@JXmXdLV??C2EGWKO\4l;6:Od3_]GVCcENGaFOMd=OTSoD Xref: news.eternal-september.org comp.lang.vhdl:1388 On Tue, 16 Jun 2009 18:49:29 -0700, Mark wrote: > Got another how do you things like in Verilog in VHDL question: what's > the "best" way to pass runtime arguements to a compiled VHDL design? > Write the test name to a file, and have the tb read the file, and > execute a particular test procedure? I've seen a Modeltech example > where the simulator force command was used to setup variables, but that > seems rather clunky to me. If the design has been compiled but not elaborated, the easiest way might be to pass the arguments in as generics. These can be of any type, including string and enumerated types. You can set the generics by using the -g or -G switches in vsim. It gets a little more complicated if you have a mix of verilog and VHDL in your hierarchy. N.B. Not all tools support setting the value of generics of an enumerated type in this way. Regards, Allan From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!feeder.news-service.com!postnews.google.com!3g2000yqk.googlegroups.com!not-for-mail From: Jon Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 04:03:10 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: References: NNTP-Posting-Host: 77.96.64.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245236590 10095 127.0.0.1 (17 Jun 2009 11:03:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 11:03:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 3g2000yqk.googlegroups.com; posting-host=77.96.64.254; posting-account=JYqZbQkAAABQnNLIpy78uFN1VnNiPBrb User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4222 comp.lang.vhdl:1391 Don't they all have cross licensing agreements in place? Jon From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!3g2000yqk.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Pulse counter verification in vhdl Date: Wed, 17 Jun 2009 07:02:07 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: NNTP-Posting-Host: 67.169.207.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245247327 7973 127.0.0.1 (17 Jun 2009 14:02:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 14:02:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 3g2000yqk.googlegroups.com; posting-host=67.169.207.204; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1392 Sreenivas, Add all signals to simulation waveform window. Run simulation. Watch what did happen. Start watching from the beginning. What went right. What did not go right. Postulate as to why. Add more signals if necessary to prove your postulation. Your counter may start running with an old value and not load the new value until it rolls over. This would cause a difference in startup than you may expect, but it may produce correct steady state system behavior if it is tolerable at the beginning to act this way. Often it is tolerable because the software does not get to your programmable counters right away anyway. I usually make my programmable counters to have two features. 1: Write counter, but do not reload until roll over. 2: Write counter and reload immediately. That way I have both possible features covered. Best, Jim From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 07:16:19 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> References: NNTP-Posting-Host: 69.110.132.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245248179 13458 127.0.0.1 (17 Jun 2009 14:16:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 14:16:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=69.110.132.66; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4223 comp.lang.vhdl:1393 On Jun 17, 4:03=A0am, Jon wrote: > Don't they all have cross licensing agreements in place? > > Jon Hi Jon, I don't think so. FPGA industry is different from CPU industry where Intel and AMD have known patent exchange agreements. Xilinx and Altera fought 7 years in the 1990s' for the FPGA first patent rights owned by Xilinx, (as you may know Xilinx is the birthplace of FPGA industry), but finally Altera won, it means Altera didn't give any compensation money to Xilinx which I heard from a Xilinx field engineer. Weng From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!a36g2000yqc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 07:31:46 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: References: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245249106 13742 127.0.0.1 (17 Jun 2009 14:31:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 14:31:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a36g2000yqc.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4224 comp.lang.vhdl:1394 On Jun 17, 9:16=A0am, Weng Tianxiang wrote: > On Jun 17, 4:03=A0am, Jon wrote: > > > Don't they all have cross licensing agreements in place? > > > Jon > > Hi Jon, > I don't think so. FPGA industry is different from CPU industry where > Intel and AMD have known patent exchange agreements. > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > patent rights owned by Xilinx, (as you may know Xilinx is the > birthplace of FPGA industry), but finally Altera won, it means Altera > didn't give any compensation money to Xilinx which I heard from a > Xilinx field engineer. > > Weng I'd be very surprised if they had no cross-licensing at all. Competing vendors often "trade" patent licenses. Xilinx may have something Altera wants, and Altera may have something Xilinx wants, so they trade licenses. Andy From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!x5g2000yqk.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 07:47:46 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> NNTP-Posting-Host: 69.110.132.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245250066 16701 127.0.0.1 (17 Jun 2009 14:47:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 14:47:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x5g2000yqk.googlegroups.com; posting-host=69.110.132.66; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4225 comp.lang.vhdl:1395 On Jun 17, 7:31=A0am, Andy wrote: > On Jun 17, 9:16=A0am, Weng Tianxiang wrote: > > > > > > > On Jun 17, 4:03=A0am, Jon wrote: > > > > Don't they all have cross licensing agreements in place? > > > > Jon > > > Hi Jon, > > I don't think so. FPGA industry is different from CPU industry where > > Intel and AMD have known patent exchange agreements. > > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > > patent rights owned by Xilinx, (as you may know Xilinx is the > > birthplace of FPGA industry), but finally Altera won, it means Altera > > didn't give any compensation money to Xilinx which I heard from a > > Xilinx field engineer. > > > Weng > > I'd be very surprised if they had no cross-licensing at all. Competing > vendors often "trade" patent licenses. Xilinx may have something > Altera wants, and Altera may have something Xilinx wants, so they > trade licenses. > > Andy- Hide quoted text - > > - Show quoted text - Hi Andy, No. Can you point out any technique in current most advanced or most obsolete FPGA products commonly shared by Xilinx and Altera? except lookup table. Weng From newsfish@newsfish Wed Aug 19 13:25:07 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.unit0.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: runtime arguments in VHDL (ala plusargs in Verilog) Date: Wed, 17 Jun 2009 10:21:57 -0700 Lines: 10 Message-ID: <79sn1nF1sf9j1U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net AsiiyogNS9eKbl7jCh5Vqw2NwcTSoGgGPSkdBmAntS1jrhcIh6 Cancel-Lock: sha1:GMN9+OnlQUNGxQzlrE6tH27mR9I= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1396 Mark wrote: > Got another how do you things like in Verilog in VHDL question: > what's the "best" way to pass runtime arguements to a compiled VHDL > design? Write the test name to a file, and have the tb read the file, > and execute a particular test procedure? That would not be my recommendation. I use vhdl procedures, and simple vsim -G generics. See the testbench example here: http://mysite.verizon.net/miketreseler/ From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.190.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!postnews.google.com!w3g2000yqf.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Testbench design references Date: Wed, 17 Jun 2009 12:48:45 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <55603193-2219-4c9c-9c23-c3c06ff96d1c@w3g2000yqf.googlegroups.com> NNTP-Posting-Host: 66.38.210.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245268125 11155 127.0.0.1 (17 Jun 2009 19:48:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 19:48:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w3g2000yqf.googlegroups.com; posting-host=66.38.210.253; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US) AppleWebKit/530.5 (KHTML, like Gecko) Chrome/2.0.172.31 Safari/530.5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1397 Hi everyone, I'm an FPGA Designer and I'm currently trying to implement self- checking testbenches. Basically, I want testbenches that would output a message saying that the module has completed the test with x number of errors. So far, I have some testbenches that are self-checking but I'm not really satisfied on the quality of my code. Do you guys have any references or book to recommend? I don't want simple testbench examples that test a 4-bit counter, I'd like more "real-world" examples. I hope I'm clear enough. Best regards. From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Testbench design references Date: Wed, 17 Jun 2009 13:04:12 -0700 Lines: 6 Message-ID: <79t0hsF1sgr8iU1@mid.individual.net> References: <55603193-2219-4c9c-9c23-c3c06ff96d1c@w3g2000yqf.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net UyPFwiv7owGIzjWQqZj/PwVTQ0JmM/FuAXJ9rwK0BQx+rCOlvA Cancel-Lock: sha1:mIxLBbgWo2n0WcEZCkYryLS4JoA= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <55603193-2219-4c9c-9c23-c3c06ff96d1c@w3g2000yqf.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1398 Benjamin Couillard wrote: > I'm an FPGA Designer and I'm currently trying to implement self- > checking testbenches. http://mysite.verizon.net/miketreseler/test_uart.vhd From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 17 Jun 2009 15:59:18 -0500 From: james Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 16:59:19 -0400 Reply-To: beerkeg@budu.edu Message-ID: References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 61 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 72.91.132.161 X-Trace: sv3-jBYijbAapFEQCD7vjJ9pyHTNcTUnBMU4oARGbS5KDCk5fIHwWWd0lTjCziN32I3LAlDpBKj2PNcriwm!ipy7luaEb7+SE15hTn+b9foXB6PPTvqWluG55L4gJzYrcdvHeTHkXyzA1BcH9SLwjob8FMdHwxg5!+AXxAb3bZe9VJ5XQhlCg/A== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3819 Xref: news.eternal-september.org comp.arch.fpga:4229 comp.lang.vhdl:1399 On Tue, 16 Jun 2009 07:10:05 -0700 (PDT), Weng Tianxiang wrote: |Hi, |Do you know how aggressive the patent fighting between Xilinx and |Alters is going? | |I give you some tastes here. But I have to make a statement first: I |don't have any internal personal relationships from neither companies |and all information about the patent fighting is derived from the |following patent I recently read: |Patent number: 7,394, 287, "Programmable Logic Device Having Complex |Logic Blocks with Improved Logic Cell Functionality" filed on May 21, |2007, by Altera. | |Here is the patent website: |http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= | |The patent contexts are all about Xilinx circuitry, but it was filed |by Altera so that O5 and O6 must be in their current status: O5 and O6 |must share 5 inputs, eliminating the chance O6 can be figured with the |6th input, an easy point to make for Xilinx. All inventions in the |patent are trivial in its ideas, but important for Xilinx architecture |to further improve its efficiency. | |What does it mean? | |It means Altera has occupied a strategic high point to prevent Xilinx |from further improving its Virtex V cell structure without avoiding |its patent violations. The working price paid by Altera is minimum and |its benifits to Altera in market competition are huge and tremendous. |In another words, it is not exaggeratory to say that Altera hit a |Superlotto in the market competition. | |I think both companies, #1 and #2, would establish, or have already |established, a division to specially research main opponent's |technology and file aggressive patents to avoid its improvements in |the future. | |It is right and normal for fighters in battlefield to use minimum of |force to get superiority in the market. | |That is why I would like to say the patent fighting between Xilinx and |Altera is so aggressive that anyone having read the patent 7394287 |would smell the powder of the fighting hanging in the air without any |internal messages leaked from both companied. | |Weng | | |============ It is not uncommon to imrove or try to circumvent another companies patents. In doing an improvement or include an area not covered by another's patent you do have to reference that patent to explain why your invention is different and improves on an existing patent. patents are a lifeline for companies. They are desired as much as gold. james From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Modelsim PE/Win in VirtualBox? Date: Wed, 17 Jun 2009 23:02:42 +0200 Organization: 502 You are not allowed to talk Lines: 20 Sender: newsmailcomp6@gustad.com Message-ID: <87bpomvaj1.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX1+VRJf5/DJZjG+Ig3GnEKUtaNKTWsBQ+3bYq9Frby8DENcnOXE6y7+HdyeUJ1pO6p0OYVq5FWGJkSds6zKbgrnvUx1wamqMKK6BJKyLnULz5GTBNWiMRy7JExyY1DosePDKimakzC+R+A== X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Wed, 17 Jun 2009 21:03:06 +0000 (UTC) X-Auth-Sender: U2FsdGVkX19z6O2ge/p+j8fMTHBbEiT25hD8j6t0elQ= Cancel-Lock: sha1:7s4X13yqn/AsoE2Ro7UPYWkJYM0= sha1:V3E6hmCH2lmkGX68vZxME3+eCno= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1400 I'm a long time Linux user but I'm currently stuck with a Modelsim PE USB dongle. Unfortunately the Modelsim LE (Linux Edition) is Verilog only and the SE edition is quite expensive. I've used lots of other EDA tools in the past, and they don't seem to discriminate Linux in this way. So I've tried to run Windows XP as a guest OS in VirtualBox. The USB dongle is detected in Windows, but most of the time Windows will crash or I will not get a license when I either try to run the license check or start vsim. Have anybody else succeeded to run Modelsim PE in a Windows XP guest in VirtualBox? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!k38g2000yqh.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Testbench design references Date: Wed, 17 Jun 2009 14:35:21 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <1830b5c3-b35f-4484-80f3-a57f44527f4b@k38g2000yqh.googlegroups.com> References: <55603193-2219-4c9c-9c23-c3c06ff96d1c@w3g2000yqf.googlegroups.com> <79t0hsF1sgr8iU1@mid.individual.net> NNTP-Posting-Host: 66.38.210.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245274522 30114 127.0.0.1 (17 Jun 2009 21:35:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Jun 2009 21:35:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k38g2000yqh.googlegroups.com; posting-host=66.38.210.253; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US) AppleWebKit/530.5 (KHTML, like Gecko) Chrome/2.0.172.31 Safari/530.5,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1401 On Jun 17, 4:04=A0pm, Mike Treseler wrote: > Benjamin Couillard wrote: > > I'm an FPGA Designer and I'm currently trying to implement self- > > checking testbenches. > > http://mysite.verizon.net/miketreseler/test_uart.vhd Thanks, that's what I needed! Best regards From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.linkpendium.com!news.linkpendium.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi150.ffdc.sbc.com.POSTED!bbf874ca!not-for-mail From: Ed McGettigan Organization: Xilinx Inc. User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? References: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> In-Reply-To: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 26 Message-ID: <7ue_l.62$cl4.39@flpi150.ffdc.sbc.com> NNTP-Posting-Host: 149.199.62.254 X-Complaints-To: abuse@prodigy.net X-Trace: flpi150.ffdc.sbc.com 1245279235 ST000 149.199.62.254 (Wed, 17 Jun 2009 18:53:55 EDT) NNTP-Posting-Date: Wed, 17 Jun 2009 18:53:55 EDT X-UserInfo1: SCSYQNONXZV]RTX[ZBCD^VX@WB]^PCPDLXUNNHDK@YUDUWYAKVUOPCW[ML\JXUCKVFDYZKBMSFX^OMSAFNTINTDDMVW[X\THOPXZRVOCJTUTPC\_JSBVX\KAOTBAJBVMZTYAKMNLDI_MFDSSOLXINH__FS^\WQGHGI^C@E[A_CF\AQLDQ\BTMPLDFNVUQ_VM Date: Wed, 17 Jun 2009 15:53:55 -0700 Xref: news.eternal-september.org comp.arch.fpga:4230 comp.lang.vhdl:1402 Weng Tianxiang wrote: > On Jun 17, 4:03 am, Jon wrote: >> Don't they all have cross licensing agreements in place? >> >> Jon > > Hi Jon, > I don't think so. FPGA industry is different from CPU industry where > Intel and AMD have known patent exchange agreements. > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > patent rights owned by Xilinx, (as you may know Xilinx is the > birthplace of FPGA industry), but finally Altera won, it means Altera > didn't give any compensation money to Xilinx which I heard from a > Xilinx field engineer. > > Weng Altera paid Xilinx $20M to settle the patent litigation back in July 2001. The agreement include a patent cross license. http://www.altera.com/corporate/news_room/releases/releases_archive/2001/corporate_partners/pr-corp0718_release.html Ed McGettigan -- Xilinx Inc. From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!p6g2000pre.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going? Date: Wed, 17 Jun 2009 18:16:35 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <2df66b83-8e76-4732-b242-ebcaf87e8f20@p6g2000pre.googlegroups.com> References: <939c1b72-cdb7-45f4-b349-53afaebc2c01@z9g2000yqi.googlegroups.com> <7ue_l.62$cl4.39@flpi150.ffdc.sbc.com> NNTP-Posting-Host: 69.110.132.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245287795 10058 127.0.0.1 (18 Jun 2009 01:16:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 18 Jun 2009 01:16:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p6g2000pre.googlegroups.com; posting-host=69.110.132.66; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4231 comp.lang.vhdl:1403 On Jun 17, 3:53=A0pm, Ed McGettigan wrote: > Weng Tianxiang wrote: > > On Jun 17, 4:03 am, Jon wrote: > >> Don't they all have cross licensing agreements in place? > > >> Jon > > > Hi Jon, > > I don't think so. FPGA industry is different from CPU industry where > > Intel and AMD have known patent exchange agreements. > > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > > patent rights owned by Xilinx, (as you may know Xilinx is the > > birthplace of FPGA industry), but finally Altera won, it means Altera > > didn't give any compensation money to Xilinx which I heard from a > > Xilinx field engineer. > > > Weng > > Altera paid Xilinx $20M to settle the patent litigation back in July > 2001. =A0The agreement include a patent cross license. > > http://www.altera.com/corporate/news_room/releases/releases_archive/2... > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - Hi Ed, Thank you for your correct and proper information about the case and you information prevents any rumors from spreading further. I really heared about the case from a Xilinx field engineer and he seemed to be unknown of $20 million after my project was switched from Altera's chips to Xilinx's and he told the story to boast the Xilinx technology reputation. Weng From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 17 Jun 2009 20:21:14 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 02:24:39 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <87bpomvaj1.fsf@pangea.home.gustad.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 39 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-eXHO063ZnA175q1iNZPT+SSccvt6TZC0v/BJOZ8HqIBzinv4uG+VM9LmbUiHoRHiwoI9BKyTuVic0IU!U7hF67dc0J2VleTW0EuwDnZNntrccOQc4Uev2PBO8gKKN1YHciAOzjkEnKK49X+RN1MuJ23XxznS!JbNEpxbm7co1kN0= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2772 Xref: news.eternal-september.org comp.lang.vhdl:1404 On Wed, 17 Jun 2009 23:02:42 +0200, Petter Gustad wrote: > >I'm a long time Linux user but I'm currently stuck with a Modelsim PE >USB dongle. Unfortunately the Modelsim LE (Linux Edition) is Verilog >only and the SE edition is quite expensive. I've used lots of other >EDA tools in the past, and they don't seem to discriminate Linux in >this way. So I've tried to run Windows XP as a guest OS in VirtualBox. > >The USB dongle is detected in Windows, but most of the time Windows >will crash or I will not get a license when I either try to run the >license check or start vsim. > >Have anybody else succeeded to run Modelsim PE in a Windows XP guest in >VirtualBox? > I presume you are using the Sun Virtualbox not the open source one, since you are virtualising a USB device. I found it pretty unstable (but hey, it gave me a genuine Win2000 BSOD in its little window while Linux ran happily on regardless!) I recommend taking a look at kvm http://www.linux-kvm.org/page/Main_Page which I adopted because (as of recent-ish builds, I think I'm using build 83) virtualises both PCI and USB; and thus lets me use some Windows-only dev tools that talk directly to a PCIe-hosted FPGA card (AND need a pesky little Aladdin HASP dongle). It was easy to install, (much easier than Xen with an NVidia graphics card!) though not very easy to use; adding/removing USB/PCI devices takes obscure commands in a slightly odd sort of shell. I can't speak for running Modelsim on it, but it seems (on my limited experience) to be considerably more stable than VirtualBox, and perfectly good at what I needed; virtualising Windows. - Brian From newsfish@newsfish Wed Aug 19 13:25:08 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!weretis.net!feeder2.news.weretis.net!feed.xsnews.nl!border-3.ams.xsnews.nl!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf02.ams.highwinds-media.com!newsfe03.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <87bpomvaj1.fsf@pangea.home.gustad.com> Subject: Re: Modelsim PE/Win in VirtualBox? Lines: 42 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe03.ams2 1245310252 86.16.123.60 (Thu, 18 Jun 2009 07:30:52 UTC) NNTP-Posting-Date: Thu, 18 Jun 2009 07:30:52 UTC Organization: virginmedia.com Date: Thu, 18 Jun 2009 08:30:44 +0100 Xref: news.eternal-september.org comp.lang.vhdl:1405 "Petter Gustad" wrote in message news:87bpomvaj1.fsf@pangea.home.gustad.com... > > I'm a long time Linux user but I'm currently stuck with a Modelsim PE > USB dongle. Unfortunately the Modelsim LE (Linux Edition) is Verilog > only and the SE edition is quite expensive. I would suggest you complain to Mentor (I did). It is quite annoying that VHDL users are considered second class users to Verilog and we are not only talking about PE/VHDL on Linux here. > I've used lots of other > EDA tools in the past, and they don't seem to discriminate Linux in > this way. So I've tried to run Windows XP as a guest OS in VirtualBox. > > The USB dongle is detected in Windows, but most of the time Windows > will crash or I will not get a license when I either try to run the > license check or start vsim. When is fails run "lmutil lmhostid -flexid" and see if your 9-xxxxxxx dongle id is being returned, if not then Virtualbox might be the issue. I am not that familiar with Virtualbox but there are Linux USB dongle drivers available on the Hasp website so perhaps you can install the drivers under Linux and somehow share that port under Virtualbox? Other suggestion is to try Vmware. Hans www.ht-lab.com > > Have anybody else succeeded to run Modelsim PE in a Windows XP guest in > VirtualBox? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 11:45:23 +0200 Organization: 502 You are not allowed to talk Lines: 18 Sender: newsmailcomp6@gustad.com Message-ID: <87ocslvpsc.fsf@pangea.home.gustad.com> References: <87bpomvaj1.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX19832eZqquQaDbLR1gBMvj2sO054/XSiP0O0qZKjxFtRJ8MHpcHCXK9Uc/EzKn32PTkw1CZ3g+SQxsDcYFNIPyCksDov9B6gzEApa57JrCmuFuenkGVC8HVLTCbIqICnlL0uEHjF2VF2Q== X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Thu, 18 Jun 2009 09:45:38 +0000 (UTC) X-Auth-Sender: U2FsdGVkX18cBlvGGrJjXPq8l7r8MPpNKeT5Yu94ZCc= Cancel-Lock: sha1:SqxsgOwqKc0cxKJsXGvmXK9RMqA= sha1:QxUZgAVbchNsKq04reazEnv9kis= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1406 Brian Drummond writes: > I presume you are using the Sun Virtualbox not the open source one, since you Correct. More speficically version 2.2.4. > I recommend taking a look at kvm Thank you. I'll look into KVM. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!r16g2000vbn.googlegroups.com!not-for-mail From: "evilkidder@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 03:16:59 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: References: <87bpomvaj1.fsf@pangea.home.gustad.com> <87ocslvpsc.fsf@pangea.home.gustad.com> NNTP-Posting-Host: 86.25.220.210 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245320219 8706 127.0.0.1 (18 Jun 2009 10:16:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 18 Jun 2009 10:16:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r16g2000vbn.googlegroups.com; posting-host=86.25.220.210; posting-account=HqbchAkAAAC-Jv0afbWZ8S8Oga-m3wGi User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042718 CentOS/3.0.10-1.el5.centos Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1409 On Jun 18, 10:45=A0am, Petter Gustad wrote: > Brian Drummond writes: > > I presume you are using the Sun Virtualbox not the open source one, sin= ce you > > Correct. More speficically version 2.2.4. > > > I recommend taking a look at kvm > > Thank you. I'll look into KVM. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? Works for me - the trick it seems is to ensure that you are running with hardware virtualization enabled. Otherwise the USB dongle driver crashes the system. I've only tried this on a core2 duo and core i7 - not sure about AMD processors. From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 12:26:12 +0200 Organization: 502 You are not allowed to talk Lines: 34 Sender: newsmailcomp6@gustad.com Message-ID: <87k539vnwb.fsf@pangea.home.gustad.com> References: <87bpomvaj1.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX18lrt06zM4wVXt+aaMN5RzmxN7EgYt+ozIE5LDmoT4PkrgDUmtcR0a58fJiV9WJMPvYS5q3qMPp4cK5/sYH7FPkjfxz75UuN/oNiuVMJ+dM4zyMxN2B7VUoQXaNl/vOwpXkMFQ+TQdg1A== X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Thu, 18 Jun 2009 10:26:29 +0000 (UTC) X-Auth-Sender: U2FsdGVkX19s5FR4bIDXW/9Or43wWSAMag6E2c83CqM= Cancel-Lock: sha1:ZrbFbeNrrlEUiDDvkgumxntDGUY= sha1:MNvyGUpERVeOWm7swBQQDknB08g= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1410 "HT-Lab" writes: > I would suggest you complain to Mentor (I did). Good point. > When is fails run "lmutil lmhostid -flexid" and see if your > 9-xxxxxxx dongle id Sometimes I see the dongle ID. Other times I just see the ethernet id (when using the license check GUI), and most of the time it will just crash and reboot the virtual machine. BTW I always see the dongle in the device manager under Windows. > is being returned, if not then Virtualbox might be the issue. I am > not that familiar with Virtualbox but there are Linux USB dongle > drivers available on the Hasp website so perhaps you can install the > drivers under Linux and somehow share that port under Virtualbox? It should be transparent so there should be no driver. > Other suggestion is to try Vmware. Have anybody tried Modelsim PE under Vmware or KVM and know that it works? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 12:32:01 +0200 Organization: 502 You are not allowed to talk Lines: 19 Sender: newsmailcomp6@gustad.com Message-ID: <87fxdxvnmm.fsf@pangea.home.gustad.com> References: <87bpomvaj1.fsf@pangea.home.gustad.com> <87ocslvpsc.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX1/l+4mEamWQi1VVWnK9OXULFCbCljB0xlwsXF39HqmOInuoPVHEqHopPWXmVNJGQ+AdEWbsez7RxIECpAB7gkrxIx8e2Cpyz+l9zZ26yJj39T8Vv7p15azQiSR3h7HoV2VihYRIyuIS+A== X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Thu, 18 Jun 2009 10:32:16 +0000 (UTC) X-Auth-Sender: U2FsdGVkX183KZRepbSZEY7qJk0cKtjR09qJBFBxQE8= Cancel-Lock: sha1:O8q+a2Hb56itDSs4MhwoyT7jEKQ= sha1:deHIVku+h3gHIk+CbMlBimozv7c= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1411 "evilkidder@googlemail.com" writes: >> Thank you. I'll look into KVM. > Works for me - the trick it seems is to ensure that you are running > with hardware virtualization enabled. Otherwise the USB dongle driver > crashes the system. I've only tried this on a core2 duo and core i7 - > not sure about AMD processors. Thanks. Looks like KVM is the first thing to try out... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!postnews.google.com!n21g2000vba.googlegroups.com!not-for-mail From: "evilkidder@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 03:46:18 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <87bpomvaj1.fsf@pangea.home.gustad.com> <87ocslvpsc.fsf@pangea.home.gustad.com> <87fxdxvnmm.fsf@pangea.home.gustad.com> NNTP-Posting-Host: 86.25.220.210 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245321978 14076 127.0.0.1 (18 Jun 2009 10:46:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 18 Jun 2009 10:46:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n21g2000vba.googlegroups.com; posting-host=86.25.220.210; posting-account=HqbchAkAAAC-Jv0afbWZ8S8Oga-m3wGi User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.0.10) Gecko/2009042718 CentOS/3.0.10-1.el5.centos Firefox/3.0.10,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1412 On Jun 18, 11:32=A0am, Petter Gustad wrote: > "evilkid...@googlemail.com" writes: > >> Thank you. I'll look into KVM. > > Works for me - the trick it seems is to ensure that you are running > > with hardware virtualization enabled. =A0Otherwise the USB dongle drive= r > > crashes the system. =A0I've only tried this on a core2 duo and core i7 = - > > not sure about AMD processors. > > Thanks. Looks like KVM is the first thing to try out... Sorry, didn't express myself too well there. It was VirtualBox I was speaking about. I did get it working it working in KVM as well but that also took a bit of fiddling (needed the latest dongle drivers I think). Andy. From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.motzarella.org!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Thu, 18 Jun 2009 13:16:18 +0200 Organization: 502 You are not allowed to talk Lines: 13 Sender: newsmailcomp6@gustad.com Message-ID: <87bpolvlkt.fsf@pangea.home.gustad.com> References: <87bpomvaj1.fsf@pangea.home.gustad.com> <87ocslvpsc.fsf@pangea.home.gustad.com> <87fxdxvnmm.fsf@pangea.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.eternal-september.org U2FsdGVkX1+6m2IIfUzcwlb2GdPHKUakzEdBMtmOn4GdeXyJx4qE+6GnPWZyOvrZmlIC95RiuzOcxTet0EAsgU8A4VUItNGqduUBOzLGtJGLy150CPo0XuXzY5CMfVjOcwqBuVlqxxXQVDGJXhmkaA== X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Thu, 18 Jun 2009 11:16:33 +0000 (UTC) X-Auth-Sender: U2FsdGVkX18TBQ036pVvaUKgxz1LxdyTCGDyybo6Iv8= Cancel-Lock: sha1:c1tOkJIKQWBtTYqL4Gg67NEK4Kw= sha1:72QRhvmtshrGrBCS7oiK705sNGM= X-Home-Page: http://gustad.com User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Xref: news.eternal-september.org comp.lang.vhdl:1413 "evilkidder@googlemail.com" writes: > Sorry, didn't express myself too well there. It was VirtualBox I was > speaking about. OK I see. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Want flag to keep value through all states Date: Thu, 18 Jun 2009 10:49:54 -0700 Lines: 5 Message-ID: <79vd23F1svc1uU1@mid.individual.net> References: <152f2f10-4e6a-4a93-865c-4a583f86c346@d7g2000prl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net DziNDzqf9Qt4ly/SVARFJADb/MFDJ5731wB7+2uitJaWDikQJ0 Cancel-Lock: sha1:EqLY5DTQ1iz+Qy8Ek32BvNrHIdg= User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: <152f2f10-4e6a-4a93-865c-4a583f86c346@d7g2000prl.googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:1414 Shannon wrote: > I'm suffering post traumatic "send" disorder.... And yet the "send" button is the source of all enlightenment ;) From newsfish@newsfish Wed Aug 19 13:25:09 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!news.glorb.com!news2.glorb.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 18 Jun 2009 18:40:49 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Modelsim PE/Win in VirtualBox? Date: Fri, 19 Jun 2009 00:44:16 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <87bpomvaj1.fsf@pangea.home.gustad.com> <87ocslvpsc.fsf@pangea.home.gustad.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 32 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-TexGatZ+k1pqtiFgzTfNDyQA+uHs9qACsqym4lnn5OLOiHjI2cZHKICENL+HWe0od0bmu+ycU1O7cpM!eXf6Hhljpj0AlQ/wbb9btqsFFS62/bD6zOQWSPfRrv5TEr5hb1cr7uk9cVvPoboHudXOU4LLRPfd!B1xr X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1415 On Thu, 18 Jun 2009 03:16:59 -0700 (PDT), "evilkidder@googlemail.com" wrote: >On Jun 18, 10:45 am, Petter Gustad wrote: >> Brian Drummond writes: >> > I presume you are using the Sun Virtualbox not the open source one, since you >> >> Correct. More speficically version 2.2.4. >> >> > I recommend taking a look at kvm >> >> Thank you. I'll look into KVM. >> >> Petter >> -- >> A: Because it messes up the order in which people normally read text. >> Q: Why is top-posting such a bad thing? >> A: Top-posting. >> Q: What is the most annoying thing on usenet and in e-mail? > > >Works for me - the trick it seems is to ensure that you are running >with hardware virtualization enabled. Otherwise the USB dongle driver >crashes the system. I've only tried this on a core2 duo and core i7 - >not sure about AMD processors. > My experience was on an AMD processor (Socket AM2 ar AM2+) with (if I understand it) hardware virtualisation but not the latest IOMMU. - Brian From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!n21g2000vba.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: set dont touch attribute in xilinx xst? Date: Fri, 19 Jun 2009 07:43:27 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <70067c08-5302-4229-8831-2b0d1b1d73d3@n21g2000vba.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245422609 27766 127.0.0.1 (19 Jun 2009 14:43:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Jun 2009 14:43:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n21g2000vba.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1418 Is there a "set_dont_touch" equaivalent version of Xilinx Xst attribute. Or is it only in synopsys? From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!newsfeed.arcor.de!newsspool1.arcor-online.net!news.arcor.de.POSTED!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.lang.vhdl Subject: cloning textio lines Date: Fri, 19 Jun 2009 18:49:58 +0200 Message-ID: X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 Organization: Arcor NNTP-Posting-Date: 19 Jun 2009 18:50:06 CEST NNTP-Posting-Host: 7b49dba5.newsspool4.arcor-online.net X-Trace: DXC=bUW]d93mm;\I?44J>Z[:RQ4IUKl@5^gUE;annMI59T^\;UiPeggM?SP Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Fri, 19 Jun 2009 18:17:36 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <6mhn35pmefp264ub0mi2i6k1c85bkq488e@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 53 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-iX1w4M17Lc2L+Pi5pLPL4A5LLoXeK6XaKcQFbEBrFlqxhgU68/290H5cwAkRlViyPib4A3toteZ4fr/!jE2h44v+k8J5h/3DEgKtRbObQDAfJ2PQsebVqWOEFh0b1hyaIqLZO2ZwylW3Ajo/FjHx5oeFdVu7!X6CwsywwjjuUNZo9 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1420 On Fri, 19 Jun 2009 18:49:58 +0200, Gerhard Hoffmann wrote: >Is there an easy way to clone a textio line including its contents? >Without memory leaks? Must be a standard task. >Probably I'm missing something obvious. I doubt it. You can use the "tee" routine in VHDL-2008 (maybe). If you want it portable, you must work a little harder: variable L, Lclone: line; ... write(L, stuff); write(L, more stuff); ... --- OK, now put L to both a file and to the console write(Lclone, L.all); -- L.all is a string!!! writeline(myfile, L); writeline(OUTPUT, Lclone); You can *almost* do it even more easily: write(OUTPUT, L.all); writeline(myfile, L); Here the write() call is the built-in write operation for the file, which is a TEXT file (i.e. FILE OF STRING) so you write the string L.all to OUTPUT. But some tools do slightly odd things about newlines when you do that, so it's safer to clone the LINE variable as I showed above. Note that you could also put L.all into a report message: report "About to write this to a file: " & L.all; writeline(myfile, L); None of these techniques suffers memory leakage, to the best of my knowledge. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Fri, 19 Jun 2009 10:53:50 -0700 Lines: 39 Message-ID: <7a21lfF1t1g0rU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net gio8lv3hSCrElLo3UsAbVw1IMNkyjhHFrRA8dyTk8vRDY2NQEA Cancel-Lock: sha1:W2gA+ldWGyHc7TI+TRH3glFmG08= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:1421 Gerhard Hoffmann wrote: > Is there an easy way to clone a textio line including its contents? The words 'easy' and 'textio' belong together. I declare vhdl constant arrays instead. > Must be a standard task. > Probably I'm missing something obvious. The 'obvious' way to do variable strings is with access types, but this is not easy either. -- Mike Treseler _________________________________________________ procedure verify is type string_p is access string; variable string_v : string_p; begin string_v := new string'(integer'image(to_integer(expect_v))); report "___Step " & integer'image(step_v); match_v := expect_v = unsigned(readData_s); pass_v := pass_v and match_v; step_v := step_v + 1; ck : if match_v then boring : if verbose_g then report "_________saw " & string_v.all & " as expected"; end if boring; else report "__________Expected byte is " & string_v.all; report "__________Actual bus data is " & integer'image(to_integer(unsigned(readData_s))) severity error; report "______________________________WIRE STATE IS " & wire_t'image(wire_g); die; end if ck; end procedure verify; From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!newsfeed.velia.net!news.tu-darmstadt.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines --typo Date: Fri, 19 Jun 2009 10:57:05 -0700 Lines: 5 Message-ID: <7a21rhF1t1g0rU2@mid.individual.net> References: <7a21lfF1t1g0rU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ib9yTCVt7ne9IuxF3mDk6AU0rem/RibqpfrA7SNqxoA4uFEu4S Cancel-Lock: sha1:/Ol1Hl3AKTBByVExmGULZxHdzrs= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <7a21lfF1t1g0rU1@mid.individual.net> Xref: news.eternal-september.org comp.lang.vhdl:1422 Mike Treseler wrote: > The words 'easy' and 'textio' belong together. ^ don't From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!s1g2000prd.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Fri, 19 Jun 2009 15:18:36 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <886cdb4f-7d43-46d6-b6e9-24569ad1ab45@s1g2000prd.googlegroups.com> References: <6mhn35pmefp264ub0mi2i6k1c85bkq488e@4ax.com> NNTP-Posting-Host: 67.169.207.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245449916 20618 127.0.0.1 (19 Jun 2009 22:18:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Jun 2009 22:18:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s1g2000prd.googlegroups.com; posting-host=67.169.207.204; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1423 > You can *almost* do it even more easily: > > =A0 write(OUTPUT, L.all); > =A0 writeline(myfile, L); On some simulators, the following does not add a linefeed. This is desirable in some cases as it allows you to prompt for a response. write(OUTPUT, L.all); The following adds the linefeed with concatenation: write(OUTPUT, L.all & LF); Note this is one place simulators seem to be inconsistent. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!x31g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: set dont touch attribute in xilinx xst? Date: Fri, 19 Jun 2009 15:24:34 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <395c5b6b-1ff7-432d-be8a-53c5932da49d@x31g2000prc.googlegroups.com> References: <70067c08-5302-4229-8831-2b0d1b1d73d3@n21g2000vba.googlegroups.com> NNTP-Posting-Host: 67.169.207.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245450274 21605 127.0.0.1 (19 Jun 2009 22:24:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Jun 2009 22:24:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x31g2000prc.googlegroups.com; posting-host=67.169.207.204; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1424 On Jun 19, 7:43=A0am, Serkan wrote: > =A0 =A0Is there a "set_dont_touch" equaivalent version of Xilinx Xst > attribute. Or is it only in synopsys? If you are trying to preserve a wire, the attribute is keep. So if you are trying to set a don't signal T1, T2 : std_logic ; Attribute keep : boolean ; Attribute keep of T1, T2 : signal is true ; Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:25:10 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Jun 2009 19:47:41 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Sat, 20 Jun 2009 01:51:10 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: <6eco35ht6gofe1br346ghpub85b3jf9ore@4ax.com> References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-umkzDw4zUgMPyMD5K8JXiM8h4aPwj66lS8SbITuvTNWq4UQ+SblUukX4SNi8DKrxK62ONbK9DeI04lN!WinqiYShOXoneL2uU9oAbbFKoBEuSo5kEgHOxxfKxEMXiUuSlg6m17W+VObhDoNlbguv/4YZZMv7!Q9Q= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: news.eternal-september.org comp.lang.vhdl:1425 On Fri, 19 Jun 2009 18:49:58 +0200, Gerhard Hoffmann wrote: > >Hi all, > >I'm writing a test bed that reads lines from a stimulus file, >writes these lines to a log file, parses them for adresses, >data, expected exceptions etc. >Then the observations are added to the log. > >The problem is, that writing the line to the log file consumes it. >Copying in the style > line2 := line1; >provides but a second pointer to the deallocated NOTHING. > >Is there an easy way to clone a textio line including its contents? I would expect something like line2 := new line1.all; (before the writeline of course!) >Without memory leaks? Must be a standard task. deallocate line2 when appropriate. - Brian From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 20 Jun 2009 04:16:24 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Sat, 20 Jun 2009 10:13:22 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <399p35dj2qoan53ukm9149i23fv9mrk6o7@4ax.com> References: <6eco35ht6gofe1br346ghpub85b3jf9ore@4ax.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 43 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rxkaPVcUUAtyeQG0Ew6ef+vb+CVpf//gnVU26f68WEvgrN90HOLKxBikesZWd8ifVZ3takZqfqumV+Z!MNzcVGnUIEVk92HxP9W7e8PsySIarNBIZVfHQ8SmxkgRcp2/PoxBcPMsT5+QBUdYVaR0lXA69+WT!hAiARgvbbhmsULYm X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2555 Xref: news.eternal-september.org comp.lang.vhdl:1427 On Sat, 20 Jun 2009 01:51:10 +0100, Brian Drummond wrote: >I would expect something like >line2 := new line1.all; >(before the writeline of course!) Nice. >>Without memory leaks? Must be a standard task. >deallocate line2 when appropriate. All this strongly suggests that the safest and most flexible way is to do as Gerhard suggested and create a nondestructive version of writeline: procedure writeline_keep ( file f: text; variable L: line ) is variable L2: line; begin L2 = new L.all; writeline(f, L2); end; Now you can call writeline_keep() as many times as you want, on as many different files as you want, and call writeline() only when writing to the last of your set of files. Now let's talk about how tedious it is that you can't have a file as a member of an aggregate... it would be SO nice if I could make a record containing a file together with all my private state information relating to it, or make an array of files. (Yes, I know, use protected types...) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!newsfeed.arcor.de!newsspool4.arcor-online.net!news.arcor.de.POSTED!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.lang.vhdl Subject: Re: cloning textio lines Date: Sat, 20 Jun 2009 13:37:47 +0200 Message-ID: References: <6eco35ht6gofe1br346ghpub85b3jf9ore@4ax.com> <399p35dj2qoan53ukm9149i23fv9mrk6o7@4ax.com> X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 Organization: Arcor NNTP-Posting-Date: 20 Jun 2009 13:37:56 CEST NNTP-Posting-Host: 8fe8055b.newsspool1.arcor-online.net X-Trace: DXC=@JkamTGFbd1n`gW2MTm]<3ic==]BZ:af>4Fo<]lROoR1^YC2XCjHcb9gcCL78iUm??E;annMI59T>:19\V1W?JK2>cL2^<2k@C: X-Complaints-To: usenet-abuse@arcor.de Xref: news.eternal-september.org comp.lang.vhdl:1428 On Sat, 20 Jun 2009 10:13:22 +0100, Jonathan Bromley wrote: >Now you can call writeline_keep() as many times as you want, >on as many different files as you want, and call writeline() >only when writing to the last of your set of files. I LIKE IT! Thanks for all the answers, Gerhard From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n4g2000vba.googlegroups.com!not-for-mail From: timinganalyzer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: TimingAnalyzer is now freeware Date: Sat, 20 Jun 2009 08:51:43 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: NNTP-Posting-Host: 76.98.36.115 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245513104 30107 127.0.0.1 (20 Jun 2009 15:51:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Jun 2009 15:51:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n4g2000vba.googlegroups.com; posting-host=76.98.36.115; posting-account=40YgGgoAAAB0oRRqyBM1Zw2iHONFVNnk User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.0.11) Gecko/2009060214 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4280 comp.lang.vhdl:1429 comp.lang.verilog:531 Hi All, I just wanted to let you know that the TimingAnalyzer is now licensed as freeware. I just don't have the time needed to make a high quality commercial product but I do want to keep the development moving forward and continue to fix problems and add new features as time permits. Recently, I have become very interested in Python and using it to develop similar type cad programs. My plan is to convert the TimingAnalyzer Java to Python with mostly a scripting interface for building complex timing diagrams, doing timing analysis, creating testbenches and testvectors from waveform diagrams, and creating timing diagrams from simulation VCD files. Most all of this is text based work anyway. Developing professional GUIs is very time consuming for me. This has been my bottleneck with the program all along. With a command line interface, you will execute a script and in one window, and view and edit and print the timing diagram shown in another window. Like Matlab interface. If anyone is interested in helping with the development, I will make this an open source project. Just let me know if your interested. Thanks, Dan Fabrizio From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000vbo.googlegroups.com!not-for-mail From: "Antti.Lukats@googlemail.com" Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: TimingAnalyzer is now freeware Date: Sat, 20 Jun 2009 09:24:37 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <7d83a6ee-0217-458a-ba5f-e628af7d2a27@o14g2000vbo.googlegroups.com> References: NNTP-Posting-Host: 90.190.248.237 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245515077 24510 127.0.0.1 (20 Jun 2009 16:24:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Jun 2009 16:24:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000vbo.googlegroups.com; posting-host=90.190.248.237; posting-account=z0FtqwoAAAB7_vrOIg6MMon_VxAOoReV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.arch.fpga:4283 comp.lang.vhdl:1430 comp.lang.verilog:532 On Jun 20, 6:51=A0pm, timinganalyzer wrote: > Hi All, > > I just wanted to let you know that the TimingAnalyzer is now licensed > as freeware. =A0 I just don't have the time needed to make a high > quality commercial product but I do want to keep the development > moving forward and continue to fix problems and add new features as > time permits. > > Recently, I have become very interested in Python and using it to > develop similar type cad programs. =A0My plan is to convert the > TimingAnalyzer Java to Python with mostly a scripting interface for > building complex timing diagrams, doing timing analysis, =A0creating > testbenches and testvectors from waveform diagrams, > and creating timing diagrams from simulation VCD files. =A0Most all of > this is text based work anyway. > > Developing professional GUIs is very time consuming for me. =A0This has > been my bottleneck with the program all along. =A0With a command line > interface, =A0you will execute a script and in one window, =A0and view an= d > edit and print the timing diagram shown in another window. =A0 Like > Matlab interface. > > If anyone is interested in helping with the development, =A0I will make > this an open source project. =A0 Just let me know if your interested. > > Thanks, > Dan Fabrizio a link to your webpage would help (for those who are lazy) Antti From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!newsfeed.datemas.de!goblin3!goblin.stu.neva.ru!exi-transit.telstra.net!pit-in1.telstra.net!news.telstra.net!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail From: "Alfonso Baz" Newsgroups: comp.lang.vhdl Subject: Power up state Date: Sun, 21 Jun 2009 12:40:06 +1000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Lines: 13 Message-ID: <4a3d9d81$0$18426$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 122.109.51.81 X-Trace: 1245552001 18426 122.109.51.81 Xref: news.eternal-september.org comp.lang.vhdl:1433 Hi all, I've just started learning VHDL so some of my questions may seem rudimentary... Is there any way of guaranteeing the state of an output pin on power up? Is it done from the VHDL or is it a constraint thing or perhaps something else Cheers Alf From newsfish@newsfish Wed Aug 19 13:25:11 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n19g2000vba.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Power up state Date: Sun, 21 Jun 2009 23:16:10 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <4a3d9d81$0$18426$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245651370 22995 127.0.0.1 (22 Jun 2009 06:16:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Jun 2009 06:16:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000vba.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.11) Gecko/2009061212 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1437 On 21 Jun., 04:40, "Alfonso Baz" wrote: > Hi all, I've just started learning VHDL so some of my questions may seem > rudimentary... > > Is there any way of guaranteeing the state of an output pin on power up? > > Is it done from the VHDL or is it a constraint thing or perhaps something > else > > Cheers > Alf Hi Alfonso, from VHDL point of view, registered outputs can have an asynchronous reset to get an initial state. Combinatorical signals immediatlely (that is after their delay) react to their inputs. you may create some output enable with an and gate or a tristate bufffer to control the power up behavior. The other thing is physics. The behavior of the target architecture. You have to read the datasheet, for CPLD and FPGAs and ask the fab if you are going to design for ASICs. The power on behavior depends on the used technology. e.g. most SRAM based FPGAs hold their I/Os in the tristate while loading their bitsreams and provide an internal reset signal (and locked signals for PLLs DCMs etc) to tell the user circuit when to start. Have a nice synthesis Eilert From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!n8g2000vbb.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: set dont touch attribute in xilinx xst? Date: Sun, 21 Jun 2009 23:39:06 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <70067c08-5302-4229-8831-2b0d1b1d73d3@n21g2000vba.googlegroups.com> <395c5b6b-1ff7-432d-be8a-53c5932da49d@x31g2000prc.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245652746 22316 127.0.0.1 (22 Jun 2009 06:39:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Jun 2009 06:39:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n8g2000vbb.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1438 thank you for your answer. best regards JimLewis wrote: > On Jun 19, 7:43=A0am, Serkan wrote: > > =A0 =A0Is there a "set_dont_touch" equaivalent version of Xilinx Xst > > attribute. Or is it only in synopsys? > > If you are trying to preserve a wire, the attribute is keep. > So if you are trying to set a don't > > signal T1, T2 : std_logic ; > > Attribute keep : boolean ; > Attribute keep of T1, T2 : signal is true ; > > > Cheers, > Jim > SynthWorks VHDL Training From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l34g2000vbi.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: Re: runtime arguments in VHDL (ala plusargs in Verilog) Date: Mon, 22 Jun 2009 06:41:58 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: References: <79sn1nF1sf9j1U1@mid.individual.net> NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245678118 13029 127.0.0.1 (22 Jun 2009 13:41:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Jun 2009 13:41:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l34g2000vbi.googlegroups.com; posting-host=132.228.195.207; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: news.eternal-september.org comp.lang.vhdl:1440 On Jun 17, 12:21=A0pm, Mike Treseler wrote: > Mark wrote: > > Got another how do you things like in Verilog in VHDL question: > > what's the "best" way to pass runtime arguements to a compiled VHDL > > design? =A0Write the test name to a file, and have the tb read the file= , > > and execute a particular test procedure? > > That would not be my recommendation. > I use vhdl procedures, and simple vsim -G generics. > See the testbench example here:http://mysite.verizon.net/miketreseler/ Thanks. I'll follow that model. From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: news.eternal-september.org!feeder.motzarella.org!news.motzarella.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail From: "Alfonso Baz" Newsgroups: comp.lang.vhdl References: <4a3d9d81$0$18426$afc38c87@news.optusnet.com.au> Subject: Re: Power up state Date: Tue, 23 Jun 2009 21:10:22 +1000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Lines: 53 Message-ID: <4a40b81a$0$7463$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 122.109.49.250 X-Trace: 1245755418 7463 122.109.49.250 Xref: news.eternal-september.org comp.lang.vhdl:1445 Thanks for the reply Eilert, you've pointed me in right direction. I've done some reading and found that for the CPLD (XC95144XL) it has two power supplies One for the internals (Vccint) and one for the IO buffers (Vccio). You were correct with the tri-state start up, the documentation reveals it also has a weak pullup. The recommended way to power up with a known state is to first apply power to Vccint enabling the logic to sort itself out and then Vccio. If both a powered up simultaneously the documentation states that for this CPLD device, an output that is meant to be low on power up will exhibit a "glitch" Cheers Alfonso "backhus" wrote in message news:bae7b315-8621-4cbc-86c3-1205ec94c3a8@n19g2000vba.googlegroups.com... > On 21 Jun., 04:40, "Alfonso Baz" wrote: >> Hi all, I've just started learning VHDL so some of my questions may seem >> rudimentary... >> >> Is there any way of guaranteeing the state of an output pin on power up? >> >> Is it done from the VHDL or is it a constraint thing or perhaps something >> else >> >> Cheers >> Alf > > Hi Alfonso, > from VHDL point of view, registered outputs can have an asynchronous > reset to get an initial state. Combinatorical signals immediatlely > (that is after their delay) react to their inputs. you may create some > output enable with an and gate or a tristate bufffer to control the > power up behavior. > > The other thing is physics. The behavior of the target architecture. > You have to read the datasheet, for CPLD and FPGAs and ask the fab if > you are going to design for ASICs. > > The power on behavior depends on the used technology. e.g. most SRAM > based FPGAs hold their I/Os in the tristate while loading their > bitsreams and provide an internal reset signal (and locked signals for > PLLs DCMs etc) to tell the user circuit when to start. > > Have a nice synthesis > Eilert From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!news.nask.pl!news.nask.org.pl!news2.icm.edu.pl!not-for-mail From: "qharz" Newsgroups: comp.lang.vhdl Subject: How to get most significant bits Date: Tue, 23 Jun 2009 20:39:14 +0200 Organization: http://news.icm.edu.pl/ Lines: 9 Message-ID: NNTP-Posting-Host: mikrus.nat.student.pw.edu.pl Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-2"; reply-type=original Content-Transfer-Encoding: 7bit X-Trace: achot.icm.edu.pl 1245782329 30965 194.29.137.2 (23 Jun 2009 18:38:49 GMT) X-Complaints-To: abuse@icm.edu.pl NNTP-Posting-Date: Tue, 23 Jun 2009 18:38:49 +0000 (UTC) Importance: Normal X-MimeOLE: Produced By Microsoft MimeOLE V14.0.8064.206 X-Priority: 3 X-Newsreader: Microsoft Windows Live Mail 14.0.8064.206 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1446 Hi How to get 17 oldest bits from variable std_logic_vector (17 + 2*CONSTANT downto 0) CONSTANT is changing manually before every compilation. Thanks -- qharz From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: eternal-september.org!news.albasani.net!newsfeed.freenet.de!feeder.news-service.com!postnews.google.com!d7g2000prl.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: How to get most significant bits Date: Tue, 23 Jun 2009 11:52:23 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <1d488fdc-8e76-4ed2-b532-ac2ca3167d91@d7g2000prl.googlegroups.com> References: NNTP-Posting-Host: 67.169.207.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245783144 15513 127.0.0.1 (23 Jun 2009 18:52:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 23 Jun 2009 18:52:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000prl.googlegroups.com; posting-host=67.169.207.204; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1447 > Hi > How to get 17 oldest bits from variable std_logic_vector (17 + 2*CONSTANT > downto 0) > CONSTANT is changing manually before every compilation. > > Thanks > -- > qharz signal V : std_logic_vector (17 + 2*MY_CONST downto 0) ; signal L, R : std_logic_vector(16 downto 0) ; -- 17 left most bits: L <= V(V'left downto V'left - 16) ; -- 17 right most bits R <= V(16 downto 0) ; Not sure what you mean by oldest, so those are my best guesses. Cheers, Jim From newsfish@newsfish Wed Aug 19 13:25:12 2009 Path: eternal-september.org!news.swapon.de!news.linkpendium.com!news.linkpendium.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi150.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <1d488fdc-8e76-4ed2-b532-ac2ca3167d91@d7g2000prl.googlegroups.com> Subject: Re: How to get most significant bits Lines: 12 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi150.ffdc.sbc.com 1245788627 ST000 99.184.242.197 (Tue, 23 Jun 2009 16:23:47 EDT) NNTP-Posting-Date: Tue, 23 Jun 2009 16:23:47 EDT Organization: at&t http://my.att.net/ X-UserInfo1: TSU[@I_AOXTEBS\Y@RHVOQH@FJT@QDDMEPWXODMMHXMTWA]EPEWUQBKZQLYJX\_ITFD_KFVLUN[DOM_A_NSYNWPFWNS[XV\I]PZ@BQ[@CDQDPCL^FKCBIPC@KLGEZEFNMDYMKHRL_YYYGDSSODXYN@[\BK[LVTWI@AXGQCOA_SAH@TPD^\AL\RLGRFWEARBM Date: Tue, 23 Jun 2009 16:23:36 -0400 Xref: eternal-september.org comp.lang.vhdl:1448 "JimLewis" wrote in message news:1d488fdc-8e76-4ed2-b532- > > Not sure what you mean by oldest, so those are my best guesses. > The older ones tend to be on the right... KJ From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!feeder.news-service.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: comp.lang.vhdl Subject: Call For Participation: WORLDCOMP'09 (The 2009 World Congress in Computer Science, Computer Engineering, and Applied Computing), USA, July 13-16, 2009 Date: Wed, 24 Jun 2009 00:52:13 -0700 (PDT) Organization: http://groups.google.com Lines: 287 Message-ID: <5b9b9c3b-6860-45f5-bc61-356bc31feb5a@k8g2000yqn.googlegroups.com> NNTP-Posting-Host: 70.64.147.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245829933 3527 127.0.0.1 (24 Jun 2009 07:52:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 07:52:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=70.64.147.19; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; OfficeLiveConnector.1.3; OfficeLivePatch.0.0),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1451 Call For Participation WORLDCOMP'09 The 2009 World Congress in Computer Science, Computer Engineering, and Applied Computing Date and Location: July 13-16, 2009, Las Vegas, USA http://www.world-academy-of-science.org/ This is an invitation to attend WORLDCOMP'09 Congress. WORLDCOMP'09 is composed of a number of tracks (22 joint conferences, 15 tutorials, 180 technical sessions and workshops, 55 keynotes and invited lectures); all will be held simultaneously, same location and dates: July 13-16, 2009. Attendees will have full access to all conferences' sessions, tracks, and tutorials. See below for the complete list of joint conferences, list of sponsors, registration information, hotel information, and some highlights. LIST OF JOINT CONFERENCES: o BIOCOMP'09: Bioinformatics and Computational Biology o CDES'09: Computer Design o CGVR'09: Computer Graphics and Virtual Reality o CSC'09: Scientific Computing o DMIN'09: Data Mining o EEE'09: e-Learning, e-Business, Enterprise Information Systems, and e-Government o ERSA'09: Engineering of Reconfigurable Systems and Algorithms o ESA'09: Embedded Systems and Applications o FCS'09: Foundations of Computer Science o FECS'09: Frontiers in Education: Computer Science and Computer Engineering o GCA'09: Grid Computing and Applications o GEM'09: Genetic and Evolutionary Methods o ICAI'09: Artificial Intelligence o ICOMP'09: Internet Computing o ICWN'09: Wireless Networks o IKE'09: Information and Knowledge Engineering o IPCV'09: Image Processing, Computer Vision, and Pattern Recognition o MSV'09: Modeling, Simulation and Visualization Methods o PDPTA'09: Parallel and Distributed Processing Techniques and Applications o SAM'09: Security and Management o SERP'09: Software Engineering Research and Practice o SWWS'09: Semantic Web and Web Services CO-SPONSORS: ACADEMIC/TECHNICAL Co-Sponsors: o United States Military Academy, Network Science Center; o Biomedical Cybernetics Lab., HST of Harvard U. and MIT; o Argonne's Leadership Computing Facility of Argonne National Lab.; o Functional Genomics Lab., U. of Illinois at Urbana-Champaign; o Minnesota Supercomputing Institute, U. of Minnesota; o Intelligent Data Exploration & Analysis Lab., U. of Texas at Austin; o Harvard Statistics Department Genomics & Bioinformatics Lab., Harvard U.; o Texas Advanced Computing Center, U. of Texas at Austin; o Center for the Bioinformatics & Computational Genomics, Georgia Institute of Technology; o Bioinformatics & Computational Biology Program, George Mason U.; o Institute of Discrete Mathematics & Geometry, Vienna U. of Technology, Austria; o BioMedical Informatics & Bio-Imaging Lab., Georgia Institute of Technology & Emory U.; o Knowledge Management & Intelligent System Center (KMIS) of U. of Siegen, Germany; o National Institute for Health Research; o Hawkeye Radiology Informatics, Department of Radiology, College of Medicine, U. of Iowa; o Institute for Informatics Problems of the Russian Academy of Sciences, Moscow, Russia; o Medical Image HPC & Informatics Lab (MiHi Lab), U. of Iowa; o SECLAB (U. of Naples Federico II, U. Naples Parthenope, & Second U. Naples, Italy; o U. of North Dakota; o Intelligent Cyberspace Engineeing Lab., ICEL, Texas A&M/Comm, U.; o International Society of Intelligent Biological Medicine; o World Academy of Biomedical Sciences and Technologies. OTHER SPONSORS: o European Commission; o Supermicro, Inc. o Salford Systems o Element CXI, California o High Performance Computing for Nanotechnology (HPCNano); o HoIP - Health without Boundaries; o The International Council on Medical and Care Compunetics; o The UK Department for Business, Enterprise & Regulatory Reform; o VMW Solutions Ltd.; o Scientific Technologies Corporation; o Hodges' Health o Bentham Science Publishers o GridToday CONFERENCE SCHEDULE/PROGRAM: The complete WORLDCOMP'09 schedule/program is available at: http://www.world-academy-of-science.org/worldcomp09/ws/program REGISTRATION INFORMATION: To attend the congress, use the following online registration link: http://www.world-academy-of-science.org/worldcomp09/ws/registration HOTEL RESERVATION: WORLDCOMP'09 will be held in the Monte Carlo resort, Las Vegas, Nevada, USA (with any overflows at other near-by hotels). This is a mega hotel with excellent conference facilities and over 3,000 rooms. It is minutes from the airport with 24-hour shuttle/taxi service to and from the airport. This hotel has many recreational attractions and is within walking distance from most other attractions. You are to reserve your hotel room directly by calling Monte Carlo Resort at 1-702-730-7000 or 1-702-730-7777. Make sure that you mention the Group Code "XWRLD9" (XWRLD9 is the keyword that the hotel will use to handle the reserved block of rooms for the Congress). You should reserve your room as soon as possible since our block is very close to being fully booked. There are also many other hotels nearby. KEYNOTE LECTURES (this is only a small subset): o Prof. Ian Foster Father of Grid Computing Distinguished Professor of Computer Science and Director, Computation Institute, University of Chicago and Argonne National Laboratory, Illinois, USA Title: Grid Computing o Dr. K. Eric Drexler Father of Nanotechnology Chief Technical Advisor, Nanorex Title: Advanced Nanotechnology: Advanced Computing on the Critical Path o Prof. Viktor K. Prasanna Fellow, IEEE; Fellow ACM Charles Lee Powell Chair in Engineering; Professor of EE, CE, CS; Executive Director of USC-Infosys Center for Advanced Software Technologies (CAST); University of Southern California, USA Title: Algorithm Design for Reconfigurable Computing Systems o Dr. Jose L. Munoz Deputy Director, National Science Foundation (NSF) Office of Cyberinfrastructure (OCI) and NSF/ICI senior advisor. Former Director of Simulation & CS Office at the National Nuclear Security Adm.'s Advanced Simulation & Computing (ASCI) program. Title: It's Like Deja-Vu All over Again ... Again o Dr. Sandeep Chatterjee Co-founder, Chief Technology Officer and Vice President, SourceTrace Systems, Inc. Title: e-Services Everywhere o Dr. Rahul Razdan CEO, Raztech LLC Title: Future Directions in Reconfigurable Computing o Prof. P. M. A. Sloot Director of the Institute for Informatics University of Amsterdam, The Netherlands Editor-in-Chief, Future Generation Computer Systems Title: Sex and the City - Modelling HIV from Molecule to Man and Title: Modeling Dynamic Systems with Cellular Automata o Prof. Michael Bank Holon Institute of Technology, Israel Inventor of Frequency Bank Signal (FBS). Title: Perception Redundancy Theory and Technical Compression Systems and Title: The Doppler Effect: Limiting Values in OFDMA Cellular Systems o Prof. Brian D. Athey University of Michigan Medical School, USA; Founding Associate Director, CCMB; Head, NIH National Center for Integrative Biomedical Informatics; Director, Biomedical Informatics Program of Michigan Institute for Clinical & Health Research; Advisor to Director of DPCPSI in the office of the Director of the NIH. Title: TBA PLANNED TUTORIALS (this is a partial list): Tutorial attendance is free to registered attendees of worldcomp and all its associated conferences (most are 3 hours long): o Robust Resource Management for Parallel and Distributed Computing Systems: Models and Methods Prof. H. J. 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Nelson School of Technology Graduate Program Director Hodges University, Ft Myers, Florida, USA o Teaching Java Through Alice and Greenfoot Dr. Peter DePasquale* and Dr. Mark Lewis** *The College of New Jersey, USA & **Trinity University, USA o Emerging Human-Web Interaction Research Dr. Peter Geczy National Institute of Advanced Industrial Science and Technology (AIST), Japan o Cryptographic Features and Applications: Java (C) Prof. Ray Kresman Bowling Green State University, Bowling Green, Ohio, USA o A Tour of Advanced Data Mining Methodologies Dr. Dan Steinberg President and CEO of Salford Systems, Inc. o Autonomous Machine Learning Prof. Asim Roy Arizona State University, Arizona, USA o Web Services in ASP.NET AJAX Khanna Samratvivekanand Omprakash Institute of Science & Technology for Advanced Studies and Research(ISTAR), Charotar Vidya Mandal (CVM), Sardar Patel University, V.V.Nagar, India From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 11:37:24 +0100 Organization: A noiseless patient Spider Lines: 101 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX19fPv1NeG4MooAM6hO79HUtw5PK5u7w7bUJ8L3ypcm8UX868OA/hgONA5gln1AZ9xMd+kLLviLjaXro2tRghhNEPenp4buSgXQLfdCBRaE4nvjYtbop5LX8KLkHoMFYQ5Z0TJGQ2RXiRw== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 10:39:53 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1+/sX4gnmg+IDq21ooZpZqcrbddrXfmuyk= Cancel-Lock: sha1:aGv0DlifS3lxxH4uiJYHM/W4/xw= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1452 comp.arch.fpga:4358 "Jonathan Bromley" wrote in message news:prs345lln7bmpp71hrk9p33ehfkq8231gj@4ax.com... > hi all, > > As promised many weeks ago, I'm building what I > hope will be a comprehensive summary of how to do > RAM inference from VHDL and Verilog code for all > the common synthesis tools and FPGAs. It will > go on our website some time this summer (sorry, > it's not a high-priority project). > > I've encountered what seems to me to be a bug > in XST (all versions from 8 to 11 inclusive) > and I would value your opinion before I start > to give Xilinx a hard time about it. By the > way, exactly the same bug appears to be present > in Quartus but I haven't yet done enough detailed > investigation to comment on that properly. > > To create true (dual-clock) dual-port RAM, > I need to create two clocked processes. This > requires me to use a shared variable for > the memory itself (ugly but possible, works > correctly in XST): > > type t_mem is array (0 to 2**ABITS-1) of > std_logic_vector(DBITS-1 downto 0); > shared variable mem: t_mem; -- the memory storage > begin -- the architecture > process (clock0) -- manages port A > begin > if rising_edge (clock0) then > if we0 = '1' then -- write to port A > mem(to_integer(unsigned(a0))) := wd0; > rd0 <= wd0; > else > rd0 <= mem(to_integer(unsigned(a0))); > end if; > end if; > end process; > -- > process (clock1) -- manages port B > begin > if rising_edge (clock1) then > if we1 = '1' then > mem(to_integer(unsigned(a1))) := wd1; > rd1 <= wd1; > else > rd1 <= mem(to_integer(unsigned(a1))); > end if; > end if; > end process; > > That, I believe, is the right way to do it. > > However, both XST and Quartus give THE SAME SYNTHESIS > RESULTS if I change "shared variable" to "signal", and > make signal assignments instead of variable assignments > to the mem() array. This is just plain WRONG! Writing > to a signal from two processes represents two resolved > drivers on the signal, and does not correctly model a > dual-port memory in simulation. > > Given that the whole point of memory inference from > HDL code is that you get a convenient, readable, > accurate simulation model as part of your design > code, this behaviour by the synthesis tools is > incomprehensible to me. Can anyone clarify? Has > anyone fallen foul of this problem? Best of all, > could Brian Philofsky, who has written so clearly > and helpfully about XST in the past, please speak > up and tell us what the blazes is going on here? > Your knowledge of VHDL is greater than mine, but I assumed that > if we1 = '1' then > mem(to_integer(unsigned(a1))) := wd1; > end if; was equivalent to; if we1 = '1' then mem(to_integer(unsigned(a1))) := wd1; else mem(to_integer(unsigned(a1))) := mem(to_integer(unsigned(a1))); end if; if you used something like; if we1 = '1' then mem(to_integer(unsigned(a1))) := wd1; else mem(to_integer(unsigned(a1))) := (others => 'Z'); end if; Would this then give more consistent results where both processes wouldn't be fighting against each other? Happy to be told I'm wrong. From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!news.mixmin.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 24 Jun 2009 06:18:46 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 12:15:39 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 56 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-hgDMz3FeVMtQT7vDvTJZAraQbrPrqzAQrJmQFM3X1mJyglEqWeuVxBTqofS1E+tOYaHL+n0yMSZF6RQ!C+1aBc6JW6kmrN3cZPCkCSJbZrc9xD/V1BxmpAJSSyCFY0EGII4ubmfme+XJVcK/iQrd1FjdU+wD!VgBNsk7+TG/YUGcr X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1453 comp.arch.fpga:4359 On Wed, 24 Jun 2009 11:37:24 +0100, "Fredxx" wrote: >if you used something like; > if we1 = '1' then > mem(to_integer(unsigned(a1))) := wd1; > else > mem(to_integer(unsigned(a1))) := (others => 'Z'); > end if; > >Would this then give more consistent results where both processes wouldn't >be fighting against each other? Sadly, no. I see what you're getting at, but I don't think you could ever get the memory to have the correct contents if both ports are doing that all the time. Each process may overwrite locations it's already correctly written, using Zs, for no good reason. Suppose you could get it right somehow, and arrange that each process is driving Z to all locations it's never written, but appropriate values to locations it has written. What then happens if the second process writes to a location that previously was written by the other? How can it tell the first process now to put Z on that location? In truth the "correct" solution would be to write the whole thing as a single process with two clocks: process (clock0, clock1) variable mem: t_mem; begin if rising_edge(clock0) then if we0 = '1' then mem(a0) := wd0; end if; end if; if rising_edge(clock1) then if we1 = '1' then mem(a1) := wd1; end if; end if; ... But I suspect synthesis tools would chuck that overboard without a second thought. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 12:44:27 +0100 Organization: A noiseless patient Spider Lines: 70 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX19YyuMqEh/k8ygRp6cvQ+6vAh6OI5Q+IzdyI2koRQ9JohleE9zOzV0oZaAtU2HwpyAol/UkYxHKqu7g5V/soB2FZyEQrsQlLKfMyTAURRrR8fr0PKFL29bc1QoI8IDPFXhA9Q0B7dHYzQ== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 11:46:54 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1+n6EBIne4iIsI11iu5urG3lrWNw86f1bU= Cancel-Lock: sha1:7Ic2+lfiTML6KL1G7buBNarWQ8o= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1454 comp.arch.fpga:4360 "Jonathan Bromley" wrote in message news:bn0445lbemmf3qnl87te1hps2l3nc9novv@4ax.com... > On Wed, 24 Jun 2009 11:37:24 +0100, "Fredxx" wrote: > >>if you used something like; >> if we1 = '1' then >> mem(to_integer(unsigned(a1))) := wd1; >> else >> mem(to_integer(unsigned(a1))) := (others => 'Z'); >> end if; >> >>Would this then give more consistent results where both processes wouldn't >>be fighting against each other? > > Sadly, no. I see what you're getting at, but I don't think you could > ever get the memory to have the correct contents if both ports are > doing that all the time. Each process may overwrite locations it's > already correctly written, using Zs, for no good reason. > > Suppose you could get it right somehow, and arrange that each process > is driving Z to all locations it's never written, but appropriate > values to locations it has written. What then happens if the second > process writes to a location that previously was written by the other? > How can it tell the first process now to put Z on that location? > > In truth the "correct" solution would be to write the whole thing > as a single process with two clocks: > > process (clock0, clock1) > variable mem: t_mem; > begin > if rising_edge(clock0) then > if we0 = '1' then > mem(a0) := wd0; > end if; > end if; > if rising_edge(clock1) then > if we1 = '1' then > mem(a1) := wd1; > end if; > end if; > ... > > But I suspect synthesis tools would chuck that overboard > without a second thought. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > I perhaps am making the (erroneous) assumption that two statements will be or'd together and the Z's will be overdriven by the signals. But as you say, I would be replacing the RAM locations with Z's or something that the synthesiser concocts. To be honest, I think it isn't good practice to have signals driven by 2 clocks, and I'd probably use clock switching primitives instead so the memory would be written in one process with just one clock. From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 24 Jun 2009 07:27:03 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 13:23:56 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-nblA7gyMI1U6evy+jp4goEV4uIGG/9DRp3QGzTZcnyPuHuuWF4o5DX90Dn9wR/mMCXXT5IxwVu9bzy7!NnrSXxwJRrwOZFUGnkzCDXHGbuCLmYzoBCAiLPMQ9QdDI22Bb39FvFvHpWZc2MoS1zcLwKvUAXO9!sAEAvptk0PfcWgmY X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1457 comp.arch.fpga:4361 On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: >I perhaps am making the (erroneous) assumption that two statements will be >or'd together and the Z's will be overdriven by the signals. That's more-or-less correct. Each process represents a driver on any signal it writes. If multiple processes write to a signal, then the actual signal value is determined by resolving the various driven values. Of course, anything else overdrives Z. The hard-to-solve problem: suppose process A writes a value to a memory location at some time; clearly, you want that value to remain in the location and not to be overwritten to Z on the next clock, so you can't allow process A to change its mind about that value. Some time later, suppose process B writes to the same location. Now you have two non-Z drivers on the same set of bits. How can process B tell process A that it's time for its driver to lapse back to Z? Shared variables, for all their ugliness, solve this problem neatly (which is why my problem simply doesn't exist in Verilog, where all variables are shared). >To be honest, I think it isn't good practice to have signals driven by 2 >clocks, and I'd probably use clock switching primitives instead so the >memory would be written in one process with just one clock. In normal logic I would 100% agree, but here I'm talking about modeling and synthesizing the FPGAs' built-in RAM blocks, which have the option of independent clocks on the two ports. So it is important to write VHDL corresponding to that behavior. You could mux the clocks onto a single port, but that would be a totally different design. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 13:54:30 +0100 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX1+iOKlsmE6W2LTX8M7KwkW9Rzkqscrn5ibyI8m0y5XurpX9+ufK5T6pxC5UKun2gc3FmK32wihZyha/AlGEtR1RyAdlQg4RAPDG7lxNY+QaP4WjLOpep7CkHHyoWJrN7LL85fiq8t9QKA== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 12:57:02 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX185z6ml6mDLnCyna2p7ToxQPrDcxkBZMrw= Cancel-Lock: sha1:tCkd2PjE+VeENCiif6t53gJHyUE= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1458 comp.arch.fpga:4362 "Jonathan Bromley" wrote in message news:e76445hlo55p6dki0oi764adcblv5oloul@4ax.com... > On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: > > > In normal logic I would 100% agree, but here I'm talking about > modeling and synthesizing the FPGAs' built-in RAM blocks, which > have the option of independent clocks on the two ports. So > it is important to write VHDL corresponding to that behavior. > You could mux the clocks onto a single port, but that would > be a totally different design. Ah - I see - that does sound rather tricky and can see where you're coming from. From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!33g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 07:18:10 -0700 (PDT) Organization: http://groups.google.com Lines: 87 Message-ID: References: NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245853097 14856 127.0.0.1 (24 Jun 2009 14:18:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 14:18:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 33g2000vbe.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1459 comp.arch.fpga:4365 On Jun 24, 7:44=A0am, "Fredxx" wrote: > "Jonathan Bromley" wrote in message > > news:bn0445lbemmf3qnl87te1hps2l3nc9novv@4ax.com... > > > > > On Wed, 24 Jun 2009 11:37:24 +0100, "Fredxx" wrote: > > >>if you used something like; > >> =A0 =A0 =A0if we1 =3D '1' then > >> =A0 =A0 =A0 =A0mem(to_integer(unsigned(a1))) :=3D wd1; > >> =A0 =A0 =A0else > >> =A0 =A0 =A0 =A0mem(to_integer(unsigned(a1))) :=3D (others =3D> 'Z'); > >> =A0 =A0 =A0end if; > > >>Would this then give more consistent results where both processes would= n't > >>be fighting against each other? > > > Sadly, no. =A0I see what you're getting at, but I don't think you could > > ever get the memory to have the correct contents if both ports are > > doing that all the time. =A0Each process may overwrite locations it's > > already correctly written, using Zs, for no good reason. > > > Suppose you could get it right somehow, and arrange that each process > > is driving Z to all locations it's never written, but appropriate > > values to locations it has written. =A0What then happens if the second > > process writes to a location that previously was written by the other? > > How can it tell the first process now to put Z on that location? > > > In truth the "correct" solution would be to write the whole thing > > as a single process with two clocks: > > > =A0process (clock0, clock1) > > =A0 =A0variable mem: t_mem; > > =A0begin > > =A0 =A0if rising_edge(clock0) then > > =A0 =A0 =A0if we0 =3D '1' then > > =A0 =A0 =A0 =A0mem(a0) :=3D wd0; > > =A0 =A0 =A0end if; > > =A0 =A0end if; > > =A0 =A0if rising_edge(clock1) then > > =A0 =A0 =A0if we1 =3D '1' then > > =A0 =A0 =A0 =A0mem(a1) :=3D wd1; > > =A0 =A0 =A0end if; > > =A0 =A0end if; > > =A0 =A0... > > > But I suspect synthesis tools would chuck that overboard > > without a second thought. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.com > >http://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > I perhaps am making the (erroneous) assumption that two statements will b= e > or'd together and the Z's will be overdriven by the signals. =A0But as yo= u > say, I would be replacing the RAM locations with Z's or something that th= e > synthesiser concocts. > > To be honest, I think it isn't good practice to have signals driven by 2 > clocks, and I'd probably use clock switching primitives instead so the > memory would be written in one process with just one clock. That would be a truly bizarre circuit design. I don't know how they actually construct memory to use separate clocks, but I expect it uses an async memory with two independent synchronous interfaces. FPGA reps have posted here that there is a lot of "magic" in the logic between the sync interfaces and the async memory inside the block ram. All of this would be very hard to describe using an HDL. But driving a signal with 'z' or switching clocks is not the way to go at all... Rick From newsfish@newsfish Wed Aug 19 13:25:13 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 15:45:37 +0100 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX1+fra844VlS9+FJVgrI09qytAaJQf4WB7v4TaxcrnCqrewd35Dfsa2vW8OEecB+XhecqAOaStUNiwccn7VOxmMddRBB6T6jAxHlf7V515AHeR5U1BuYF2+SgL8nM75TaUP4ZFgD69yu+Q== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 14:48:17 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1/WTj9yM3VWEkw+xcReyFc/9kBPxEb9KCQ= Cancel-Lock: sha1:dB0e+Ah3nvS2gPstiHSAsLXRzDI= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1460 comp.arch.fpga:4366 "Jonathan Bromley" wrote in message news:e76445hlo55p6dki0oi764adcblv5oloul@4ax.com... > On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: > >>I perhaps am making the (erroneous) assumption that two statements will be >>or'd together and the Z's will be overdriven by the signals. > > That's more-or-less correct. Each process represents a driver > on any signal it writes. If multiple processes write to a signal, > then the actual signal value is determined by resolving the > various driven values. Of course, anything else overdrives Z. > > The hard-to-solve problem: suppose process A writes a value > to a memory location at some time; clearly, you want that > value to remain in the location and not to be overwritten > to Z on the next clock, so you can't allow process A to change > its mind about that value. Some time later, suppose process B > writes to the same location. Now you have two non-Z drivers > on the same set of bits. How can process B tell process A > that it's time for its driver to lapse back to Z? Shared > variables, for all their ugliness, solve this problem > neatly (which is why my problem simply doesn't exist in > Verilog, where all variables are shared). > >>To be honest, I think it isn't good practice to have signals driven by 2 >>clocks, and I'd probably use clock switching primitives instead so the >>memory would be written in one process with just one clock. > > In normal logic I would 100% agree, but here I'm talking about > modeling and synthesizing the FPGAs' built-in RAM blocks, which > have the option of independent clocks on the two ports. So > it is important to write VHDL corresponding to that behavior. > You could mux the clocks onto a single port, but that would > be a totally different design. What's wrong with an asynchronous memory, where the appropriate clocks latch the control signals to create synchronous RAM. Then we can do something like: process (a0, we0, wd0, a1, we1, wd1) begin if we0 = '1' then -- write to port A mem(conv_integer(a0)) <= wd0; end if; if we1 = '1' then -- write to port A mem(conv_integer(a1)) <= wd1; end if; rd0 <= mem(conv_integer(a0)); rd1 <= mem(conv_integer(a1)); end process; It works in simulation!! From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!f30g2000vbf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 08:00:54 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: References: NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245855654 25163 127.0.0.1 (24 Jun 2009 15:00:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 15:00:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f30g2000vbf.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1461 comp.arch.fpga:4367 On Jun 24, 10:45=A0am, "Fredxx" wrote: > "Jonathan Bromley" wrote in message > > news:e76445hlo55p6dki0oi764adcblv5oloul@4ax.com... > > > > > On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: > > >>I perhaps am making the (erroneous) assumption that two statements will= be > >>or'd together and the Z's will be overdriven by the signals. > > > That's more-or-less correct. =A0Each process represents a driver > > on any signal it writes. =A0If multiple processes write to a signal, > > then the actual signal value is determined by resolving the > > various driven values. =A0Of course, anything else overdrives Z. > > > The hard-to-solve problem: =A0suppose process A writes a value > > to a memory location at some time; clearly, you want that > > value to remain in the location and not to be overwritten > > to Z on the next clock, so you can't allow process A to change > > its mind about that value. =A0Some time later, suppose process B > > writes to the same location. =A0Now you have two non-Z drivers > > on the same set of bits. =A0How can process B tell process A > > that it's time for its driver to lapse back to Z? =A0Shared > > variables, for all their ugliness, solve this problem > > neatly (which is why my problem simply doesn't exist in > > Verilog, where all variables are shared). > > >>To be honest, I think it isn't good practice to have signals driven by = 2 > >>clocks, and I'd probably use clock switching primitives instead so the > >>memory would be written in one process with just one clock. > > > In normal logic I would 100% agree, but here I'm talking about > > modeling and synthesizing the FPGAs' built-in RAM blocks, which > > have the option of independent clocks on the two ports. =A0So > > it is important to write VHDL corresponding to that behavior. > > You could mux the clocks onto a single port, but that would > > be a totally different design. > > What's wrong with an asynchronous memory, where the appropriate clocks la= tch > the control signals to create synchronous RAM. > > Then we can do something like: > > process (a0, we0, wd0, a1, we1, wd1) > begin > =A0 if we0 =3D '1' then =A0-- write to port A > =A0 =A0 mem(conv_integer(a0)) <=3D wd0; > =A0 end if; > =A0 if we1 =3D '1' then =A0-- write to port A > =A0 =A0 mem(conv_integer(a1)) <=3D wd1; > =A0 end if; > =A0 rd0 <=3D mem(conv_integer(a0)); > =A0 rd1 <=3D mem(conv_integer(a1)); > end process; > > It works in simulation!! I doubt that it will synthesize. Synthesis is largely a matter of template matching. You can describe a behavior any way you want in simulation. But if the synthesis tool does not recognize that form, it won't synthesize to anything useful. Often memory that is not recognized as a block ram is synthesized as distributed memory using much of the FFs on a chip. Not only that, but it takes forever to complete just to find out you don't have a workable design. Rick From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!news.mixmin.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 24 Jun 2009 10:00:47 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 15:57:41 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ojoUSjVgVIBz/3N0xp/ecFJN82oonJnFtWEJYqdEgZCtn14RSpsUfbPivgkOkVyMb8b+b1cKVVpSUg5!fgCH1mik4+y/uGTPwZgaLsuuLZQnsJP7hoEFIM+FYvKNmOb/3BHGo3CQSpcp7QNckmeIGBribzoX!A7DiP+F0TgCZyhk9 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1462 comp.arch.fpga:4368 On Wed, 24 Jun 2009 15:45:37 +0100, "Fredxx" wrote: >What's wrong with an asynchronous memory[...] >It works in simulation!! Nothing wrong with them, except that they don't exist in real FPGAs. By contrast, dual-ported dual-clock synchronous RAMs most certainly do :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!de-l.enfer-du-nord.net!feeds.phibee-telecom.net!news-xfer.nntp.sonic.net!news.astraweb.com!border5.newsrouter.astraweb.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi144.ffdc.sbc.com.POSTED!bbf874ca!not-for-mail From: Ed McGettigan Organization: Xilinx Inc. User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 70 Message-ID: NNTP-Posting-Host: 149.199.62.254 X-Complaints-To: abuse@prodigy.net X-Trace: flpi144.ffdc.sbc.com 1245857072 ST000 149.199.62.254 (Wed, 24 Jun 2009 11:24:32 EDT) NNTP-Posting-Date: Wed, 24 Jun 2009 11:24:32 EDT X-UserInfo1: FKPO@MC@OHUURU\YZBNDM^P@VZ\LPCXLLBWLOOAFQATJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 24 Jun 2009 08:24:02 -0700 Xref: eternal-september.org comp.lang.vhdl:1463 comp.arch.fpga:4369 Fredxx wrote: > "Jonathan Bromley" wrote in message > news:e76445hlo55p6dki0oi764adcblv5oloul@4ax.com... >> On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: >> >>> I perhaps am making the (erroneous) assumption that two statements will be >>> or'd together and the Z's will be overdriven by the signals. >> That's more-or-less correct. Each process represents a driver >> on any signal it writes. If multiple processes write to a signal, >> then the actual signal value is determined by resolving the >> various driven values. Of course, anything else overdrives Z. >> >> The hard-to-solve problem: suppose process A writes a value >> to a memory location at some time; clearly, you want that >> value to remain in the location and not to be overwritten >> to Z on the next clock, so you can't allow process A to change >> its mind about that value. Some time later, suppose process B >> writes to the same location. Now you have two non-Z drivers >> on the same set of bits. How can process B tell process A >> that it's time for its driver to lapse back to Z? Shared >> variables, for all their ugliness, solve this problem >> neatly (which is why my problem simply doesn't exist in >> Verilog, where all variables are shared). >> >>> To be honest, I think it isn't good practice to have signals driven by 2 >>> clocks, and I'd probably use clock switching primitives instead so the >>> memory would be written in one process with just one clock. >> In normal logic I would 100% agree, but here I'm talking about >> modeling and synthesizing the FPGAs' built-in RAM blocks, which >> have the option of independent clocks on the two ports. So >> it is important to write VHDL corresponding to that behavior. >> You could mux the clocks onto a single port, but that would >> be a totally different design. > > What's wrong with an asynchronous memory, where the appropriate clocks latch > the control signals to create synchronous RAM. > > Then we can do something like: > > process (a0, we0, wd0, a1, we1, wd1) > begin > if we0 = '1' then -- write to port A > mem(conv_integer(a0)) <= wd0; > end if; > if we1 = '1' then -- write to port A > mem(conv_integer(a1)) <= wd1; > end if; > rd0 <= mem(conv_integer(a0)); > rd1 <= mem(conv_integer(a1)); > end process; > > It works in simulation!! > > Asynchronous memories only work correctly if the input delays are well controlled and internal self timed circuits function correctly. In order to achieve reliability memory designers have to build in a lot of margin so asynchronous memories will operate much slower than a synchronous memory and even then there are tight specs on the address and data busses. For example take the code example that you have above and instead of having a test bench that transitions the a0, a1, wd0 and wd1 at the same time add some delay to various bits in the address and data busses and observe the results. Ed McGettigan -- Xilinx Inc. From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!news.tu-darmstadt.de!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Code Coverage in ModelSim Date: Wed, 24 Jun 2009 17:20:22 +0200 Organization: Universitaet Kaiserslautern Lines: 32 Message-ID: NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245856867 12365 131.246.73.199 (24 Jun 2009 15:21:07 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Wed, 24 Jun 2009 15:21:07 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) Xref: eternal-september.org comp.lang.vhdl:1464 Hi! I'm currently performing code coverage with ModelSim on a design. However I observe a problem regarding the branch coverage with clocked processes: process(clk,rst) is begin if rst = '1' then elsif clk'event and clk = '1' then end if; end process; The problem I have is that the elsif-branch for the clock is not considered to be tested, so in the statistic the branch coverage will never reach the 100%. The detail to this line is: File: test.vhd Line: 70 Branch Coverage for: elsif clk = '1' and clk'event then Branch if: True: 140036 False: 0 But in case of the falling edge the condition should be false, only the clk'event will always be true, since clk is part of the sensitivity list. What am I missing?? Thanks in advance! Matthias From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!n19g2000vba.googlegroups.com!not-for-mail From: Sandro Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 08:31:26 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> References: NNTP-Posting-Host: 151.80.82.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245857486 31323 127.0.0.1 (24 Jun 2009 15:31:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 15:31:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000vba.googlegroups.com; posting-host=151.80.82.15; posting-account=OSNX1AoAAABZtvrWgfgFvYi2krfS2o9W User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.7) Gecko/2009030814 Iceweasel/3.0.9 (Debian-3.0.9-1),gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 mylinbox.mydomai.my:3128 (squid/2.7.STABLE6) Xref: eternal-september.org comp.lang.vhdl:1465 comp.arch.fpga:4370 On Jun 24, 2:23=A0pm, Jonathan Bromley > ... > In normal logic I would 100% agree, but here I'm talking about > modeling and synthesizing the FPGAs' built-in RAM blocks, which > have the option of independent clocks on the two ports. =A0So > it is important to write VHDL corresponding to that behavior. > You could mux the clocks onto a single port, but that would > be a totally different design. > ... If you are curious please take a look to the vhdl VITAL simulations sources... you can find in /Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd but be careful ;-) ... they are NOT 20 lines of code. Regards Sandro From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 16:27:30 +0100 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX1/5O14K/FGbhNFlZeszHenSZOasQ9JAI954uvSop80rEwF/athXde7JG3dnFKKKQ3TSiFnO8+oargsoQnBKJiGu14dnE7E8OgsH08ECpU//kSjll9OGuPMBLBir0D5H8pBKAVSIRGtrwQ== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 15:33:46 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1+SwfvEQtl5GuFq+J/e+cxT9vCb/vQhRXY= Cancel-Lock: sha1:koWkgy8lZDmMbKJfbcMLF1RbFY8= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1466 comp.arch.fpga:4371 "Jonathan Bromley" wrote in message news:akf4459nrqg50jo7q29e4h3sbf5uf4gcp4@4ax.com... > On Wed, 24 Jun 2009 15:45:37 +0100, "Fredxx" wrote: > >>What's wrong with an asynchronous memory[...] >>It works in simulation!! > > Nothing wrong with them, except that they don't exist > in real FPGAs. By contrast, dual-ported dual-clock > synchronous RAMs most certainly do :-) I thought you were trying to simulate and synthesise dual port block RAM, without using the normal block RAM primitives. In your first post you said "of how to do RAM inference from VHDL and Verilog code for all the common synthesis tools and FPGAs". The asynchronous memory is an array of flip-flops rather than a memory, but that's a mute point. It does both synthesise and simulate in Xilinx ISE tools. From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 16:31:10 +0100 Organization: A noiseless patient Spider Lines: 80 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX18dMkaK7CQYIn1YRYXYmOUyw9X5EIfe9DKapKdeVLtMQBwy87lKGSUKB8tpBDr2UiWMBoOZdFMhi8EbAwxcyVqQfpL08A7xogBx5jwsTgHaVhCz0bpbPpjGzdnIz7/QWqbjZvh63ICAxQ== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 15:33:47 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1946dmmU+8YBFDO0VODi/uho+4R4LAgJLI= Cancel-Lock: sha1:RBqtKcA0vLSXmjtJdPZNhWrAHkM= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1467 comp.arch.fpga:4372 rickman wrote: > On Jun 24, 10:45 am, "Fredxx" wrote: >> "Jonathan Bromley" wrote in message >> >> news:e76445hlo55p6dki0oi764adcblv5oloul@4ax.com... >> >> >> >>> On Wed, 24 Jun 2009 12:44:27 +0100, "Fredxx" wrote: >> >>>> I perhaps am making the (erroneous) assumption that two statements >>>> will be or'd together and the Z's will be overdriven by the >>>> signals. >> >>> That's more-or-less correct. Each process represents a driver >>> on any signal it writes. If multiple processes write to a signal, >>> then the actual signal value is determined by resolving the >>> various driven values. Of course, anything else overdrives Z. >> >>> The hard-to-solve problem: suppose process A writes a value >>> to a memory location at some time; clearly, you want that >>> value to remain in the location and not to be overwritten >>> to Z on the next clock, so you can't allow process A to change >>> its mind about that value. Some time later, suppose process B >>> writes to the same location. Now you have two non-Z drivers >>> on the same set of bits. How can process B tell process A >>> that it's time for its driver to lapse back to Z? Shared >>> variables, for all their ugliness, solve this problem >>> neatly (which is why my problem simply doesn't exist in >>> Verilog, where all variables are shared). >> >>>> To be honest, I think it isn't good practice to have signals >>>> driven by 2 clocks, and I'd probably use clock switching >>>> primitives instead so the memory would be written in one process >>>> with just one clock. >> >>> In normal logic I would 100% agree, but here I'm talking about >>> modeling and synthesizing the FPGAs' built-in RAM blocks, which >>> have the option of independent clocks on the two ports. So >>> it is important to write VHDL corresponding to that behavior. >>> You could mux the clocks onto a single port, but that would >>> be a totally different design. >> >> What's wrong with an asynchronous memory, where the appropriate >> clocks latch the control signals to create synchronous RAM. >> >> Then we can do something like: >> >> process (a0, we0, wd0, a1, we1, wd1) >> begin >> if we0 = '1' then -- write to port A >> mem(conv_integer(a0)) <= wd0; >> end if; >> if we1 = '1' then -- write to port A >> mem(conv_integer(a1)) <= wd1; >> end if; >> rd0 <= mem(conv_integer(a0)); >> rd1 <= mem(conv_integer(a1)); >> end process; >> >> It works in simulation!! > > I doubt that it will synthesize. Synthesis is largely a matter of > template matching. You can describe a behavior any way you want in > simulation. But if the synthesis tool does not recognize that form, > it won't synthesize to anything useful. Often memory that is not > recognized as a block ram is synthesized as distributed memory using > much of the FFs on a chip. Not only that, but it takes forever to > complete just to find out you don't have a workable design. > Perhaps I've been lucky with ISE tools, but I have found constructs like this to work. I was of the opinion that Johnathan wanted to create a VHDL block which could replace the normal dual port block RAMs normlly found in FPGAs. Therefore I don't see the problem in using std_logic_vector flipflops to create the memory. From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!weretis.net!feeder2.news.weretis.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Wed, 24 Jun 2009 08:55:52 -0700 Lines: 19 Message-ID: <7af0k8F1va8i1U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net NB6lcIoNJVDYVg9AoYeo7wHKXySMILhvjVyBlVtmzbgzv6S8/m Cancel-Lock: sha1:RAMt2bnkHU4Zw3JVuI1LELxpOZ8= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1468 Matthias Alles wrote: > File: test.vhd > Line: 70 > Branch Coverage for: > elsif clk = '1' and clk'event then > Branch if: True: 140036 False: 0 > > But in case of the falling edge the condition should be false, only the > clk'event will always be true, since clk is part of the sensitivity list. Coverage concerns the testbench test.vhd not the synthesis code. Sounds like modelsim is saying that that the testbench never tests the case of no reset and a falling edge clock. That is true for every testbench I have ever seen, and I might ignore this warning rather than cover it. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:14 2009 Path: eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!l28g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Wed, 24 Jun 2009 09:44:35 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <0c822326-37a2-44dd-8f7a-dc9a58744536@l28g2000vba.googlegroups.com> References: <7af0k8F1va8i1U1@mid.individual.net> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245861875 13752 127.0.0.1 (24 Jun 2009 16:44:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 16:44:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l28g2000vba.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1469 Code coverage on your RTL is what tells you to what extent you have under- (or over-) exercised the unit under test (the RTL), and is highly recommended, particularly in constrained-random testing. It also points out code that may not be used, but the resulting circuitry is not likely to be optiminzed away either. Code coverage of your testbench, assuming requirements are traceable to testbench code, can tell you when your testbench has executed all the requirements (at least those that are known/traceable). I suppose this boils down to black-box vs white-box vs grey-box verification, which is a whole 'nother issue on its own. We've seen this exact issue in modelsim, and it occurs because modelsim has an optimization where positive-edge-only processes are not even run on negative edges of the clock. IIRC, the optimisation can be disabled, with an accompanying increase in run-time, to get rid of the coverage issue. Or you can ignore it, but that often means having to massage the overal coverage metrics. I'm in a constant battle with management regarding code coverage metrics, and this is just one of many reasons why having requirements (or even goals) for N% code coverage is useless. Code coverage is an excellent tool to tell you, in general, how well your testbench is exercising the RTL and testbench code, but the percentage coverage score is marketing hype directed at managers who see it as a perfect score of when you are done simulating. Thus code coverage is neither necessary nor sufficient to tell you when you are done with verification. It is just a tool (one of many) that helps you to decide when enough is enough. Andy From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!feeder.news-service.com!transit4.hitnews.eu!xlned.com!feeder1.xlned.com!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!newsfeed2.telusplanet.net!newsfeed.telus.net!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!nlpi064.nbdc.sbc.com.POSTED!857c7983!not-for-mail From: Muzaffer Kal Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Message-ID: <4ul445tbv9klgrceumj15dd2jfcpjp4raq@4ax.com> References: X-Newsreader: Forte Free Agent 3.3/32.846 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 NNTP-Posting-Host: 71.141.126.135 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi064.nbdc.sbc.com 1245862029 ST000 71.141.126.135 (Wed, 24 Jun 2009 12:47:09 EDT) NNTP-Posting-Date: Wed, 24 Jun 2009 12:47:09 EDT Organization: at&t http://my.att.net/ X-UserInfo1: TSU[@I_A\S@IB\\Y\RHFO_TDFZ\@@FXLM@TDOCQDJ@_@FN\CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Wed, 24 Jun 2009 09:50:53 -0700 Xref: eternal-september.org comp.lang.vhdl:1470 comp.arch.fpga:4373 On Wed, 24 Jun 2009 16:27:30 +0100, "Fredxx" wrote: >The asynchronous memory is an array of flip-flops rather than a memory, but >that's a mute point. It does both synthesise and simulate in Xilinx ISE >tools. > Flip-flops need a clock to function. How do you write to them without a clock to implement asynchronous memory (which by definition doesn't have it?). You can use an array of latches as opposed to flip-flops but timing latches is quite difficult especially in an fpga context where tools are really not geared towards it. You maybe able to synthesize it in ISE and the original code simulates for sure but have you tried a back-annotated gate level simulation? It would be an interesting challenge to get it to work fully unless your read/write pulse widths and separations are extremely conservative. One last to remember is that there are a lot fewer slice registers (from which latches are made) than memory bits in an FPGA so you're quite limited in how much async memory of this type you can make. --- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!feeder.news-service.com!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!l5g2000vbp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 10:53:49 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245866029 24411 127.0.0.1 (24 Jun 2009 17:53:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 17:53:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l5g2000vbp.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1471 comp.arch.fpga:4375 On Jun 24, 6:15=A0am, Jonathan Bromley wrote: > In truth the "correct" solution would be to write the whole thing > as a single process with two clocks: > > =A0 process (clock0, clock1) > =A0 =A0 variable mem: t_mem; > =A0 begin > =A0 =A0 if rising_edge(clock0) then > =A0 =A0 =A0 if we0 =3D '1' then > =A0 =A0 =A0 =A0 mem(a0) :=3D wd0; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 =A0 if rising_edge(clock1) then > =A0 =A0 =A0 if we1 =3D '1' then > =A0 =A0 =A0 =A0 mem(a1) :=3D wd1; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 =A0 ... > > But I suspect synthesis tools would chuck that overboard > without a second thought. Current synthesis tools would probably have an issue with this, but there's no good reason for it. DDR synthesis (though not the same as independent clock, dual port memories) needs it anyway. Some synthesis tools support dual clock processes, just not writes to the same var/ sig on both clocks. The only time this example does not behave like a true dual clock/port ram is when two writes are attempted to the same address at exactly the same time, which is not even defined for the real HW. Good system design makes that case meaningless anyway. Andy From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!weretis.net!feeder2.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 24 Jun 2009 13:00:36 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 18:57:29 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Rufs/XQFFvxPoP0vvWjR7AhYXsfUjrhTItA3kmb15UTzp3wZHxIr+p2UAub3PRdF9Lx8GDdTdN9uFke!qdMCHN791wLbDt7Rm0dleVt/WPq2DTdgw3bHgemcH/sgQICrWqt7mboX/fwxpPdgRjNiEt0wTmE/!xR4LVmt7VED4YiJo X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1472 comp.arch.fpga:4376 On Wed, 24 Jun 2009 08:31:26 -0700 (PDT), Sandro wrote: >If you are curious please take a look to the vhdl VITAL >simulations sources... I know about the vendor-provided simulation models, which are fine pieces of work that do their job well. But they are completely irrelevant both to my original problem and to the issue I asked about. I'm trying to assemble a complete and accurate list of the _synthesizable_ templates for all common types of FPGA memory, and I have discovered a template that synthesizes to dual-clock RAM in two FPGA vendors' tools but is a complete nonsense for simulation. I want to know why this has happened, what we can do about it, and why the vendors haven't already been beaten to pulp over it by users. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 24 Jun 2009 13:04:15 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 19:01:09 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gvcgH0E6wUoqfvsJqzui5rmIyuZ57ilyllHuO7KAge6HCwSJ6WTBouJj4H/drP72byykh+fQnUtttPu!DNGICzmAKCzNbI7qv7dUb2Ha6h+L65jDGgVHxxKpxye9FYZb2wVqPcUhigQIMht+mfmqa6312u/f!171mJgZiZPDG2hdu X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1473 comp.arch.fpga:4377 On Wed, 24 Jun 2009 10:53:49 -0700 (PDT), Andy wrote: [of multi-clocked processes in VHDL] >Current synthesis tools would probably have an issue with this, but >there's no good reason for it. DDR synthesis (though not the same as >independent clock, dual port memories) needs it anyway. I completely agree. One of the side-effects of the survey I'm doing will probably be that I'll log requests for exactly this feature with all the synthesis vendors. I don't hold out much hope, though. Support welcomed ;-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!news.mb-net.net!open-news-network.org!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!news.glorb.com!news-xfer.nntp.sonic.net!news.astraweb.com!border5.newsrouter.astraweb.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!nlpi070.nbdc.sbc.com.POSTED!857c7983!not-for-mail From: Muzaffer Kal Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> X-Newsreader: Forte Free Agent 3.3/32.846 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 NNTP-Posting-Host: 71.141.126.135 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi070.nbdc.sbc.com 1245866932 ST000 71.141.126.135 (Wed, 24 Jun 2009 14:08:52 EDT) NNTP-Posting-Date: Wed, 24 Jun 2009 14:08:52 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[OIBTSEGRUQB_H]]RKB_UDAZZ\DPCPDLXUNNHLIWIWTEPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Wed, 24 Jun 2009 11:11:47 -0700 Xref: eternal-september.org comp.lang.vhdl:1474 comp.arch.fpga:4378 On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley wrote: >I'm trying to assemble a complete and accurate list >of the _synthesizable_ templates for all common types >of FPGA memory, and I have discovered a template >that synthesizes to dual-clock RAM in two FPGA >vendors' tools but is a complete nonsense for >simulation. I want to know why this has happened, >what we can do about it, and why the vendors haven't >already been beaten to pulp over it by users. Originally coming from ASIC side I find this incredible but it seems that majority of people doing FPGA design don't simulate. I was at an FPGA infomercial the other day about two new device families coming out from a vendor to stay nameless and only %20 or so people raised their hands when asked this question. This might explain how these templates survived as is for such a long time. --- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 12:05:39 -0700 Lines: 27 Message-ID: <7afbo3F1te5adU1@mid.individual.net> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net DSZkDNMz+/uLcz4BdTr/Cw1y7TFtLFmH5iT64V2q8b+m5WW7DN Cancel-Lock: sha1:LP+MkH1F+PcsJkQvXwcYrzVxRds= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> Xref: eternal-september.org comp.lang.vhdl:1475 comp.arch.fpga:4383 Jonathan Bromley wrote: > I'm trying to assemble a complete and accurate list > of the _synthesizable_ templates for all common types > of FPGA memory, and I have discovered a template > that synthesizes to dual-clock RAM in two FPGA > vendors' tools but is a complete nonsense for > simulation. I want to know why this has happened, > what we can do about it, and why the vendors haven't > already been beaten to pulp over it by users. This has happen because the majority of FPGA designers prefer to wire together blocks by others, and verify on the bench using trial and error synthesis. The silly dual clock RAM model is ignored not because it is silly, but because a vendor netlist is preferred to RTL to get at all the asynchronous black magic. What to do? I stick with single clock RAMs and arbitrate synchronously. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 20:43:39 +0100 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <4ul445tbv9klgrceumj15dd2jfcpjp4raq@4ax.com> X-Trace: news.eternal-september.org U2FsdGVkX1/GYE96wlSue2/NFJ8W/x/AI42A9z1wJJUPY19MfxOyfDlKS4ZHJCn2FaHUyeHfh59CLDUZ9WBNdSO3uZ+OxWVUV6UekZTIF8Tc5GhNFNSExYVu+6wsWdqjgwT50gDBJ6yd9iXng3bSPg== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Wed, 24 Jun 2009 19:49:51 +0000 (UTC) X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1+Iv5JTxvAXwl1dleWGTqlLW03BDmky+1Q= Cancel-Lock: sha1:A7tjfOJ6AI9ZEsUJnLvwkv0VDLY= X-Priority: 3 X-MSMail-Priority: Normal X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 Xref: eternal-september.org comp.lang.vhdl:1477 comp.arch.fpga:4387 "Muzaffer Kal" wrote in message news:4ul445tbv9klgrceumj15dd2jfcpjp4raq@4ax.com... > On Wed, 24 Jun 2009 16:27:30 +0100, "Fredxx" wrote: >>The asynchronous memory is an array of flip-flops rather than a memory, >>but >>that's a mute point. It does both synthesise and simulate in Xilinx ISE >>tools. >> > Flip-flops need a clock to function. How do you write to them without > a clock to implement asynchronous memory (which by definition doesn't > have it?). You can use an array of latches as opposed to flip-flops > but timing latches is quite difficult especially in an fpga context > where tools are really not geared towards it. You maybe able to > synthesize it in ISE and the original code simulates for sure but have > you tried a back-annotated gate level simulation? It would be an > interesting challenge to get it to work fully unless your read/write > pulse widths and separations are extremely conservative. > One last to remember is that there are a lot fewer slice registers > (from which latches are made) than memory bits in an FPGA so you're > quite limited in how much async memory of this type you can make. Different types of flip flops can be inferred by VHDL. Not all have to use the global clock, or even a clock as such. True - if it was my problem, I would look at the logic it creates, but at the moment I don't have time. From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!y34g2000prb.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 13:02:06 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <504f1ed4-df0a-4749-b2fa-f47efa8b7df2@y34g2000prb.googlegroups.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245873726 17331 127.0.0.1 (24 Jun 2009 20:02:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 24 Jun 2009 20:02:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y34g2000prb.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1478 comp.arch.fpga:4388 On Jun 24, 10:57=A0am, Jonathan Bromley wrote: > I'm trying to assemble a complete and accurate list > of the _synthesizable_ templates for all common types > of FPGA memory, and I have discovered a template > that synthesizes to dual-clock RAM in two FPGA > vendors' tools but is a complete nonsense for > simulation. =A0I want to know why this has happened, > what we can do about it, and why the vendors haven't > already been beaten to pulp over it by users. The vendors say, "Instantiate the component from the library," which neatly sidesteps the difficult work of actually enabling such inference. -a From newsfish@newsfish Wed Aug 19 13:25:15 2009 Path: eternal-september.org!feeder.news-service.com!de-l.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!news.glorb.com!news.acm.uiuc.edu!not-for-mail From: Matthew Hicks Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Wed, 24 Jun 2009 21:01:23 +0000 (UTC) Organization: Usenet @ UIUC - http://www.acm.uiuc.edu/news/ Lines: 38 Sender: mdhicks2@outside.world Message-ID: <6004390c24e0c8cbc2fc27d11e50@news.acm.uiuc.edu> References: NNTP-Posting-Host: 98.220.249.110 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news.acm.uiuc.edu 1245877282 14497 98.220.249.110 (24 Jun 2009 21:01:22 GMT) X-Complaints-To: news@acm.uiuc.edu NNTP-Posting-Date: Wed, 24 Jun 2009 21:01:22 +0000 (UTC) X-Newsreader: JetBrains Omea Reader 1098.1 Xref: eternal-september.org comp.lang.vhdl:1479 Add these cases to your set of exclusions and be done with it. ---Matthew Hicks > Hi! > > I'm currently performing code coverage with ModelSim on a design. > However I observe a problem regarding the branch coverage with clocked > processes: > > process(clk,rst) is > begin > if rst = '1' then > elsif clk'event and clk = '1' then > > end if; > end process; > The problem I have is that the elsif-branch for the clock is not > considered to be tested, so in the statistic the branch coverage will > never reach the 100%. The detail to this line is: > > File: test.vhd > Line: 70 > Branch Coverage for: > elsif clk = '1' and clk'event then > Branch if: True: 140036 False: 0 > But in case of the falling edge the condition should be false, only > the clk'event will always be true, since clk is part of the > sensitivity list. > > What am I missing?? > > Thanks in advance! > Matthias From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!i4g2000prm.googlegroups.com!not-for-mail From: Alex Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Wed, 24 Jun 2009 18:43:43 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> NNTP-Posting-Host: 71.37.219.245 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245894223 25307 127.0.0.1 (25 Jun 2009 01:43:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 01:43:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i4g2000prm.googlegroups.com; posting-host=71.37.219.245; posting-account=ctr1xQoAAACVG65HCG7wVkrUETtUwrgR User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1480 comp.arch.fpga:4397 On Jun 24, 10:57=A0am, Jonathan Bromley wrote: > On Wed, 24 Jun 2009 08:31:26 -0700 (PDT), Sandro wrote: > >If you are curious please take a look to the vhdl VITAL > >simulations sources... > > I know about the vendor-provided simulation models, > which are fine pieces of work that do their job well. > But they are completely irrelevant both to my original > problem and to the issue I asked about. =A0 > > I'm trying to assemble a complete and accurate list > of the _synthesizable_ templates for all common types > of FPGA memory, and I have discovered a template > that synthesizes to dual-clock RAM in two FPGA > vendors' tools but is a complete nonsense for > simulation. =A0I want to know why this has happened, > what we can do about it, and why the vendors haven't > already been beaten to pulp over it by users. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. The truth is that current FPGA Synthesis tools quite often do a poor job (not counting trivial cases here) in inference of FPGA vendors' macros. From the other hand FPGA vendors want users to instantiate their macros (and so to be locked into their devices) and make it very easy to configure and generate the code for instantiation using proprietary vendor tools. So majority of users prefers to instantiate the macros as a better alternative to make the Synthesis tools infer the necessary structure (and lose sometimes days on debugging different synthesis attributes, directives etc...) Just wanted to offer a possible explanation in answer to your question, Jonathan :^) Theoretically, independent FPGA synthesis tools vendors (Mentor, Synopsys) should be interested for users to create a vendor independent code. This way they'll have a much stronger case for multi- vendor tools... Alex Yourovski From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Thu, 25 Jun 2009 07:57:20 +0200 Organization: Universitaet Kaiserslautern Lines: 22 Message-ID: References: <7af0k8F1va8i1U1@mid.individual.net> NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245909491 16875 131.246.73.199 (25 Jun 2009 05:58:11 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Thu, 25 Jun 2009 05:58:11 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) In-Reply-To: <7af0k8F1va8i1U1@mid.individual.net> Xref: eternal-september.org comp.lang.vhdl:1481 Mike Treseler schrieb: > Matthias Alles wrote: > >> File: test.vhd >> Line: 70 >> Branch Coverage for: >> elsif clk = '1' and clk'event then >> Branch if: True: 140036 False: 0 >> >> But in case of the falling edge the condition should be false, only the >> clk'event will always be true, since clk is part of the sensitivity list. > > Coverage concerns the testbench test.vhd not the synthesis code. > Sounds like modelsim is saying that that the testbench > never tests the case of no reset and a falling edge clock. > That is true for every testbench I have ever seen, > and I might ignore this warning rather than cover it. Well the name test.vhd is maybe misleading. Actually I'm talking about synthesizable RTL code. Matthias From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Thu, 25 Jun 2009 08:05:00 +0200 Organization: Universitaet Kaiserslautern Lines: 13 Message-ID: References: <6004390c24e0c8cbc2fc27d11e50@news.acm.uiuc.edu> NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245909951 17589 131.246.73.199 (25 Jun 2009 06:05:51 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Thu, 25 Jun 2009 06:05:51 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) In-Reply-To: <6004390c24e0c8cbc2fc27d11e50@news.acm.uiuc.edu> Xref: eternal-september.org comp.lang.vhdl:1482 Matthew Hicks schrieb: > Add these cases to your set of exclusions and be done with it. That is what I thought about first. But the thing is that if I have hundred clocked processes in my design I have to exclude each single test for the rising edge by hand (giving the line number in the VHDL code), as far as I could see from the ModelSim manual. Furthermore, every time when I change something in a source file such that the line numbers change, I have to adjust the exclusion stuff. Isn't there a simpler solution for exclusion? Matthias From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!t-online.de!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Thu, 25 Jun 2009 08:08:24 +0200 Organization: Universitaet Kaiserslautern Lines: 18 Message-ID: References: <7af0k8F1va8i1U1@mid.individual.net> <0c822326-37a2-44dd-8f7a-dc9a58744536@l28g2000vba.googlegroups.com> NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245910155 17840 131.246.73.199 (25 Jun 2009 06:09:15 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Thu, 25 Jun 2009 06:09:15 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) In-Reply-To: <0c822326-37a2-44dd-8f7a-dc9a58744536@l28g2000vba.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1483 Hi Andy, > We've seen this exact issue in modelsim, and it occurs because > modelsim has an optimization where positive-edge-only processes are > not even run on negative edges of the clock. IIRC, the optimisation > can be disabled, with an accompanying increase in run-time, to get rid > of the coverage issue. Or you can ignore it, but that often means > having to massage the overal coverage metrics. I had a look into the ModelSim manual but couldn't find something about this kind of optimization. I tried to simulate with vsim -cover -novopt work.testbench but the problem is still there. Do you know how exactly this can be disabled? Matthias From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Followup-To: comp.lang.vhdl,comp.arch.fpga Date: Thu, 25 Jun 2009 11:03:25 +0100 Organization: TRW Conekt Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 2EULvUCNrl7GYE8Y1KQejQzlq9EFrcmsw5MPz6FdJR8o7/+hE= Cancel-Lock: sha1:asW2HirqcG+49JZAHL1Rs07/OEo= sha1:wYOVook9rFbqxvu4snYBAVSsS9c= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.3 (windows-nt) Xref: eternal-september.org comp.lang.vhdl:1484 comp.arch.fpga:4407 Jonathan Bromley writes: > I completely agree. One of the side-effects of the > survey I'm doing will probably be that I'll log requests > for exactly this feature with all the synthesis vendors. > I don't hold out much hope, though. Support welcomed ;-) You have mine! And thanks for sharing the results of your investigations with us all! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "Nial Stewart" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Thu, 25 Jun 2009 11:55:44 +0100 Lines: 15 Message-ID: <7ah3dlF1v1nhrU1@mid.individual.net> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> X-Trace: individual.net gmWCQoyjCqLwm7e7bQLJ8QDjMWkJCMVJFX62hrIMWmaNfU9P48 Cancel-Lock: sha1:FzqZd1lSdfR0zWHnh4U+fDwf3xQ= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 Xref: eternal-september.org comp.lang.vhdl:1485 comp.arch.fpga:4409 > Originally coming from ASIC side I find this incredible but it seems > that majority of people doing FPGA design don't simulate. I was at an > FPGA infomercial the other day about two new device families coming > out from a vendor to stay nameless and only %20 or so people raised > their hands when asked this question. This might explain how these > templates survived as is for such a long time. Do you mean don't simulate the P&R'd design, or not at all? Nial. From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!nlpi057.nbdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi147.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <6004390c24e0c8cbc2fc27d11e50@news.acm.uiuc.edu> Subject: Re: Code Coverage in ModelSim Lines: 32 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Response X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi147.ffdc.sbc.com 1245927901 ST000 99.184.242.197 (Thu, 25 Jun 2009 07:05:01 EDT) NNTP-Posting-Date: Thu, 25 Jun 2009 07:05:01 EDT Organization: at&t http://my.att.net/ X-UserInfo1: OP[EB[SE[RUABQTY]BCBNWX@RJ_XPDLMN@GZ_GYO^BTJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Thu, 25 Jun 2009 07:12:44 -0400 Xref: eternal-september.org comp.lang.vhdl:1486 "Matthias Alles" wrote in message news:h1v43v$h5l$1@news.uni-kl.de... > Matthew Hicks schrieb: >> Add these cases to your set of exclusions and be done with it. > > That is what I thought about first. But the thing is that if I have > hundred clocked processes in my design I have to exclude each single test > for the rising edge by hand (giving the line number in the VHDL code), as > far as I could see from the ModelSim manual. Furthermore, every time when > I change something in a source file such that the line numbers change, I > have to adjust the exclusion stuff. > > Isn't there a simpler solution for exclusion? > Use the -- coverage off/on pragmas process(clk,rst) is begin if rst = '1' then -- coverage off elsif clk'event and clk = '1' then -- coverage on end if; end process; KJ From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweaknews.nl!193.201.147.81.MISMATCH!border-1.ams.xsnews.nl!border-3.ams.xsnews.nl!feed.xsnews.nl!border-4.ams.xsnews.nl!69.16.177.242.MISMATCH!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: Code Coverage in ModelSim Lines: 43 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1245930601 86.16.123.60 (Thu, 25 Jun 2009 11:50:01 UTC) NNTP-Posting-Date: Thu, 25 Jun 2009 11:50:01 UTC Organization: virginmedia.com Date: Thu, 25 Jun 2009 12:49:53 +0100 Xref: eternal-september.org comp.lang.vhdl:1487 "Matthias Alles" wrote in message news:h1tg93$c2d$1@news.uni-kl.de... > Hi! > > I'm currently performing code coverage with ModelSim on a design. However I > observe a problem regarding the branch coverage with clocked processes: > > process(clk,rst) is > begin > if rst = '1' then > > elsif clk'event and clk = '1' then > > end if; > end process; > > The problem I have is that the elsif-branch for the clock is not considered to > be tested, so in the statistic the branch coverage will never reach the 100%. > The detail to this line is: > > File: test.vhd > Line: 70 > Branch Coverage for: > elsif clk = '1' and clk'event then > Branch if: True: 140036 False: 0 > > But in case of the falling edge the condition should be false, only the > clk'event will always be true, since clk is part of the sensitivity list. > > What am I missing?? Try vcom -coveropt=1, that should fix it, Hans www.ht-lab.com > > Thanks in advance! > Matthias From newsfish@newsfish Wed Aug 19 13:25:16 2009 Path: eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: Code Coverage in ModelSim Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1245930734 86.16.123.60 (Thu, 25 Jun 2009 11:52:14 UTC) NNTP-Posting-Date: Thu, 25 Jun 2009 11:52:14 UTC Organization: virginmedia.com Date: Thu, 25 Jun 2009 12:52:08 +0100 Xref: eternal-september.org comp.lang.vhdl:1488 >> >> What am I missing?? > > Try vcom -coveropt=1, that should fix it, lets try again, vcom -coveropt 1 Hans www.ht-lab.com > > Hans > www.ht-lab.com > > >> >> Thanks in advance! >> Matthias > > From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!j19g2000vbp.googlegroups.com!not-for-mail From: sleeman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Thu, 25 Jun 2009 05:09:41 -0700 (PDT) Organization: http://groups.google.com Lines: 105 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7ah3dlF1v1nhrU1@mid.individual.net> NNTP-Posting-Host: 70.50.188.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245931781 9971 127.0.0.1 (25 Jun 2009 12:09:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 12:09:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j19g2000vbp.googlegroups.com; posting-host=70.50.188.93; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1489 comp.arch.fpga:4412 On Jun 25, 6:55=A0am, "Nial Stewart" wrote: > > Originally coming from ASIC side I find this incredible but it seems > > that majority of people doing FPGA design don't simulate. I was at an > > FPGA infomercial the other day about two new device families coming > > out from a vendor to stay nameless and only %20 or so people raised > > their hands when asked this question. This might explain how these > > templates survived as is for such a long time. > > Do you mean don't simulate the P&R'd design, or not at all? > > Nial. This thread has brought up several very interesting themes. I'd like to add my two cents to each. 1) Synthesis templates for RAMS. I think what Jonathan is doing is a great idea. I'd love to see a better definition of what cross-device code patterns are safe to use and supported by which tools. From experience, I can say that I've done it right for a few key designs, and managed to leverage off of that by wrapping this inference in an entity, giving me a device-independent (more-or-less) codebase but still requiring structural coding around the RAM. It's not ideal by a long shot. But by enforcing good version control discipline through the organization and introducing a mindset that says "don't fiddle around with a perfectly good library module, use it as-is or not at all", we have managed to reduce the number of times designers sit there, asking the same questions: "I only changed one line of code; why did it start making distributed RAM? What were those attributes again? When I don't use the read port how do I stop the synthesizer from complaining?" and so on and so on. 2) Clocks versus asynchronous logic. My view of this is that clocks are both an obvious physical thing (as anyone who flies a scope for living well knows) as well as an abstraction. This abstraction is what constitutes the "contract", or point of demarcation between high- level circuit digital designer, and the guy who actually codes the gate-level RAM and control logic. The job of the low-level transistor guy is to provide a circuit that acts as if the clock abstraction is a true representation of what actually happens inside. He may use flops, latches, vernier timing thingies, or whatever the heck he needs. But he *must* obey the clock-concept contract. The job of the high-level (FPGA application developer) is to make use of the clock concept abstraction in order to make his design synchronous, which implies robustness, maintainability, and all the other virtues that regular posters here know so well. 3) People who don't do simulation? Definitely. I've help manage the change in an organization growing from a couple of FPGA guys to a fairly well-oiled FPGA talent pool with established version control, substantial as-is module re-use, and an ingrained mindset that a modules doesn't get released without a scripted, regressionable testbench. They're two points at opposite ends of a continuum of process, but I see a lot of real work in industry done at both ends. The "garage shop" FPGA approach typically has some guys who learned VHDL in school, then got thrown into the deep end alone, or who "came up through the ranks" from CPLDs and board design. No VC, no software techniques, no libraries, packages, functions or elegant code in the source. Hack job, in short. Two of these guys working on the same project may often be running different tool versions, and not even be able to load the design as-is from the other guy's sources, without a lot of manual GUI fiddling to reset paths, manually link in the right libraries, and so on. There's little chance of even building the same design twice in a row. These are the guys who throw their bitfile onto the board, and if it doesn't work, start writing some testbenches (aww, do I *have* to do that... what a pain). They don't want to simulate because its too hard/too long to sim the whole chip, and because there's poor structure and/or modularity in their own code to begin with, so it's also too hard to isolate a portion and make a simple test for it, too. The "pro" is at the other end of the continuum. Most of the regular posters here try to answer the "garage guys" with answers that will point them in the direction of becoming a "pro". It's a lot more work, but there's a lot of benefit to being able to release a chip that you know that anyone on your team can build again, bit/UCF/source- accurately, when you're on vacation. Of course, some "pros" work in garage shops. But the Big Tool (Big Two?) vendors tend to cater most of their tools to the garage shop guys. Everything can be set by clicking on a GUI button. Everything about a project is stored in unreadable binary files. They try to force you into their half-assed version control scheme, if they offer one at all. How are you ever going to share designs or document them for the future that way? And all of the "sex appeal" about the new devices is put into the GUI, the new buttons that you can click on, and the new auto-wizards (that don't usually have a mode to generate output from anything other than unreliable, unrepeatable user mouse clicks). ( I tend to think of this emphasis on sexy GUI tools leading then to bad project practices as being akin to drug dealers pushing crack in the schoolyards, but that would get me in trouble with my local FAEs so I'll refrain :-) Don't get me wrong... I had a lot of fun as a garage guy myself. I built some pretty damn fine hardware "back in the day" before I even had the option of simulating my code. But I agree, there are still a lot of guys who view testbenches and simulation as something painful and only to be done if really necessary. In truth, it's like pretty much everything else in life: you get out more when you put in more work. OK, I'm done ranting now :-) - Kenn From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Thu, 25 Jun 2009 14:15:50 +0200 Organization: Universitaet Kaiserslautern Lines: 37 Message-ID: References: NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245932204 15159 131.246.73.199 (25 Jun 2009 12:16:44 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Thu, 25 Jun 2009 12:16:44 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1490 Close... ;-) CoverOpt is a parameter in modelsim.ini and cannot be overwritten by vcom. But setting this parameter in the modelsim.ini to 1 and then start the simulation with vsim -cover -novopt dut works! Thanks Hans! Matthias HT-Lab schrieb: >>> What am I missing?? >> Try vcom -coveropt=1, that should fix it, > > lets try again, > > vcom -coveropt 1 > > Hans > www.ht-lab.com > > >> Hans >> www.ht-lab.com >> >> >>> Thanks in advance! >>> Matthias >> > > From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.erje.net!lightspeed.eweka.nl!81.171.88.16.MISMATCH!eweka.nl!hq-usenetpeers.eweka.nl!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe08.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: Code Coverage in ModelSim Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe08.ams2 1245934898 86.16.123.60 (Thu, 25 Jun 2009 13:01:38 UTC) NNTP-Posting-Date: Thu, 25 Jun 2009 13:01:38 UTC Organization: virginmedia.com Date: Thu, 25 Jun 2009 14:01:28 +0100 Xref: eternal-september.org comp.lang.vhdl:1491 "Matthias Alles" wrote in message news:h1vprc$epn$1@news.uni-kl.de... > Close... ;-) > > CoverOpt is a parameter in modelsim.ini and cannot be overwritten by vcom. But > setting this parameter in the modelsim.ini to 1 and then start the simulation > with > Seems to work fine in 6.5b, vcom -help # Model Technology ModelSim PE vcom 6.5b Compiler 2009.05 May 21 2009 # Usage: vcom [options] files # Options: # -coveropt Specify a digit for code coverage optimization level: 1 through 4. Regards, Hans. www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.velia.net!news.tu-darmstadt.de!news.belwue.de!news.uni-kl.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Thu, 25 Jun 2009 15:43:35 +0200 Organization: Universitaet Kaiserslautern Lines: 5 Message-ID: References: NNTP-Posting-Host: zmk199.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-kl.de 1245937469 21919 131.246.73.199 (25 Jun 2009 13:44:29 GMT) X-Complaints-To: usenet@news.uni-kl.de NNTP-Posting-Date: Thu, 25 Jun 2009 13:44:29 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (X11/20090409) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1492 > Seems to work fine in 6.5b, Ah, OK. I am using 6.3g at the moment. It's not supported for this version. Matthias From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!news.tornevall.net!aioe.org!gegeweb.org!news.glorb.com!postnews.google.com!n30g2000vba.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Thu, 25 Jun 2009 07:33:06 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> NNTP-Posting-Host: 66.82.9.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245940389 18451 127.0.0.1 (25 Jun 2009 14:33:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 14:33:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n30g2000vba.googlegroups.com; posting-host=66.82.9.74; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1493 comp.arch.fpga:4419 On Jun 24, 2:11=A0pm, Muzaffer Kal wrote: > On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley > > wrote: > >I'm trying to assemble a complete and accurate list > >of the _synthesizable_ templates for all common types > >of FPGA memory, and I have discovered a template > >that synthesizes to dual-clock RAM in two FPGA > >vendors' tools but is a complete nonsense for > >simulation. =A0I want to know why this has happened, > >what we can do about it, and why the vendors haven't > >already been beaten to pulp over it by users. > > Originally coming from ASIC side I find this incredible but it seems > that majority of people doing FPGA design don't simulate. I was at an > FPGA infomercial the other day about two new device families coming > out from a vendor to stay nameless and only %20 or so people raised > their hands when asked this question. I missed something. What question exactly? Rick From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.velia.net!news.tu-darmstadt.de!news.belwue.de!rz.uni-karlsruhe.de!feed.news.schlund.de!schlund.de!news.online.de!not-for-mail From: "Dr. Thomas Ansorg" Newsgroups: comp.lang.vhdl Subject: conversion variable to std_logic Date: Thu, 25 Jun 2009 17:21:52 +0200 Organization: 1&1 Internet AG Lines: 7 Message-ID: NNTP-Posting-Host: brln-4db93893.pool.einsundeins.de Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Trace: online.de 1245943313 6795 77.185.56.147 (25 Jun 2009 15:21:53 GMT) X-Complaints-To: abuse@einsundeins.com NNTP-Posting-Date: Thu, 25 Jun 2009 15:21:53 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 14.0.8064.206 X-MimeOLE: Produced By Microsoft MimeOLE V14.0.8064.206 Xref: eternal-september.org comp.lang.vhdl:1494 Hello all I need to convert a variable to a std_logic or std_logic_vector for monitoring in the simulation. The variable is a natural range 0 to 39. Tom From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!feeder06.uucp-net.de!news.uucp.at!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!dc3peer1.nntp.savvis.net!peer.nntp.savvis.net!nlpi057.nbdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi146.ffdc.sbc.com.POSTED!857c7983!not-for-mail From: Muzaffer Kal Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Organization: DSPIA INC. http://www.dspia.com Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> X-Newsreader: Forte Agent 5.00/32.1171 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 33 NNTP-Posting-Host: 71.141.126.135 X-Complaints-To: abuse@prodigy.net X-Trace: flpi146.ffdc.sbc.com 1245944196 ST000 71.141.126.135 (Thu, 25 Jun 2009 11:36:36 EDT) NNTP-Posting-Date: Thu, 25 Jun 2009 11:36:36 EDT X-UserInfo1: O@Z[S\OG[JVWCFD[LZKJOPHAWB\^PBQLGPQRJRQIMASJETAANVW[AKWZE\]^XQWIGNE_[EBL@^_\^JOCQ^RSNVLGTFTKHTXHHP[NB\_C@\SD@EP_[KCXX__AGDDEKGFNB\ZOKLRNCY_CGG[RHT_UN@C_BSY\G__IJIX_PLSA[CCFAULEY\FL\VLGANTQQ]FN Date: Thu, 25 Jun 2009 08:44:33 -0700 Xref: eternal-september.org comp.lang.vhdl:1495 comp.arch.fpga:4423 On Thu, 25 Jun 2009 07:33:06 -0700 (PDT), rickman wrote: >On Jun 24, 2:11 pm, Muzaffer Kal wrote: >> On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley >> >> wrote: >> >I'm trying to assemble a complete and accurate list >> >of the _synthesizable_ templates for all common types >> >of FPGA memory, and I have discovered a template >> >that synthesizes to dual-clock RAM in two FPGA >> >vendors' tools but is a complete nonsense for >> >simulation.  I want to know why this has happened, >> >what we can do about it, and why the vendors haven't >> >already been beaten to pulp over it by users. >> >> Originally coming from ASIC side I find this incredible but it seems >> that majority of people doing FPGA design don't simulate. I was at an >> FPGA infomercial the other day about two new device families coming >> out from a vendor to stay nameless and only %20 or so people raised >> their hands when asked this question. > >I missed something. What question exactly? Whether they simulate their designs, (before downloading & testing on the board). - Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.news-service.com!de-l.enfer-du-nord.net!gegeweb.org!news.glorb.com!postnews.google.com!o36g2000vbi.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: conversion variable to std_logic Date: Thu, 25 Jun 2009 10:29:49 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <6fbb548e-a626-4d76-8286-df9b50fc8ff1@o36g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245950989 7487 127.0.0.1 (25 Jun 2009 17:29:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 17:29:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o36g2000vbi.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1496 On Jun 25, 10:21=A0am, "Dr. Thomas Ansorg" wrote: > Hello all > I need to convert a variable to a std_logic or std_logic_vector for > monitoring in the simulation. The variable is a natural range 0 to 39. > > Tom use ieee.numeric_std.all; ... sig <=3D std_logic_vector(to_unsigned(var, sig'length)); However, signals can be integer/natural types too, or numeric_std.signed/unsigned. On device level ports, post-synthesis/P&R gate level netlists will use SL/SLV datatypes on those ports no matter what your RTL used (or you can build a type conversion wrapper for the device when/if the gate level netlist is needed for simulation). For internal signals & ports, use whatever makes the most sense. Andy From newsfish@newsfish Wed Aug 19 13:25:17 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!v2g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Thu, 25 Jun 2009 11:11:59 -0700 (PDT) Organization: http://groups.google.com Lines: 72 Message-ID: <61384dc0-3939-4653-bda9-94248e01d737@v2g2000vbb.googlegroups.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> NNTP-Posting-Host: 173.72.224.212 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245953519 30543 127.0.0.1 (25 Jun 2009 18:11:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 18:11:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v2g2000vbb.googlegroups.com; posting-host=173.72.224.212; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1497 comp.arch.fpga:4431 On Jun 25, 11:44=A0am, Muzaffer Kal wrote: > On Thu, 25 Jun 2009 07:33:06 -0700 (PDT), rickman > wrote: > > > > >On Jun 24, 2:11=A0pm, Muzaffer Kal wrote: > >> On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley > > >> wrote: > >> >I'm trying to assemble a complete and accurate list > >> >of the _synthesizable_ templates for all common types > >> >of FPGA memory, and I have discovered a template > >> >that synthesizes to dual-clock RAM in two FPGA > >> >vendors' tools but is a complete nonsense for > >> >simulation. =A0I want to know why this has happened, > >> >what we can do about it, and why the vendors haven't > >> >already been beaten to pulp over it by users. > > >> Originally coming from ASIC side I find this incredible but it seems > >> that majority of people doing FPGA design don't simulate. I was at an > >> FPGA infomercial the other day about two new device families coming > >> out from a vendor to stay nameless and only %20 or so people raised > >> their hands when asked this question. > > >I missed something. =A0What question exactly? > > Whether they simulate their designs, (before downloading & testing on > the board). Oh, I see. The last place I worked was a pretty good sized defense contractor making push to talk radios. They actually had the FPGA group under the software department because they felt it has more in common (such as using version control on the source files). I was in the hardware group and so not allowed to work on anything in the FPGA, including code to test my hardware. One of the other "hardware" engineers gave a "training" lecture to the entire hardware department (most of who were RF designers) about FPGA design. His method of doing timing analysis was to run a simulation!!! I had to stop him right there are point out that was what static timing analysis was for. He said that was not needed, since he could do a post route simulation. How insane is that!!!!!???? The other side of the coin was that they had a newbie working the FPGA code which was a collection of a couple of UARTs, I2C and a custom serial interface. Instead of simulating (or maybe just not a very good simulation) they were relying on the Xilinx logic analyzer tool. I can't think of a more painful way of doing the initial debug. I was asked to help them get the FPGA to load a bit file the first time and they didn't want to listen much to me. They had five (yes FIVE!!!) engineers working on it including a very senior engineer and a first level manager. No one could seem to figure out what was wrong. I had to wedge my way into the fray and started showing them the few simple steps you have to take to get it going. I kept pointing out that you need to give a few extra clocks at the end of downloading the file to get the part out of configuration mode and they kept telling me that was already tried. But the symptoms all pointed to this as the problem. So I had to beat on it over and over again until finally someone realized that they had tried adding strobes up to 64k as a magic bullet and when that didn't make it work (they had more than one problem) it was removed entirely! So they finally listened to me for a moment and the devices loaded... FIVE engineers couldn't figure that out!!! So we have engineers who don't believe it is productive to run simulation, engineers who believe they don't need to use static timing analysis and engineers who can't debug their way out of a paper bag!!! Are engineers the stupidest people in the world or is it just defense contractors? Rick From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 25 Jun 2009 13:56:19 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Thu, 25 Jun 2009 19:53:11 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <9bh7459dgvvpg89ar3to5k1k9ngogigoe7@4ax.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <61384dc0-3939-4653-bda9-94248e01d737@v2g2000vbb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 41 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-DAm/PC05hOh9ipzPua4red/puhgb6v12xbjfUj20mxyfNqF1K5fCgXBA6Q3rUnAIjclvtrDQX9maYsJ!d8JjY4HQSjKsQc+V2QL3JDpyS4u6CnIYQH7dqHdBafn5RTXOIHragU7DJMfTo6foD3T56gz0Hq/P!ip2n7bQfcagjemvZ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1498 comp.arch.fpga:4435 On Thu, 25 Jun 2009 11:11:59 -0700 (PDT), rickman wrote: >Are engineers the stupidest people in the world No, I don't think so. I meet loads of engineers in my training work, and it is rare indeed to find a stupid one. Some are quite extraordinarily smart. However, engineers do very complicated, occasionally very difficult, and certainly very arcane things. I reckon they get used to the idea that no-one they meet is likely to be able to help them much. So they get very narrowly focused on the (perceived) task at hand, and lose the ability to look outside their narrow concerns. (I'm sure I fall into that trap frequently myself.) That narrowness can easily come across as arrogance and/or reluctance to accept advice. Getting software folk and digital designers talking to each other would be a big step in the right direction. Sometimes that works well, but certain project management styles (as in Rick's story) go a long way towards preventing it. Re-skilling, as often as you get the chance, is a pretty good antidote to belief that you know it all. Career circumstances don't usually make that easy to do, sadly. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!j20g2000vbp.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: pre-initialized dpram functional simulation Date: Thu, 25 Jun 2009 13:47:30 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> NNTP-Posting-Host: 78.174.139.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245962850 29785 127.0.0.1 (25 Jun 2009 20:47:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 20:47:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j20g2000vbp.googlegroups.com; posting-host=78.174.139.225; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; tr; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1501 I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C I am generating a dpram_32k using Core Generator. All I can see is 0s (zero) at the output. How can I see pre-entered initial values in the functional simulation? serkan From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Thu, 25 Jun 2009 14:31:39 -0700 Lines: 11 Message-ID: <7ai8lrF1vh0vhU1@mid.individual.net> References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ZvzbqGySlapf9YaQh5dwpAwCgQYva1HPjCsIPvUB2d0V0p2nHq Cancel-Lock: sha1:/5xIKwzHFF/glRaDAWQ8BW+pkYA= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1502 Serkan wrote: > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > I am generating a dpram_32k using Core Generator. > All I can see is 0s (zero) at the output. > How can I see pre-entered initial values in the functional > simulation? I would have the testbench write to the ram and read it back. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!f38g2000pra.googlegroups.com!not-for-mail From: Hemang Newsgroups: comp.lang.vhdl Subject: assigning different elements of array Date: Thu, 25 Jun 2009 15:02:45 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1245967367 28395 127.0.0.1 (25 Jun 2009 22:02:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 22:02:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f38g2000pra.googlegroups.com; posting-host=149.199.62.254; posting-account=DYba0wkAAACK0YptECaLZuvcP9W3TAQK User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1503 Hi, I have an small test case below.. This code when simulated with modelsim v6.4b or d (haven't tried other simulators) give me U on all the data_delay array elements and also on the dout port. If I move the data_delay(0) assignment to be within the same process (as shown in the commented code in the architecture), it starts to work.. I was wondering if VHDL LRM stipulates ALL elements of an array to be assigned within the same "scope", or is this a bug in modelsim? -------- Code begins ------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dut is port ( data : in std_logic_vector(15 downto 0) := X"0030"; dout : out std_logic_vector(15 downto 0) ); end dut; architecture behav of dut is type array_data_term is array (0 to 7) of std_logic_vector(15 downto 0); signal data_delay : array_data_term; signal clk : std_logic; constant C_CLK_PERIOD : time := 5 ns; begin clk_gen: process begin clk <= '0'; wait for C_CLK_PERIOD/2; clk <= '1'; wait for (C_CLK_PERIOD - C_CLK_PERIOD/2); end process clk_gen; data_delay(0) <= data; process(clk) begin if clk'event and clk='1' then for i in 1 to 7 loop data_delay(i) <= data_delay(i-1); end loop; end if; end process; dout <= data_delay(7); -- process(clk,data) -- begin -- data_delay(0) <= data; -- -- if clk'event and clk='1' then -- for i in 1 to 7 loop -- data_delay(i) <= data_delay(i-1); -- end loop; -- end if; -- end process; end behav; ---------- Code ends ---------- I have run vsim with and without the -novopt option as well. and also tried vcom with -O0 option too. Thanks Hemang From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: assigning different elements of array Date: Thu, 25 Jun 2009 15:54:03 -0700 Lines: 15 Message-ID: <7aidgcF1vaf20U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net RPR3oPHoIB/s9qO8B/pawgmUkRwFX2T0F1vDGqrC1iHGBcvHes Cancel-Lock: sha1:X7Fy2rTxa6qYRo2JC5ZN9maXGHg= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1504 Hemang wrote: > I have an small test case below.. This code when simulated with > modelsim v6.4b or d (haven't tried other simulators) give me U on all > the data_delay array elements and also on the dout port. If I move the > data_delay(0) assignment to be within the same process (as shown in > the commented code in the architecture), it starts to work.. That's right. Except for a tri-state node, a signal can only be driven by one process. Otherwise I am shorting two outputs together. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!news.albasani.net!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!x1g2000prh.googlegroups.com!not-for-mail From: Hemang Newsgroups: comp.lang.vhdl Subject: Re: assigning different elements of array Date: Thu, 25 Jun 2009 16:15:40 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <7aidgcF1vaf20U1@mid.individual.net> NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245971740 27388 127.0.0.1 (25 Jun 2009 23:15:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 25 Jun 2009 23:15:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x1g2000prh.googlegroups.com; posting-host=149.199.62.254; posting-account=DYba0wkAAACK0YptECaLZuvcP9W3TAQK User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1505 On Jun 25, 3:54=A0pm, Mike Treseler wrote: > Hemang wrote: > > I have an small test case below.. This code when simulated with > > modelsim v6.4b or d (haven't tried other simulators) give me U on all > > the data_delay array elements and also on the dout port. If I move the > > data_delay(0) assignment to be within the same process (as shown in > > the commented code in the architecture), it starts to work.. > > That's right. > Except for a tri-state node, > a signal can only be driven by one process. > > Otherwise I am shorting two outputs together. > > =A0 =A0 -- Mike Treseler Thanks Mike.. I am thinking that this is a little too much of a constrain on interpreting use model of "signals" which are aggregates of "bits" and "vectors".. From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: assigning different elements of array Date: Thu, 25 Jun 2009 20:41:20 -0700 Lines: 16 Message-ID: <4A444360.1020200@gmail.com> References: <7aidgcF1vaf20U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net iK8fWstcRO45iK+gGpHiNwCVavE+TiTK8xRsqMbjLSfZ8GSmOq Cancel-Lock: sha1:MiQ7xqR/SYC6XmdKOGoNLc/3kPU= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1506 Hemang wrote: > Thanks Mike.. I am thinking that this is a little too much of a > constrain on interpreting use model of "signals" which are aggregates > of "bits" and "vectors".. Signals, variables and constants are vhdl "objects" -- containers for values. Bits and vectors can be of any object. But I think we agree that signals are unnecessarily complicated for logic description. That's why I use variables and single process entities. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:18 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Thu, 25 Jun 2009 22:35:53 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1245994553 18447 127.0.0.1 (26 Jun 2009 05:35:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 05:35:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1507 On Jun 26, 12:31=A0am, Mike Treseler wrote: > Serkan wrote: > > > =A0 I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > > =A0 I am generating a dpram_32k using Core Generator. > > =A0 All I can see is 0s (zero) at the output. > > =A0 How can I see pre-entered initial values in the functional > > simulation? > > I would have the testbench write to the ram and read it back. > > =A0 =A0 =A0 -- Mike Treseler It takes two much time to simulate using that method. Is not there any way to do it without the testbench writing the values? From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!y6g2000prf.googlegroups.com!not-for-mail From: Amit Newsgroups: comp.lang.vhdl Subject: VHDL and Spartan 3E Date: Fri, 26 Jun 2009 00:18:57 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <236ef17d-f983-4db4-b5a1-9af39bb3b404@y6g2000prf.googlegroups.com> NNTP-Posting-Host: 75.142.50.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246000737 6404 127.0.0.1 (26 Jun 2009 07:18:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 07:18:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y6g2000prf.googlegroups.com; posting-host=75.142.50.253; posting-account=mAJBZAoAAAADkVIbl_HAX1n55aYMpDgZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1508 Hello group, Does anybody know any resource that I can use for Spartan 3E I recently have bought? I need to use some basic codes and run them using the board. I've planned to use VHDL. Thanks, Amit From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!f16g2000vbf.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Fri, 26 Jun 2009 00:25:00 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246001101 7493 127.0.0.1 (26 Jun 2009 07:25:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 07:25:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f16g2000vbf.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1509 On 26 June, 06:35, Serkan wrote: > On Jun 26, 12:31=A0am, Mike Treseler wrote: > > > Serkan wrote: > > > > =A0 I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > > > =A0 I am generating a dpram_32k using Core Generator. > > > =A0 All I can see is 0s (zero) at the output. > > > =A0 How can I see pre-entered initial values in the functional > > > simulation? > > > I would have the testbench write to the ram and read it back. > > > =A0 =A0 =A0 -- Mike Treseler > > =A0It takes two much time to simulate using that method. > =A0Is not there any way to do it without the testbench writing the > values? Welcome to the world of VHDL simulation. You could just write an initialisation function to read the values from a text file. From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe05.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: assigning different elements of array Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe05.ams2 1246001241 86.16.123.60 (Fri, 26 Jun 2009 07:27:21 UTC) NNTP-Posting-Date: Fri, 26 Jun 2009 07:27:21 UTC Organization: virginmedia.com Date: Fri, 26 Jun 2009 08:27:13 +0100 Xref: eternal-september.org comp.lang.vhdl:1510 "Hemang" wrote in message news:c1b803d9-7531-401c-8895-d0985fc9217a@f38g2000pra.googlegroups.com... > Hi, > > I have an small test case below.. This code when simulated with > modelsim v6.4b or d (haven't tried other simulators) give me U on all > the data_delay array elements and also on the dout port. If I move the > data_delay(0) assignment to be within the same process (as shown in > the commented code in the architecture), it starts to work.. > > I was wondering if VHDL LRM stipulates ALL elements of an array to be > assigned within the same "scope", or is this a bug in modelsim? > It is called the longest static prefix, have a look at this question: http://www.ht-lab.com/question.jpg The answer is not A....... Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!s6g2000vbp.googlegroups.com!not-for-mail From: "Niv (KP)" Newsgroups: comp.lang.vhdl Subject: BCH(256,16,113) code Date: Fri, 26 Jun 2009 01:18:45 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com> NNTP-Posting-Host: 195.59.43.240 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246004325 6972 127.0.0.1 (26 Jun 2009 08:18:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 08:18:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s6g2000vbp.googlegroups.com; posting-host=195.59.43.240; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1511 I'm looking at a paper owhich talks about BCH(256,16,113) code. I think it is some form of CRC, but acn't find any details on how to implement in VHDL. If it is just a CRC variant, I'd like to know what the appropriate taps are. Anyone done this already? Regards, Kev P. From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!j12g2000vbl.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Fri, 26 Jun 2009 01:55:37 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246006537 24856 127.0.0.1 (26 Jun 2009 08:55:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 08:55:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j12g2000vbl.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1512 On 26 Haziran, 10:25, Tricky wrote: > On 26 June, 06:35, Serkan wrote: > > > > > On Jun 26, 12:31=A0am, Mike Treseler wrote: > > > > Serkan wrote: > > > > > =A0 I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > > > > =A0 I am generating a dpram_32k using Core Generator. > > > > =A0 All I can see is 0s (zero) at the output. > > > > =A0 How can I see pre-entered initial values in the functional > > > > simulation? > > > > I would have the testbench write to the ram and read it back. > > > > =A0 =A0 =A0 -- Mike Treseler > > > =A0It takes two much time to simulate using that method. > > =A0Is not there any way to do it without the testbench writing the > > values? > > Welcome to the world of VHDL simulation. > > You could just write an initialisation function to read the values > from a text file. any guide or link?. From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.erje.net!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf02.ams.highwinds-media.com!newsfe23.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com> Subject: Re: BCH(256,16,113) code Lines: 23 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe23.ams2 1246007781 86.16.123.60 (Fri, 26 Jun 2009 09:16:21 UTC) NNTP-Posting-Date: Fri, 26 Jun 2009 09:16:21 UTC Organization: virginmedia.com Date: Fri, 26 Jun 2009 10:16:13 +0100 Xref: eternal-september.org comp.lang.vhdl:1513 "Niv (KP)" wrote in message news:5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com... > I'm looking at a paper owhich talks about BCH(256,16,113) code. I > think it is some form of CRC, but acn't find any details on how to > implement in VHDL. If it is just a CRC variant, I'd like to know what > the appropriate taps are. > > Anyone done this already? > > Regards, Kev P. It is far more complex than your ordinary CRC, http://en.wikipedia.org/wiki/BCH_code Galois Fields mathematics is a good place to start :-) Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe23.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> Subject: Re: pre-initialized dpram functional simulation Lines: 42 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe23.ams2 1246008088 86.16.123.60 (Fri, 26 Jun 2009 09:21:28 UTC) NNTP-Posting-Date: Fri, 26 Jun 2009 09:21:28 UTC Organization: virginmedia.com Date: Fri, 26 Jun 2009 10:21:24 +0100 Xref: eternal-september.org comp.lang.vhdl:1514 "Serkan" wrote in message news:d0ae7137-f79b-4d1e-b12a-7049a1bf7548@j12g2000vbl.googlegroups.com... On 26 Haziran, 10:25, Tricky wrote: > On 26 June, 06:35, Serkan wrote: > > > > > On Jun 26, 12:31 am, Mike Treseler wrote: > > > > Serkan wrote: > > > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > > > > I am generating a dpram_32k using Core Generator. > > > > All I can see is 0s (zero) at the output. > > > > How can I see pre-entered initial values in the functional > > > > simulation? > > > > I would have the testbench write to the ram and read it back. > > > > -- Mike Treseler > > > It takes two much time to simulate using that method. > > Is not there any way to do it without the testbench writing the > > values? > > Welcome to the world of VHDL simulation. > > You could just write an initialisation function to read the values > from a text file. > > >any guide or link?. Can't you pre-load it with an MIF file? Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!g20g2000vba.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Fri, 26 Jun 2009 02:55:48 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246010148 26449 127.0.0.1 (26 Jun 2009 09:55:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 09:55:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000vba.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1515 On 26 Haziran, 12:21, "HT-Lab" wrote: > "Serkan" wrote in message > > news:d0ae7137-f79b-4d1e-b12a-7049a1bf7548@j12g2000vbl.googlegroups.com... > On 26 Haziran, 10:25, Tricky wrote: > > > > > On 26 June, 06:35, Serkan wrote: > > > > On Jun 26, 12:31 am, Mike Treseler wrote: > > > > > Serkan wrote: > > > > > > I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C > > > > > I am generating a dpram_32k using Core Generator. > > > > > All I can see is 0s (zero) at the output. > > > > > How can I see pre-entered initial values in the functional > > > > > simulation? > > > > > I would have the testbench write to the ram and read it back. > > > > > -- Mike Treseler > > > > It takes two much time to simulate using that method. > > > Is not there any way to do it without the testbench writing the > > > values? > > > Welcome to the world of VHDL simulation. > > > You could just write an initialisation function to read the values > > from a text file. > > >any guide or link?. > > Can't you pre-load it with an MIF file? > > Hanswww.ht-lab.com I tried using a mif file but all I can see is zeros at the output when I do functional simulation. But if I do timing simulation then I can see correct data values. Very strange I must admit. From newsfish@newsfish Wed Aug 19 13:25:19 2009 Path: eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe17.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> Subject: Re: pre-initialized dpram functional simulation Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe17.ams2 1246015118 86.16.123.60 (Fri, 26 Jun 2009 11:18:38 UTC) NNTP-Posting-Date: Fri, 26 Jun 2009 11:18:38 UTC Organization: virginmedia.com Date: Fri, 26 Jun 2009 12:18:29 +0100 Xref: eternal-september.org comp.lang.vhdl:1516 "Serkan" wrote in message news:c0899c4d-dd8b-4c9b-84d7-4f78cd7374dd@g20g2000vba.googlegroups.com... > On 26 Haziran, 12:21, "HT-Lab" wrote: >> "Serkan" wrote in message .. >> >> > You could just write an initialisation function to read the values >> > from a text file. >> >> >any guide or link?. >> >> Can't you pre-load it with an MIF file? >> >> Hanswww.ht-lab.com > > > > I tried using a mif file but all I can see is zeros at the output when > I do functional simulation. > But if I do timing simulation then I can see correct data values. > Very strange I must admit. > Looks like a timing or delta-delay issue. Have a look in the manual to see how to use the list window. Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!z34g2000vbl.googlegroups.com!not-for-mail From: "Niv (KP)" Newsgroups: comp.lang.vhdl Subject: Re: BCH(256,16,113) code Date: Fri, 26 Jun 2009 04:36:37 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: References: <5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com> NNTP-Posting-Host: 195.59.43.240 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246016197 23640 127.0.0.1 (26 Jun 2009 11:36:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 11:36:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z34g2000vbl.googlegroups.com; posting-host=195.59.43.240; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; .NET CLR 2.0.50727),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1517 On 26 June, 10:16, "HT-Lab" wrote: > "Niv (KP)" wrote in message > > news:5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com... > > > I'm looking at a paper owhich talks about BCH(256,16,113) code. =A0I > > think it is some form of CRC, but acn't find any details on how to > > implement in VHDL. =A0If it is just a CRC variant, I'd like to know wha= t > > the appropriate taps are. > > > Anyone done this already? > > > Regards, Kev P. > > It is far more complex than your ordinary CRC, > > http://en.wikipedia.org/wiki/BCH_code > > Galois Fields mathematics is a good place to start :-) > > Hanswww.ht-lab.com Yes, I've tried, but it's fairly heavy going, mostly above my head; haven't done any serious math since uni, and that was long, long ago, in a galaxy......!! KP. From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!n19g2000vba.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Fri, 26 Jun 2009 05:56:49 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <6f6452a7-1ff0-4e14-b5ed-13dc9a089de8@n19g2000vba.googlegroups.com> References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> <204a7bda-2fb8-4359-8469-d21fb6dc250a@f16g2000vbf.googlegroups.com> NNTP-Posting-Host: 78.189.78.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246021009 30283 127.0.0.1 (26 Jun 2009 12:56:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 12:56:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000vba.googlegroups.com; posting-host=78.189.78.15; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1518 On 26 Haziran, 14:18, "HT-Lab" wrote: > "Serkan" wrote in message > > news:c0899c4d-dd8b-4c9b-84d7-4f78cd7374dd@g20g2000vba.googlegroups.com... > > > On 26 Haziran, 12:21, "HT-Lab" wrote: > >> "Serkan" wrote in message > .. > > >> > You could just write an initialisation function to read the values > >> > from a text file. > > >> >any guide or link?. > > >> Can't you pre-load it with an MIF file? > > >> Hanswww.ht-lab.com > > > I tried using a mif file but all I can see is zeros at the output when > > I do functional simulation. > > But if I do timing simulation then I can see correct data values. > > Very strange I must admit. > > Looks like a timing or delta-delay issue. > > Have a look in the manual to see how to use the list window. > > Hanswww.ht-lab.com It is not related to timing or delta delay issue :) Searched other forums. People are wining about the same problem. I even saw other Mike Treseler posts. Some say, a modelsim bug. If I manage to do it, I will post the solution. thank you all for your answers. From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Fri, 26 Jun 2009 14:05:22 +0100 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> X-Trace: news.eternal-september.org U2FsdGVkX19G14ZEwKCYuvnxvp96Muvbdjp3/c1D/yEjIqY2no7CPq4UwIe5ZjzL4R+Kp4eXOsWN2Q8MJqwxLYJqgfMIxyxnI1fNNTyRe2ZO+CFVf35eHjJlqjbPfoxe9tdrr4uzK+pQ2FAhy2OOjg== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Fri, 26 Jun 2009 13:07:51 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1/wl+41/HtknV4WVMY+VsPrvYcKVbwsyrg= Cancel-Lock: sha1:/xHAcVfall8LQ1sAXjRaj+6hjnc= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1519 comp.arch.fpga:4454 "Muzaffer Kal" wrote in message news:csq445t6012cnufggai343t9jqptbe2pnd@4ax.com... > On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley > wrote: > >>I'm trying to assemble a complete and accurate list >>of the _synthesizable_ templates for all common types >>of FPGA memory, and I have discovered a template >>that synthesizes to dual-clock RAM in two FPGA >>vendors' tools but is a complete nonsense for >>simulation. I want to know why this has happened, >>what we can do about it, and why the vendors haven't >>already been beaten to pulp over it by users. > > Originally coming from ASIC side I find this incredible but it seems > that majority of people doing FPGA design don't simulate. I was at an > FPGA infomercial the other day about two new device families coming > out from a vendor to stay nameless and only %20 or so people raised > their hands when asked this question. This might explain how these > templates survived as is for such a long time. At the same time blind reliance of simulators is just as bad. There is the old saying garbage in = garbage out. Personally I choose a mix as an early misunderstanding can otherwise waste an inordinate amount of time. In the past I have also come across instances where simulation has taken so long, and created such large files, that reality has been quicker with a few debugging flags in the code! Each to their own. From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!news.swapon.de!news.glorb.com!news2.glorb.com!postnews.google.com!n21g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Fri, 26 Jun 2009 06:35:19 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <874f4eb2-c389-44ba-b222-87e927b33764@n21g2000vba.googlegroups.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <61384dc0-3939-4653-bda9-94248e01d737@v2g2000vbb.googlegroups.com> <9bh7459dgvvpg89ar3to5k1k9ngogigoe7@4ax.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246023323 14324 127.0.0.1 (26 Jun 2009 13:35:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 13:35:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n21g2000vba.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1520 comp.arch.fpga:4455 On Jun 25, 1:53=A0pm, Jonathan Bromley wrote: > > Getting software folk and digital designers > talking to each other would be a big step in > the right direction. =A0Sometimes that works well, > but certain project management styles (as in Rick's > story) go a long way towards preventing it. > > Re-skilling, as often as you get the chance, is > a pretty good antidote to belief that you know > it all. =A0Career circumstances don't usually make > that easy to do, sadly. Most of the time when I mention that FPGA/ASIC engineers could learn a trick or three from their SW brethren, I get bombarded with "FPGA/ASIC design is not SW!" True enough, but the discipline of code design, and to a lesser extent testing, is very much the same between the two. The requirements for the code are much different (usually), but the method in which complex requirements must be analyzed, broken down, designed into code and verified are incredibly similar. SW has developed over the years many techniques for dealing with the complexity of all things coded, and we HW engineers can learn an awful lot from them about at least that. I have worked with some SW engineers that fairly quickly grasped the HW nature of HDL code, and some that didn't ever get it. I have also worked with some HW engineers that grasped the SW nature of their design, and some that didn't. Those that do understand the similarities and the differences between the two, and exploit the similarities while observing the limitations of the differences, are the ones I want on my team. There are often organizational turf battles that get in the way of honest exchange of ideas and solutions between SW and HW. It seems to be the mavericks from both camps that tend to understand the common ground and then exploit it, to the benefit of both. Andy From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!p23g2000vbl.googlegroups.com!not-for-mail From: NigelE Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Fri, 26 Jun 2009 07:44:42 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <51fb9a69-c41d-4978-9bda-5697654b3cc5@p23g2000vbl.googlegroups.com> References: NNTP-Posting-Host: 192.94.31.2 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246027482 19913 127.0.0.1 (26 Jun 2009 14:44:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 14:44:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p23g2000vbl.googlegroups.com; posting-host=192.94.31.2; posting-account=1DUvGAkAAACTjqYMxU2yO0fPMeK-QMLM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; .NET CLR 3.0.04506.30; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1521 On Jun 25, 2:43=A0pm, Matthias Alles wrote: > > Seems to work fine in 6.5b, > > Ah, OK. I am using 6.3g at the moment. It's not supported for this versio= n. > > Matthias Take a look at the 'allfalse' exclude option. This excludes the implicit branches of 'if' statements without an 'else'. It's available as part of the 'coverage exclude' command and the coverage exlclusion pragmas - Nigel From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!f10g2000vbf.googlegroups.com!not-for-mail From: NigelE Newsgroups: comp.lang.vhdl Subject: Re: Code Coverage in ModelSim Date: Fri, 26 Jun 2009 08:31:21 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <0b7e1b27-84ff-4db9-b23f-a3e584bb09f5@f10g2000vbf.googlegroups.com> References: <51fb9a69-c41d-4978-9bda-5697654b3cc5@p23g2000vbl.googlegroups.com> NNTP-Posting-Host: 192.94.31.2 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246030281 4687 127.0.0.1 (26 Jun 2009 15:31:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 15:31:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f10g2000vbf.googlegroups.com; posting-host=192.94.31.2; posting-account=1DUvGAkAAACTjqYMxU2yO0fPMeK-QMLM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; .NET CLR 3.0.04506.30; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1522 On Jun 26, 3:44=A0pm, NigelE wrote: > On Jun 25, 2:43=A0pm, Matthias Alles > kl.de> wrote: > > > Seems to work fine in 6.5b, > > > Ah, OK. I am using 6.3g at the moment. It's not supported for this vers= ion. > > > Matthias > > Take a look at the 'allfalse' exclude option. > > This excludes the implicit branches of 'if' statements without an > 'else'. > It's available as part of the 'coverage exclude' command and the > coverage exlclusion pragmas > > - Nigel I should have added that this requires 6.5a or later From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!nwrddc02.gnilink.net.POSTED!e65bc745!not-for-mail From: Dave P Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Spartan 3E Message-ID: References: <236ef17d-f983-4db4-b5a1-9af39bb3b404@y6g2000prf.googlegroups.com> X-Newsreader: Forte Agent 4.2/32.1118 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 21 Date: Fri, 26 Jun 2009 16:26:39 GMT NNTP-Posting-Host: 71.191.199.139 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1246033599 71.191.199.139 (Fri, 26 Jun 2009 12:26:39 EDT) NNTP-Posting-Date: Fri, 26 Jun 2009 12:26:39 EDT Xref: eternal-september.org comp.lang.vhdl:1523 On Fri, 26 Jun 2009 00:18:57 -0700 (PDT), Amit wrote: > >Hello group, > >Does anybody know any resource that I can use for Spartan 3E I >recently have bought? I need to use some basic codes and run them >using the board. >I've planned to use VHDL. > >Thanks, >Amit I'm not sure what you mean by "resource", but the Xilinx/Digilent Spartan-3E development board comes with lots of hardware goodies, lots of documentation, and ISE (Xilinx's VHDL/Verilog synthesizer). There are lots of VHDL books available. "FPGA Prototyping by VHDL Examples" (by Pong Chu) is a good starter book. -Dave Pollum From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!weretis.net!feeder2.news.weretis.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Fri, 26 Jun 2009 09:58:32 -0700 Lines: 11 Message-ID: <7akd1oF1vg0g9U1@mid.individual.net> References: <0cb39939-7faf-4cfe-a0b8-987c980d4149@j20g2000vbp.googlegroups.com> <7ai8lrF1vh0vhU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net pMZQg7FF/OdF4dFp6+NMSQ4vzfApDIwSGi+HnazZxIb0bpw9cl Cancel-Lock: sha1:AZsrsZtTR6cd+PDllykiz5fFy3I= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1524 Serkan wrote: > It takes two much time to simulate using that method. > Is not there any way to do it without the testbench writing the > values? Is your intent to test the ram design? Finding the init data does not prove that the ram works. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:20 2009 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Fri, 26 Jun 2009 10:37:56 -0700 Lines: 22 Message-ID: <7akfblF1v0bpnU1@mid.individual.net> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <61384dc0-3939-4653-bda9-94248e01d737@v2g2000vbb.googlegroups.com> <9bh7459dgvvpg89ar3to5k1k9ngogigoe7@4ax.com> <874f4eb2-c389-44ba-b222-87e927b33764@n21g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4/4ZfACSB95okmvWpARDAg0AcEuLPB2tH1D+A1RENFx6s0H2o0 Cancel-Lock: sha1:phHHcAU/KFG05cSe31uNIze+MNE= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <874f4eb2-c389-44ba-b222-87e927b33764@n21g2000vba.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1525 comp.arch.fpga:4468 Andy wrote: > I have worked with some SW engineers that fairly quickly grasped the > HW nature of HDL code, and some that didn't ever get it. I have also > worked with some HW engineers that grasped the SW nature of their > design, and some that didn't. Those that do understand the > similarities and the differences between the two, and exploit the > similarities while observing the limitations of the differences, are > the ones I want on my team. I agree. Thanks for the posting. I would only add that it is curious that the same software engineers that insist on careful version control and unit testing for their own code, are often content to accept a binary fpga image file directly into their firmware without insisting on having any of the supporting sources or build processes. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Fri, 26 Jun 2009 10:51:41 -0700 Lines: 24 Message-ID: <7akg5eF1tmmprU1@mid.individual.net> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Trace: individual.net xBfv/I5u6VXGnfvGWUsFfwFgtKxzsWlffbB/KPBGfYiA+UrmGQ Cancel-Lock: sha1:X+Y3w6ubFMi8S/MibdalJOy1VmU= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1526 comp.arch.fpga:4469 Fredxx wrote: > At the same time blind reliance of simulators is just as bad. As is blind reliance on anything. > There is the old saying garbage in = garbage out. An rtl sim is a pretty good garbage filter. It is only sufficient with a well-tested set of design rules. > In the past I have also come across instances where simulation has taken so > long, and created such large files, that reality has been quicker with a few > debugging flags in the code! I have worked on projects where a few debugging flags in the code would never have found all of the logical errors. A good testbench doesn't produce large files. It reports pass or fail. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!j9g2000prh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: enum as array index Date: Fri, 26 Jun 2009 10:53:57 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246038839 25828 127.0.0.1 (26 Jun 2009 17:53:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 17:53:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1527 I think this is how I have to do it. Am I making it too complex? Will it synthesize? type flag_type is (this, that, other); type flag_array_type is array (flag_type range <>) of std_logic; signal flag : flag_array_type(other downto this); ... --set the flag flag(that) <= '1'; yes? Shannon From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 26 Jun 2009 13:21:58 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 19:18:48 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 46 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Coc3seMtFVVEnszVuMN3y28hkbO8saUz+kUxoYJQyTLmbefG0OH2w+X5IXfv19rmk/TbyCsOrtZ7CSW!qBwUCqu+Uy+/FohfCLnMofEDOQmGZ00w66JyMwpa+7yF7xfGiWmUNLjoa+hAnJpw6yU6IeS1pw20!uRSMNuE4n6TMnJd2 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1528 On Fri, 26 Jun 2009 10:53:57 -0700 (PDT), Shannon wrote: >type flag_type is (this, that, other); >type flag_array_type is array (flag_type range <>) of std_logic; >signal flag : flag_array_type(other downto this); >... >flag(that) <= '1'; > Am I making it too complex? Possibly. Unless you really need arrays indexed by a subtype of the enum, you could simply do type flag_array_type is array(flag_type) of std_logic; signal flag: flag_array_type; Since the ordering of an enum is rarely interesting, this seems likely to be just as useful. You could also consider making the array elements be of boolean type. It's rather nice to be able to write things like flag(this <= (valueA /= valueB); if flag(that) then .... >Will it synthesize? No reason why not. Yell if it doesn't, and we'll all gang up on the synthesis vendors and give them a hard time :-) Of course, you are leaving it up to the synth tool to choose an encoding for the enum. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: eternal-september.org!news.mixmin.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 11:23:38 -0700 Lines: 18 Message-ID: <7aki1bF1us9imU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net UNHmFfZ0miVG+zy/UANubAIzecKwknfnm2dz6zWmX3rK7DPKfX Cancel-Lock: sha1:ePPJHR4Y3V+8NJ3evG+hRC25hEQ= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1529 Shannon wrote: > type flag_type is (this, that, other); > type flag_array_type is array (flag_type range <>) of std_logic; > signal flag : flag_array_type(other downto this); I use the type enum directly as the array index: type quality_t is (too_big, too_small, just_right); type stats_t is array (quality_t) of natural; constant stats_c : stats_t := (too_small => 2, too_big => 1, just_right => 5); Works fine for synthesis. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c20g2000prh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 12:52:08 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> References: <7aki1bF1us9imU1@mid.individual.net> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246045928 22969 127.0.0.1 (26 Jun 2009 19:52:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 19:52:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000prh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1530 On Jun 26, 11:23=A0am, Mike Treseler wrote: > Shannon wrote: > > type flag_type is (this, that, other); > > type flag_array_type is array (flag_type range <>) of std_logic; > > signal flag : flag_array_type(other downto this); > > I use the type enum directly as the array index: > > type quality_t is (too_big, too_small, just_right); > > type stats_t is array (quality_t) of natural; > > constant stats_c : stats_t :=3D > (too_small =3D> 2, too_big =3D> 1, just_right =3D> 5); > > Works fine for synthesis. > > =A0 =A0 -- Mike Treseler I was specific about the ordering since I am going to use the flag array to update a vector where the specific location of each bit is important (and fixed). Something like: Loop reg_status(i) <=3D reg_status(i) or flag(i); end loop This flag array is a list of fault bits. I like the looks of: flag(over_current) <=3D '1'; ... flag(under_volt) <=3D '1'; etc. Then the processor can read the reg_status word and can mask bits to look for certain faults. So the plan was to enum in order the fault flags. Shannon From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!q3g2000pra.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 13:02:10 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: References: <7aki1bF1us9imU1@mid.individual.net> <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246046532 25054 127.0.0.1 (26 Jun 2009 20:02:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 20:02:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q3g2000pra.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1531 > Loop > =A0 =A0reg_status(i) <=3D reg_status(i) or flag(i); > end loop Which of course I just realized I can't do since the index here would be an integer and wouldn't match flag_type. grrrr Shannon From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 26 Jun 2009 15:05:44 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 21:02:34 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <7aki1bF1us9imU1@mid.individual.net> <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 68 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-9yVDZ0oxqOqHJLpAKizXgVZTfNjWiQUhdjsldfJCfadRidAsY/+JzRfm63t6PhvHXss1Iy3jkxfB+1E!So/q4p9ClzggcfhuGF36mPrdWlvsn/k76urORPj9efFX2P90j7uOwrwehjcIWPnHuTsbEs8qBxcm!i3KSvd/PzO8hz5Ps X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1532 On Fri, 26 Jun 2009 12:52:08 -0700 (PDT), Shannon wrote: >I was specific about the ordering since I am going to use the flag >array to update a vector where the specific location of each bit is >important (and fixed). In that case, you really DON'T want to use an enum. It gives you no control over the mapping from enum positions to bit positions in the vector. Consider named constants instead. That gives you the same readable usage, but anchors the flag positions in the std_logic_vector. It also allows you to create named bit-fields by using subtypes. As an example, suppose you have an 8-bit flag vector laid out like this: bit 7: flag "f7" bits 6..5: two-bit control code "cc2" bit 4: flag "f4" bits 3..1: three-bit control code "cc3" bit 0: flag "f0" Then you could do... subtype flag_vector_t is std_logic_vector (7 downto 0); constant f7: positive := 7; subtype cc2 is positive range 6 downto 5; subtype code2_t is std_logic_vector(cc2); constant f4: positive := 4; subtype cc3 is positive range 3 downto 1; subtype code3_t is std_logic_vector(cc3); constant f0: positive := 0; signal flags: flag_vector_t; signal code3: code3_t; signal code2: code2_t; ... flags(f0) <= '1'; flags(cc2) <= code2; code3 <= flags(cc3); if flags(f0)='1' then ... But of course your flag word is now simply a std_logic_vector, which can freely be copied to or from any other such. There are other games you can play with records, but named constants and subtypes are flexible and painless. They don't bring you a whole lot of type checking, but there are times when you don't want that anyway. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c18g2000prh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 13:12:13 -0700 (PDT) Organization: http://groups.google.com Lines: 80 Message-ID: References: <7aki1bF1us9imU1@mid.individual.net> <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246047133 26865 127.0.0.1 (26 Jun 2009 20:12:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 26 Jun 2009 20:12:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c18g2000prh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1533 On Jun 26, 1:02=A0pm, Jonathan Bromley wrote: > On Fri, 26 Jun 2009 12:52:08 -0700 (PDT), Shannon wrote: > >I was specific about the ordering since I am going to use the flag > >array to update a vector where the specific location of each bit is > >important (and fixed). > > In that case, you really DON'T want to use an enum. > It gives you no control over the mapping from > enum positions to bit positions in the vector. > > Consider named constants instead. =A0That gives you > the same readable usage, but anchors the flag > positions in the std_logic_vector. =A0It also > allows you to create named bit-fields by using > subtypes. > > As an example, suppose you have an 8-bit > flag vector laid out like this: > > =A0 bit 7: flag "f7" > =A0 bits 6..5: two-bit control code "cc2" > =A0 bit 4: =A0flag "f4" > =A0 bits 3..1: three-bit control code "cc3" > =A0 bit 0: flag "f0" > > Then you could do... > > =A0 subtype flag_vector_t is std_logic_vector (7 downto 0); > =A0 constant f7: positive :=3D 7; > =A0 subtype cc2 is positive range 6 downto 5; > =A0 subtype code2_t is std_logic_vector(cc2); > =A0 constant f4: positive :=3D 4; > =A0 subtype cc3 is positive range 3 downto 1; > =A0 subtype code3_t is std_logic_vector(cc3); > =A0 constant f0: positive :=3D 0; > > =A0 signal flags: flag_vector_t; > =A0 signal code3: code3_t; > =A0 signal code2: code2_t; > > =A0 ... > > =A0 flags(f0) <=3D '1'; > =A0 flags(cc2) <=3D code2; > =A0 code3 <=3D flags(cc3); > =A0 if flags(f0)=3D'1' then ... > > But of course your flag word is now simply a > std_logic_vector, which can freely be copied > to or from any other such. > > There are other games you can play with records, > but named constants and subtypes are flexible > and painless. =A0They don't bring you a whole lot > of type checking, but there are times when you > don't want that anyway. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thanks Jonathan. This is the reason I posted since I had a sneaking suspicion I was making things too hard. You are right of course. I would make the "look-up table" more readable anyway: constant over_current : positive 1; constant over_voltage : positive 2; etc... rather than having to count your way through and enum (which could get reordered by the synth anyway...) Thanks. From newsfish@newsfish Wed Aug 19 13:25:21 2009 Path: feeder.eternal-september.org!eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.visyn.net!open-news-network.org!visyn.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: enum as array index Date: Fri, 26 Jun 2009 13:24:34 -0700 Lines: 28 Message-ID: <7akp42F1vr0tiU1@mid.individual.net> References: <7aki1bF1us9imU1@mid.individual.net> <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net jBEoQlp3oRxUPGRG4cuOpgEjb8lXbaH4ewd56H6yUUO8FM3YSJ Cancel-Lock: sha1:JlAj2EH6iPm2o0yMR8cQEaPBdvw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1534 Shannon wrote: >> Loop >> reg_status(i) <= reg_status(i) or flag(i); >> end loop > > Which of course I just realized I can't do since the index here would > be an integer and wouldn't match flag_type. grrrr > > Shannon hmmm. 'pos worked with quartus like this: ____________________________________________________________________ function op2vec (arg : op_t) return std_logic_vector is variable argn_v : natural; ----------------------------------------- -- type op_t is (ts_load, cal_load, cmd2, cmd3); -- 00 01 10 11 -- cal_adr port values ----------------------------------------- begin argn_v := op_t'pos(arg); return std_logic_vector(to_unsigned(argn_v, adr_len_c)); end function op2vec; ____________________________________________________________________ -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.linkpendium.com!news.linkpendium.com!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!nlpi070.nbdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <7aki1bF1us9imU1@mid.individual.net> <46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com> Subject: Re: enum as array index Lines: 99 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: nlpi070.nbdc.sbc.com 1246066667 ST000 99.184.242.197 (Fri, 26 Jun 2009 21:37:47 EDT) NNTP-Posting-Date: Fri, 26 Jun 2009 21:37:47 EDT Organization: at&t http://my.att.net/ X-UserInfo1: Q[R_PJSCTS@ERS@XKRHX_RLARRXFBL@MAHU^_BAMEH]TCDYG^WHKAH_[JTXDX_KI\VB]JBVMS^YT_G[CZVWAOS\DHFWEH]@KGXYHB\_CMDSFABP^J[AHHRKARLE_JDBLJ\XA[JRMEI]MGJSPB\Y]^KG\@S^@VQKI_Q[G@@_ACSARASDEFLBJ]S\GFNTUAVBL Date: Fri, 26 Jun 2009 21:37:35 -0400 Xref: eternal-september.org comp.lang.vhdl:1535 "Shannon" wrote in message news:46e51543-b2f8-492e-a5ec-744111354683@c20g2000prh.googlegroups.com... > I was specific about the ordering since I am going to use the flag > array to update a vector where the specific location of each bit is > important (and fixed). Something like: > > Loop > reg_status(i) <= reg_status(i) or flag(i); > end loop > > This flag array is a list of fault bits. For processor register maps I prefer to define a record type like this... type t_INPUT_DMA_STATUS_PORT is record Done: std_ulogic_vector(31 downto 31); Reserved: std_ulogic_vector(30 downto 26); Current_Count: std_ulogic_vector(25 downto 0); end record; Then create a pair of functions to convert to and from std_ulogic_vectors like this... function To_Std_ULogic_Vector(L : t_INPUT_DMA_STATUS_PORT) return std_ulogic_vector is variable RetVal: std_ulogic_vector(31 downto 0); begin RetVal := (others => '0'); RetVal(L.Done'range) := L.Done; RetVal(L.Reserved'range) := L.Reserved; RetVal(L.Current_Count'range) := L.Current_Count; return(RetVal); end To_Std_ULogic_Vector; function From_Std_ULogic_Vector(L : std_ulogic_vector) return t_INPUT_DMA_STATUS_PORT is variable RetVal: t_INPUT_DMA_STATUS_PORT; variable Lx: std_ulogic_vector(L'length - 1 downto 0); begin Lx := L; RetVal.Done := Lx(RetVal.Done'range); RetVal.Reserved := Lx(RetVal.Reserved'range); RetVal.Current_Count := Lx(RetVal.Current_Count'range); return(RetVal); end From_Std_ULogic_Vector; All of this goes into a package that goes along with the entity. Creating and maintaining these functions as the basic type evolves over time is fairly straight forward, in fact changes that involves only the bits within an existing field (like making a particular field be two bits wide rather than one) involve editing only the type definition to put in the new bit definitions, no other edits are needed, just recompile. Adding or removing fields only requires editing the record and the to/from functions. If there is any code anywhere else in the model that then would be affected (such as X.Done <= "1" where the 'Done' field for whatever reason now changes to be 2 bits) you don't need to hunt these affected areas down, simply recompile and the compiler will flag it for you (in this case the complaint being the assignment of a vector of size one to something that is two bits wide)...much less tedious. Having done that bit of groundwork (which can be somewhat or mostly 'macro-ized' depending on your fav editor's capabilities) lots of things come out looking clean Simple assignment: Status.Done <= "1"; Logic operations (such as masking the bits of one reg with another) are handled mostly by type conversion using the to/from functions: Status <= From_Std_ULogic_Vector(To_Std_ULogic_Vector(Status) and To_Std_ULogic_Vector(Mask_Reg)); When you get around to writing the testbench code for the processor model these to/from functions will come in handy yet again since the model for the 'source code' of the processor will look clean dealing with the record types (as above for 'simple assignment') but at some point the basic 'processor model' itself will need to communicate via generic std_(u)logic_vectors. That I generally wrap up inside a procedure (or function) in process scope like this... procedure Write_Port(Data: t_INPUT_DMA_STATUS_PORT) Do that for each and every software port in your design and the testbench processor model reduces down to a whole bunch of simple 'write_port' and 'read_port' calls without having to even specify addresses of those ports in the call since those procedures can be written to contain the address by virtue of VHDL's function/procedure overloading. As long as you only have one port that is of type 't_INPUT_DMA_STATUS_PORT' the address of the port can be defined as a constant in the procedure, so no need to pass it in as a parameter as you would with a less general 'write anything' or 'read anything' set of procedures. These 'register specific' read and write procedures in turn generally call a more basic 'read' or 'write' procedure that works with std_(u)logic_vectors that implements whatever the basic protocol of a read or write actually is at the signal level (i.e. set strobe low, wait 100 ns, drop 'wr_n'...blah, blah...) and works with any address and data since it is working at the std_(u)logic_vector level. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r10g2000yqa.googlegroups.com!not-for-mail From: Serkan Newsgroups: comp.lang.vhdl Subject: Re: pre-initialized dpram functional simulation Date: Sat, 27 Jun 2009 14:30:50 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <423ba81c-59b4-4ad4-bf66-d2f205a40f21@r10g2000yqa.googlegroups.com> References: 7akd1oF1vg0g9U1@mid.individual.net NNTP-Posting-Host: 78.174.188.148 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246138251 26191 127.0.0.1 (27 Jun 2009 21:30:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 27 Jun 2009 21:30:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r10g2000yqa.googlegroups.com; posting-host=78.174.188.148; posting-account=Tp-sowoAAADe-T7Ld01TgZp_e4XE1mGu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; tr; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1539 On 26 Haziran, 19:58, Mike Treseler wrote: > Serkan wrote: > > =A0It takes two much time to simulate using that method. > > =A0Is not there any way to do it without the testbench writing the > > values? > > Is your intent to test the ram design? > Finding the init data does not prove > that the ram works. > > =A0 =A0 =A0 -- Mike Treseler No I do not want to test the ram. I have a design to test which has a dpram. So I need a dpram model to help testing my design. I created a ram(in my case dpram_32k) using the Xilinx Core Generator. I have a mif file that has the initial values to be entered to the ram at the time 0 of test.(I do not want to do it on the testbench by myself for timing purposes. This is important) I just want to make a functinal simulation using Modelsim with the ram initialized using the mif file that I have before the test starts. I am missing something in the steps that I cant be able to initialize the ram with the numbers in the milf file. serkan From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l31g2000yqb.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Expand unsigned 4*4 module to signed 16*16 module Date: Sat, 27 Jun 2009 17:39:50 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: NNTP-Posting-Host: 69.111.114.48 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246149590 29665 127.0.0.1 (28 Jun 2009 00:39:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 28 Jun 2009 00:39:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l31g2000yqb.googlegroups.com; posting-host=69.111.114.48; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4506 comp.lang.vhdl:1540 Hi, I want to expand unsigned 4*4 module to signed 16*16 module and cannot find any references. Who knows it please give me a help. Thank you. Weng From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Expand unsigned 4*4 module to signed 16*16 module Date: Sat, 27 Jun 2009 18:10:38 -0700 Lines: 6 Message-ID: <4A46C30E.5050704@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net zUcpJC8loezjqCtHQeCg4AuXm8GvaeZ7uJFLQ34rtYSi6CfcK+ Cancel-Lock: sha1:PVI0GRe96Cxv0XSHugB5e/dA7ZU= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.arch.fpga:4507 comp.lang.vhdl:1541 Weng Tianxiang wrote: > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > find any references. Post your 4*4. From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Sun, 28 Jun 2009 02:13:15 +0100 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7akg5eF1tmmprU1@mid.individual.net> X-Trace: news.eternal-september.org U2FsdGVkX18bcqp+yXkHJi2VxkxUEZaDPlT6saIDfqYBmcBeaHhlaBwjapX1pzLWs02IxK7Jk2/NWwgQQMNLY2eaa8juffUYJRV231ggyCNPs7e79PIU/12PWRZgElicunvPNHMRWtU0GAgUEEKv9Q== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Sun, 28 Jun 2009 01:17:43 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX19vlGaB8yKtXZEZir0YvcsPFEi6Ceb0l1g= Cancel-Lock: sha1:pJxoBZU9ShtFfjcO4BCnBAjUePg= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1542 comp.arch.fpga:4508 "Mike Treseler" wrote in message news:7akg5eF1tmmprU1@mid.individual.net... > Fredxx wrote: > >> At the same time blind reliance of simulators is just as bad. > > As is blind reliance on anything. > >> There is the old saying garbage in = garbage out. > > An rtl sim is a pretty good garbage filter. > It is only sufficient with a well-tested set of design rules. Hmm - perhaps you're interfacing with an external IC. Are you going to tell me you'd blindly write a testbench without confirming that your interface in real hardware is correctly understood? It's clear you've never got a PCI or PCIe interface working without resorting to the likes of chipscope, where reality doesn't even match signals as per standards. > >> In the past I have also come across instances where simulation has taken >> so >> long, and created such large files, that reality has been quicker with a >> few >> debugging flags in the code! > > I have worked on projects where a few debugging > flags in the code would never have found > all of the logical errors. Couldn't agree more. > > A good testbench doesn't produce large files. I was thinking of waveform files, where perhaps the simulation has to first wade though a million states to start providing data. > It reports pass or fail. You're just not living in the real world of FPGA design which ought to be a mix of simulation and reality. Anything else, and you are either assuming your test bench doesn't have any flaws, or just fumbling in the dark. From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z9g2000yqi.googlegroups.com!not-for-mail From: Weng Tianxiang Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Expand unsigned 4*4 module to signed 16*16 module Date: Sat, 27 Jun 2009 19:06:57 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <311d04ab-7110-4e77-9459-e2e276633e16@z9g2000yqi.googlegroups.com> References: <4A46C30E.5050704@gmail.com> NNTP-Posting-Host: 69.111.114.48 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246154817 14116 127.0.0.1 (28 Jun 2009 02:06:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 28 Jun 2009 02:06:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqi.googlegroups.com; posting-host=69.111.114.48; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4509 comp.lang.vhdl:1543 On Jun 27, 6:10=A0pm, Mike Treseler wrote: > Weng Tianxiang wrote: > > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > > find any references. > > Post your 4*4. Hi Mike, Here it is a Xilinx invention about 4*4 module. http://www.google.com/patents/about?id=3DaoQSAAAAEBAJ&dq=3Dpatent:6708191&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D Configurable logic block with and gate for efficient multiplication in FPGAS by Xilinx Kenneth D. Chapman et al in FIG. 9, 16 and 17. Weng From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!ecngs!feeder2.ecngs.de!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Sun, 28 Jun 2009 06:43:15 -0700 Lines: 18 Message-ID: <4A477373.8040406@gmail.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7akg5eF1tmmprU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Udp5uFN8QQiyzOxKUrwdwgSr/vZyMqCzv6YL/g5oIogP8I0W8H Cancel-Lock: sha1:ImkEahCPIy38lwXIrrMG5AbHQNg= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1545 comp.arch.fpga:4518 Fredxx wrote: > Hmm - perhaps you're interfacing with an external IC. Are you going to tell > me you'd blindly write a testbench without confirming that your interface in > real hardware is correctly understood? Standard interfaces are well documented. Certainly I have to verify a few things on the bench, but starting with a sim improves my odds. > It's clear you've never got a PCI or PCIe interface working without > resorting to the likes of chipscope, where reality doesn't even match > signals as per standards. We purchased a PCIe core that came with a testbench. I just worked. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:22 2009 Path: feeder.eternal-september.org!eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question -typo Date: Sun, 28 Jun 2009 06:49:39 -0700 Lines: 8 Message-ID: <4A4774F3.6000104@gmail.com> References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7akg5eF1tmmprU1@mid.individual.net> <4A477373.8040406@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net kPrBfsziX7TvFsY/+14fegiZHMbVY28B8rmtBdhEigUa/xC8Vt Cancel-Lock: sha1:+8qr8tHYuF5BfZU9hIDGGhAA5Sc= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: <4A477373.8040406@gmail.com> Xref: eternal-september.org comp.lang.vhdl:1546 comp.arch.fpga:4519 Mike Treseler wrote: > We purchased a PCIe core that came with a testbench. > I just worked. It From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Expand unsigned 4*4 module to signed 16*16 module Date: Sun, 28 Jun 2009 06:53:52 -0700 Lines: 9 Message-ID: <4A4775F0.8030803@gmail.com> References: <4A46C30E.5050704@gmail.com> <311d04ab-7110-4e77-9459-e2e276633e16@z9g2000yqi.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 6/ty+dStj/ijFBmFxtOOeQOU5XFdctOjaPml6C8QnVxCinMsaD Cancel-Lock: sha1:mlitcL17IS8N2Kf6s4wA8mXkk9A= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: <311d04ab-7110-4e77-9459-e2e276633e16@z9g2000yqi.googlegroups.com> Xref: eternal-september.org comp.arch.fpga:4520 comp.lang.vhdl:1547 Weng Tianxiang wrote: > Here it is a Xilinx invention about 4*4 module. The topic of this newsgroup is vhdl. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!not-for-mail From: "Fredxx" Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Sun, 28 Jun 2009 15:07:21 +0100 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7akg5eF1tmmprU1@mid.individual.net> <4A477373.8040406@gmail.com> X-Trace: news.eternal-september.org U2FsdGVkX19ONtw0gzpltfz7Xxvp1S+VjLPG0ubLn7WoG4vZ5xNfXlsOTHwz8vo0NTNvWbOCz0fEuzefXxewlxyIZ0rO2mh1h3K5gEQWMZmtS0uEy90DabO6K6cazQYKKmIOVpBbGvmj2C1JBjW78Q== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Sun, 28 Jun 2009 14:10:19 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX188TeGH1LMDt5wvxVtLtHdtALMlulGyWS4= Cancel-Lock: sha1:gTrVzuVlWXON3RtSWgCuGvujo6A= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1548 comp.arch.fpga:4521 "Mike Treseler" wrote in message news:4A477373.8040406@gmail.com... > Fredxx wrote: > >> Hmm - perhaps you're interfacing with an external IC. Are you going to >> tell me you'd blindly write a testbench without confirming that your >> interface in real hardware is correctly understood? > > Standard interfaces are well documented. > Certainly I have to verify a few things on the bench, > but starting with a sim improves my odds. It sounds we're really singing from the same hymn sheet, the difference is I'm more honest to say that simulation is sometimes no substitution for reality. > >> It's clear you've never got a PCI or PCIe interface working without >> resorting to the likes of chipscope, where reality doesn't even match >> signals as per standards. > > We purchased a PCIe core that came with a testbench. > I just worked. > Perhaps I'm missing something here, but I would hope the purchased core and test bench would work straight out of the box? From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!33g2000vbe.googlegroups.com!not-for-mail From: cpld-fpga-asic Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Sun, 28 Jun 2009 07:09:07 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> NNTP-Posting-Host: 173.26.91.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246198148 22447 127.0.0.1 (28 Jun 2009 14:09:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 28 Jun 2009 14:09:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 33g2000vbe.googlegroups.com; posting-host=173.26.91.145; posting-account=388PUgkAAABmij3aN_Sp29ABT5cSB5Mc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; Trident/4.0; GTB6; SLCC1; .NET CLR 2.0.50727; Media Center PC 5.0; .NET CLR 3.5.30729; .NET CLR 3.0.30618; FDM; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1549 comp.arch.fpga:4522 comp.lang.verilog:551 Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as well. Vendors included: Xilinx, Altera, Actel, Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn can be a way to get technical questions answered. It can also be a way to meet contacts with expertise in other domains of knowledge other than your own. Additionally, many career enhancing contacts, and mentors can potentially found especially if one is at a smaller company that lacks the resources for extensive internal networking. http://www.linkedin.com/groups?about=&gid=56713 Website: https://sites.google.com/site/fpgacpldgroup/ From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j12g2000vbl.googlegroups.com!not-for-mail From: "Antti.Lukats@googlemail.com" Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Sun, 28 Jun 2009 07:52:09 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> NNTP-Posting-Host: 217.71.35.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246200729 30530 127.0.0.1 (28 Jun 2009 14:52:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 28 Jun 2009 14:52:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j12g2000vbl.googlegroups.com; posting-host=217.71.35.1; posting-account=z0FtqwoAAAB7_vrOIg6MMon_VxAOoReV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1550 comp.arch.fpga:4523 comp.lang.verilog:552 On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: > Group for People Involved In the Design and Verification of FPGA's, > other Programmable Logic , and CPLD's to Exchange Idea's and > Techniques. You should have FPGA / CPLD Design / Verification on your > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > Synopsys, Aldec, NI, Altium, and Many Others. > > Networking on LinkedIn can be a way to get technical questions > answered. It can also be a way to meet contacts with expertise in > other domains of knowledge other than your own. Additionally, many > career enhancing contacts, and mentors can potentially found > especially if one is at a smaller company that lacks the resources for > extensive internal networking. > > http://www.linkedin.com/groups?about=3D&gid=3D56713 > > Website:https://sites.google.com/site/fpgacpldgroup/ could you describe the last technical FPGA related question that your linkedin networking group solved? unless you are able todo that, i see you repeated postings to c.a.f. as complete spam Antti From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 28 Jun 2009 16:05:51 -0500 From: Jonathan Bromley Newsgroups: comp.arch.fpga;,comp.lang.vhdl Subject: Dual-port RAM synthesis - AN APOLOGY to Xilinx Date: Sun, 28 Jun 2009 22:02:40 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 72 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-MhmlkbC92FrGBOOUc+8SCSj2a3gOeJ+KOtUMWo4TkmJ/izinJ7R/8YM3liJl+vsWyTKLHNSZ0hAL3sZ!+B2swrRKUQJES4/Vvtx76bhtLX2WLfAlktiaYNmluLsi3BZYPaMdHjTKjZDCI16nOqPY0+XQeA4Z!vn8nztg/nTN2LMyQ X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 4002 Xref: eternal-september.org comp.lang.vhdl:1554 In a recent thread "True dual-port RAM in VHDL: XST question" I claimed that, in my tests, I had found XST tolerating a bad description of dual-port dual-clock RAM. ********************************************** I WAS COMPLETELY WRONG in my criticism of XST. ********************************************** Apology first, then the details. ***************************************** I hope Xilinx will accept my sincere apology for wrongly describing a problem that in fact does not exist in their tool. Thanks to the WebCase team for responding promptly and courteously to my inappropriate bug report. ***************************************** I was right about the VHDL; the template I described (two processes writing to the same signal) is indeed a bad description of a RAM, and should not be tolerated for synthesis. I was wrong to say that XST accepts it. It simply doesn't. Way back, certainly since version 8.2, XST has got this right; it rejects the bad code with a helpful diagnostic. So, how did I get this so badly wrong? I was trying out a very large number of different RAM models on a very large number of different tools, so of course I wrote a script to drive synthesis. For some reason that I still don't understand, when I compiled first a Verilog version and then a VHDL version of the same design, XST was processing the compiled results from the Verilog code on both occasions (even though the first few lines of the report file told me, as expected, that it was compiling the VHDL file second time around). Consequently I thought the bad VHDL version was getting through, when in fact it was the (correct) Verilog code that was being processed. Very, very careful and thorough clean-out of working directories was required to get the VHDL version to be compiled - and to throw the error. A nasty case of "back to the drawing board". It should also be noted that XST does indeed correctly synthesize dual-clock RAM from a shared-variable model. So, retreating from Xilinx with tail firmly between legs, I shall saddle up the old warhorse and ride it in the direction of a different vendor.... One final point: why, one might ask, did I go to Usenet first, rather than to Xilinx direct, when I found the problem? Simply because I didn't want to go to Xilinx with a spurious bug report, and I hoped to calibrate my own understanding against others. Yet another well-meaning plan backfires... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed1.swip.net!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000vba.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Expand unsigned 4*4 module to signed 16*16 module Date: Sun, 28 Jun 2009 20:06:07 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <56ad61a2-0e95-4a2d-9ea3-b7b194d9e3fa@l32g2000vba.googlegroups.com> References: NNTP-Posting-Host: 76.100.116.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246244767 9605 127.0.0.1 (29 Jun 2009 03:06:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Jun 2009 03:06:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000vba.googlegroups.com; posting-host=76.100.116.251; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4533 comp.lang.vhdl:1555 On Jun 27, 8:39=A0pm, Weng Tianxiang wrote: > Hi, > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > find any references. > > Who knows it please give me a help. > > Thank you. > > Weng To use a multiplier module, you must consider the product output from this module to be a partial product which is added to the other partial products to form the complete product. To do a 16x16 multiply using 4x4 multiplier modules will require 16 of these modules. Consider each 16 bit number to be composed of a3*2**12 + a2*2**8 + a1*2**4 + a0 and b3*2**12 + b2*2**8 + b1*2**4 + b0 Your partial products will be a0*b0 + a0*b1*2**4 + a1*b0*2**4 + a1*b1*2**8 + ... I think you can see where this is going. Rick From newsfish@newsfish Wed Aug 19 13:25:23 2009 Path: feeder.eternal-september.org!eternal-september.org!news.motzarella.org!feeder.motzarella.org!news.motzarella.org!motzarella.org!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!k15g2000yqc.googlegroups.com!not-for-mail From: Amit Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Spartan 3E Date: Sun, 28 Jun 2009 18:11:22 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <236ef17d-f983-4db4-b5a1-9af39bb3b404@y6g2000prf.googlegroups.com> NNTP-Posting-Host: 75.142.50.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246237882 20188 127.0.0.1 (29 Jun 2009 01:11:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Jun 2009 01:11:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k15g2000yqc.googlegroups.com; posting-host=75.142.50.253; posting-account=mAJBZAoAAAADkVIbl_HAX1n55aYMpDgZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1556 On Jun 26, 9:26=A0am, Dave P wrote: > On Fri, 26 Jun 2009 00:18:57 -0700 (PDT), Amit > wrote: > > > > >Hello group, > > >Does anybody know any resource that I can use for Spartan 3E I > >recently have bought? I need to use some basic codes and run them > >using the board. > >I've planned to use VHDL. > > >Thanks, > >Amit > > I'm not sure what you mean by "resource", but the Xilinx/Digilent > Spartan-3E development board comes with lots of hardware goodies, lots of > documentation, and ISE (Xilinx's VHDL/Verilog synthesizer). =A0There are = lots > of VHDL books available. =A0"FPGA Prototyping by VHDL Examples" (by Pong = Chu) > is a good starter book. > -Dave Pollum Thanks! no I just have received a box with no single paper or any documentation but yes the book you pointed out is the one I found on amazon. Regards. From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n19g2000vba.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Mon, 29 Jun 2009 08:08:16 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246288097 19045 127.0.0.1 (29 Jun 2009 15:08:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Jun 2009 15:08:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000vba.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1558 comp.arch.fpga:4545 comp.lang.verilog:557 On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" wrote: > On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: > > > > > Group for People Involved In the Design and Verification of FPGA's, > > other Programmable Logic , and CPLD's to Exchange Idea's and > > Techniques. You should have FPGA / CPLD Design / Verification on your > > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > > Synopsys, Aldec, NI, Altium, and Many Others. > > > Networking on LinkedIn can be a way to get technical questions > > answered. It can also be a way to meet contacts with expertise in > > other domains of knowledge other than your own. Additionally, many > > career enhancing contacts, and mentors can potentially found > > especially if one is at a smaller company that lacks the resources for > > extensive internal networking. > > >http://www.linkedin.com/groups?about=3D&gid=3D56713 > > > Website:https://sites.google.com/site/fpgacpldgroup/ > > could you describe the last technical FPGA related question > that your linkedin networking group solved? > > unless you are able todo that, i see you repeated postings > to c.a.f. as complete spam > > Antti Hi, I am one of the moderators at this group and I must be honest about it. It is not a very technically oriented group. I have tried to make some technically oriented posts there with few responses. This did not seem to stimulate much in the way of subsequent new topics either. I have also made an effort to separate the technical content from the recruiting content and gotten feedback that the recruiters are the ones paying the way for LinkedIn and cutting them out would be a mistake. So I have given up on this group as well as other FPGA related groups at LinkedIn. I have not removed myself from membership, but I can't say I recommend them unless you wish to use it for employment or self promotion. Rick From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p23g2000vbl.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: I've got a case of the latches.... Date: Mon, 29 Jun 2009 09:10:55 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <6da3261f-fc29-4882-bb89-3d95a70413e0@p23g2000vbl.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246291855 31171 127.0.0.1 (29 Jun 2009 16:10:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Jun 2009 16:10:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p23g2000vbl.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1559 Ok, I know how latches can be inferred from missing assignments. Here is what I have: process(clk, reset) begin if reset = '1' then ... x < = '0'; ... elsif rising_edge clk then x <= '0'; case state is when.... when.... when.... if something then x <= '1'; elsif something_else then .... else .... end if; end case; end if; end process; why is 'x' a latch? Shannon From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: I've got a case of the latches.... Date: Mon, 29 Jun 2009 09:21:17 -0700 Lines: 13 Message-ID: <7as7vuF20dnjpU1@mid.individual.net> References: <6da3261f-fc29-4882-bb89-3d95a70413e0@p23g2000vbl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net gcE0zDK1cy6u3tRiAkO5igvZMglACn0o36yqkbDIWAphhkikhY Cancel-Lock: sha1:YP1WIH6HCfvrdxxbGFHlQ9sQiTw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <6da3261f-fc29-4882-bb89-3d95a70413e0@p23g2000vbl.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1560 Shannon wrote: > Ok, I know how latches can be inferred from missing assignments. Only in an unclocked process. > Here is what I have: > ... > why is 'x' a latch? I don't see how it could be. Post a complete entity. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j12g2000vbl.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: I've got a case of the latches.... Date: Mon, 29 Jun 2009 09:33:36 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <6da3261f-fc29-4882-bb89-3d95a70413e0@p23g2000vbl.googlegroups.com> <7as7vuF20dnjpU1@mid.individual.net> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246293216 3108 127.0.0.1 (29 Jun 2009 16:33:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Jun 2009 16:33:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j12g2000vbl.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1561 On Jun 29, 9:21=A0am, Mike Treseler wrote: > Shannon wrote: > > Ok, I know how latches can be inferred from missing assignments. > > Only in an unclocked process. > > > =A0Here is what I have: > > =A0 =A0 ... > > why is 'x' a latch? > > I don't see how it could be. > Post a complete entity. > > =A0 =A0 =A0 -- Mike Treseler I think I misunderstood the error message. I was getting (from Quartus) the message: "analyzing combinational loop as a latch: "x" is a latch" What this error means is that 'x' is not a latch but how I'm using it is. The offending statement was where I was using 'x' outside of a clocked process: y <=3D z or x; (or some such thing). The point being y was being assigned outside of the clocked process (mistakenly). It was THAT that was forming the combinational loop. Moving the 'y' assignment inside the clocked process fixed it. Shannon From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: I've got a case of the latches.... Date: Mon, 29 Jun 2009 09:56:13 -0700 Lines: 12 Message-ID: <7asa1eF20l7v7U1@mid.individual.net> References: <6da3261f-fc29-4882-bb89-3d95a70413e0@p23g2000vbl.googlegroups.com> <7as7vuF20dnjpU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ivJ+U4FO6ISMPmy7BCWxEALUxc/vCibrh2Gtuu04hVNHaLjl51 Cancel-Lock: sha1:xCDBz8BXfsr+pz1bNcC7ogcM+OI= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1562 Shannon wrote: > The offending statement was where I was using 'x' outside of a clocked > process: > y <= z or x; (or some such thing). The point being y was being > assigned outside of the clocked process (mistakenly). It was THAT > that was forming the combinational loop. Moving the 'y' assignment > inside the clocked process fixed it. That's it. An assignment 'outside' of a process is in fact, an asynchronous process. From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.motzarella.org!not-for-mail From: "Symon" Newsgroups: comp.lang.vhdl Subject: Re: BCH(256,16,113) code Date: Mon, 29 Jun 2009 22:25:20 +0100 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <5ac84a5a-5044-4a71-bc3a-b09c38f0eccd@s6g2000vbp.googlegroups.com> X-Trace: news.eternal-september.org U2FsdGVkX1/jIgNFoItAgFB2/UDwozMggA3FPry3042+oMu32BsYinL8bVgfEoL4HCK0hq3WSp+zBlPZfROGpw8DfTU0A3eWaTVp3zesbVtSn5iYVRgLpf8ppDo91jjPlaSq0S1Daco= X-Complaints-To: abuse@motzarella.org NNTP-Posting-Date: Mon, 29 Jun 2009 21:25:17 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX19r/EKcW+8klFPM7C9KunqGJEBAovyf+bg= Cancel-Lock: sha1:5o88rFNjuOwFoC5EVNZK03sGduw= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1563 Niv (KP) wrote: > > Yes, I've tried, but it's fairly heavy going, mostly above my head; > haven't done any serious math since uni, and that was long, long ago, > in a galaxy......!! > > KP. To remind yourself about GF arithmetic, have a read of a textbook or two, maybe Lin and Costello would be a good place to start. Also, xapp371 might give you some insight. HTH, Syms. From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000vba.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: True dual-port RAM in VHDL: XST question Date: Tue, 30 Jun 2009 07:24:10 -0700 (PDT) Organization: http://groups.google.com Lines: 76 Message-ID: References: <008ac323-21ef-44c5-a851-a4217265720f@n19g2000vba.googlegroups.com> <0rp445tqrmicerhmqtqe6f0b4pmruk7aod@4ax.com> <7akg5eF1tmmprU1@mid.individual.net> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246371851 30476 127.0.0.1 (30 Jun 2009 14:24:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Jun 2009 14:24:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000vba.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1564 comp.arch.fpga:4561 On Jun 27, 9:13=A0pm, "Fredxx" wrote: > "Mike Treseler" wrote in message > > news:7akg5eF1tmmprU1@mid.individual.net... > > > Fredxx wrote: > > >> At the same time blind reliance of simulators is just as bad. > > > As is blind reliance on anything. > > >> There is the old saying garbage in =3D garbage out. > > > An rtl sim is a pretty good garbage filter. > > It is only sufficient with a well-tested set of design rules. > > Hmm - perhaps you're interfacing with an external IC. =A0Are you going to= tell > me you'd blindly write a testbench without confirming that your interface= in > real hardware is correctly understood? > > It's clear you've never got a PCI or PCIe interface working without > resorting to the likes of chipscope, where reality doesn't even match > signals as per standards. > > > > >> In the past I have also come across instances where simulation has tak= en > >> so > >> long, and created such large files, that reality has been quicker with= a > >> few > >> debugging flags in the code! > > > I have worked on projects where a few debugging > > flags in the code would never have found > > all of the logical errors. > > Couldn't agree more. > > > > > A good testbench doesn't produce large files. > > I was thinking of waveform files, where perhaps the simulation has to fir= st > wade though a million states to start providing data. > > > It reports pass or fail. > > You're just not living in the real world of FPGA design which ought to be= a > mix of simulation and reality. =A0Anything else, and you are either assum= ing > your test bench doesn't have any flaws, or just fumbling in the dark. Nobody is saying you never have to test a design in the chip. I think Mike is just saying that time spent on a good test bench is work many more hours in the lab with an O-scope. I know that my designs typically are much harder to debug on the bench than in simulation. I seldom get my test benches honed to the point of giving me a pass/fail indication, but I know that I am going to be running them many more times than once and construct them accordingly. In fact, I typically design a test bench for each module and unit test before I integrate. If the module changes during integration, I rework the unit test bench to keep up with the changes. This can add greatly to module reuse as well as helping to keep the bulk of debugging at a lower level where it is easier to find and repair bugs. The software community has a lot of good ideas that *do* apply to writing HDL code. We just need to consider these ideas and use them appropriately. Rick From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!18g2000yqa.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Simulating Inverted Registers Date: Tue, 30 Jun 2009 13:48:32 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246394912 17688 127.0.0.1 (30 Jun 2009 20:48:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Jun 2009 20:48:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 18g2000yqa.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1565 Seems like I'm posting a lot lately. I really appreciate all the help you guys have given. You are helping bring me up to speed quickly. On to the question.... Although my question is about simulation, this concerns a design for synthesis. I have a 32-bit register that I load a default value into during reset. As Altera has explained to me, the hardware can only pre-load zeros. To get a '1' bit they put inverters on each side of the flip- flop and force it clear. Ok I get that. In actuality the "inverters" don't really exist. They get pushed into the surrounding logic. So when I simulate using Quartus's simulator or ModelSim I probe my register and I get some inverted bits. (corresponding to where the ones are in my default value). I've tested the real hardware and it works fine. I know I'm not the first person to load a default value into a register. Is there a "standard" way of dealing with this in simulation? I have lots of ideas but they all seem kludge-y. I suspect there is some common ways of dealing with it. I hope I've explained the situation clear enough. Thanks, Shannon From newsfish@newsfish Wed Aug 19 13:25:24 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c36g2000yqn.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Simulating Inverted Registers Date: Tue, 30 Jun 2009 14:04:12 -0700 (PDT) Organization: http://groups.google.com Lines: 69 Message-ID: <9f18025e-91e8-421f-bf55-58d6dda2aef1@c36g2000yqn.googlegroups.com> References: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246395852 11918 127.0.0.1 (30 Jun 2009 21:04:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Jun 2009 21:04:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c36g2000yqn.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1566 On Jun 30, 1:48=A0pm, Shannon wrote: > Seems like I'm posting a lot lately. =A0I really appreciate all the help > you guys have given. =A0You are helping bring me up to speed quickly. > On to the question.... > > Although my question is about simulation, this concerns a design for > synthesis. > > I have a 32-bit register that I load a default value into during > reset. =A0As Altera has explained to me, the hardware can only pre-load > zeros. =A0To get a '1' bit they put inverters on each side of the flip- > flop and force it clear. =A0Ok I get that. > > In actuality the "inverters" don't really exist. =A0They get pushed into > the surrounding logic. =A0So when I simulate using Quartus's simulator > or ModelSim I probe my register and I get some inverted bits. > (corresponding to where the ones are in my default value). > > I've tested the real hardware and it works fine. =A0I know I'm not the > first person to load a default value into a register. =A0Is there a > "standard" way of dealing with this in simulation? =A0I have lots of > ideas but they all seem kludge-y. =A0I suspect there is some common ways > of dealing with it. > > I hope I've explained the situation clear enough. > > Thanks, > Shannon Here is a complete entity that simulates what I'm talking about: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity inverted is port ( reset : in std_logic; clk : in std_logic; byte_out : out std_logic_vector(7 downto 0) ); end inverted; architecture rtl of inverted is signal byte : unsigned(7 downto 0); begin process(clk, reset) begin if reset =3D '1' then byte <=3D X"42"; --arbitrary number for example elsif rising_edge(clk) then byte <=3D byte + 1; end if; end process; byte_out <=3D std_logic_vector(byte); end rtl; In this example byte_out will simulate exactly as you would expect - starting off at 42h and counting up each clock. "byte" however will not simulate as you would expect. Well at least not how "I" would expect. lol Shannon From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!newspeer1.nac.net!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n30g2000vba.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Simulating Inverted Registers Date: Tue, 30 Jun 2009 15:21:50 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: References: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> <9f18025e-91e8-421f-bf55-58d6dda2aef1@c36g2000yqn.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246400510 4101 127.0.0.1 (30 Jun 2009 22:21:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Jun 2009 22:21:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n30g2000vba.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1567 You could reset to zeroes, then synchronously load your default value on the first clock. That may even take less logic than inverting/ uninverting the bits in some cases. There are lots of times where RTL vs post-S/P&R models don't match, such as enumerated types, etc., but not many good tricks for dealing with it, except to avoid it (i.e. use a self-checking testbench, not just one that dumps a lot of signals to a waveform for you to check manually). Assuming "byte" comes out on a port somewhere that the TB can access it, it should have the same semantics there as your RTL, even if it is a gate level model. Andy From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed1.swip.net!feeder.erje.net!ecngs!feeder2.ecngs.de!newsfeed.freenet.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Simulating Inverted Registers Date: Tue, 30 Jun 2009 17:22:33 -0700 Lines: 26 Message-ID: <7avoiaF2042qvU1@mid.individual.net> References: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /ywXoEh0eA7uRNDhWe28LgiqmAMxZ6z/dqauqlRz3WdIrSzZX5 Cancel-Lock: sha1:8ZzyWpwtf3UiMg8vRuNusCBNq2k= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1568 Shannon wrote: > Seems like I'm posting a lot lately. I really appreciate all the help > you guys have given. You are helping bring me up to speed quickly. > On to the question.... > > Although my question is about simulation, this concerns a design for > synthesis. > > I have a 32-bit register that I load a default value into during > reset. As Altera has explained to me, the hardware can only pre-load > zeros. To get a '1' bit they put inverters on each side of the flip- > flop and force it clear. Ok I get that. Device registers without a direct asynchronous preset may not handle both an asynchronous *and* synchronous preset to the same value. I ran into a case once where a cyclic synchronous preset of a 32 bit register would not route with an asynchronous preset to the same value. I expect that an asynchronous reset to zero would have worked, but I didn't try that at the time. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l31g2000yqb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Simulating Inverted Registers Date: Tue, 30 Jun 2009 22:48:38 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <8bde6898-40b8-4ce3-8f17-4c2d3deb62cb@l31g2000yqb.googlegroups.com> References: <3594a94d-8908-4ad4-bb5c-272c4b7def9d@18g2000yqa.googlegroups.com> <9f18025e-91e8-421f-bf55-58d6dda2aef1@c36g2000yqn.googlegroups.com> NNTP-Posting-Host: 94.218.72.71 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246427319 28945 127.0.0.1 (1 Jul 2009 05:48:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Jul 2009 05:48:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l31g2000yqb.googlegroups.com; posting-host=94.218.72.71; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1569 On 30 Jun., 23:04, Shannon wrote: > > the surrounding logic. =A0So when I simulate using Quartus's simulator > > or ModelSim I probe my register and I get some inverted bits. > > (corresponding to where the ones are in my default value). > =A0 =A0 =A0 =A0 if reset =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 byte <=3D X"42"; =A0--arbitrary number fo= r example [..] > byte_out <=3D std_logic_vector(byte); [..] > In this example byte_out will simulate exactly as you would expect > starting off at 42h and counting up each clock. =A0"byte" however will > not simulate as you would expect. =A0Well at least not how "I" would > expect. lol If you mean that the netlist simulation shows you "inverted" registers for some bits than you have a normal result for synthesis over boundaries of ff. A inverter after the FF output is just moved in front of the FF with inverting even reset case. In fact this is no problem of functionality but of verification as you need information from your tool which FF is inverted. This is less a problem for FPGA but a real pain for an ASIC when it comes to formal verification or ASIC test with dedicated scanpattern. bye Thomas From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k8g2000yqn.googlegroups.com!not-for-mail From: Ben Voigt Newsgroups: comp.lang.vhdl Subject: modelsim doesn't like my increment w/wraparound Date: Wed, 1 Jul 2009 14:04:48 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> NNTP-Posting-Host: 12.148.70.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246482288 32499 127.0.0.1 (1 Jul 2009 21:04:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Jul 2009 21:04:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000yqn.googlegroups.com; posting-host=12.148.70.158; posting-account=2OOufwoAAAAGLFjUteRw5xio0LqsvCyz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1573 I'm getting this error: Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to 124999. >From this code: SUBTYPE tick_t IS NATURAL RANGE 0 TO 124999; SIGNAL tick, inc_tick : tick_t; SIGNAL tick_overflow : BOOLEAN; tick_overflow <= (tick = tick_t'HIGH); inc_tick <= tick_t'LOW WHEN tick_overflow ELSE tick + 1; The expression tick+1 overflowed, but it can at most glitch (the other path of the selected assignment is active) and the setup time for the flip-flop shouldn't be an issue. This synthesizes just fine, but fails under simulation. I can get it to simulate using a process and sequential if statement, but that's about five times more code than I have now (I need the overflow flag for other logic). Any ideas how to do this elegantly? From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!news.mb-net.net!open-news-network.org!news.mind.de!bolzen.all.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Wed, 01 Jul 2009 15:19:08 -0700 Lines: 19 Message-ID: <7b25msF215brrU1@mid.individual.net> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net NTnibjZauUH2atQH7zdxlgGI+cnQ4pkcj7EN5MHUUKby4NLDOd Cancel-Lock: sha1:Bssm+9BbFBVHo5L6aAu/gjtsZsw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1574 Ben Voigt wrote: > I'm getting this error: > Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to > 124999. > Any ideas how to do this elegantly? Include the overflow value in the subtype range. This value is needed for simulation. SUBTYPE tick_t IS NATURAL RANGE 0 TO 125000; or maybe SUBTYPE tick_t IS NATURAL RANGE 0 TO -1 + 2**17 Synthesis utilization will not be affected. -- Mike Treselre From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r36g2000vbn.googlegroups.com!not-for-mail From: Ben Voigt Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Wed, 1 Jul 2009 15:37:32 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <3cc7c7de-d996-4040-9e55-cb7c50741125@r36g2000vbn.googlegroups.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7b25msF215brrU1@mid.individual.net> NNTP-Posting-Host: 12.148.70.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246487853 18157 127.0.0.1 (1 Jul 2009 22:37:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Jul 2009 22:37:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbn.googlegroups.com; posting-host=12.148.70.158; posting-account=2OOufwoAAAAGLFjUteRw5xio0LqsvCyz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1575 On Jul 1, 5:19=A0pm, Mike Treseler wrote: > Ben Voigt wrote: > > I'm getting this error: > > Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to > > 124999. > > Any ideas how to do this elegantly? > > Include the overflow value in the subtype range. > This value is needed for simulation. > > =A0SUBTYPE tick_t IS NATURAL RANGE 0 TO 125000; Yes, but... that changes the period of my counter and still breaks. I can compare against tick_t'HIGH-1 instead, but that's a magic number which I don't like. I eventually got rid of the inc_tick signal completely, since the process doing tick <=3D inc_tick can use a IF directly with no glitching (it's clocked, the value of tick_overflow has time to settle and the problematic addition is never simulated). > > or maybe > > =A0SUBTYPE tick_t IS NATURAL RANGE 0 TO -1 + 2**17 > > Synthesis utilization will not be affected. > > =A0 =A0 =A0 -- Mike Treselre From newsfish@newsfish Wed Aug 19 13:25:25 2009 Path: feeder.eternal-september.org!eternal-september.org!news.albasani.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Wed, 01 Jul 2009 16:33:19 -0700 Lines: 14 Message-ID: <7b2a21F21be0jU1@mid.individual.net> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7b25msF215brrU1@mid.individual.net> <3cc7c7de-d996-4040-9e55-cb7c50741125@r36g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net dpNWi2fhaJmFfdflwjlPnwI+6PZe4kg0I5xUm3M1JgEsuvBHPI Cancel-Lock: sha1:bcJoPMn85i+l01Tprf6UC4/pvm4= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: <3cc7c7de-d996-4040-9e55-cb7c50741125@r36g2000vbn.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1576 Ben Voigt wrote: > Yes, but... that changes the period of my counter and still breaks. I > can compare against tick_t'HIGH-1 instead, but that's a magic number > which I don't like. Sometimes the range has to exceed the rollover value. > I eventually got rid of the inc_tick signal completely, since the > process doing tick <= inc_tick can use a IF directly with no glitching > (it's clocked, the value of tick_overflow has time to settle and the > problematic addition is never simulated). That's even better. From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!newspeer1.nac.net!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n16g2000yqm.googlegroups.com!not-for-mail From: One Cent Newsgroups: comp.lang.vhdl Subject: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Date: Wed, 1 Jul 2009 18:58:12 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> NNTP-Posting-Host: 66.35.226.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246499892 15304 127.0.0.1 (2 Jul 2009 01:58:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Jul 2009 01:58:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n16g2000yqm.googlegroups.com; posting-host=66.35.226.228; posting-account=qw0X_QoAAAB1I2iX11mgzRedwBoFMKA- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.2; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1577 Hi, I am interested to know how can i force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? In verilog, i can write in this way at top level testbench as below: initial begin force tb.design.memory.rx_buffer.enable_model = 1'b0; #100; force tb.design.memory.rx_buffer.enable_model = 1'b1; end But how can I do this in a VHDL testbench? Thanks. From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!x17g2000yqd.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Date: Wed, 1 Jul 2009 23:50:16 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <4b340b68-7f85-4ff7-8e08-e62aa64bd0ad@x17g2000yqd.googlegroups.com> References: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246517416 8826 127.0.0.1 (2 Jul 2009 06:50:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Jul 2009 06:50:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x17g2000yqd.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.11) Gecko/2009061212 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1578 On 2 Jul., 03:58, One Cent wrote: > Hi, > I am interested to know how can i force an internal wire which is deep > inside DUT hierachy at top level testbench using VHDL design? > In verilog, i can write in this way at top level testbench as below: > > initial > begin > =A0force tb.design.memory.rx_buffer.enable_model =3D 1'b0; > =A0#100; > =A0 force tb.design.memory.rx_buffer.enable_model =3D 1'b1; > end > > But how can I do this in a VHDL testbench? > > Thanks. Hi, if you are using Modelsim you can use the SignalSpy functions. There you can access signals(wires/regs) by providing their hierarchical path in the system. Do a search for it in the documentation. It's all well explained. Have a nice simulation Eilert From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l31g2000yqb.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Thu, 2 Jul 2009 00:04:19 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <26f09f36-3e92-426e-a61e-bde94a406f5a@l31g2000yqb.googlegroups.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> NNTP-Posting-Host: 195.37.178.175 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246518259 18861 127.0.0.1 (2 Jul 2009 07:04:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Jul 2009 07:04:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l31g2000yqb.googlegroups.com; posting-host=195.37.178.175; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.11) Gecko/2009061212 Iceweasel/3.0.6 (Debian-3.0.6-1),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1579 On 1 Jul., 23:04, Ben Voigt wrote: > I'm getting this error: > Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to > 124999. > > From this code: > =A0 =A0SUBTYPE tick_t IS NATURAL RANGE 0 TO 124999; > =A0 =A0SIGNAL tick, inc_tick : tick_t; > =A0 =A0SIGNAL tick_overflow : BOOLEAN; > =A0 =A0tick_overflow <=3D (tick =3D tick_t'HIGH); > =A0 =A0inc_tick <=3D tick_t'LOW WHEN tick_overflow ELSE tick + 1; > > The expression tick+1 overflowed, but it can at most glitch (the other > path of the selected assignment is active) and the setup time for the > flip-flop shouldn't be an issue. > > This synthesizes just fine, but fails under simulation. =A0I can get it > to simulate using a process and sequential if statement, but that's > about five times more code than I have now (I need the overflow flag > for other logic). > > Any ideas how to do this elegantly? Hi, if this is just a n error that happens on the delta-cycle level, it has no real meaning, but is still annoying. Likle others said it would be a good idea to expand the range of your type by one. Maybe like this: SUBTYPE tick_t IS NATURAL RANGE 0 TO 125000; SIGNAL tick, inc_tick : tick_t; SIGNAL tick_overflow : BOOLEAN; tick_overflow <=3D (tick =3D tick_t'HIGH-1); -- regard the -1 here. your flag will come at the right time inc_tick <=3D tick_t'LOW WHEN tick_overflow ELSE tick + 1; Give it a try and if it works take a look at the delta-cycles of signal inc_tick. You probably will still find the value of 125000 there, but only for a few delta cycles, then it should be overridden by 0. Have a nice simulation Eilert From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-ID: <4A4C6435.10606@xs4all.nl> Date: Thu, 02 Jul 2009 09:39:33 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Ben Voigt Subject: Re: modelsim doesn't like my increment w/wraparound References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> In-Reply-To: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 34 NNTP-Posting-Host: 80.127.156.245 X-Trace: 1246520373 news.xs4all.nl 184 [::ffff:80.127.156.245]:52511 X-Complaints-To: abuse@xs4all.nl Xref: eternal-september.org comp.lang.vhdl:1580 Ben Voigt wrote: > I'm getting this error: > Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to > 124999. > > From this code: > SUBTYPE tick_t IS NATURAL RANGE 0 TO 124999; > SIGNAL tick, inc_tick : tick_t; > SIGNAL tick_overflow : BOOLEAN; > tick_overflow <= (tick = tick_t'HIGH); > inc_tick <= tick_t'LOW WHEN tick_overflow ELSE tick + 1; > > The expression tick+1 overflowed, but it can at most glitch (the other > path of the selected assignment is active) and the setup time for the > flip-flop shouldn't be an issue. > > This synthesizes just fine, but fails under simulation. I can get it > to simulate using a process and sequential if statement, but that's > about five times more code than I have now (I need the overflow flag > for other logic). > > Any ideas how to do this elegantly? How about: tick_overflow <= (tick = tick_t'HIGH); inc_tick <= tick_t'LOW WHEN (tick = tick_t'HIGH) ELSE tick + 1; ? Kind regards, Pieter Hulshoff PS: I hope this is inside a clocked process, otherwise you should get some interesting synthesis results. :) From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2009 06:27:47 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Thu, 02 Jul 2009 12:31:23 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 48 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-2dPq4US957r2FHEG9zyBKltjw5voC3hwRn33WfPE4FW9ieXz3IxBcuQ4wx5yAatkaqhbaBD+X0W6tYq!hs3g1K2Q5VUxIEffp0vKaLUf07tb9bF4lyHYa00BcDlQ501Rqai9PLwFwQi7LE2/TMUyKKFTeXq5!fX8= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1581 On Wed, 1 Jul 2009 14:04:48 -0700 (PDT), Ben Voigt wrote: >I'm getting this error: >Fatal: (vsim-3421) Value 125000 for inc_tick is out of range 0 to >124999. > >From this code: > SUBTYPE tick_t IS NATURAL RANGE 0 TO 124999; > SIGNAL tick, inc_tick : tick_t; > SIGNAL tick_overflow : BOOLEAN; > tick_overflow <= (tick = tick_t'HIGH); > inc_tick <= tick_t'LOW WHEN tick_overflow ELSE tick + 1; > >The expression tick+1 overflowed, but it can at most glitch (the other >path of the selected assignment is active) and the setup time for the >flip-flop shouldn't be an issue. > >This synthesizes just fine, but fails under simulation. I can get it >to simulate using a process and sequential if statement, but that's >about five times more code than I have now (I need the overflow flag >for other logic). > >Any ideas how to do this elegantly? Looks like an order-of-evaluation thing; when tick becomes tick'high, it propagates into both next_tick and tick_overflow. Therefore inc_tick WILL overflow until tick_overflow propagates in the next delta cycle. Obviously you meant inc_tick <= tick_t'LOW WHEN tick = tick_t'HIGH ELSE tick + 1; which, by avoiding the race, cannot raise the constraint error. The trick is to do this without duplicating code which WILL get out of sync during later updates. function overflow (t:tick_t) return boolean is begin return tick = tick_t'HIGH; end function overflow; tick_overflow <= overflow(tick); inc_tick <= tick_t'LOW WHEN overflow(tick) ELSE tick + 1; is one answer. - Brian From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!198.186.194.250.MISMATCH!news-xxxfer.readnews.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!news1.google.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 08:23:03 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 59 Message-ID: References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1582 comp.arch.fpga:4619 comp.lang.verilog:568 On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote (in article <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com>): > On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" > wrote: >> On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: >> >> >> >>> Group for People Involved In the Design and Verification of FPGA's, >>> other Programmable Logic , and CPLD's to Exchange Idea's and >>> Techniques. You should have FPGA / CPLD Design / Verification on your >>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to >>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC >>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, >>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, >>> Synopsys, Aldec, NI, Altium, and Many Others. >> >>> Networking on LinkedIn can be a way to get technical questions >>> answered. It can also be a way to meet contacts with expertise in >>> other domains of knowledge other than your own. Additionally, many >>> career enhancing contacts, and mentors can potentially found >>> especially if one is at a smaller company that lacks the resources for >>> extensive internal networking. >> >>> http://www.linkedin.com/groups?about=3D&gid=3D56713 >> >>> Website:https://sites.google.com/site/fpgacpldgroup/ >> >> could you describe the last technical FPGA related question >> that your linkedin networking group solved? >> >> unless you are able todo that, i see you repeated postings >> to c.a.f. as complete spam >> >> Antti > > Hi, I am one of the moderators at this group and I must be honest > about it. It is not a very technically oriented group. I have tried > to make some technically oriented posts there with few responses. > This did not seem to stimulate much in the way of subsequent new > topics either. I have also made an effort to separate the technical > content from the recruiting content and gotten feedback that the > recruiters are the ones paying the way for LinkedIn and cutting them > out would be a mistake. > > So I have given up on this group as well as other FPGA related groups > at LinkedIn. I have not removed myself from membership, but I can't > say I recommend them unless you wish to use it for employment or self > promotion. > > Rick I'm completely confused as to how you can have a FPGA group that is not "technically orientated" , it would be like having a flower arranging class without the flowers. From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!newsfeed.freenet.de!multikabel.net!newsfeed20.multikabel.net!ramfeed-1.ams.xsnews.nl!feed.xsnews.nl!border-1.ams.xsnews.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: issue with Chipscope Date: Fri, 3 Jul 2009 09:19:32 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 29 Message-ID: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1583 Hi, I'm new to FPGA design but I have a minor issue with chipscope . To get access 'inside' the user core i use 'core generator' followed by the usual incantations of sticking the pre-generated deffs at the start of the user_logic. (who thought up this half assed system?) Then I break my signals out and mask into chipscope (all is well with the world for 90% of my signals). BUT I have the following user enumerated types type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE; signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; how do i mask this damned thing into chipscope, I just get errors about the types not matching,. TRIG2(31 downto ????) => fifo_cntl_cs , Thanks steve From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Thu, 02 Jul 2009 21:31:13 -0700 Lines: 17 Message-ID: <7b5fs9F224u62U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net agTcQs2+aRSusRutMT696AQ/m8m+OVrkCB0TX4xrEUa3nd0mF/ Cancel-Lock: sha1:Bwhk2R+jYO6SVJwz6eIlcD+gZdY= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1584 steve wrote: > Then I break my signals out and mask into chipscope (all is well with the > world for 90% of my signals). > BUT I have the following user enumerated types > > type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); > signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE; > signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; > > how do i mask this damned thing into chipscope, I just get errors about the > types not matching,. The synthesis report has the state encodings. Next time, try vhdl simulation, and you can use the enum names directly. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:26 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g7g2000prg.googlegroups.com!not-for-mail From: One Cent Newsgroups: comp.lang.vhdl Subject: Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Date: Thu, 2 Jul 2009 22:27:48 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com> References: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> <4b340b68-7f85-4ff7-8e08-e62aa64bd0ad@x17g2000yqd.googlegroups.com> NNTP-Posting-Host: 210.19.133.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246598869 24067 127.0.0.1 (3 Jul 2009 05:27:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 05:27:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g7g2000prg.googlegroups.com; posting-host=210.19.133.3; posting-account=qw0X_QoAAAB1I2iX11mgzRedwBoFMKA- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.2; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1585 On Jul 2, 2:50=A0pm, backhus wrote: > On 2 Jul., 03:58, One Cent wrote: > > > Hi, > > I am interested to know how can i force an internal wire which is deep > > inside DUT hierachy at top level testbench using VHDL design? > > In verilog, i can write in this way at top level testbench as below: > > > initial > > begin > > =A0force tb.design.memory.rx_buffer.enable_model =3D 1'b0; > > =A0#100; > > =A0 force tb.design.memory.rx_buffer.enable_model =3D 1'b1; > > end > > > But how can I do this in a VHDL testbench? > > > Thanks. > > Hi, > if you are using Modelsim you can use the SignalSpy functions. > There you can access signals(wires/regs) by providing their > hierarchical path in the system. > Do a search for it in the documentation. It's all well explained. > > Have a nice simulation > =A0 Eilert Thanks Eilert! This reminds me the use of init_signal_spy function in Modelsim!! Thanks again =3D) From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe21.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> <4b340b68-7f85-4ff7-8e08-e62aa64bd0ad@x17g2000yqd.googlegroups.com> <9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com> Subject: Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Lines: 44 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe21.ams2 1246607302 86.16.123.60 (Fri, 03 Jul 2009 07:48:22 UTC) NNTP-Posting-Date: Fri, 03 Jul 2009 07:48:22 UTC Organization: virginmedia.com Date: Fri, 3 Jul 2009 08:47:48 +0100 Xref: eternal-september.org comp.lang.vhdl:1586 "One Cent" wrote in message news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com... On Jul 2, 2:50 pm, backhus wrote: > On 2 Jul., 03:58, One Cent wrote: > > > Hi, > > I am interested to know how can i force an internal wire which is deep > > inside DUT hierachy at top level testbench using VHDL design? > > In verilog, i can write in this way at top level testbench as below: > > > initial > > begin > > force tb.design.memory.rx_buffer.enable_model = 1'b0; > > #100; > > force tb.design.memory.rx_buffer.enable_model = 1'b1; > > end > > > But how can I do this in a VHDL testbench? > > > Thanks. > > Hi, > if you are using Modelsim you can use the SignalSpy functions. > There you can access signals(wires/regs) by providing their > hierarchical path in the system. > Do a search for it in the documentation. It's all well explained. > > Have a nice simulation > Eilert > >Thanks Eilert! >This reminds me the use of init_signal_spy function in Modelsim!! And at the same time you might want to email your favourite Mentor support engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references implemented ;-) Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 03 Jul 2009 03:59:05 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 09:55:47 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 61 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-mxCH3tGa9bFb9RNRtUspHp431uzu79hKXDRRqAHG82uCAuIQvTe3jFHk4UjwwkC0y+x4ZqOiGSCwpOS!4UEeIbmZRKDgqw1iLkGlozz83qtR7aM3/ZvOlbR2Ed7LbIkSoip7yvwSFyRa9Txg1wWOp+A2Foa6!dWxOYOtjUcpnQbhg X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 3155 Xref: eternal-september.org comp.lang.vhdl:1587 On Fri, 3 Jul 2009 09:19:32 +0800, steve wrote: >BUT I have the following user enumerated types > > type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); > signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; > >how do i mask this damned thing into chipscope, I just get errors about the >types not matching,. > >TRIG2(31 downto ????) => fifo_cntl_cs , You need a conversion function. TRIG2(31 downto 29) => to_slv(fifo_cntl_cs), You don't want to introduce any additional logic if you can avoid it, so it makes sense for the conversion function to match the internal encoding that XST has created - see Mike's post. In practice that's likely to be one-hot. So you could do something like this in which each output represents one state. It has the advantage that it won't need to be rewritten if you add or change state names: function to_slv(code: FIFO_CNTL_SM_TYPE) return std_logic_vector is constant LAST: integer := FIFO_CNTL_SM_TYPE'POS(FIFO_CNTL_SM_TYPE'HIGH); variable result: std_logic_vector(0 to LAST); begin result := (others => '0'); result(FIFO_CNTL_SM_TYPE'POS(code)) := '1'; return result; end; If you're short of pins on the ChipScope, you could simply convert the integer FIFO_CNTL_SM_TYPE'POS(code) to a std_logic_vector and put that out instead. XST is happy with the 'POS and 'HIGH attributes; I'm not sure it will be OK in all synthesis tools, although there's really no excuse for it not being. Do be aware that adding any such decoder, to observe an enumerated signal, may change the optimization so that the enumeration is encoded differently. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 3 Jul 2009 17:49:36 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 31 Message-ID: References: <7b5fs9F224u62U1@mid.individual.net> Reply-To: steve@aol.com NNTP-Posting-Host: p502391ba5b3ddb4a5c7b85ec6230fe36f6517f457556d709.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1588 On Fri, 3 Jul 2009 12:31:13 +0800, Mike Treseler wrote (in article <7b5fs9F224u62U1@mid.individual.net>): > steve wrote: > >> Then I break my signals out and mask into chipscope (all is well with the >> world for 90% of my signals). >> BUT I have the following user enumerated types >> >> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); >> signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE; >> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; >> >> how do i mask this damned thing into chipscope, I just get errors about the >> types not matching,. > > The synthesis report has the state encodings. > Next time, try vhdl simulation, and you can use the enum names directly. > > -- Mike Treseler Hi Mike, I don't want to simulate it , because i have a 'double clocking' bug that does not show up in simulation, this has to be a hardware probe, into User_logic,. These signals do not show up due to them being optimized out. We are talking about direct injection of the chipscope core into the user logic, not it sitting externally. From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q11g2000yqi.googlegroups.com!not-for-mail From: NigelE Newsgroups: comp.lang.vhdl Subject: Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Date: Fri, 3 Jul 2009 03:03:40 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: <6ee02237-3e7e-4e16-8b27-ec4e9191669b@q11g2000yqi.googlegroups.com> References: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> <4b340b68-7f85-4ff7-8e08-e62aa64bd0ad@x17g2000yqd.googlegroups.com> <9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com> NNTP-Posting-Host: 192.94.31.2 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246615420 8859 127.0.0.1 (3 Jul 2009 10:03:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 10:03:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q11g2000yqi.googlegroups.com; posting-host=192.94.31.2; posting-account=1DUvGAkAAACTjqYMxU2yO0fPMeK-QMLM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; .NET CLR 3.0.04506.30; MS-RTC LM 8),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1589 On Jul 3, 8:47=A0am, "HT-Lab" wrote: > "One Cent" wrote in message > > news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com... > On Jul 2, 2:50 pm, backhus wrote: > > > > > > > On 2 Jul., 03:58, One Cent wrote: > > > > Hi, > > > I am interested to know how can i force an internal wire which is dee= p > > > inside DUT hierachy at top level testbench using VHDL design? > > > In verilog, i can write in this way at top level testbench as below: > > > > initial > > > begin > > > force tb.design.memory.rx_buffer.enable_model =3D 1'b0; > > > #100; > > > force tb.design.memory.rx_buffer.enable_model =3D 1'b1; > > > end > > > > But how can I do this in a VHDL testbench? > > > > Thanks. > > > Hi, > > if you are using Modelsim you can use the SignalSpy functions. > > There you can access signals(wires/regs) by providing their > > hierarchical path in the system. > > Do a search for it in the documentation. It's all well explained. > > > Have a nice simulation > > Eilert > > >Thanks Eilert! > >This reminds me the use of init_signal_spy function in Modelsim!! > > And at the same time you might want to email your favourite Mentor suppor= t > engineer and ask him/her to raise an ER to get VHDL2008 hierarchical refe= rences > implemented ;-) > > Hanswww.ht-lab.com- Hide quoted text - > > - Show quoted text - It is already ! VHDL-2008 external names was implemented in 6.5 It works across mixed languages provided both ends are VHDL - Nigel From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 03 Jul 2009 05:07:44 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Fri, 03 Jul 2009 11:04:26 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 79 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-s1e880IfqYCkQm4nu+8hhnU4qABG0I2zomrezME/yWPnXcnjMf5OZHsDPBYB1m6zqHll+LQWgGraWGZ!ZPaRRaHhF1WtTVCbsiHCUj32sLMVKN6sq66Md4AZdaMXPyKX0FGcb/vtg55vmd2vBFHQ2F5q95No!R6fjnGvytr5avclA X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1590 On Wed, 1 Jul 2009 14:04:48 -0700 (PDT), Ben Voigt wrote: > SUBTYPE tick_t IS NATURAL RANGE 0 TO 124999; > SIGNAL tick, inc_tick : tick_t; > SIGNAL tick_overflow : BOOLEAN; > tick_overflow <= (tick = tick_t'HIGH); > inc_tick <= tick_t'LOW WHEN tick_overflow ELSE tick + 1; > >I can get it >to simulate using a process and sequential if statement, but that's >about five times more code than I have now Hmmm... let's compare tick_overflow <= (tick = tick_t'HIGH); inc_tick <= tick_t'LOW WHEN tick_overflow ELSE tick + 1; with this, which won't suffer the delta-glitches in simulation and (I believe) reflects the same design intent: process (tick) begin if tick = tick_t'HIGH then tick_overflow <= '1'; inc_tick <= tick_t'LOW; else tick_overflow <= '0'; inc_tick <= tick + 1; end if; end process; OK, it's a few more _lines_, but it's not very much more code; and I find it hugely more readable than the conditional assignments, which look to me like someone trying to use VHDL to describe a schematic. Better still, roll the whole mess into a single clocked process (your counter is clocked, right????), using a variable that captures the next-count value and tests it to generate a glitch-free, synchronous overflow output. Add resets, mode controls etc. to taste: -- utility function that everyone needs function to_SL(flag: boolean) return std_logic is begin if flag then return '1'; else return '0'; end if; end; -- bounded counter with overflow indication process (clock) variable next_tick: tick_t; begin if rising_edge (clock) then if tick = tick_t'HIGH then next_tick := tick_t'LOW; else next_tick := tick + 1; end if; if count_enable = '1' then tick <= next_tick; tick_overflow <= to_SL(next_tick = tick_t'HIGH); end if; end if; end process; -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!not-for-mail From: "Symon" Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 3 Jul 2009 11:38:25 +0100 Organization: A noiseless patient Spider Lines: 5 Message-ID: References: X-Trace: news.eternal-september.org U2FsdGVkX18Ni5ugIfl5P8pMDWl+up4klPS1Lg0blR4Xt/mMJBJ41eD29XqKC5Jscw11vMQpjJ8Fn1nWNTTrqU9Ly4JQfCq7Fvhem+VF8PQSATSt++k0P9o2xAc6u2g2OTVOMOQmpnBvqq1jMGmg2A== X-Complaints-To: abuse@eternal-september.org NNTP-Posting-Date: Fri, 3 Jul 2009 10:42:08 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Auth-Sender: U2FsdGVkX1/H8Fppm5l8xO0OB7P7GOBKc4xFYwPcxU8= Cancel-Lock: sha1:mcR6LbiM9kXudz7zRquLe4OsiEQ= X-Priority: 3 X-MSMail-Priority: Normal Xref: eternal-september.org comp.lang.vhdl:1591 Steve, Use the 'core inserter' instead. HTH., Syms. From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 3 Jul 2009 18:48:55 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 85 Message-ID: References: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1592 X-Original-Bytes: 3682 On Fri, 3 Jul 2009 16:55:47 +0800, Jonathan Bromley wrote (in article ): > On Fri, 3 Jul 2009 09:19:32 +0800, steve wrote: > >> BUT I have the following user enumerated types >> >> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); >> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; >> >> how do i mask this damned thing into chipscope, I just get errors about the >> types not matching,. >> >> TRIG2(31 downto ????) => fifo_cntl_cs , > > You need a conversion function. > > TRIG2(31 downto 29) => to_slv(fifo_cntl_cs), > > You don't want to introduce any additional logic if you > can avoid it, so it makes sense for the conversion > function to match the internal encoding that XST has > created - see Mike's post. > > In practice that's likely to be one-hot. So you could do > something like this in which each output represents one > state. It has the advantage that it won't > need to be rewritten if you add or change state names: > > function to_slv(code: FIFO_CNTL_SM_TYPE) > return std_logic_vector > is > constant LAST: integer := > FIFO_CNTL_SM_TYPE'POS(FIFO_CNTL_SM_TYPE'HIGH); > variable result: std_logic_vector(0 to LAST); > begin > result := (others => '0'); > result(FIFO_CNTL_SM_TYPE'POS(code)) := '1'; > return result; > end; > > If you're short of pins on the ChipScope, you could > simply convert the integer FIFO_CNTL_SM_TYPE'POS(code) > to a std_logic_vector and put that out instead. > > XST is happy with the 'POS and 'HIGH attributes; I'm > not sure it will be OK in all synthesis tools, > although there's really no excuse for it not being. > > Do be aware that adding any such decoder, to observe > an enumerated signal, may change the optimization > so that the enumeration is encoded differently. > Hi Jonathan, Thanks for your concise description, it's exactly the guidance I needed. Being new to FPGA's I did not realize how gash these tools were. As regards , changing the logic/ optimization, I'm already aware of that. when I try and put my chipscope external to my user_logic and probe internally, sometimes the stuff is accessible , other times it disappears, I keep looking to see if paul Daniels is behind me.. Like I say these tools and systems are gash, good job Xilinx would never dare charging for them. ;-) Just trying this...... It looks like it will not work, after adding in the library , it compiles fine, but as soon as it links up to chipscope.... to_slv(xxx) FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Steve From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 3 Jul 2009 18:52:18 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 11 Message-ID: References: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1593 On Fri, 3 Jul 2009 18:38:25 +0800, Symon wrote (in article ): > Steve, > Use the 'core inserter' instead. > HTH., Syms. > > It is better you do not comment if you do not read the post. From newsfish@newsfish Wed Aug 19 13:25:27 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe05.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <5feeb172-0e4a-43da-98bf-8587d68f3d04@n16g2000yqm.googlegroups.com> <4b340b68-7f85-4ff7-8e08-e62aa64bd0ad@x17g2000yqd.googlegroups.com> <9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com> <6ee02237-3e7e-4e16-8b27-ec4e9191669b@q11g2000yqi.googlegroups.com> Subject: Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design? Lines: 39 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Original Message-ID: <_Vl3m.8426$ME1.414@newsfe05.ams2> NNTP-Posting-Host: 86.16.123.60 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe05.ams2 1246620410 86.16.123.60 (Fri, 03 Jul 2009 11:26:50 UTC) NNTP-Posting-Date: Fri, 03 Jul 2009 11:26:50 UTC Organization: virginmedia.com Date: Fri, 3 Jul 2009 12:26:43 +0100 Xref: eternal-september.org comp.lang.vhdl:1594 "NigelE" wrote in message news:6ee02237-3e7e-4e16-8b27-ec4e9191669b@q11g2000yqi.googlegroups.com... On Jul 3, 8:47 am, "HT-Lab" wrote: > "One Cent" wrote in message > > news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com... > On Jul 2, 2:50 pm, backhus wrote: > .. > > And at the same time you might want to email your favourite Mentor support > engineer and ask him/her to raise an ER to get VHDL2008 hierarchical > references > implemented ;-) > > Hanswww.ht-lab.com- Hide quoted text - > > - Show quoted text - > >It is already ! > >VHDL-2008 external names was implemented in 6.5 >It works across mixed languages provided both ends are VHDL > >- Nigel Hi Nigel, You are right, I totally missed that one when I read the vhdl2008 technote. I tried it out and it works great. local_enable <= <>; Thanks, Hans www.ht-lab.com From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d32g2000yqh.googlegroups.com!not-for-mail From: James Harris Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: TimingAnalyzer is now freeware Date: Fri, 3 Jul 2009 06:18:39 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <9ee29b6f-36e1-4121-9d5b-a242a6f2684b@d32g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 87.115.210.196 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246627125 14067 127.0.0.1 (3 Jul 2009 13:18:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 13:18:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d32g2000yqh.googlegroups.com; posting-host=87.115.210.196; posting-account=Ss8wVAkAAADjaLf6nhKZFuysJxWaHI9Z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4636 comp.lang.vhdl:1595 comp.lang.verilog:573 On 20 June, 16:51, timinganalyzer wrote: > Hi All, > > I just wanted to let you know that the TimingAnalyzer is now licensed > as freeware. =A0 I just don't have the time needed to make a high > quality commercial product but I do want to keep the development > moving forward and continue to fix problems and add new features as > time permits. > > Recently, I have become very interested in Python and using it to > develop similar type cad programs. =A0My plan is to convert the > TimingAnalyzer Java to Python with mostly a scripting interface for > building complex timing diagrams, doing timing analysis, =A0creating > testbenches and testvectors from waveform diagrams, > and creating timing diagrams from simulation VCD files. =A0Most all of > this is text based work anyway. > > Developing professional GUIs is very time consuming for me. =A0This has > been my bottleneck with the program all along. =A0With a command line > interface, =A0you will execute a script and in one window, =A0and view an= d > edit and print the timing diagram shown in another window. =A0 Like > Matlab interface. > > If anyone is interested in helping with the development, =A0I will make > this an open source project. =A0 Just let me know if your interested. I prefer command-line interfaces in general. They are more flexible and can be automated. Good choice to move to Python as long as the speed holds up. You may want to inclulde comp.lang.python. James From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!gegeweb.org!news.glorb.com!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 11:10:29 -0300 Organization: W Software & FPGA Services Lines: 97 Message-ID: References: NNTP-Posting-Host: 190.135.52.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: adenine.netfront.net 1246630230 94093 190.135.52.204 (3 Jul 2009 14:10:30 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Fri, 3 Jul 2009 14:10:30 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1596 steve escribió: > On Fri, 3 Jul 2009 16:55:47 +0800, Jonathan Bromley wrote > (in article ): > >> On Fri, 3 Jul 2009 09:19:32 +0800, steve wrote: >> >>> BUT I have the following user enumerated types >>> >>> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); >>> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; >>> >>> how do i mask this damned thing into chipscope, I just get errors about the >>> types not matching,. >>> >>> TRIG2(31 downto ????) => fifo_cntl_cs , >> You need a conversion function. >> >> TRIG2(31 downto 29) => to_slv(fifo_cntl_cs), >> >> You don't want to introduce any additional logic if you >> can avoid it, so it makes sense for the conversion >> function to match the internal encoding that XST has >> created - see Mike's post. >> >> In practice that's likely to be one-hot. So you could do >> something like this in which each output represents one >> state. It has the advantage that it won't >> need to be rewritten if you add or change state names: >> >> function to_slv(code: FIFO_CNTL_SM_TYPE) >> return std_logic_vector >> is >> constant LAST: integer := >> FIFO_CNTL_SM_TYPE'POS(FIFO_CNTL_SM_TYPE'HIGH); >> variable result: std_logic_vector(0 to LAST); >> begin >> result := (others => '0'); >> result(FIFO_CNTL_SM_TYPE'POS(code)) := '1'; >> return result; >> end; >> >> If you're short of pins on the ChipScope, you could >> simply convert the integer FIFO_CNTL_SM_TYPE'POS(code) >> to a std_logic_vector and put that out instead. >> >> XST is happy with the 'POS and 'HIGH attributes; I'm >> not sure it will be OK in all synthesis tools, >> although there's really no excuse for it not being. >> >> Do be aware that adding any such decoder, to observe >> an enumerated signal, may change the optimization >> so that the enumeration is encoded differently. >> > > Hi Jonathan, > > Thanks for your concise description, it's exactly the guidance I needed. > Being new to FPGA's I did not realize how gash these tools were. > > As regards , changing the logic/ optimization, I'm already aware of that. > when I try and put my chipscope external to my user_logic and probe > internally, sometimes the stuff is accessible , other times it disappears, I > keep looking to see if paul Daniels is behind me.. > > Like I say these tools and systems are gash, good job Xilinx would never > dare charging for them. ;-) > > Just trying this...... > It looks like it will not work, after adding in the library , it compiles > fine, but as soon as it links up to chipscope.... > to_slv(xxx) > > FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application > has discovered an exceptional condition from which it cannot recover. > Process will terminate. For technical support on this issue, please open a > WebCase with this project attached at http://www.xilinx.com/support. > > > > Steve > > > With a simple SM you can use a simple approach, TRIGs(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0'; TRIGs(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0'; TRIGs(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0'; If XST use one-hot encoding this code are only connections. Walter, From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!newsgate.cuhk.edu.hk!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 11:37:57 -0300 Organization: W Software & FPGA Services Lines: 20 Message-ID: References: NNTP-Posting-Host: 190.135.52.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: adenine.netfront.net 1246631878 97301 190.135.52.204 (3 Jul 2009 14:37:58 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Fri, 3 Jul 2009 14:37:58 +0000 (UTC) User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1597 steve escribió: > > As regards , changing the logic/ optimization, I'm already aware of that. > when I try and put my chipscope external to my user_logic and probe > internally, sometimes the stuff is accessible , other times it disappears, I > keep looking to see if paul Daniels is behind me.. > > Like I say these tools and systems are gash, good job Xilinx would never > dare charging for them. ;-) > FPGA and Xilinx software are not easy to drive, as a Porsche, but when you know how; you have a good chance to win; user_logic sound as you are using others cores into your project, correct ? Walter From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!s9g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 08:08:51 -0700 (PDT) Organization: http://groups.google.com Lines: 72 Message-ID: <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246633731 2980 127.0.0.1 (3 Jul 2009 15:08:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 15:08:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000yqd.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1) Gecko/20090624 Firefox/3.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1598 comp.arch.fpga:4640 comp.lang.verilog:574 On Jul 2, 8:23=A0pm, steve wrote: > On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote > (in article > <68320efd-477b-4818-95dd-d4639d7e2...@n19g2000vba.googlegroups.com>): > > > > > On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" > > wrote: > >> On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: > > >>> Group for People Involved In the Design and Verification of FPGA's, > >>> other Programmable Logic , and CPLD's to Exchange Idea's and > >>> Techniques. You should have FPGA / CPLD Design / Verification on your > >>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to > >>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > >>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > >>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > >>> Synopsys, Aldec, NI, Altium, and Many Others. > > >>> Networking on LinkedIn can be a way to get technical questions > >>> answered. It can also be a way to meet contacts with expertise in > >>> other domains of knowledge other than your own. Additionally, many > >>> career enhancing contacts, and mentors can potentially found > >>> especially if one is at a smaller company that lacks the resources fo= r > >>> extensive internal networking. > > >>>http://www.linkedin.com/groups?about=3D&gid=3D56713 > > >>> Website:https://sites.google.com/site/fpgacpldgroup/ > > >> could you describe the last technical FPGA related question > >> that your linkedin networking group solved? > > >> unless you are able todo that, i see you repeated postings > >> to c.a.f. as complete spam > > >> Antti > > > Hi, I am one of the moderators at this group and I must be honest > > about it. =A0It is not a very technically oriented group. =A0I have tri= ed > > to make some technically oriented posts there with few responses. > > This did not seem to stimulate much in the way of subsequent new > > topics either. =A0I have also made an effort to separate the technical > > content from the recruiting content and gotten feedback that the > > recruiters are the ones paying the way for LinkedIn and cutting them > > out would be a mistake. > > > So I have given up on this group as well as other FPGA related groups > > at LinkedIn. =A0I have not removed myself from membership, but I can't > > say I recommend them unless you wish to use it for employment or self > > promotion. > > > Rick > > =A0I'm completely confused as to how you can have a FPGA =A0group that is= not =A0 > "technically orientated" , it would be like having a flower arranging cla= ss > without the flowers. There are other aspects to any occupation than just the technical issues. LinkedIn is oriented toward the business issues such as getting a job or filling a job. As much as I would like to see it be more technical, it seems like it is pretty firmly rooted in networking with technical discussions being secondary. Is it really that odd to consider? Rick From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.enother.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 03 Jul 2009 10:23:02 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 16:19:43 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-HvheMkFx02qVM+fr/bncArUU0uUBPt9/Ok4WRMJfv9vE/2iw9QNYCHPIEgst9sqGYiVSxhH1PWn6iPl!gDCgjbtnHRxgvhLHMV5HdrVgcjNj7WUHCfR/T2XLOihcIYlONQkZHGpLfjboQn2EipXH0bRKVuy0!fF1Gz+Cs9TouxOLC X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1599 On Fri, 3 Jul 2009 18:48:55 +0800, steve wrote: >It looks like it will not work, after adding in the library , it compiles >fine, but as soon as it links up to chipscope.... >to_slv(xxx) > >FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application >has discovered an exceptional condition from which it cannot recover. That'll be a bug, then :-) I'd guess it's related to the use of a conversion function in the port map, which is perfectly legal but isn't so commonly used, so maybe has not been debugged as thoroughly as one might hope. Try using the conversion function to put the value onto a new std_logic_vector signal, and then hook that signal to the appropriate ports. Might give the tools rather less of a headache. I synthesized a small design with the conversion function in it, so there's no fundamental problem! Walter's simpler approach needs an extra signal in any case. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!h18g2000yqj.googlegroups.com!not-for-mail From: chewie Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: TimingAnalyzer is now freeware Date: Fri, 3 Jul 2009 08:52:07 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <851eb257-c850-4e4c-a1e5-638e4752bafe@h18g2000yqj.googlegroups.com> References: <9ee29b6f-36e1-4121-9d5b-a242a6f2684b@d32g2000yqh.googlegroups.com> NNTP-Posting-Host: 76.98.36.115 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246636327 20604 127.0.0.1 (3 Jul 2009 15:52:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 15:52:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h18g2000yqj.googlegroups.com; posting-host=76.98.36.115; posting-account=40YgGgoAAAB0oRRqyBM1Zw2iHONFVNnk User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.0.11) Gecko/2009060214 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4643 comp.lang.vhdl:1600 comp.lang.verilog:576 On Jul 3, 9:18=A0am, James Harris wrote: > On 20 June, 16:51, timinganalyzer wrote: > > > > > Hi All, > > > I just wanted to let you know that the TimingAnalyzer is now licensed > > as freeware. =A0 I just don't have the time needed to make a high > > quality commercial product but I do want to keep the development > > moving forward and continue to fix problems and add new features as > > time permits. > > > Recently, I have become very interested in Python and using it to > > develop similar type cad programs. =A0My plan is to convert the > > TimingAnalyzer Java to Python with mostly a scripting interface for > > building complex timing diagrams, doing timing analysis, =A0creating > > testbenches and testvectors from waveform diagrams, > > and creating timing diagrams from simulation VCD files. =A0Most all of > > this is text based work anyway. > > > Developing professional GUIs is very time consuming for me. =A0This has > > been my bottleneck with the program all along. =A0With a command line > > interface, =A0you will execute a script and in one window, =A0and view = and > > edit and print the timing diagram shown in another window. =A0 Like > > Matlab interface. > > > If anyone is interested in helping with the development, =A0I will make > > this an open source project. =A0 Just let me know if your interested. > > I prefer command-line interfaces in general. They are more flexible > and can be automated. > > Good choice to move to Python as long as the speed holds up. You may > want to inclulde comp.lang.python. > > James Thanks James. I did post a similar message on comp.lang.python. If there are some speed bottlenecks in Python, there is always the option of writing only those parts in a C extension. From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 09:18:49 -0700 Lines: 14 Message-ID: <7b6pb9F229lspU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net WnhmmkjBw0eGnSLOv5+65Q6V5nXUmoNoNpW/f/bv1mPqADs+Vb Cancel-Lock: sha1:/3fsf8YjpHNclxeEBJY9wk1Wnhw= User-Agent: Thunderbird 2.0.0.19 (X11/20081227) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1601 steve wrote: > It is better you do not comment if you do not read the post. Got it. On thunderbird that's Message, Create filter from message, OK -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!e21g2000yqb.googlegroups.com!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 3 Jul 2009 10:44:18 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> NNTP-Posting-Host: 190.135.58.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246643058 725 127.0.0.1 (3 Jul 2009 17:44:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 17:44:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000yqb.googlegroups.com; posting-host=190.135.58.172; posting-account=iKewXwoAAABMdzxglOc51qcPJlFEv-hI User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; es-AR; rv:1.9.0.11) Gecko/2009060310 Ubuntu/8.10 (intrepid) Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1602 On 3 jul, 12:19, Jonathan Bromley wrote: > > Walter's simpler approach needs an extra signal > in any case. I make a mistake; TRIGs must be TRIG2 but where is the "extra" signal ? TRIG2(x) must be directly connected to FFx; Walter. From newsfish@newsfish Wed Aug 19 13:25:28 2009 Path: feeder.eternal-september.org!eternal-september.org!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "MM" Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 13:47:52 -0400 Lines: 27 Message-ID: <7b6uklF22hbunU1@mid.individual.net> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> X-Trace: individual.net 8G82Y6REc0rjHxuv6BecrgEnRBn6O3p55HOuJq2w1pYKajdU2d Cancel-Lock: sha1:6iP2keK1Qm+qH/fknDjMa1UQylU= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 Xref: eternal-september.org comp.lang.vhdl:1603 comp.arch.fpga:4648 comp.lang.verilog:577 "rickman" wrote in message news:8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com... On Jul 2, 8:23 pm, steve wrote: > > There are other aspects to any occupation than just the technical > issues. LinkedIn is oriented toward the business issues such as > getting a job or filling a job. As much as I would like to see it be > more technical, it seems like it is pretty firmly rooted in networking > with technical discussions being secondary. > > Is it really that odd to consider? > > Rick A bigger problem is how technical discussions are set up (or at least used to be set up when I last looked) and viewed on LinkedIn. Answering questions is supposed to earn you points to improve your image. The questions remain active for only limited period of time upon expiration of which no one can contribute. Finally, you need to be a premium (read paid) member to be able to send a private message to another member. /Mikhail From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a36g2000yqc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 11:53:39 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> <7b6uklF22hbunU1@mid.individual.net> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246647220 14477 127.0.0.1 (3 Jul 2009 18:53:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 18:53:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a36g2000yqc.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1) Gecko/20090624 Firefox/3.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1604 comp.arch.fpga:4650 comp.lang.verilog:578 On Jul 3, 1:47=A0pm, "MM" wrote: > "rickman" wrote in message > > news:8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com... > On Jul 2, 8:23 pm, steve wrote: > > > > > There are other aspects to any occupation than just the technical > > issues. =A0LinkedIn is oriented toward the business issues such as > > getting a job or filling a job. =A0As much as I would like to see it be > > more technical, it seems like it is pretty firmly rooted in networking > > with technical discussions being secondary. > > > Is it really that odd to consider? > > > Rick > > A bigger problem is how technical discussions are set up (or at least use= d > to be set up when I last looked) and viewed on LinkedIn. Answering questi= ons > is supposed to earn you points to improve your image. The questions remai= n > active for only limited period of time upon expiration of which no one ca= n > contribute. Finally, you need to be a premium (read paid) member to be ab= le > to send a private message to another member. > > /Mikhail I have not seen anything about points on LinkedIn. I think the only way to "improve" your image at LinkedIn is what you put in your profile. LinkedIn does not rate anyone that I am aware of. I think you may be remembering a different site than LinkedIn. They don't limit the time to reply to a discussion and I am not a paid member and I can send private messages. If I could find you, I would send you a private message to demonstrate, but there are a lot of Mikhails on LinkedIn. Rick From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!weretis.net!feeder2.news.weretis.net!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "MM" Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 15:46:41 -0400 Lines: 27 Message-ID: <7b75jjF22g63aU1@mid.individual.net> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> <7b6uklF22hbunU1@mid.individual.net> <7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com> X-Trace: individual.net 93KC872O3Gc4f0mc/T+CeQlUWD9LlR6ZANNuVApJWRZqlOAK9I Cancel-Lock: sha1:a+xqUneUgppDlx91H2GPi5YyydI= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 Xref: eternal-september.org comp.lang.vhdl:1605 comp.arch.fpga:4654 comp.lang.verilog:579 "rickman" wrote in message news:7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com... On Jul 3, 1:47 pm, "MM" wrote: > >I have not seen anything about points on LinkedIn. I think the only >way to "improve" your image at LinkedIn is what you put in your >profile. LinkedIn does not rate anyone that I am aware of. > >I think you may be remembering a different site than LinkedIn. They >don't limit the time to reply to a discussion and I am not a paid >member and I can send private messages. If I could find you, I would >send you a private message to demonstrate, but there are a lot of >Mikhails on LinkedIn. I should have put points in quote marks. There is no rating, but there is an option to see all the answers by a person. I am not confusing LinkedIn with another site but I might be confusing discussions in its groups with its Answers section though. With regards to the private mail, it seems as they have recently changed their policy. It used to be that you could only send a message to someone in your network, for anyone else the only type of message you could send was an invitation to join your network. /Mikhail From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 03 Jul 2009 14:48:06 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 20:44:48 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-L7ns2xM4LiGEgLIfyUSvLhTpB53P1u64j/8oTTRP4CG1UTVmvGBZ8DjZy1C+eePBzFt73TV9k6iqrwK!+7vIOw3Krfcnn/Dr5MBoDsSuPyqZ5I15xm75YX4lImXkfXV15OjRIJAMepTh6AQLGFjagoEEiShL!TqmFiOufy9c57V78 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1606 On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: > where is the "extra" signal ? >TRIG2(x) must be directly connected to FFx; I agree that there is no new hardware. In the original post, steve wrote: > TRIG2(31 downto ????) => fifo_cntl_cs , In other words, TRIG2() is not a signal in his design; it's a port on the ChipScope instance. So it's impossible to write what you suggested; it's necessary to declare an additional signal, use the three assignments to put the appropriate values on that signal, and then attach that signal to the ChipScope port. Nothing more than that: you need to declare a suitable signal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!newsgate.cuhk.edu.hk!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Fri, 03 Jul 2009 19:06:43 -0300 Organization: W Software & FPGA Services Lines: 51 Message-ID: <4A4E80F3.3010803@adinet.com.uy> References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> NNTP-Posting-Host: 190.135.58.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: adenine.netfront.net 1246658804 7393 190.135.58.172 (3 Jul 2009 22:06:44 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Fri, 3 Jul 2009 22:06:44 +0000 (UTC) To: jonathan.bromley@MYCOMPANY.com Disposition-Notification-To: Walter User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1607 Jonathan Bromley escribió: > On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: > >> where is the "extra" signal ? >> TRIG2(x) must be directly connected to FFx; > > I agree that there is no new hardware. > > In the original post, steve wrote: > >> TRIG2(31 downto ????) => fifo_cntl_cs , > > In other words, TRIG2() is not a signal in > his design; it's a port on the ChipScope > instance. So it's impossible to write what > you suggested; it's necessary to declare > an additional signal, use the three assignments > to put the appropriate values on that signal, > and then attach that signal to the ChipScope > port. > > Nothing more than that: you need to declare > a suitable signal. I agree, as basic as I forget to mention... Here a more "complete" simple solution to a simple problem. .. SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0); .. TRIG2(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0'; TRIG2(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0'; TRIG2(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0'; --- IN CHIPSCOPE INSTANCE --- ... TRIG2 => TRIG2, ... When in trainings I recommend to all write code as simple as possible, many times "complex" solutions or no common used structures are poorly supported or totally unsupported in one or other synthesis tool. I like your solution as generic solution, but if I have a more "standard" or low level solution, thinking in the synthesis tool, I take it. Walter. From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r33g2000yqn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Fri, 3 Jul 2009 15:45:00 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: <273f7256-121b-45e0-b08f-033f82b3872b@r33g2000yqn.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> <7b6uklF22hbunU1@mid.individual.net> <7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com> <7b75jjF22g63aU1@mid.individual.net> NNTP-Posting-Host: 64.241.37.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246661100 26968 127.0.0.1 (3 Jul 2009 22:45:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Jul 2009 22:45:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r33g2000yqn.googlegroups.com; posting-host=64.241.37.140; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1) Gecko/20090624 Firefox/3.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1608 comp.arch.fpga:4657 comp.lang.verilog:581 On Jul 3, 3:46 pm, "MM" wrote: > "rickman" wrote in message > > news:7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com... > On Jul 3, 1:47 pm, "MM" wrote: > > > > >I have not seen anything about points on LinkedIn. I think the only > >way to "improve" your image at LinkedIn is what you put in your > >profile. LinkedIn does not rate anyone that I am aware of. > > >I think you may be remembering a different site than LinkedIn. They > >don't limit the time to reply to a discussion and I am not a paid > >member and I can send private messages. If I could find you, I would > >send you a private message to demonstrate, but there are a lot of > >Mikhails on LinkedIn. > > I should have put points in quote marks. There is no rating, but there is an > option to see all the answers by a person. I am not confusing LinkedIn with > another site but I might be confusing discussions in its groups with its > Answers section though. With regards to the private mail, it seems as they > have recently changed their policy. It used to be that you could only send a > message to someone in your network, for anyone else the only type of message > you could send was an invitation to join your network. > > /Mikhail I believe you are correct about the change. I don't use it that often so I don't recall all the details, but I seem to recall that when I tried to contact someone a while back I had to "invite" them to my network. Fortunately that has changed now. I'm not at all familiar with the Answers section. I guess I just have not explored it a lot. I find the interface to be a bit less than obvious, but then I think that about a lot of web sites like Facebook and Twitter. For example, I can't find a way to reach a human at Twitter to report spam to or to ask to block emails to my domain. I keep getting form emails back about using their support web pages. I guess I will have to resort to the post office. Speaking of Twitter, I got some spam (an invitation to join as one of their "twits") from someone there and I can't find a way to report them. There used to be a law here in Maryland that would allow you to sue a spammer for $500 for each email they knowingly sent to a Maryland state resident. A guy decided to fight back by taking an email address at and started suing spammers. He snared a couple of small time spammers selling BS assembly projects that you could assemble and then get paid for. Of course no one ever made them good enough to get through "quality control". Then a spammer fought back and won in court with the ruling that it would be next to impossible for a spammer to "know" he was spamming a Maryland state resident. Otherwise participation by the State Attorney General is required in order to sue a spammer if I understand the current law. Rick From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news2.google.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 06:57:32 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 48 Message-ID: References: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1609 On Fri, 3 Jul 2009 22:37:57 +0800, Walter wrote (in article ): > steve escribi=F3: >> >> As regards , changing the logic/ optimization, I'm already aware of that. >> when I try and put my chipscope external to my user_logic and probe >> internally, sometimes the stuff is accessible , other times it disappears, >> I >> keep looking to see if paul Daniels is behind me.. >> >> Like I say these tools and systems are gash, good job Xilinx would never >> dare charging for them. ;-) >> > > FPGA and Xilinx software are not easy to drive, as a Porsche, but when > you know how; you have a good chance to win; > > user_logic sound as you are using others cores into your project, correct ? > > Walter > > > Hi walter, Yep, there is a bit of everything , networking , ppc, PLB, OPB2PLB bridge buttons & led's for debugging, it is a computer forensics project for my thesis. But my main issue was the double/triple clocking of a variable that was only supposed to clock once on a signal transition. It of course is controlled by the only signal i could not investigate. my background is software, and we are really spoiled for tools and debugging setups, I was actually shocked at how bad and messy the hardware development kit is. (i might take a look at Altera later) But your solution has been great, I also filed a webcase with xilinx over the above problem. Anyway thanks for helping out a noob. Steve From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 07:01:54 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 46 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1610 On Fri, 3 Jul 2009 23:19:43 +0800, Jonathan Bromley wrote (in article <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com>): > On Fri, 3 Jul 2009 18:48:55 +0800, steve wrote: > >> It looks like it will not work, after adding in the library , it compiles >> fine, but as soon as it links up to chipscope.... >> to_slv(xxx) >> >> FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application >> has discovered an exceptional condition from which it cannot recover. > > That'll be a bug, then :-) > > I'd guess it's related to the use of a conversion > function in the port map, which is perfectly legal > but isn't so commonly used, so maybe has not been > debugged as thoroughly as one might hope. > > Try using the conversion function to put the value > onto a new std_logic_vector signal, and then hook > that signal to the appropriate ports. Might give > the tools rather less of a headache. I synthesized > a small design with the conversion function in it, > so there's no fundamental problem! > > Walter's simpler approach needs an extra signal > in any case. > That was my second thought :-) , and the damned thing compiles and works!! You can stick the result of the conversion into a variable: signal dummy :std_logic_vector (0 to NAND_WR_SM_TYPE'POS(NAND_WR_SM_TYPE'HIGH)); ...... TRIG3(0 to NAND_WR_SM_TYPE'POS(NAND_WR_SM_TYPE'HIGH)) => dummy, --"000", --to_slv(nand_wr_ns), once I had the 'mental' tools , the solution presented it's self. Steve From newsfish@newsfish Wed Aug 19 13:25:29 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 07:06:59 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 65 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1611 On Sat, 4 Jul 2009 03:44:48 +0800, Jonathan Bromley wrote (in article ): > On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: > >> where is the "extra" signal ? >> TRIG2(x) must be directly connected to FFx; > > I agree that there is no new hardware. > > In the original post, steve wrote: > >> TRIG2(31 downto ????) => fifo_cntl_cs , > > In other words, TRIG2() is not a signal in > his design; it's a port on the ChipScope > instance. So it's impossible to write what > you suggested; it's necessary to declare > an additional signal, use the three assignments > to put the appropriate values on that signal, > and then attach that signal to the ChipScope > port. > > Nothing more than that: you need to declare > a suitable signal. > Yep the chipscope comes in as: component icon PORT ( CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)); end component; component ila PORT ( CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CLK : IN STD_LOGIC; TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); TRIG2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0); TRIG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); end component; sorry I thought this would be common code , so i did not post it. This is built using the code generator. I don't use the data ports, but instead tie my signals to the trigger ports, so i can use any of them to trigger on. Steve From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 07:13:21 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 78 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> <4A4E80F3.3010803@adinet.com.uy> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1612 On Sat, 4 Jul 2009 06:06:43 +0800, Walter wrote (in article <4A4E80F3.3010803@adinet.com.uy>): > Jonathan Bromley escribi=F3: >> On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: >> >>> where is the "extra" signal ? >>> TRIG2(x) must be directly connected to FFx; >> >> I agree that there is no new hardware. >> >> In the original post, steve wrote: >> >>> TRIG2(31 downto ????) =3D> fifo_cntl_cs , >> >> In other words, TRIG2() is not a signal in >> his design; it's a port on the ChipScope >> instance. So it's impossible to write what >> you suggested; it's necessary to declare >> an additional signal, use the three assignments >> to put the appropriate values on that signal, >> and then attach that signal to the ChipScope >> port. >> >> Nothing more than that: you need to declare >> a suitable signal. > > I agree, as basic as I forget to mention... > > Here a more "complete" simple solution to a simple problem. > > .. > SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0); > > > .. > TRIG2(31) <=3D '1' WHEN fifo_cntl_cs =3D IDLE ELSE '0'; > TRIG2(30) <=3D '1' WHEN fifo_cntl_cs =3D RD_REQ ELSE '0'; > TRIG2(29) <=3D '1' WHEN fifo_cntl_cs =3D WR_REQ ELSE '0'; > > --- IN CHIPSCOPE INSTANCE --- > ... > TRIG2 =3D> TRIG2, > ... > > When in trainings I recommend to all write code as simple as possible, > many times "complex" solutions or no common used structures are poorly > supported or totally unsupported in one or other synthesis tool. > I like your solution as generic solution, but if I have a more > "standard" or low level solution, thinking in the synthesis tool, I take > it. > > Walter. > Hi walter, It's only 'simple' if you are a diehard VHDL programmer , I'm 2 weeks into this, have all the xilix documentation and god knows how many VHDL books No where in chipscopes manuals is this mentioned, but it is exactly the sort of thing people need to debug. But what is really anoying , is the fact that you cannot turn off sections of VHDL optimization to stop signals disappearing. (yes I know about keep and noopt ,but they don't make a difference) Steve From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 11:19:44 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 61 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> <4A4E80F3.3010803@adinet.com.uy> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1613 On Sat, 4 Jul 2009 06:06:43 +0800, Walter wrote (in article <4A4E80F3.3010803@adinet.com.uy>): > Jonathan Bromley escribi=F3: >> On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: >> >>> where is the "extra" signal ? >>> TRIG2(x) must be directly connected to FFx; >> >> I agree that there is no new hardware. >> >> In the original post, steve wrote: >> >>> TRIG2(31 downto ????) =3D> fifo_cntl_cs , >> >> In other words, TRIG2() is not a signal in >> his design; it's a port on the ChipScope >> instance. So it's impossible to write what >> you suggested; it's necessary to declare >> an additional signal, use the three assignments >> to put the appropriate values on that signal, >> and then attach that signal to the ChipScope >> port. >> >> Nothing more than that: you need to declare >> a suitable signal. > > I agree, as basic as I forget to mention... > > Here a more "complete" simple solution to a simple problem. > > .. > SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0); > > > .. > TRIG2(31) <=3D '1' WHEN fifo_cntl_cs =3D IDLE ELSE '0'; > TRIG2(30) <=3D '1' WHEN fifo_cntl_cs =3D RD_REQ ELSE '0'; > TRIG2(29) <=3D '1' WHEN fifo_cntl_cs =3D WR_REQ ELSE '0'; > > --- IN CHIPSCOPE INSTANCE --- > ... > TRIG2 =3D> TRIG2, > ... > > When in trainings I recommend to all write code as simple as possible, > many times "complex" solutions or no common used structures are poorly > supported or totally unsupported in one or other synthesis tool. > I like your solution as generic solution, but if I have a more > "standard" or low level solution, thinking in the synthesis tool, I take > it. > > Walter. > Hi Walter, just to let you know this was the only solution that worked out finally. steve From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!border1.nntp.dca.giganews.com!nntp.giganews.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 4 Jul 2009 11:22:33 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 63 Message-ID: References: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1614 On Fri, 3 Jul 2009 16:55:47 +0800, Jonathan Bromley wrote (in article ): > On Fri, 3 Jul 2009 09:19:32 +0800, steve wrote: > >> BUT I have the following user enumerated types >> >> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ); >> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE; >> >> how do i mask this damned thing into chipscope, I just get errors about the >> types not matching,. >> >> TRIG2(31 downto ????) => fifo_cntl_cs , > > You need a conversion function. > > TRIG2(31 downto 29) => to_slv(fifo_cntl_cs), > > You don't want to introduce any additional logic if you > can avoid it, so it makes sense for the conversion > function to match the internal encoding that XST has > created - see Mike's post. > > In practice that's likely to be one-hot. So you could do > something like this in which each output represents one > state. It has the advantage that it won't > need to be rewritten if you add or change state names: > > function to_slv(code: FIFO_CNTL_SM_TYPE) > return std_logic_vector > is > constant LAST: integer := > FIFO_CNTL_SM_TYPE'POS(FIFO_CNTL_SM_TYPE'HIGH); > variable result: std_logic_vector(0 to LAST); > begin > result := (others => '0'); > result(FIFO_CNTL_SM_TYPE'POS(code)) := '1'; > return result; > end; > > If you're short of pins on the ChipScope, you could > simply convert the integer FIFO_CNTL_SM_TYPE'POS(code) > to a std_logic_vector and put that out instead. > > XST is happy with the 'POS and 'HIGH attributes; I'm > not sure it will be OK in all synthesis tools, > although there's really no excuse for it not being. > > Do be aware that adding any such decoder, to observe > an enumerated signal, may change the optimization > so that the enumeration is encoded differently. > Hi Jonathan, this worked fine for one instance , but even with 50% of the FPGA spare , I started getting routing errors if I did more than one instance of a variable, which is real stupid when I think about it. I guess it's down to some interaction with chipscope. From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!nx01.iad01.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 04 Jul 2009 06:41:53 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 04 Jul 2009 12:45:42 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-stJdXdb16Hkw/Jt/eP4/1Nrln/eJhiFhi/9pMsqww20vEWCB9B/XrfXlPVj7psYO2H/9BjNq4p0xzoK!9TbmE/s0Gg/04CANda9Lr8DBOSdBVA6d8RPWy543Z6fmUGiP7dmJIelMinAoLMBl3fXrtG5ERA26!Dqtp X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2478 Xref: eternal-september.org comp.lang.vhdl:1616 On Fri, 03 Jul 2009 16:19:43 +0100, Jonathan Bromley wrote: >On Fri, 3 Jul 2009 18:48:55 +0800, steve wrote: > >>It looks like it will not work, after adding in the library , it compiles >>fine, but as soon as it links up to chipscope.... >>to_slv(xxx) >> >>FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application >>has discovered an exceptional condition from which it cannot recover. > >That'll be a bug, then :-) > >I'd guess it's related to the use of a conversion >function in the port map, which is perfectly legal >but isn't so commonly used, so maybe has not been >debugged as thoroughly as one might hope. Possibly because the Chipscope core is a black box, or something other than VHDL, so XST doesn't have access to both sides of the port. I have also brought XST down with port type conversions. Can't remember where; probably connecting to a memory model only available in Verilog. >Try using the conversion function to put the value >onto a new std_logic_vector signal, and then hook >that signal to the appropriate ports. Definitely the answer in this case. (More of a headache with an inout port!) - Brian From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!newsgate.cuhk.edu.hk!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 04 Jul 2009 11:44:36 -0300 Organization: W Software & FPGA Services Lines: 86 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> <4A4E80F3.3010803@adinet.com.uy> NNTP-Posting-Host: 190.135.3.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit X-Trace: adenine.netfront.net 1246718677 78933 190.135.3.19 (4 Jul 2009 14:44:37 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Sat, 4 Jul 2009 14:44:37 +0000 (UTC) User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1617 steve escribió: > On Sat, 4 Jul 2009 06:06:43 +0800, Walter wrote > (in article <4A4E80F3.3010803@adinet.com.uy>): > >> Jonathan Bromley escribió: >>> On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote: >>> >>>> where is the "extra" signal ? >>>> TRIG2(x) must be directly connected to FFx; >>> I agree that there is no new hardware. >>> >>> In the original post, steve wrote: >>> >>>> TRIG2(31 downto ????) => fifo_cntl_cs , >>> In other words, TRIG2() is not a signal in >>> his design; it's a port on the ChipScope >>> instance. So it's impossible to write what >>> you suggested; it's necessary to declare >>> an additional signal, use the three assignments >>> to put the appropriate values on that signal, >>> and then attach that signal to the ChipScope >>> port. >>> >>> Nothing more than that: you need to declare >>> a suitable signal. >> I agree, as basic as I forget to mention... >> >> Here a more "complete" simple solution to a simple problem. >> >> .. >> SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0); >> >> >> .. >> TRIG2(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0'; >> TRIG2(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0'; >> TRIG2(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0'; >> >> --- IN CHIPSCOPE INSTANCE --- >> ... >> TRIG2 => TRIG2, >> ... >> >> When in trainings I recommend to all write code as simple as possible, >> many times "complex" solutions or no common used structures are poorly >> supported or totally unsupported in one or other synthesis tool. >> I like your solution as generic solution, but if I have a more >> "standard" or low level solution, thinking in the synthesis tool, I take >> it. >> >> Walter. >> > > Hi Walter, > > just to let you know this was the only solution that worked out finally. > > steve > Hi steve, As Jonathan remark, you can't assign values in this form directly to a component port. The work around is doing with de help of an extra signal : SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0); make the signal assignments : TRIG2(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0'; TRIG2(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0'; TRIG2(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0'; if others bits of TRIG2 still unconnected place a '0' on each, think, the syntheses tool, the ChipScope IP mmm...? Take safe way. and then connect the signal to CHIPSCOPE instance port with : TRIG2 => TRIG2, No extra logic was created (if you use one-hot encoding) your state machine FF was conected to CHIPSCOPE trig/data inputs. Walter From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!zen.net.uk!dedekind.zen.co.uk!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sat, 04 Jul 2009 12:14:54 -0300 Organization: W Software & FPGA Services Lines: 12 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> <4A4E80F3.3010803@adinet.com.uy> NNTP-Posting-Host: 190.135.27.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit X-Trace: adenine.netfront.net 1246720494 82353 190.135.27.15 (4 Jul 2009 15:14:54 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Sat, 4 Jul 2009 15:14:54 +0000 (UTC) User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:1618 Walter escribió: > > The work around is doing with de help of an extra signal : > > Apologies, "The work around is doing with help of an extra signal :" Walter, From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: "MM" Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Sat, 4 Jul 2009 23:02:04 -0400 Lines: 9 Message-ID: <7baji6F22q7e6U1@mid.individual.net> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> <7b6uklF22hbunU1@mid.individual.net> <7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com> <7b75jjF22g63aU1@mid.individual.net> <273f7256-121b-45e0-b08f-033f82b3872b@r33g2000yqn.googlegroups.com> X-Trace: individual.net qMT+93FPrGiUGFxnJ90QRwFJjIpTRoC4MoGAIupoF41u+tTHU1 Cancel-Lock: sha1:nHGSnCdldhqIsdx0bH0SP4hfjG0= X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3198 X-RFC2646: Format=Flowed; Original Xref: eternal-september.org comp.lang.vhdl:1619 comp.arch.fpga:4682 comp.lang.verilog:584 "rickman" wrote > > For example, I can't find a way to reach a human at Twitter Why on earth a grown man would want to use Twitter? :) /Mikhail From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!24g2000yqm.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Sat, 4 Jul 2009 23:16:58 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <15179e48-1cf4-4f69-bf54-6a43a9379ae4@24g2000yqm.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <8d00a3a1-3187-4421-aed4-6b1df3c71b97@s9g2000yqd.googlegroups.com> <7b6uklF22hbunU1@mid.individual.net> <7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com> <7b75jjF22g63aU1@mid.individual.net> <273f7256-121b-45e0-b08f-033f82b3872b@r33g2000yqn.googlegroups.com> <7baji6F22q7e6U1@mid.individual.net> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246774618 32520 127.0.0.1 (5 Jul 2009 06:16:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Jul 2009 06:16:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 24g2000yqm.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1) Gecko/20090624 Firefox/3.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1620 comp.arch.fpga:4683 comp.lang.verilog:585 On Jul 4, 11:02=A0pm, "MM" wrote: > "rickman" wrote > > > > > For example, I can't find a way to reach a human at Twitter > > Why on earth a grown man would want to use Twitter? :) > > /Mikhail I'm not trying to *use* it, I want them to stop sending me junk email! Didn't you read the post? Rick From newsfish@newsfish Wed Aug 19 13:25:30 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Sun, 5 Jul 2009 14:41:53 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 33 Message-ID: References: <748s45hkmqurk1bhgjr5gvoqfk123tlmj0@4ax.com> <24db3bbe-2398-42cd-a73c-d377cfffd870@e21g2000yqb.googlegroups.com> <4A4E80F3.3010803@adinet.com.uy> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1621 On Sat, 4 Jul 2009 23:14:54 +0800, Walter wrote (in article ): > Walter escribi=F3: > >> >> The work around is doing with de help of an extra signal : >> >> > > Apologies, > > "The work around is doing with help of an extra signal :" > > Walter, Hi walter , yep i got it working. Just one last question: on an "out" port: ram_rb : out std_logic; ram_data_O : out std_logic_vector(7 downto 0); ram_data_T : out std_logic; what is the best way to tap into this to feed it into chipscope ? Keeping in mind that there are about 20 places in the code where it is set & unset...... tying them directly to chipscope WHEN chipscope is IN your user_logic will not work. Steve From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!gnilink.net!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Spartan 3E Date: Sun, 5 Jul 2009 14:50:00 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 17 Message-ID: References: <236ef17d-f983-4db4-b5a1-9af39bb3b404@y6g2000prf.googlegroups.com> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1622 On Fri, 26 Jun 2009 15:18:57 +0800, Amit wrote (in article <236ef17d-f983-4db4-b5a1-9af39bb3b404@y6g2000prf.googlegroups.com>): > > Hello group, > > Does anybody know any resource that I can use for Spartan 3E I > recently have bought? I need to use some basic codes and run them > using the board. > I've planned to use VHDL. > > Thanks, > Amit Google is your friend From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!multikabel.net!newsfeed20.multikabel.net!pfeed08.wxs.nl!newsfeed.kpn.net!pfeed14.wxs.nl!pfeed15.wxs.nl!not-for-mail From: nico@puntnl.niks (Nico Coesel) Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Sun, 05 Jul 2009 08:23:01 GMT Message-ID: <4a506294.2904187875@news.planet.nl> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> X-Newsreader: Forte Free Agent 1.21/32.243 Lines: 54 NNTP-Posting-Host: 213.10.147.3 X-Trace: 1246782171 textnews.kpn.nl 1638 213.10.147.3:4445 X-Complaints-To: abuse@planet.nl Xref: eternal-september.org comp.lang.vhdl:1623 comp.arch.fpga:4686 comp.lang.verilog:586 steve wrote: >On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote >(in article ><68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com>): > >> On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" >> wrote: >>> On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: >>> >>> >>> >>>> Group for People Involved In the Design and Verification of FPGA's, >>>> other Programmable Logic , and CPLD's to Exchange Idea's and >>>> Techniques. You should have FPGA / CPLD Design / Verification on your >>>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to >>>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC >>>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, >>>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, >>>> Synopsys, Aldec, NI, Altium, and Many Others. >>> >>> could you describe the last technical FPGA related question >>> that your linkedin networking group solved? >>> >>> unless you are able todo that, i see you repeated postings >>> to c.a.f. as complete spam >>> >>> Antti >> >> Hi, I am one of the moderators at this group and I must be honest >> about it. It is not a very technically oriented group. I have tried >> to make some technically oriented posts there with few responses. >> out would be a mistake. >> >> So I have given up on this group as well as other FPGA related groups >> at LinkedIn. I have not removed myself from membership, but I can't >> say I recommend them unless you wish to use it for employment or self >> promotion. >> >> Rick > > I'm completely confused as to how you can have a FPGA group that is not >"technically orientated" , it would be like having a flower arranging class >without the flowers. LinkedIn is not about solving problems. It is about hiring the right people to solve problems. To get back to your example: you could find someone thru LinkedIn that can arrange the flowers for you. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... "If it doesn't fit, use a bigger hammer!" -------------------------------------------------------------- From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!13g2000prl.googlegroups.com!not-for-mail From: "bharat1986@gmail.com" Newsgroups: comp.lang.vhdl Subject: How can I access a 2d array completely. Date: Mon, 6 Jul 2009 00:26:41 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <62d2cc61-2129-47cb-af1b-07985f0da762@13g2000prl.googlegroups.com> NNTP-Posting-Host: 220.227.243.139 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246865201 31449 127.0.0.1 (6 Jul 2009 07:26:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Jul 2009 07:26:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 13g2000prl.googlegroups.com; posting-host=220.227.243.139; posting-account=P1dstgoAAACU5lYh6miqZxPa3tZIW-g4 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0),gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 mic.co.in:8080 (squid/2.5.STABLE14) Xref: eternal-september.org comp.lang.vhdl:1625 I have used a 2d array type CRC is array(3 downto 0) of std_logic_vector(7 downto 0); signal Frame_CRC : CRC; now I want to access all the 32 bits in the Frame_CRC... to assign a 32bit signal to that Frame_CRC.. How can I do it??? From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Jul 2009 02:44:27 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: How can I access a 2d array completely. Date: Mon, 06 Jul 2009 08:41:09 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <56a355h4rsqt8p5g95enrb7ss0tgccbom6@4ax.com> References: <62d2cc61-2129-47cb-af1b-07985f0da762@13g2000prl.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 48 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-GAP8TGA9v66HGAd1Fi5GkrGcBAy9ycykguOGsyOPH9vbLsy2gNnkbKFnxeh2kqUxC2YyyEAQfMcOEEH!5qPxUKI+SnaukqawLqmYdPQ92sheJpE/sV3Pp5OxvzeBD+Vh3MTuUsjNR6qwDVujQzeiNTmOQjaK!yrMhNEhxLA7Z+ECI X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1626 On Mon, 6 Jul 2009 00:26:41 -0700 (PDT), wrote: >type CRC is array(3 downto 0) of std_logic_vector(7 downto 0); >signal Frame_CRC : CRC; > >now I want to access all the 32 bits in the Frame_CRC... >to assign a 32bit signal to that Frame_CRC.. By re-assembling them into a single 32-bit vector. Assuming CRC(3) is the most-significant byte: signal CRC32: std_logic_vector(31 downto 0); ... CRC32 <= CRC(3) & CRC(2) & CRC(1) & CRC(0); If you expect to do that more than once, it's better to write functions to convert: subtype slv32 is std_logic_vector(31 downto 0); function to_vec32(Frame_CRC CRC) return slv32 is begin return CRC(3) & CRC(2) & CRC(1) & CRC(0); end; function to_CRC(slv32 crc32) return Frame_CRC is begin return ( 0 => crc32(7 downto 0), 1 => crc32(15 downto 8), 2 => crc32(23 downto 16), 3 => crc32(31 downto 24) ); end; If you find yourself using 2-d arrays a great deal, you may wish to write more general pack/unpack functions using for-loops and the 'RANGE attributes. But the examples I've given are easy to understand, and do the job for your specific problem. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cyclone1.gnilink.net!gnilink.net!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Mon, 6 Jul 2009 21:02:42 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 60 Message-ID: References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <4a506294.2904187875@news.planet.nl> Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1627 comp.arch.fpga:4706 comp.lang.verilog:588 On Sun, 5 Jul 2009 16:23:01 +0800, Nico Coesel wrote (in article <4a506294.2904187875@news.planet.nl>): > steve wrote: > >> On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote >> (in article >> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com>): >> >>> On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" >>> wrote: >>>> On Jun 28, 5:09=A0pm, cpld-fpga-asic wrote: >>>> >>>> >>>> >>>>> Group for People Involved In the Design and Verification of FPGA's, >>>>> other Programmable Logic , and CPLD's to Exchange Idea's and >>>>> Techniques. You should have FPGA / CPLD Design / Verification on your >>>>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to >>>>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC >>>>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, >>>>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, >>>>> Synopsys, Aldec, NI, Altium, and Many Others. >>>> >>>> could you describe the last technical FPGA related question >>>> that your linkedin networking group solved? >>>> >>>> unless you are able todo that, i see you repeated postings >>>> to c.a.f. as complete spam >>>> >>>> Antti >>> >>> Hi, I am one of the moderators at this group and I must be honest >>> about it. It is not a very technically oriented group. I have tried >>> to make some technically oriented posts there with few responses. >>> out would be a mistake. >>> >>> So I have given up on this group as well as other FPGA related groups >>> at LinkedIn. I have not removed myself from membership, but I can't >>> say I recommend them unless you wish to use it for employment or self >>> promotion. >>> >>> Rick >> >> I'm completely confused as to how you can have a FPGA group that is not >> "technically orientated" , it would be like having a flower arranging class >> without the flowers. > > LinkedIn is not about solving problems. It is about hiring the right > people to solve problems. To get back to your example: you could find > someone thru LinkedIn that can arrange the flowers for you. > > we are not talking about "linkedin" ,we are talking about a technical group within the "LI" network. If you cannot keep up, there is Lego and crayons over in the play area. From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Jul 2009 08:15:46 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Mon, 06 Jul 2009 14:12:28 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <4a506294.2904187875@news.planet.nl> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-NNVgQHHE0+oThfVfv0C5+0ye3cbO3/UtqmpV4DEFy2N5mHtpjRKjpx282t2Po12DwveCXemSJ4zcUxy!wIQ1A93EHdwvY8tAdMOwifz37VCJ2+OCfclvWt2Td9VdT5b07FldLKK+nbj7ASmU1kxQ7pFojsUk!O/41GT2CjkahBzLL X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1628 comp.arch.fpga:4708 comp.lang.verilog:589 On Mon, 6 Jul 2009 21:02:42 +0800, steve wrote: >we are not talking about "linkedin" ,we are talking about a technical group >within the "LI" network. >If you cannot keep up, there is Lego and crayons over in the play area. Ah, the New Media Priesthood. Their mantra: If you Don't Get It, we will patronize you to death. Me, I definitely Don't Get It, and I really don't care all that much, and I've been patronized in the past by people I respect a lot more than the Noo Meeja Vangelists, so I don't feel too worried. Is there a LinkedIn group for elderly curmudgeons? I'm in there... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t21g2000yqi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: FPGA / CPLD Group on LinkedIn -- Networking Group Date: Mon, 6 Jul 2009 06:19:45 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <0fa40b51-7fb7-4df7-a2cd-50720ed99760@t21g2000yqi.googlegroups.com> References: <4a80c3e1-cebd-4411-86ee-c3498ebe1a29@33g2000vbe.googlegroups.com> <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com> <4a506294.2904187875@news.planet.nl> NNTP-Posting-Host: 24.126.90.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246886385 2621 127.0.0.1 (6 Jul 2009 13:19:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Jul 2009 13:19:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t21g2000yqi.googlegroups.com; posting-host=24.126.90.233; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1) Gecko/20090624 Firefox/3.5 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1629 comp.arch.fpga:4710 comp.lang.verilog:590 On Jul 6, 9:12=A0am, Jonathan Bromley wrote: > On Mon, 6 Jul 2009 21:02:42 +0800, steve wrote: > >we are not talking about "linkedin" =A0,we are talking about a technical= group > >within the =A0"LI" network. > >If you cannot keep up, there =A0is Lego and crayons over in the play are= a. > > Ah, the New Media Priesthood. =A0Their mantra: If you > Don't Get It, we will patronize you to death. > > Me, I definitely Don't Get It, and I really don't > care all that much, and I've been patronized in > the past by people I respect a lot more than the > Noo Meeja Vangelists, so I don't feel too worried. > > Is there a LinkedIn group for elderly curmudgeons? > I'm in there... > -- > Jonathan Bromley, Consultant I haven't found one, but you can start it! I'll probably join as well. What is it about getting old anyway??? Rick From newsfish@newsfish Wed Aug 19 13:25:31 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Jul 2009 11:13:59 -0500 Date: Mon, 6 Jul 2009 09:14:08 -0700 From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Message-ID: <20090706091408.00001634@unknown> References: Organization: Highland Technology, Inc. X-Newsreader: Claws Mail 3.7.0 (GTK+ 2.10.13; i586-pc-mingw32msvc) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 24 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-lBVbzfatT4t/BpEBCRHIgihefBTwxds6m5ydJ8+buKWQeDRWmYPICur/d7NK8WEz/MrrOURO8p9K05a!LCW5/fXaQlJSNTDKnDldy+eEMWkMFZCk81LNGdpnMYv61B8eTAkCxWn/NB/x6xP50g== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1630 On Sat, 4 Jul 2009 06:57:32 +0800 steve wrote: > [snip] > > But my main issue was the double/triple clocking of a variable that > was only supposed to clock once on a signal transition. It of course > is controlled by the only signal i could not investigate. > > [snip 2: snip returns] > This is a bit outside of your original request, but "a variable that was only supposed to clock once on a signal transition" sounds AWFULLY a lot like the classic rookie mistake of using data signals to clock things, rather than running everything off of a system clock and just synchronizing the data. That sort of thing leads to situations that a) don't show up in simulation and b) are murderously difficult to try to hunt down. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!h2g2000yqg.googlegroups.com!not-for-mail From: Petrov Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: TimingAnalyzer is now freeware Date: Mon, 6 Jul 2009 10:14:35 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <02ef6902-2b1c-4736-bdab-a154696db841@h2g2000yqg.googlegroups.com> References: <9ee29b6f-36e1-4121-9d5b-a242a6f2684b@d32g2000yqh.googlegroups.com> <851eb257-c850-4e4c-a1e5-638e4752bafe@h18g2000yqj.googlegroups.com> NNTP-Posting-Host: 158.69.100.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246900475 16365 127.0.0.1 (6 Jul 2009 17:14:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Jul 2009 17:14:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h2g2000yqg.googlegroups.com; posting-host=158.69.100.6; posting-account=PhLy1gkAAAAmsggEVxX45M2WxRhuGteG User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Tyco Electronics 01/2003; .NET CLR 1.1.4322; InfoPath.1; TEIS-7-20080923; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; TEIS-7-20080923),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:4713 comp.lang.vhdl:1631 comp.lang.verilog:591 On Jul 3, 11:52=A0am, chewie wrote: > Thanks James. =A0I did post a similar message on comp.lang.python. > If there are some speed bottlenecks in Python, =A0there is always the > option > of writing only those parts in a C extension.- Hide quoted text - > > - Show quoted text - Personally... I wouldn't bother optimizing it with a C extension. Programmer time is more expensive than computing time. Computers are getting faster every year. Soon, the slow parts might not even be noticeable. Pete From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o9g2000prg.googlegroups.com!not-for-mail From: Hemang Newsgroups: comp.lang.vhdl Subject: Re: assigning different elements of array Date: Mon, 6 Jul 2009 16:14:53 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <89bdd217-61c6-4088-b0fe-1c2356544afb@o9g2000prg.googlegroups.com> References: NNTP-Posting-Host: 149.199.62.254 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246922094 22449 127.0.0.1 (6 Jul 2009 23:14:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Jul 2009 23:14:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000prg.googlegroups.com; posting-host=149.199.62.254; posting-account=DYba0wkAAACK0YptECaLZuvcP9W3TAQK User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1632 On Jun 26, 12:27=A0am, "HT-Lab" wrote: > "Hemang" wrote in message > > news:c1b803d9-7531-401c-8895-d0985fc9217a@f38g2000pra.googlegroups.com... > > > Hi, > > > I have an small test case below.. This code when simulated with > > modelsim v6.4b or d (haven't tried other simulators) give me U on all > > the data_delay array elements and also on the dout port. If I move the > > data_delay(0) assignment to be within the same process (as shown in > > the commented code in the architecture), it starts to work.. > > > I was wondering if VHDL LRM stipulates ALL elements of an array to be > > assigned within the same "scope", or is this a bug in modelsim? > > It is called the longest static prefix, have a look at this question: > > http://www.ht-lab.com/question.jpg > > The answer is not A....... > > Hanswww.ht-lab.com That is an interesting jpg.. My answer would have been (B), but when I see my code's results, I expect modelsim to give "UUUUUUUU" as the answer to your question's code, which is what bothers me.. From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!newsfeed.freenet.de!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!spln!extra.newsguy.com!newsp.newsguy.com!not-for-mail From: steve Newsgroups: comp.lang.vhdl Subject: Dual_port_BRAM Date: Tue, 7 Jul 2009 19:12:59 +0800 Organization: NewsGuy - Unlimited Usenet $19.95 Lines: 28 Message-ID: Reply-To: steve@aol.com NNTP-Posting-Host: p24d1bfbfff00000035db4db291872eb0665c234cac8c0402.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hogwasher/4.3 Xref: eternal-september.org comp.lang.vhdl:1633 Hi, I have a dual port BRAM, accessible from the PPC of a virtex. I was looking for some VHDL to take the contents of an address from the other port (port B) , decrement the content , then stick it back into the same address , word, byte ,long word, it does not matter., via port B. I know it sounds like a stupid waste of time, but specifically I need something to test the PPC and data paths , because something is corrupting someplace, (data or timing), i need to track it down) I've had a look around , but good examples seem to be in short supply. Can anyone offer some pointers to examples. The other question that is confusing me about Xilinx, If I try and take a dual port memory and set port A to an XPS_BRAM_controller at one address, then set port B to another XPS_BRAM_controller at a second address (to build a loop back test at two different addresses) Xilinx tools will not allow it? Steve From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l31g2000yqb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Tue, 7 Jul 2009 07:17:21 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <0af08f57-35d3-42a8-80ca-3c9bbe1efe04@l31g2000yqb.googlegroups.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1246976271 3005 127.0.0.1 (7 Jul 2009 14:17:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Jul 2009 14:17:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l31g2000yqb.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1634 Jonathan's response illustrates another subtle issue: scope control. >From the OP example we cannot tell whether tick_overflow, inc_tick, or tick itself is needed elsewhere, since they are all signals. Since we don't see the actual update to tick (hopefully synchronous!), we can assume that inc_tick is needed there, but where else? By using variables, Jonathan has declared that next_tick (FKA inc_tick) is only needed within that process, in which only the signals tick and tick_overflow are used/exported. If it turns out that tick itself is not really needed anywhere (just tick_overflow), then tick could be a variable too, and we would then be able to work with up or down counters, whichever might be more efficient in the target architecture. Sometimes detecting a rollover on a down counter requires less logic. By isolating tick from external access, it can be changed/optimized without fear of breaking something else. By deliberately controlling scope, you are telling future maintainers (perhaps even yourself in a few weeks/months/years) important information about the ripple effect of potential changes. Block statements can be used for "local signals" to control scope as well, if you prefer the delayed-update semantics of signal assignments. Andy From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!postnews.google.com!h18g2000yqj.googlegroups.com!not-for-mail From: Mark Newsgroups: comp.lang.vhdl Subject: Re: VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST) Date: Tue, 7 Jul 2009 08:02:36 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <232ab7a0-d615-48fb-a4b1-241e491880aa@h18g2000yqj.googlegroups.com> References: <79q8v6F1r36pkU1@mid.individual.net> NNTP-Posting-Host: 132.228.195.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246978956 1269 127.0.0.1 (7 Jul 2009 15:02:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Jul 2009 15:02:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h18g2000yqj.googlegroups.com; posting-host=132.228.195.207; posting-account=LjPxrAoAAAD7iuf3bbEduxohPcE6_m-z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1635 On Jun 16, 2:09=A0pm, Mike Treseler wrote: > Mark wrote: > > I'm coding for the first time in 10 years in VHDL and am trying to > > find equivalents to my oldverilogtool-box. =A0One tool I found > > extremely useful was theAUTOINSTfeatures of theverilog-mode in > > emacs where it would automatically connect instance ports and where > > you could define per-instance naming rules via AUTO_TEMPLATE. =A0 I've > > discovered the port copy/port-paste as... feature in the emacs vhdl- > > mode, but am wondering if that's as close as I can get to the auto- > > instantiate feature of theverilog-mode? > > That's it for vhdl-mode, > unless you can tolerate functions and variables instead. > > VHDL,Port,Copy > VHDL,Port,Paste as instance. > > =A0 =A0 =A0 -- Mike Treseler Thought I'd follow-up for the next person looking for autostitch in vhdl-mode. Just discovered vhdl-compose-wire-components in the emacs mode which goes a bit further than just port-copy-and-paste. Not sure all its capabilities yet, but it filled out all my signals, which was very nice. Mark From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 07 Jul 2009 11:57:59 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Tue, 07 Jul 2009 17:54:38 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <72v65599vipfbf7q5ee06f9iiga6ritc5a@4ax.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> <0af08f57-35d3-42a8-80ca-3c9bbe1efe04@l31g2000yqb.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gqnMD8UAMIbw913Js3pOY3E/VlNC3MHwmbK2ItqjNY9L0HN7/oxq0kvOHLVxfOyKpKqTnEuXWEzfaj6!upi3R5iOaAPHHJI3KJXHx1WPB6A0UU4zZR5o5fGpBSgS2WDvd2Yqiv9F0FrB2JOZSeBfYMpfc7tY!PwxwpCVIJ/iZKfoK X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2745 Xref: eternal-september.org comp.lang.vhdl:1636 On Tue, 7 Jul 2009 07:17:21 -0700 (PDT), Andy wrote: > another subtle issue: scope control. [...] > By isolating tick from external access, it can be > changed/optimized without fear of breaking something else. > > By deliberately controlling scope, you are telling future maintainers > (perhaps even yourself in a few weeks/months/years) important > information about the ripple effect of potential changes. Beautifully said, and I couldn't agree more. Is that statement in the public domain so I can repeat it frequently and openly? Especially when talking to Verilog folk, for many of whom "scope control" means the timebase knob ;-) >Block statements can be used for "local signals" to control scope as >well, if you prefer the delayed-update semantics of signal >assignments. That's true, and it's something I all too often ignore. One of my reasons for ignoring blocks is a vague folk-memory that tool support for blocks is not as good as it might be. Have you (or anyone) ever encountered problems with VHDL block statements in real tools? Thanks -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c1g2000yqi.googlegroups.com!not-for-mail From: sleeman Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Tue, 7 Jul 2009 10:11:37 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <02651487-5ad7-4d6f-8576-f97d764eb426@c1g2000yqi.googlegroups.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> <0af08f57-35d3-42a8-80ca-3c9bbe1efe04@l31g2000yqb.googlegroups.com> <72v65599vipfbf7q5ee06f9iiga6ritc5a@4ax.com> NNTP-Posting-Host: 161.44.227.200 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246986697 4761 127.0.0.1 (7 Jul 2009 17:11:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Jul 2009 17:11:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c1g2000yqi.googlegroups.com; posting-host=161.44.227.200; posting-account=PSVy5AoAAAAJ2JXBkdUK7etuKgFOgBr0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) X-HTTP-Via: 1.1 Application and Content Networking System Software 5.5.9 Xref: eternal-september.org comp.lang.vhdl:1637 On Jul 7, 12:54=A0pm, Jonathan Bromley wrote: > > That's true, and it's something I all too often ignore. > One of my reasons for ignoring blocks is a vague > folk-memory that tool support for blocks is not as > good as it might be. =A0Have you (or anyone) ever encountered > problems with VHDL block statements in real tools? It would be ironic if it there were such problems, since blocks are (during elaboration, per the LRM) the penultimate simplification of the structural aspect the entire design. There's nothing "closer to the metal" in terms of language semantics until the entire design is turned into the simulator's "grist for the mill" : nets and processes. - Kenn From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!37g2000yqp.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Tue, 7 Jul 2009 11:25:33 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <74cda1b6-672f-412c-a57e-79ed888b6520@37g2000yqp.googlegroups.com> References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> <0af08f57-35d3-42a8-80ca-3c9bbe1efe04@l31g2000yqb.googlegroups.com> <72v65599vipfbf7q5ee06f9iiga6ritc5a@4ax.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1246991134 10162 127.0.0.1 (7 Jul 2009 18:25:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Jul 2009 18:25:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000yqp.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1638 > Beautifully said, and I couldn't agree more. =A0Is that > statement in the public domain so I can repeat it > frequently and openly? =A0Especially when talking to > Verilog folk, for many of whom "scope control" means > the timebase knob ;-) Repeat at will... I've not used block statements very much, and not any that I recall in synthesis; I tend to use variables/processes instead. To be fair, my processes tend to be on the large side (too bad blocks can't be used inside processes). Andy From newsfish@newsfish Wed Aug 19 13:25:32 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 07 Jul 2009 14:00:56 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: modelsim doesn't like my increment w/wraparound Date: Tue, 07 Jul 2009 19:57:35 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <491f7b04-2979-41cc-ae35-47246ef87a7a@k8g2000yqn.googlegroups.com> <7ikr455t4kikm2cpngj099d67dv7ulsotf@4ax.com> <0af08f57-35d3-42a8-80ca-3c9bbe1efe04@l31g2000yqb.googlegroups.com> <72v65599vipfbf7q5ee06f9iiga6ritc5a@4ax.com> <02651487-5ad7-4d6f-8576-f97d764eb426@c1g2000yqi.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 49 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-pYttyWOYLlc2SBEDKUB7eXFAa32+d1NMLpjwGBqflR53/y0ati4vglNfg0P7qyw/YVh1DyQUdIw3b5a!+6g14lMBpLdlBmjXe+h6H2m/OftmifgP5+4Z4HCy6PFIkDexeiDbfrnamkVLNedcM4UfzFbdDRNc!QqMa/VAdw3zp9hO5 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1639 On Tue, 7 Jul 2009 10:11:37 -0700 (PDT), sleeman wrote: >> Have you (or anyone) ever encountered >> problems with VHDL block statements in real tools? > >It would be ironic if it there were such problems, since blocks are >(during elaboration, per the LRM) the penultimate simplification of >the structural aspect the entire design. There's nothing "closer to >the metal" in terms of language semantics until the entire design is >turned into the simulator's "grist for the mill" : nets and processes. You're right, of course. I don't even know where my irrational avoidance of blocks originally came from - probably just pig-headedness, or ignorance. They're a rather useful way to localize type, signal and subprogram declarations in a big architecture. I think we would all be pretty cross if our tools were to choke on G: if TRUE generate ... begin ... end generate G; and it's hard to find any difference between that and G: BLOCK -- with no ports and no guard ... begin ... end block G; Interestingly, our Golden Reference Guide still suggests that blocks are not widely supported by synthesis tools. Maybe it's time to review that statement. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 07 Jul 2009 15:18:30 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Dual_port_BRAM Date: Tue, 07 Jul 2009 21:15:08 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 57 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ggM4ISq39Tz8AGwx5lwkWxWOSW6tLzaCol/bMxnxBNVe4stQRar5iXQ630k+sfeZqRXvJVAEuKIt++w!GF8E40eQ5kEN6OzfX3RZO9u/EhY3/NXCHNrLEZoKyar/D27JSGA38M5bNdybn7JU1gjFAn9LpWPD!HCUD0IOHMqCSAQ6D X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1640 On Tue, 7 Jul 2009 19:12:59 +0800, steve wrote: >I have a dual port BRAM, accessible from the PPC of a virtex. > >I was looking for some VHDL to take the contents of an address from the >other port (port B) , decrement the content , then stick it back into the >same address , word, byte ,long word, it does not matter., via port B. It's easy provided nothing else needs to access port B. How do you plan to specify the address? Is there a register, writeable by the CPU? Or do you intend to hard-code the port B address, just as a test? Do you want the decrement to run continuously, as some sort of timed downcounter; or do you want it to be one-shot, triggered by some write to a peripheral by the PPC? >I've had a look around , but good examples seem to be in short supply. >Can anyone offer some pointers to examples. The read/decr/write thing is surely just a fairly simple state machine and a decrementer; I'm not too surprised there are few examples, but it should be easy to throw one together along these lines: State 0: waiting for the start signal. On start, go to... State 1: drive address on to BRAM, enable read, go to... State 2: capture data into a register that feeds a decrementer whose output goes to the write data port. Go to: State 3: do nothing, just give the decr time to settle. Go to... State 4: assert write-enable (address is still OK from state 1). Go to state 0 and wait for the next start command. >The other question that is confusing me about Xilinx, If I try and take a >dual port memory and set port A to an XPS_BRAM_controller at one address, >then set port B to another XPS_BRAM_controller at a second address (to >build a loop back test at two different addresses) Xilinx tools will not >allow it? Never used the XPS_BRAM_... macros; I guess others here have, though. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. > >Steve > > > From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o18g2000pra.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: issue with Chipscope Date: Tue, 7 Jul 2009 16:31:12 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1247009473 14121 127.0.0.1 (7 Jul 2009 23:31:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Jul 2009 23:31:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000pra.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1641 On Jul 3, 3:52=A0am, steve wrote: > On Fri, 3 Jul 2009 18:38:25 +0800, Symon wrote > (in article ): > > > Steve, > > Use the 'core inserter' instead. > > HTH., Syms. > > It is better you do not comment if you do not read the post. I don't understand your comment, because Symon's suggestion is exactly what I was thinking as I read through this thread. I've never instantiated a chipscope core in any design. I've always used the Core Inserter, which is actually one of Xilinx' better tools. Its main benefits are: a) you don't have to decide in advance what signals you will always analyze. You do it after your coding is done. b) It's not in your HDL at all, which helps if you'd like to simulate or whatever. c) When you're satisfied that the design is functioning, you simply delete the core from your project and rebuild. -a From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed1.swip.net!News-Peer-Europe!news-peer-europe.sprintlink.net!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Date: Thu, 09 Jul 2009 11:18:48 +0200 Subject: syncronizer From: "Michael Thomsen" Content-Type: text/plain; format=flowed; delsp=yes; charset=iso-8859-15 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Content-Transfer-Encoding: 7bit Message-ID: User-Agent: Opera Mail/9.64 (Win32) Lines: 77 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 130.225.77.198 X-Trace: news.sunsite.dk DXC=5e1FBL?6OHVOH21j@:G^6UYSB=nbEKnk[6UoW8Q]dZd[8lVl=EEe;_RejKDMNg5:@TYL[aH^E3@Y^U^ HBLKNM = "sync_reg">: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /SigGenTop/EXPANDED/S0\/sreg<1>' because those design objects do not contain or drive any instances of the correct type. WARNING:ConstraintSystem:119 - Constraint HBLKNM = "sync_reg">: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /SigGenTop/EXPANDED/S0\/sreg<0>' because those design objects do not contain or drive any instances of the correct type. Anybody can explain what this means, and how I can avoid it? ------------- Synchronizer: ------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity syncronizer is Port ( clk : in std_logic; async_in : in STD_LOGIC; sync_out : out STD_LOGIC); end syncronizer; architecture Behavioral of syncronizer is signal sreg : std_logic_vector(1 downto 0); attribute TIG : string; attribute IOB : string; attribute ASYNC_REG : string; attribute SHIFT_EXTRACT : string; attribute HBLKNM : string; attribute TIG of async_in : signal is "TRUE"; attribute IOB of async_in : signal is "FALSE"; attribute ASYNC_REG of sreg : signal is "TRUE"; attribute SHIFT_EXTRACT of sreg : signal is "NO"; attribute HBLKNM of sreg : signal is "sync_reg"; begin process (clk) begin if clk'event and clk='1' then sync_out <= sreg(1); sreg <= sreg(0) & async_in; end if; end process; end Behavioral; -------------- Instantiation: -------------- S0: entity WORK.syncronizer port map(Clk=> MClk, async_in => SS, sync_out => synchedSS); //michael -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/ From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!y4g2000prf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: syncronizer Date: Thu, 9 Jul 2009 06:54:47 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: References: NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247147692 7540 127.0.0.1 (9 Jul 2009 13:54:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Jul 2009 13:54:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y4g2000prf.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1645 Not sure if this is related, but sreg(1) should not be considered an asynchronous register, only sreg(0). You may have to split them up into separate signals to handle it. You will also want to make sure (constrain) that sreg(0) does not get replicated for fanout (e.g. if sreg(1) gets replicated enough due to high fanout, that can ripple to replicating sreg(0).) Is the output from your syncrhonizer going anywhere? If not it may be getting optimized away, thus prompting the warnings. Andy From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Date: Fri, 10 Jul 2009 09:47:47 +0200 Subject: Re: syncronizer From: "Michael Thomsen" Content-Type: text/plain; format=flowed; delsp=yes; charset=iso-8859-15 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl References: Content-Transfer-Encoding: 7bit Message-ID: User-Agent: Opera Mail/9.64 (Win32) Lines: 25 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 130.225.77.198 X-Trace: news.sunsite.dk DXC=VKM=kD=3g5]0Sc_VCmP]hZYSB=nbEKnk[_OR4oRM;NgQ8lVl=EEe;_RejKDMNg5:@TYL[aH^E3@Y^U^LPk[F[ X-Complaints-To: staff@sunsite.dk Xref: eternal-september.org comp.lang.vhdl:1646 On Thu, 09 Jul 2009 15:54:47 +0200, Andy wrote: > Not sure if this is related, but sreg(1) should not be considered an > asynchronous register, only sreg(0). You may have to split them up > into separate signals to handle it. Ok, I will look at that. > You will also want to make sure (constrain) that sreg(0) does not get > replicated for fanout (e.g. if sreg(1) gets replicated enough due tohigh > fanout, that can ripple to replicating sreg(0).) It doesn't look like it is getting replicated (and it shouldn't unless I had made a mistake). > Is the output from your syncrhonizer going anywhere? If not it may be > getting optimized away, thus prompting the warnings. Yes, it is being used (SPI-slave), and it works, but still I would like to know the meaning and consequences of this warning. //michael -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/ From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x3g2000yqa.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: std_logic_textio library Date: Fri, 10 Jul 2009 08:12:27 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <0be08e86-8d83-4447-8c50-60f08f289e5e@x3g2000yqa.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247238747 1121 127.0.0.1 (10 Jul 2009 15:12:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jul 2009 15:12:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqa.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1649 I'm planning on using std_logic_textio library for my testbench. I just want access to the hread / hwrite functions. I don't like doing non-standard things. Am I making a mistake? Shannon From newsfish@newsfish Wed Aug 19 13:25:33 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!216.196.98.140.MISMATCH!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 10 Jul 2009 11:34:04 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: std_logic_textio library Date: Fri, 10 Jul 2009 17:30:37 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: References: <0be08e86-8d83-4447-8c50-60f08f289e5e@x3g2000yqa.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-21m2N2DU10JW9NfeRRKtN+igxyoO7fG3tKTYCKC/i7IyPwO7FR2OVpP7+ST0sGpAFXfARXeJUH2JZWv!iinA0Rk0QhYn1xyarfP6lfmFgJl3FS2k/+w1qRMUiHQZCsbDsiNHxPZyCGV2cGV1NugBK7Ead0bJ!IavHEZ1ZbMHnZ6j7 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 X-Original-Bytes: 2055 Xref: eternal-september.org comp.lang.vhdl:1650 On Fri, 10 Jul 2009 08:12:27 -0700 (PDT), Shannon wrote: >I'm planning on using std_logic_textio library for my testbench. I >just want access to the hread / hwrite functions. I don't like doing >non-standard things. Am I making a mistake? No. It's all there, supported by every simulator I've ever come across. And it's officially supported in the 2008 standard. Allergy to non-standard is good, but std_logic_textio is as near as it gets to a standard without the official rubber-stamp, and even that is on the way. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!goblin2!goblin.stu.neva.ru!feed1.news.be.easynet.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 10 Jul 2009 18:51:35 +0200 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Back to the future Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 59 Message-ID: <4a57714f$0$2863$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: ee243f7c.news.skynet.be X-Trace: 1247244623 news.skynet.be 2863 81.240.83.139:46791 X-Complaints-To: usenet-abuse@skynet.be Xref: eternal-september.org comp.lang.vhdl:1651 comp.lang.verilog:597 Since I started with RTL design in 1991, my goal has been to raise the abstraction level as much as possible. Two key characteristics of my design style are: * using a single clocked process for both control and data operations * using variables, including register inference from them Since the early days I am convinced that this is a superior coding style. Therefore, I always expected it would become the mainstream style anytime soon. On this I have been dead wrong. In the past two decades, the mainstream style has moved in the opposite direction. The absolute low point was Cliff Cummings' guideline not to use blocking assignments in a clocked process, which effectively bans variable semantics for RTL designers. However, now there may a new fact. For the first time, a high-profile publication is in the making with a different message. It is appropriately called "The Art of Good Design". Interestingly, it is being written by Mike Keating, the co-author of the Reuse Methodology Manual (RMM). I believe the RMM is partially responsible for the "unstructured chaos" we are in (Mr. Keatings' words). So it's good to see that he is changing his mind. I have the impression that the change comes after a careful study and rewriting of real designs. Good that someone takes the time to do this. In a recent post on his blog, Mr. Keating announced a preview of Chapter 3 of The Art of Good Design: http://synopsysoc.org/futureofdesign/?p=35 In this chapter (after a false start on perl hacking stuff) he acknowledges the superiority of the single clocked process to describe an FSM with embedded data operations. Moreover, he discards the guideline not to mix blocking and non-blocking assignments. He does this implicitly, as all blocking assignments are encapsulated in functions, but this doesn't fundamentally alter the conclusion. He has yet to endorse variable semantics (blocking assignments) as a generally valuable coding technique, including register inference. But still, it's a good start. The idea to encapsulate logic systematically in functions is interesting. Add variables and procedures to the mix, and what you end up with is the purest form of abstract RTL design - a.k.a. Mike Treseler's style! Mike Keatings' blog is called "the future of design". I'd rather call it "back to the future of design" :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i6g2000yqj.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future Date: Fri, 10 Jul 2009 15:19:52 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <76684e75-a4ac-460d-8e53-ee7d50205b7e@i6g2000yqj.googlegroups.com> References: <4a57714f$0$2863$ba620e4c@news.skynet.be> NNTP-Posting-Host: 76.71.195.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247264392 22844 127.0.0.1 (10 Jul 2009 22:19:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jul 2009 22:19:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i6g2000yqj.googlegroups.com; posting-host=76.71.195.228; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/530.5 (KHTML, like Gecko) Chrome/2.0.172.33 Safari/530.5,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1652 comp.lang.verilog:598 There is also a good article on a VHDL-design methodology using 2 processes per file. In the article, the combinational part and sequential parts are separated. I'm not convinced it's necessary to separate them but the ideas in the article are pretty good. http://www.gaisler.com/doc/vhdl2proc.pdf On general I would say that smaller blocks are easier to understand, but sometimes, smaller means more obfuscation which goes against the idea of making the design easier to understand. From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!32g2000yqj.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: std_logic_textio library Date: Fri, 10 Jul 2009 15:47:39 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <0be08e86-8d83-4447-8c50-60f08f289e5e@x3g2000yqa.googlegroups.com> NNTP-Posting-Host: 67.169.207.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1247266059 28361 127.0.0.1 (10 Jul 2009 22:47:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jul 2009 22:47:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 32g2000yqj.googlegroups.com; posting-host=67.169.207.204; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.10 NET_mmhpset,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1653 On Jul 10, 9:30=A0am, Jonathan Bromley wrote: > On Fri, 10 Jul 2009 08:12:27 -0700 (PDT), Shannon wrote: > >I'm planning on using std_logic_textio library for my testbench. =A0I > >just want access to the hread / hwrite functions. =A0I don't like doing > >non-standard things. =A0Am I making a mistake? > > And it's officially supported in the 2008 standard. Try turning on the VHDL-2008 switch in your simulator. If hread and hwrite work without the package reference to std_logic_textio, then these new features has been implemented. It works in a couple of the simulators I have tried it. In the 2008 standard, these functions were upgraded (now handle parameters that are not a multiple of 4 bits for hexadecimal or 3 bits for octal) and were moved to std_logic_1164. The package std_logic_textio still exists for backward compatibility. It has aliases to the functions in std_logic_1164 (to allow selected name references to the package to still work). If your simulator does not support VHDL-2008 textio yet, use std_logic_textio, but avoid selected name references (such as ieee.std_logic_textio.hwrite) to the subprograms in the package. This way when you have VHDL-2008 support, your design will work with or without the reference to std_logic_textio. Cheers, Jim SynthWorks VHDL Training www.SynthWorks.com From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!newspeer.monmouth.com!newsswitch.lcs.mit.edu!news.uchicago.edu!nntp-server.caltech.edu!news.jpl.nasa.gov!not-for-mail From: Jason Zheng Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future Date: Fri, 10 Jul 2009 15:15:48 -0700 Organization: JPL Lines: 38 Message-ID: <20090710151548.45082866@wolfenstein.jpl.nasa.gov> References: <4a57714f$0$2863$ba620e4c@news.skynet.be> NNTP-Posting-Host: wolfenstein.jpl.nasa.gov Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: news.jpl.nasa.gov 1247264148 32251 137.79.12.68 (10 Jul 2009 22:15:48 GMT) X-Complaints-To: newsmaster@jpl.nasa.gov NNTP-Posting-Date: Fri, 10 Jul 2009 22:15:48 +0000 (UTC) X-Newsreader: Claws Mail 3.7.1 (GTK+ 2.16.2; i686-pc-linux-gnu) X-Received-Date: Sat, 11 Jul 2009 03:10:16 CDT (news.uchicago.edu) Xref: eternal-september.org comp.lang.vhdl:1654 comp.lang.verilog:599 Interesting post. But I bet you expected people to disagree with you, didn't you? > Since the early days I am convinced that this is a superior coding > style. Therefore, I always expected it would become the mainstream > style anytime soon. On this I have been dead wrong. In the past two > decades, the mainstream style has moved in the opposite direction. The > absolute low point was Cliff Cummings' guideline not to use blocking > assignments in a clocked process, which effectively bans variable > semantics for RTL designers. Cliff Cummings doesn't have a whip. He has a following because what he pointed out in his papers make sense, are easy to follow, and, when followed, make a designer's life very easy. > He has yet to endorse variable semantics (blocking assignments) as a > generally valuable coding technique, including register inference. But > still, it's a good start. The idea to encapsulate logic systematically > in functions is interesting. Add variables and procedures to the mix, > and what you end up with is the purest form of abstract RTL design - > a.k.a. Mike Treseler's style! I believe that this is really in the eye of beholder. It's hard to make conclusions without looking at some concrete examples. I personally believe that with SystemVerilog, the blocking assignment issue has been resolved. If you want to combine complex abstract logic with register inference, just use local non-reg-type variables. They won't infer extra flip-flops and have limited scope. I think Mike Treseler's style makes it easy to auto-generate HDLs, but not necessarily easy for designers and analysts. To me, RTL implementation is 75% art, 25% science. I have yet to see something molded to a systematic template that can be considered artful design. ~Jason Zheng From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!weretis.net!feeder1.news.weretis.net!news.szaf.org!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!novia!newspump.monmouth.com!newspeer.monmouth.com!newsswitch.lcs.mit.edu!news.uchicago.edu!nntp-server.caltech.edu!news.jpl.nasa.gov!not-for-mail From: Jason Zheng Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future Date: Fri, 10 Jul 2009 15:18:15 -0700 Organization: JPL Lines: 16 Message-ID: <20090710151815.1287f2a9@wolfenstein.jpl.nasa.gov> References: <4a57714f$0$2863$ba620e4c@news.skynet.be> <20090710151548.45082866@wolfenstein.jpl.nasa.gov> NNTP-Posting-Host: wolfenstein.jpl.nasa.gov Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: news.jpl.nasa.gov 1247264295 32251 137.79.12.68 (10 Jul 2009 22:18:15 GMT) X-Complaints-To: newsmaster@jpl.nasa.gov NNTP-Posting-Date: Fri, 10 Jul 2009 22:18:15 +0000 (UTC) X-Newsreader: Claws Mail 3.7.1 (GTK+ 2.16.2; i686-pc-linux-gnu) X-Received-Date: Sat, 11 Jul 2009 03:10:16 CDT (news.uchicago.edu) Xref: eternal-september.org comp.lang.vhdl:1655 comp.lang.verilog:600 On Fri, 10 Jul 2009 15:15:48 -0700 Jason Zheng wrote: > I think Mike Treseler's style makes it easy to auto-generate HDLs, but > not necessarily easy for designers and analysts. To me, RTL > implementation is 75% art, 25% science. I have yet to see something > molded to a systematic template that can be considered artful design. > Hate to reply to myself, but what I was really referring to the "put everything in a giant always block, and use functions for logic" style. -- Early to rise, early to bed, makes a man healthy, wealthy and dead. -- Terry Pratchett, "The Light Fantastic" From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!newsfeed.velia.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail From: "Alfonso Baz" Newsgroups: comp.lang.vhdl Subject: Constants? Date: Sat, 11 Jul 2009 09:51:28 +1000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Lines: 22 Message-ID: <4a57d3fd$0$21180$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 110.32.225.19 X-Trace: 1247269885 21180 110.32.225.19 Xref: eternal-september.org comp.lang.vhdl:1656 I come from a C programming background where something like this can be done #define MAX 32 at compile time the source code is parsed and any instants of MAX are replaced with 32 before being passed to the compiler proper I have been using constants thinking they were the same thing, but on closer inspection I see we're having to give it a type also. This is leading me to believe that a constant takes up hardware resources. Does VHDL have some kind of pre-compiler/parser that can handle substitution and math prior to compiling such as this in C #define MAX 32 #define EXP 2 ... if( x == MAX^EXP)... which gets changed to if(x == 1024) Thanks From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!newsfeed2.telusplanet.net!newsfeed.telus.net!flph200.ffdc.sbc.com!prodigy.net!flph199.ffdc.sbc.com!prodigy.com!nlpi071.nbdc.sbc.com!flpi150.ffdc.sbc.com.POSTED!88425514!not-for-mail From: "KJ" Newsgroups: comp.lang.vhdl References: <4a57d3fd$0$21180$afc38c87@news.optusnet.com.au> Subject: Re: Constants? Lines: 71 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 99.184.242.197 X-Complaints-To: abuse@prodigy.net X-Trace: flpi150.ffdc.sbc.com 1247275719 ST000 99.184.242.197 (Fri, 10 Jul 2009 21:28:39 EDT) NNTP-Posting-Date: Fri, 10 Jul 2009 21:28:39 EDT Organization: at&t http://my.att.net/ X-UserInfo1: TSU[@ION^ZTGRTPX@JIX_UXBUSXB@DTMNHWB_EYLJZ]BGIELNVUEAE[YETZPIWWI[FCIZA^NBFXZ_D[BFNTCNVPDTNTKHWXKB@X^B_OCJLPZ@ET_O[G\XSG@E\G[ZKVLBL^CJINM@I_KVIOR\T_M_AW_M[_BWU_HFA_]@A_A^SGFAUDE_DFTMQPFWVW[QPJN Date: Fri, 10 Jul 2009 21:28:20 -0400 Xref: eternal-september.org comp.lang.vhdl:1657 "Alfonso Baz" wrote in message news:4a57d3fd$0$21180$afc38c87@news.optusnet.com.au... >I come from a C programming background where something like this can be >done > #define MAX 32 > > at compile time the source code is parsed and any instants of MAX are > replaced with 32 before being passed to the compiler proper > > I have been using constants thinking they were the same thing, but on > closer inspection I see we're having to give it a type also. This is > leading me to believe that a constant takes up hardware resources. > Constants do not use any hardware resources. The reason VHDL constants must have a type is because the VHDL language is strongly typed whereas C with #define is not. Whether you've hard coded value or defined a constant that evaluates to the value doesn't matter. The synthesized result will be the same. > Does VHDL have some kind of pre-compiler/parser that can handle > substitution and math prior to compiling such as this in C > #define MAX 32 > #define EXP 2 > ... > if( x == MAX^EXP)... > which gets changed to > if(x == 1024) > You can generally use the language itself without any pre-compiler/parser. Any place where you would generally type in some hard coded constant you can use a function of arbitrary complexity instead. Some examples: Assume you have some function called 'foo' that takes a couple of arguments and returns a value of type integer function foo(a: real; b:integer) return integer; Then you can use foo to define constants like any of the following... entity ent_foo is generic( some_real_generic: real; some_integer_generic: integer); port( -- foo is used to define the upper end of the range of a vector xyz: in std_ulogic_vector(foo(some_real_generic, some_integer_generic) downto 0)); end ent_foo; architecture foofoo of ent_foo is constant some_constant: integer := foo(1.0, 3); ... Usually the only limitations you may run into with a synthesis tool is whether or not they support the underlying data types. Quartus and Synplify both support use of 'unsynthesizable' types such as 'time' and 'real' when they are used to compute constants even though you can't create signals of those types. Functions of course can return any data types that you'd like, so you can define vectors, arrays, custom types, etc. The hurdle for those used to C programming is that in C the #define is a text substitution that doesn't care about what it is being subbed into whereas VHDL, because of the strong typing doesn't allow for such shenanigans. While it seems at first to be a pain, the advantages of the type checking make it worth the effort. It's not harder in VHDL, just different so that's the only hurdle. Kevin Jennings From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 11 Jul 2009 17:58:45 +0200 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future References: <4a57714f$0$2863$ba620e4c@news.skynet.be> <20090710151548.45082866@wolfenstein.jpl.nasa.gov> In-Reply-To: <20090710151548.45082866@wolfenstein.jpl.nasa.gov> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 26 Message-ID: <4a58b66c$0$2855$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 86434b05.news.skynet.be X-Trace: 1247327852 news.skynet.be 2855 81.240.83.139:43425 X-Complaints-To: usenet-abuse@skynet.be Xref: eternal-september.org comp.lang.vhdl:1658 comp.lang.verilog:601 Jason Zheng wrote: > Interesting post. But I bet you expected people to disagree with you, > didn't you? Well, yes, I hope I'm not being trivial if that's what you mean. > I personally > believe that with SystemVerilog, the blocking assignment issue has been > resolved. If you want to combine complex abstract logic with register > inference, just use local non-reg-type variables. They won't infer > extra flip-flops and have limited scope. But surely they would be assigned using blocking assignments, while the non-local regs would presumably be assigned using non-blocking assignments. Perfectly fine with me, but that style does violate that infamous guideline. Why don't we join forces and finally get rid of it :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Wed Aug 19 13:25:34 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future Date: Sat, 11 Jul 2009 12:02:00 -0700 Lines: 39 Message-ID: <7bs5uiF24ij3eU1@mid.individual.net> References: <4a57714f$0$2863$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net kfOXrp5RRT1ig49NpTp2SwAcHLJjOpOmKu+80zwdnvrHkrUoiV Cancel-Lock: sha1:jWAzczm+iXMNmHftkLjQUC0JFKE= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: <4a57714f$0$2863$ba620e4c@news.skynet.be> Xref: eternal-september.org comp.lang.vhdl:1659 comp.lang.verilog:602 Jan Decaluwe wrote: > Since I started with RTL design in 1991, my goal has been to raise the > abstraction level as much as possible. Two key characteristics of my > design style are: > * using a single clocked process for both control and data operations > * using variables, including register inference from them > Since the early days I am convinced that this is a superior coding > style. Therefore, I always expected it would become the mainstream > style anytime soon. On this I have been dead wrong. The upside to this fact is that a few hdl designers will enjoy an unfair advantage as long as confusion continues to be promoted by the vendors. > I have the impression that the > change comes after a careful study and rewriting of real designs. Good > that someone takes the time to do this. Yes, papers that do real A-B testing of style issues are rare because it does take a lot of time. My informal tests have convinced me that synthesis does not care if I code the same design in one process per register or one process per entity. > In a recent post on his blog, Mr. Keating announced a preview of > Chapter 3 of The Art of Good Design: > http://synopsysoc.org/futureofdesign/?p=35 > In this chapter (after a false start on perl hacking stuff) That "synatatic fluff" of multiple processes is what got me started. > Mike Keatings' blog is called "the future of design". I'd rather call > it "back to the future of design" :-) Thanks for the link. If brand S is coming around, that is good news. That style is what trickles down to the fpga vendors' training material. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future Date: Sat, 11 Jul 2009 12:29:28 -0700 Lines: 15 Message-ID: <7bs7hvF2541bgU1@mid.individual.net> References: <4a57714f$0$2863$ba620e4c@news.skynet.be> <76684e75-a4ac-460d-8e53-ee7d50205b7e@i6g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net rOFBrkGdQL896IpXSXVSMQyp31a6V9k7dAdzc6C9G3x1RNa7eb Cancel-Lock: sha1:HaTDQO0gyBx91aK3CS1c0K7r8ew= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: <76684e75-a4ac-460d-8e53-ee7d50205b7e@i6g2000yqj.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1660 comp.lang.verilog:603 Benjamin Couillard wrote: > There is also a good article on a VHDL-design methodology using 2 > processes per file. In the article, the combinational part and > sequential parts are separated. I'm not convinced it's necessary to > separate them but the ideas in the article are pretty good. > > http://www.gaisler.com/doc/vhdl2proc.pdf Thanks for the link. Sections 5.1 and 5.2 are excellent. I would substitute vhdl functions for the asynchronous processes in the examples. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.news-service.com!news2.euro.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 11 Jul 2009 21:38:31 +0200 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.16 (X11/20080723) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Back to the future References: <4a57714f$0$2863$ba620e4c@news.skynet.be> <76684e75-a4ac-460d-8e53-ee7d50205b7e@i6g2000yqj.googlegroups.com> In-Reply-To: <76684e75-a4ac-460d-8e53-ee7d50205b7e@i6g2000yqj.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 24 Message-ID: <4a58e9f8$0$2860$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 8a122267.news.skynet.be X-Trace: 1247341048 news.skynet.be 2860 81.240.83.139:51439 X-Complaints-To: usenet-abuse@skynet.be Xref: eternal-september.org comp.lang.vhdl:1661 comp.lang.verilog:604 Benjamin Couillard wrote: > There is also a good article on a VHDL-design methodology using 2 > processes per file. In the article, the combinational part and > sequential parts are separated. I'm not convinced it's necessary to > separate them but the ideas in the article are pretty good. Indeed, the separation is not necessary. I don't see how it would change Gaisler's message. It's a pity though, because as you say his ideas are good: moving to higher abstraction levels in general, and the use of record types and variable-centric design in particular. Transforming his style into a single-process style would be trivial, but still significant. Once there, new possibilities pop up, in particular elegant coding solutions that may result in register inference from variables directly. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail From: "Alfonso Baz" Newsgroups: comp.lang.vhdl References: <4a57d3fd$0$21180$afc38c87@news.optusnet.com.au> Subject: Re: Constants? Date: Sun, 12 Jul 2009 09:49:50 +1000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 X-RFC2646: Format=Flowed; Response Lines: 68 Message-ID: <4a592522$0$2227$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 110.32.225.242 X-Trace: 1247356195 2227 110.32.225.242 X-Original-Bytes: 3260 Xref: eternal-september.org comp.lang.vhdl:1664 "KJ" wrote > Constants do not use any hardware resources. The reason VHDL constants > must have a type is because the VHDL language is strongly typed whereas C > with #define is not. Whether you've hard coded value or defined a > constant that evaluates to the value doesn't matter. The synthesized > result will be the same. Good to hear. >> Does VHDL have some kind of pre-compiler/parser that can handle >> substitution and math prior to compiling such as this in C >> #define MAX 32 >> #define EXP 2 >> ... >> if( x == MAX^EXP)... >> which gets changed to >> if(x == 1024) >> > > You can generally use the language itself without any pre-compiler/parser. > Any place where you would generally type in some hard coded constant you > can use a function of arbitrary complexity instead. Some examples: > > Assume you have some function called 'foo' that takes a couple of > arguments and returns a value of type integer > function foo(a: real; b:integer) return integer; > > Then you can use foo to define constants like any of the following... > > entity ent_foo is generic( > some_real_generic: real; > some_integer_generic: integer); > port( > -- foo is used to define the upper end of the range of a vector > xyz: in std_ulogic_vector(foo(some_real_generic, some_integer_generic) > downto 0)); > end ent_foo; > architecture foofoo of ent_foo is > constant some_constant: integer := foo(1.0, 3); > ... Wow, you could almost call that a compile time macro > Usually the only limitations you may run into with a synthesis tool is > whether or not they support the underlying data types. Quartus and > Synplify both support use of 'unsynthesizable' types such as 'time' and > 'real' when they are used to compute constants even though you can't > create signals of those types. > > Functions of course can return any data types that you'd like, so you can > define vectors, arrays, custom types, etc. The hurdle for those used to C > programming is that in C the #define is a text substitution that doesn't > care about what it is being subbed into whereas VHDL, because of the > strong typing doesn't allow for such shenanigans. While it seems at first > to be a pain, the advantages of the type checking make it worth the > effort. It's not harder in VHDL, just different so that's the only > hurdle. > > Kevin Jennings Thanks very much for your in-depth reply Kevin, much appreciated and enlightened Alfonso From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r36g2000vbn.googlegroups.com!not-for-mail From: fl Newsgroups: comp.lang.vhdl Subject: Why self defined type signal cannot assign value multiple times? Date: Sun, 12 Jul 2009 12:35:39 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <08b60262-936c-4dda-bd1f-9f010a0cd8e0@r36g2000vbn.googlegroups.com> NNTP-Posting-Host: 96.11.199.87 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247427339 9903 127.0.0.1 (12 Jul 2009 19:35:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Jul 2009 19:35:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000vbn.googlegroups.com; posting-host=96.11.199.87; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 6.0; GTB6; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30618; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1665 Hi, I am learning VHDL by exercises. I find a self defined type signal cannot assign value more than one time, see below example please. type symbol is ('a', 't', 'd', digit, cr, other); signal ss : symbol; BEGIN ss <= 't'; ss <= 'a'; Modelsim gives the following error message: ** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41): Nonresolved signal 'ss' has multiple sources. It is different from the built-in types? Thanks you very much. From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p23g2000vbl.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: Why self defined type signal cannot assign value multiple times? Date: Sun, 12 Jul 2009 12:58:32 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <08b60262-936c-4dda-bd1f-9f010a0cd8e0@r36g2000vbn.googlegroups.com> NNTP-Posting-Host: 163.252.207.174 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1247428712 21509 127.0.0.1 (12 Jul 2009 19:58:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Jul 2009 19:58:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p23g2000vbl.googlegroups.com; posting-host=163.252.207.174; posting-account=6EXVhgoAAADHUz2PM_sUCsUneKlVYJfy User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1666 On Jul 12, 3:35=A0pm, fl wrote: > Hi, > I am learning VHDL by exercises. I find a self defined type signal > cannot assign value more than one time, see below example please. > > type symbol is ('a', 't', 'd', digit, cr, other); > signal ss : symbol; > > BEGIN > > ss <=3D 't'; > ss <=3D 'a'; > > Modelsim gives the following error message: > ** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41): > Nonresolved signal 'ss' has multiple sources. > > It is different from the built-in types? Thanks you very much. Because this is hardware, and not software, things happen differently than you would expect coming form a software background. These two assignments are essentially happening in parallel, at the same time. So, you are trying to drive the 'ss' signal with two different values, at the same time, which won't work. This is not particularly due to the type being user-defined. However, the error wouldn't show up for some pre-defined types because they are 'resolved', which means there is a mechanism to handle the results of a single signal being driven by multiply sources. For instance, with the std_logic type, if you were to drive it with both a '0' and '1', the result would be the signal having the value 'X' - and hopefully this would alert the designer that there is a problem. Either way, resolved or not, a synthesizer would error out. Dave From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail From: "Alfonso Baz" Newsgroups: comp.lang.vhdl References: <08b60262-936c-4dda-bd1f-9f010a0cd8e0@r36g2000vbn.googlegroups.com> Subject: Re: Why self defined type signal cannot assign value multiple times? Date: Mon, 13 Jul 2009 05:59:06 +1000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Lines: 34 Message-ID: <4a5a4086$0$29475$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 110.32.225.242 X-Trace: 1247428742 29475 110.32.225.242 Xref: eternal-september.org comp.lang.vhdl:1667 "fl" wrote in message news:08b60262-936c-4dda-bd1f-9f010a0cd8e0@r36g2000vbn.googlegroups.com... > Hi, > I am learning VHDL by exercises. I find a self defined type signal > cannot assign value more than one time, see below example please. > > > type symbol is ('a', 't', 'd', digit, cr, other); > signal ss : symbol; > > BEGIN > > ss <= 't'; > ss <= 'a'; > > > Modelsim gives the following error message: > ** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41): > Nonresolved signal 'ss' has multiple sources. > > > It is different from the built-in types? Thanks you very much. I'm just learning also and dont know anything about "self defined types" but the message "Nonresolved signal 'ss' has multiple sources." looks fairly straight forward in that 'ss' is driven by both 't' and 'a' at the same time. If this code is part of a testbench then wait for some time between statements If not then you need some conditional statement that will assign 't' or 'a' but not both From newsfish@newsfish Wed Aug 19 13:25:35 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f16g2000vbf.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Why self defined type signal cannot assign value multiple times? Date: Sun, 12 Jul 2009 14:05:53 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: <08b60262-936c-4dda-bd1f-9f010a0cd8e0@r36g2000vbn.googlegroups.com> NNTP-Posting-Host: 94.218.69.185 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247432753 27994 127.0.0.1 (12 Jul 2009 21:05:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Jul 2009 21:05:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f16g2000vbf.googlegroups.com; posting-host=94.218.69.185; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1668 On 12 Jul., 21:35, fl wrote: > cannot assign value more than one time, see below example please. > > type symbol is ('a', 't', 'd', digit, cr, other); > signal ss : symbol; > > BEGIN > > ss <= 't'; > ss <= 'a'; This is a concurent statement, which happens at the same time, you need to specify your expected result of ss in case of this contradictional assignment. In VHDL this is called a resolution function. > It is different from the built-in types? Thanks you very much. No, in no way. But the type std_logic has a resolution function that specifies what should happen if you write sig <= '0'; sig <= 'Z'; You could of course write such a function for every own type. I guess your real intention was to have the signal set to 't' and after a dedicated delay/condition switching to 's'. In that case you need to learn more about concurrent statements (and processes) bye Thomas From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!j21g2000vbn.googlegroups.com!not-for-mail From: "seth.mart" Newsgroups: comp.lang.vhdl Subject: Re: Constants? Date: Mon, 13 Jul 2009 04:56:54 -0700 (PDT) Organization: http://groups.google.com Lines: 84 Message-ID: <4ed7f997-1eb4-45b3-8beb-cc3dc1502598@j21g2000vbn.googlegroups.com> References: <4a57d3fd$0$21180$afc38c87@news.optusnet.com.au> <4a592522$0$2227$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 32.134.12.134 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1247486214 8769 127.0.0.1 (13 Jul 2009 11:56:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jul 2009 11:56:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j21g2000vbn.googlegroups.com; posting-host=32.134.12.134; posting-account=A9x1FwoAAACNCEEfbD5BmHKRLW7cZisU User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (iPhone; U; CPU iPhone OS 3_0 like Mac OS X; en-us) AppleWebKit/528.18 (KHTML, like Gecko) Version/4.0 Mobile/7A341 Safari/528.16,gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1671 On Jul 11, 7:49=A0pm, "Alfonso Baz" wrote: > "KJ" wrote > > > Constants do not use any hardware resources. =A0The reason VHDL constan= ts > > must have a type is because the VHDL language is strongly typed whereas= C > > with #define is not. =A0Whether you've hard coded value or defined a > > constant that evaluates to the value doesn't matter. =A0The synthesized > > result will be the same. > > Good to hear. > > > > > > >> Does VHDL have some kind of pre-compiler/parser that can handle > >> substitution and math prior to compiling such as this in C > >> #define MAX 32 > >> #define EXP 2 > >> ... > >> if( x =3D=3D MAX^EXP)... > >> which gets changed to > >> if(x =3D=3D 1024) > > > You can generally use the language itself without any pre-compiler/pars= er. > > Any place where you would generally type in some hard coded constant yo= u > > can use a function of arbitrary complexity instead. =A0Some examples: > > > Assume you have some function called 'foo' that takes a couple of > > arguments and returns a value of type integer > > function foo(a: real; b:integer) return integer; > > > Then you can use foo to define constants like any of the following... > > > entity ent_foo is generic( > > =A0some_real_generic: =A0real; > > =A0some_integer_generic: integer); > > port( > > -- foo is used to define the upper end of the range of a vector > > =A0xyz: in =A0std_ulogic_vector(foo(some_real_generic, some_integer_gen= eric) > > downto 0)); > > end ent_foo; > > architecture foofoo of ent_foo is > > =A0constant some_constant: integer :=3D foo(1.0, 3); > > ... > > Wow, you could almost call that a compile time macro > > > > > > > Usually the only limitations you may run into with a synthesis tool is > > whether or not they support the underlying data types. =A0Quartus and > > Synplify both support use of 'unsynthesizable' types such as 'time' and > > 'real' when they are used to compute constants even though you can't > > create signals of those types. > > > Functions of course can return any data types that you'd like, so you c= an > > define vectors, arrays, custom types, etc. =A0The hurdle for those used= to C > > programming is that in C the #define is a text substitution that doesn'= t > > care about what it is being subbed into whereas VHDL, because of the > > strong typing doesn't allow for such shenanigans. =A0While it seems at = first > > to be a pain, the advantages of the type checking make it worth the > > effort. =A0It's not harder in VHDL, just different so that's the only > > hurdle. > > > Kevin Jennings > > Thanks very much for your in-depth reply Kevin, much appreciated and > enlightened > > Alfonso excellent explaination of strong typing in vhdl. From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!h30g2000vbr.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Constants? Date: Mon, 13 Jul 2009 06:36:19 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <9c0ccc8d-b154-40ef-8d98-0c5bbcf842d9@h30g2000vbr.googlegroups.com> References: <4a57d3fd$0$21180$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247492179 31135 127.0.0.1 (13 Jul 2009 13:36:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jul 2009 13:36:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h30g2000vbr.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1672 To add a little to KJ's excellent explanation, Constants sometimes do consume hardware, depending on how they are used, which is no different from pre-processor macros. For example, constant arrays which are indexed by dynamic signals are usually implemented as logic or ROMs in hardware. Constant arrays indexed by other constants are often completely optimized, just like scalar constants. A constant array can also be initialized by a function call. Most tools also allow top-level generics to have their values set via command line arguments. Generics also allow default values to be specified, which makes passing them down from above optional. For example, the size of a graphic image to be processed could be controlled via a generic, and defaulted to the size required in hardware, but made smaller when the UUT is instantiated in the test bench to speed up simulations that are merely attempting to proof out the image operations. Andy From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y10g2000prf.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: testbench question Date: Mon, 13 Jul 2009 10:09:16 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <66b81457-1fbd-4da3-96db-ecb3faa7836d@y10g2000prf.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: posting.google.com 1247504956 9816 127.0.0.1 (13 Jul 2009 17:09:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jul 2009 17:09:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y10g2000prf.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1673 I'm a hardware guy so please excuse me if this question is too simple. I working through writing my first non-synthesizeable (i.e. testbench) code. I have a process with no sensitivity list and a couple of wait statements structurally like this: process begin wait until Reset = '0'; while not endfile(commands) loop ... do stuff ... wait until send_done; end loop; end process; All works surprisingly well (to me) except for that last "wait until send_done" part. I can't seem to get the process to notice send_done has changed state. What am I doing wrong? if you need to see more code I can post it but it will take a little while for me to "sanitize" it for public release. Shannon From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!o9g2000prg.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: testbench question Date: Mon, 13 Jul 2009 10:16:37 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <65fb5b5c-7f78-4c35-b1b3-4f94f42934bc@o9g2000prg.googlegroups.com> References: <66b81457-1fbd-4da3-96db-ecb3faa7836d@y10g2000prf.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1247505397 11505 127.0.0.1 (13 Jul 2009 17:16:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jul 2009 17:16:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000prg.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.11) Gecko/2009060215 Firefox/3.0.11 (.NET CLR 3.5.30729),gzip(gfe),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:1674 On Jul 13, 10:09=A0am, Shannon wrote: > I'm a hardware guy so please excuse me if this question is too > simple. =A0I working through writing my first non-synthesizeable (i.e. > testbench) code. > > I have a process with no sensitivity list and a couple of wait > statements structurally like this: > > process > begin > wait until Reset =3D '0'; > while not endfile(commands) loop > =A0 =A0... do stuff ... > =A0 wait until send_done; > end loop; > end process; > > All works surprisingly well (to me) except for that last "wait until > send_done" part. =A0I can't seem to get the process to notice send_done > has changed state. =A0What am I doing wrong? > > if you need to see more code I can post it but it will take a little > while for me to "sanitize" it for public release. > > Shannon AAAAAAARRRRRRRRRRRRRGGGGGGGGGGGGGGGGGHHHHHHHHH ok. never mind. got it. I keep getting stuck on the concept that signals won't update until the process suspends. It's just not something I worry about with synth. code. Shannon From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: testbench question Date: Mon, 13 Jul 2009 10:22:39 -0700 Lines: 38 Message-ID: <7c18sjF24okbgU1@mid.individual.net> References: <66b81457-1fbd-4da3-96db-ecb3faa7836d@y10g2000prf.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 2NrvFrzfnFjKughUkjj9NghuqbzlbMV6x713b1xfY/2dHlZ5QL Cancel-Lock: sha1:iguv4wx7PqrpSkTWBaHPLq11llg= User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) In-Reply-To: <66b81457-1fbd-4da3-96db-ecb3faa7836d@y10g2000prf.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:1675 Shannon wrote: > I have a process with no sensitivity list and a couple of wait > statements structurally like this: > > process > begin > wait until Reset = '0'; > while not endfile(commands) loop > ... do stuff ... > wait until send_done; > end loop; > end process; I do the same thing, but use synchronous delays. > All works surprisingly well (to me) except for that last "wait until > send_done" part. I can't seem to get the process to notice send_done > has changed state. What am I doing wrong? I would run a sim to see what is happening. Here's how I exit a testbench: procedure coda is begin results; done_s <= true; tic; wait; end procedure coda; details here: http://mysite.verizon.net/miketreseler/test_uart.vhd Good luck. -- Mike Treseler From newsfish@newsfish Wed Aug 19 13:25:36 2009 Path: feeder.eternal-september.org!eternal-september.org!news.glorb.com!news2.glorb.com!bigfeed3.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!nntp.giganews.com!backlog2.nntp.dca.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 13 Jul 2009 14:35:47 -0500 From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: testbench question Date: Mon, 13 Jul 2009 20:32:21 +0100 Organization: Doulos Ltd Reply-To: jonathan.bromley@MYCOMPANY.com Message-ID: <4t1n551agdn4m6fc3056jeao7h5kqa2mmu@4ax.com> References: <66b81457-1fbd-4da3-96db-ecb3faa7836d@y10g2000prf.googlegroups.com> X-Newsreader: Forte Free Agent 3.1/32.783 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 116 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-DyQyeKw/RYB46bpPPNzUd3ss4hH1641uJP9TDKLogfyxDj+164rNDGYRDkbzeXVdZbQDKhV2XLs0MrE!gdvOzNag8Mu0p9LH9eKS7GARp5B+BMEdZyO7K7g99q7z4403nY5kzKpwgzvI1WDaeBRUIOPnIWhk!pMvIo/gJ/+fgGMhn X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: eternal-september.org comp.lang.vhdl:1676 On Mon, 13 Jul 2009 10:09:16 -0700 (PDT), Shannon wrote: >I'm a hardware guy So am I; we won't hold it against you :-) > I working through writing my first non-synthesizeable (i.e. >testbench) code. And, presumably, first suffering the considerable mindset shift that it brings; soon, though, you'll see what a liberating step you've taken. The whole language to play around in! No ringfences around the synthesisable templates! >I have a process with no sensitivity list and a couple of wait >statements structurally like this: > >process >begin >wait until Reset = '0'; >while not endfile(commands) loop > ... do stuff ... > wait until send_done; >end loop; >end process; > >All works surprisingly well (to me) except for that last "wait until >send_done" part. I can't seem to get the process to notice send_done >has changed state. What am I doing wrong? Obviously, see your self-reply; but there are a couple of other things worth bearing in mind. ~~~~~~~~~~~~~~~~~~~~~~~~~~ First off, know your WAIT statement. It's a powerful beast. wait on signalA, signalB... until for