From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!e30g2000vbl.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Precision and VHDL2008 Date: Tue, 27 Jul 2010 06:23:26 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <7b75e831-2124-408d-a4a3-00e2c4871c46@e30g2000vbl.googlegroups.com> References: <9004d975-2efe-466c-9a26-996fd2b9d14d@w30g2000yqw.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280237006 7693 127.0.0.1 (27 Jul 2010 13:23:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Jul 2010 13:23:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e30g2000vbl.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.99 Safari/533.4,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3933 On Jul 20, 6:04=A0am, Tricky wrote: > Id say until Modelsim supports it people wont really start using > VHDL2008 at all (apart from the 1993 versions of the float/fixed > packages, that comes included with modelsim) Unfortunately this is true, though I understand Aldec's simulation package has far better 2008 support. I recently discussed the roadmap with a Mentor support engineer and their implementation roadmap stretches out to 2011a and 6.8. The only support that I know is in for certain right now is the encrypted source code. Personally I don't know why, of all the VHDL-2008 features, that was the one that got the initial support, but there it is. (Likely they had someone pay them for it I suppose.) And while I was pleased to see Precision start implementing it, it really doesn't make any sense to have different RTL for simulation and synthesis. The VHDL-2008 support for Modelsim exists as an enhancement request ticket. If you feel strongly like you'd use it, call up Mentor and ask to have your name and company added to the enhancement request. With enough interest, perhaps they'll move up their implementation timeline. Best regards, Mark Norton From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!open-news-network.org!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!t35g2000vbb.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: New Version of Emacs vhdl-mode Available Date: Tue, 27 Jul 2010 06:26:21 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <1464e71d-b076-4721-86bc-f3bbbc8516ca@t35g2000vbb.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280237182 9552 127.0.0.1 (27 Jul 2010 13:26:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Jul 2010 13:26:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000vbb.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.99 Safari/533.4,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3934 Just wanted to let other emacs enthusiasts know that a new version of the vhdl-mode.el is available. Changelog is available at http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html. Many, many thanks to Reto Zimmerman for maintaining this excellent tool. Mark From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!l20g2000vbd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL ... Sideways? Date: Tue, 27 Jul 2010 10:02:03 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <105c135c-dc31-4828-afc7-4bd4cab8c713@l20g2000vbd.googlegroups.com> References: <12af3ef9-29f7-48f3-9b24-a0b298cc2829@f6g2000yqa.googlegroups.com> <879g46pvaib3rb3vk964ipr8m36epjbr2v@4ax.com> <87277e87-1cd4-4acf-8668-f60b4c15c28c@5g2000yqz.googlegroups.com> <6ccdf91e-ba3a-4d83-82c9-08a2d08e03e4@s9g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280250123 27470 127.0.0.1 (27 Jul 2010 17:02:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Jul 2010 17:02:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000vbd.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3935 I have not lobbied in any of your list of the "right places". A review of my posting record here would indicate that I have advocated for this for a long time (perhaps in hopes of someone else championing the issue :) . Andy From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!q2g2000vbd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL ... Sideways? Date: Tue, 27 Jul 2010 10:07:00 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <12af3ef9-29f7-48f3-9b24-a0b298cc2829@f6g2000yqa.googlegroups.com> <879g46pvaib3rb3vk964ipr8m36epjbr2v@4ax.com> <4deb3e9c-4dee-43be-b54b-36a57244a67a@u26g2000yqu.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280250420 30005 127.0.0.1 (27 Jul 2010 17:07:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Jul 2010 17:07:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbd.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3936 On Jul 23, 2:31=A0am, Thomas Stanka wrote: > On 22 Jul., 15:58, Brian Drummond > wrote: > > > >Is there any way for me to "bring" ports from entities lower in the > > >hierarchy up to the top without threading them all the way through? > > > There are "shared variables" but they won't help you if the intent is s= ynthesis. > > They can be used as test points in testbenches so that you don't need t= o bring > > internal test points all the way up the hierarchy, but synthesis suppor= t for > > these is likely to be somewhere between poor and non-existent. > > You can use global signals in your design and will end up with a good > synthesis result (at least with Synplify) > In therory this would allow you to build all entities without ports > and save a lot of signal routing through hierarchies. > > Nevertheless I would recommend not to use global signals in rtl > because you will likely break on several points when maintaining the > code. > > bye Thomas I have not tried it lately, but Synplify used to accept a global signal declaration, but each invocation was a separate, local signal and they were not global. I don't remember the details about what constituted a separate invocation, but I know that two architectures of two entities both had the signal, but not connected between them. This was a long time ago, and they may well have fixed it by now. Andy From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!feeder.erje.net!newsfeed1.swip.net!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.lang.vhdl Subject: Re: VHDL ... Sideways? Message-ID: From: Andreas Ehliar Date: 28 Jul 10 09:21:04 MET References: <12af3ef9-29f7-48f3-9b24-a0b298cc2829@f6g2000yqa.googlegroups.com> <879g46pvaib3rb3vk964ipr8m36epjbr2v@4ax.com> <87277e87-1cd4-4acf-8668-f60b4c15c28c@5g2000yqz.googlegroups.com> <207h469h2bg9s2rib5loumpbrm0l2cbhvt@4ax.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 24 Xref: eternal-september.org comp.lang.vhdl:3937 On 2010-07-22, Andy wrote: > others (receivers or ignorers) always drive 'Z's. No muxes, the > synthesis tool just figures it out. > > The only downside is you can't use enums, integers, booleans, etc. Another downside is that you may cause a mismatch between synthesis and simulation if you are not careful. Consider the following part of a process: if ctrl = '1' then led1_o <= data; end if; if ctrl = '0' then led2_o <= data; end if; Lets just say that this code is unlikely to behave in the same way in both synthesis and simulation if ctrl is set to 'Z'. regards /Andreas From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!postnews.google.com!s17g2000prh.googlegroups.com!not-for-mail From: vipin lal Newsgroups: comp.lang.vhdl Subject: function overloading in vhdl Date: Wed, 28 Jul 2010 04:21:41 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> NNTP-Posting-Host: 203.199.213.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280316102 13661 127.0.0.1 (28 Jul 2010 11:21:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 11:21:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s17g2000prh.googlegroups.com; posting-host=203.199.213.66; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy2.iitm.ac.in:3128 (squid/2.7.STABLE7), 1.0 proxyp1.iitm.ac.in:3128 (squid/2.7.STABLE7) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.3 (KHTML, like Gecko) Chrome/5.0.360.0 Safari/533.3,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3938 Hi guys, I want to do function overloading in one of my designs.I googled for some examples and I learned that for function overloading to work, you need either different number of parameters or different type of parameters. But I want something like this in my code: function f(a : in std_logic_vector(1 downto 0)) return std_logic is .... end f; function f(b : in std_logic_vector(2 downto 0)) return std_logic is .... end f; The only change is that a is 2 bit in size and b is 3 bit in size. How do I do something like this. Is there any hack to get this kind of thing working? Thanks vipin From newsfish@newsfish Fri Dec 24 22:54:43 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w30g2000yqw.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 04:54:42 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <73e6a9aa-3337-44f5-9b0a-e03c750ba880@w30g2000yqw.googlegroups.com> References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> NNTP-Posting-Host: 86.111.223.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280318083 30751 127.0.0.1 (28 Jul 2010 11:54:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 11:54:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w30g2000yqw.googlegroups.com; posting-host=86.111.223.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.2 (14893) 05j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3939 > The only change is that a is 2 bit in size and b is 3 bit in size. How > do I do something like this. Is there any hack to get this kind of > thing working? No hack required; instead, you can tap in to one of the very best features of VHDL: unconstrained subprogram parameters. Just use ordinary array attributes to inspect the argument you have been given. function f (in v: std_logic_vector) -- NO SIZE HERE! return std_logic_vector is -- NO RESULT SIZE! constant msb: integer := v'left; constant lsb: integer := v'right; constant size: integer := v'length; variable normalized_v: std_logic_vector(size-1 downto 0); variable result: std_logic; begin normalized_v := v; // avoid slice-direction trouble result := v(msb) xor v(lsb); return result & normalized_v(size-2 downto 0); end; OK, the code is silly, but you see what I mean - this function returns a vector that's the same as its input vector, but with the MSB replaced with the XOR of the original MSB and LSB. Love it. Eat your heart out, Verilog. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v32g2000prd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 04:55:24 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <5f6fc271-19cc-4422-a38c-c5cb13796116@v32g2000prd.googlegroups.com> References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280318124 993 127.0.0.1 (28 Jul 2010 11:55:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 11:55:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v32g2000prd.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3940 On Jul 28, 7:21=A0am, vipin lal wrote: > Hi guys, > I want to do function overloading in one of my designs.I googled for > some examples and I learned that for function overloading to work, you > need either different number of parameters or different type of > parameters. > But I want something like this in my code: > > function f(a : in std_logic_vector(1 downto 0)) return std_logic is > .... > end f; > > function f(b : in std_logic_vector(2 downto 0)) return std_logic is > .... > end f; > > The only change is that a is 2 bit in size and b is 3 bit in size. How > do I do something like this. Is there any hack to get this kind of > thing working? > > Thanks > vipin You don't need to overload the function call at all in your instance function f(a : in std_logic_vector) return std_logic is begin if (a'length =3D 2) then ... elsif (a'length =3D 3) then ... else ... end if; end function f; KJ From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l25g2000prn.googlegroups.com!not-for-mail From: vipin lal Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 05:57:19 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> <5f6fc271-19cc-4422-a38c-c5cb13796116@v32g2000prd.googlegroups.com> NNTP-Posting-Host: 203.199.213.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280321840 30885 127.0.0.1 (28 Jul 2010 12:57:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 12:57:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l25g2000prn.googlegroups.com; posting-host=203.199.213.66; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy2.iitm.ac.in:3128 (squid/2.7.STABLE7), 1.0 proxyp1.iitm.ac.in:3128 (squid/2.7.STABLE7) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.3 (KHTML, like Gecko) Chrome/5.0.360.0 Safari/533.3,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3941 Thanks a lot for the replies. But I guess I will give you some more details about the module I want to design. The size of the input parameter(std_logic_vector) is a generic value.So if I write the function as KJ mentioned, then I will be wasting resources,I think. Thats why I want separate functions and these functions I will put it in a package.This will ensure that only required logic is implemented. The functions should look like this: function f(a : in std_logic_vector(1 downto 0)) return std_logic is output := some xor operations between the bits of 'a'. end f; function f(b : in std_logic_vector(2 downto 0)) return std_logic is output := some xor operations between the bits of 'b'. end f; Here the logic inside each function is different.Also size of signal a or b is a generic parameter.So I will be using only one function when synthesising the function for a device. Thanks vipin From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!g19g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 06:37:26 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <7801ba45-e2cd-4e0d-b618-59bbb32587df@g19g2000yqc.googlegroups.com> References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> <5f6fc271-19cc-4422-a38c-c5cb13796116@v32g2000prd.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280324247 19896 127.0.0.1 (28 Jul 2010 13:37:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 13:37:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g19g2000yqc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3943 On 28 July, 13:57, vipin lal wrote: > Thanks a lot for the replies. But I guess I will give you some more > details about the module I want to design. > The size of the input parameter(std_logic_vector) is a generic > value.So if I write the function as KJ mentioned, then I will be > wasting resources,I think. > Thats why I want separate functions and these functions I will put it > in a package.This will ensure that only required logic is implemented. > > The functions should look like this: > > function f(a : in std_logic_vector(1 downto 0)) return std_logic is > output := some xor operations between the bits of 'a'. > end f; > > function f(b : in std_logic_vector(2 downto 0)) return std_logic is > output := some xor operations between the bits of 'b'. > end f; > > Here the logic inside each function is different.Also size of signal a > or b is a generic parameter.So I will be using only one function when > synthesising the function for a device. > > Thanks > vipin Synthesisors are pretty good at minimising resource usage for you. Best thing about this: write easy to understand functions - let synthesisors do the hard work. Unless you need the function to be very different for each value of the generic. In this case, KJ's option is probably the only way to do it. In this case, unused paths in the function (because the length is fixed) will be ignored. From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i18g2000pro.googlegroups.com!not-for-mail From: vipin lal Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 06:51:30 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <30e75ce7-d23a-46c8-a6d8-7bf7c660bf5d@i18g2000pro.googlegroups.com> References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> <5f6fc271-19cc-4422-a38c-c5cb13796116@v32g2000prd.googlegroups.com> <7801ba45-e2cd-4e0d-b618-59bbb32587df@g19g2000yqc.googlegroups.com> NNTP-Posting-Host: 203.199.213.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280325091 26909 127.0.0.1 (28 Jul 2010 13:51:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 13:51:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000pro.googlegroups.com; posting-host=203.199.213.66; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy2.iitm.ac.in:3128 (squid/2.7.STABLE7), 1.0 proxyp1.iitm.ac.in:3128 (squid/2.7.STABLE7) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.3 (KHTML, like Gecko) Chrome/5.0.360.0 Safari/533.3,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3944 On Jul 28, 6:37=A0pm, Tricky wrote: > On 28 July, 13:57, vipin lal wrote: > > > > > > > Thanks a lot for the replies. But I guess I will give you some more > > details about the module I want to design. > > The size of the input parameter(std_logic_vector) is a generic > > value.So if I write the function as KJ mentioned, then I will be > > wasting resources,I think. > > Thats why I want separate functions and these functions I will put it > > in a package.This will ensure that only required logic is implemented. > > > The functions should look like this: > > > function f(a : in std_logic_vector(1 downto 0)) return std_logic is > > output :=3D some xor operations between the bits of 'a'. > > end f; > > > function f(b : in std_logic_vector(2 downto 0)) return std_logic is > > output :=3D some xor operations between the bits of 'b'. > > end f; > > > Here the logic inside each function is different.Also size of signal a > > or b is a generic parameter.So I will be using only one function when > > synthesising the function for a device. > > > Thanks > > vipin > > Synthesisors are pretty good at minimising resource usage for you. > Best thing about this: write easy to understand functions - let > synthesisors do the hard work. > > Unless you need the function to be very different for each value of > the generic. In this case, KJ's option is probably the only way to do > it. In this case, unused paths in the function (because the length is > fixed) will be ignored. Ok, I will try KJ's method and see if it generates extra logic or not. Thanks vipin From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!j8g2000yqd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: function overloading in vhdl Date: Wed, 28 Jul 2010 07:48:41 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <5099cb63-dc78-40c8-9a24-b670667a6005@j8g2000yqd.googlegroups.com> References: <7ccb2cf7-0d28-470d-97bb-952095d542dc@s17g2000prh.googlegroups.com> <5f6fc271-19cc-4422-a38c-c5cb13796116@v32g2000prd.googlegroups.com> <7801ba45-e2cd-4e0d-b618-59bbb32587df@g19g2000yqc.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280328521 24503 127.0.0.1 (28 Jul 2010 14:48:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 14:48:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j8g2000yqd.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3945 On Jul 28, 8:37=A0am, Tricky wrote: > > Synthesisors are pretty good at minimising resource usage for you. > Best thing about this: write easy to understand functions - let > synthesisors do the hard work. > Agreed whole-heartedly! Since the length of a vector argument is "static" in the synthesis realm (determinable when the synthesizer runs), it gets treated like a constant, and optimized away. The if statements that are false for any given invocation of the function get pruned. Whether the tool shows you this in its "RTL" schematic view, or in its "Technology" schematic view, it gets pruned eventually. The same thing is true with for-loop indices. Since the bounds of synthesizeable loops must be static (loops are unrolled in synthesis), the index is treated as static for each trip through the loop. Andy From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u26g2000yqu.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL ... Sideways? Date: Wed, 28 Jul 2010 08:49:14 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <288811c7-bead-4e18-bdde-a66ddb9a6acb@u26g2000yqu.googlegroups.com> References: <12af3ef9-29f7-48f3-9b24-a0b298cc2829@f6g2000yqa.googlegroups.com> <879g46pvaib3rb3vk964ipr8m36epjbr2v@4ax.com> <87277e87-1cd4-4acf-8668-f60b4c15c28c@5g2000yqz.googlegroups.com> <207h469h2bg9s2rib5loumpbrm0l2cbhvt@4ax.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280332155 26080 127.0.0.1 (28 Jul 2010 15:49:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 15:49:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000yqu.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3946 In most cases where you would use an inout port instead of an in port or an out port, if ctrl = 'Z', then there was no driver connected, and neither of these if statements will get implemented, just like neither of these will be executed in simulation. But no errors would be generated in simulation (warnings are generated in synthesis). If the inout is used for a truly bidirectional signal (that would be implemented with two unidirectional signals), you would still have to safely handle the condition when nobody was driving (or nobody's mux input was enabled). I use home-grown functions is1() and is0() that test for meta-values, and convert weak values. Is1(ctrl) asserts an error if ctrl is 'Z' (or '-', 'X', 'U', or 'W'), but returns true if ctrl is 'H' or '1'. I can default a tri-state signal to 'H' or 'L' instead of 'Z' (or just create a continuous driver to 'H' or 'L'), but that might hide cases where a driver was mistakenly omitted. I use is1() or is0() everywhere I need a boolean condition, not just when I think there might be a meta-value. I use Rising_edge(clk) because it correctly handles transitions to and from weak values (not to mention it is more self-documenting). Andy From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: VHDL vs. verilog question Date: Wed, 28 Jul 2010 21:13:59 +0200 Lines: 33 Message-ID: <8bbdrnFdocU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net y+8JDpfI6/n/ADSnwWtvSwQrKEH8+s1HsFcD9K9iC637qZGao= Cancel-Lock: sha1:NN77Y7yiAsCtAtyL0+iRU1frUkk= User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) Xref: eternal-september.org comp.lang.vhdl:3947 I'm trying to create a phase frequency detector, like the one in figure 1 of this article: http://www.analog.com/library/analogDialogue/archives/33-07/phase3/ I believe the VHDL code would be something like this: process(in_a, in_b, up, down) begin if up = '1' and down = '1' then up <= '0'; down <= '0'; else if rising_edge(in_a) then up <= '1'; end if; if rising_edge(in_b) then down <= '1'; end if; end if; end process; Now, what I *actually* want to do is to model this circuit in MyHDL: www.myhdl.org MyHDL follows the verilog coding style (I understand a little bit of VHDL but not verilog). My question is: Is it possible to write the above code in a similar way in verilog (or MyHDL)? Is it possible to have a 'process' or what it's called in verilog that has two edge sensitive signals in the sensitivity list? Hope you can understand my question and thanks, Thomas From newsfish@newsfish Fri Dec 24 22:54:44 2010 Path: eternal-september.org!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!t10g2000yqg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 28 Jul 2010 15:36:37 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280356598 12366 127.0.0.1 (28 Jul 2010 22:36:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Jul 2010 22:36:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t10g2000yqg.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3948 This can be represented in two separate processes, one clocked by in_a, and the other by in_b. I hope you are not planning on synthesizing this to an FPGA. Andy From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 28 Jul 2010 18:20:22 -0500 Date: Wed, 28 Jul 2010 16:20:29 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.10) Gecko/20100512 Thunderbird/3.0.5 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> In-Reply-To: <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 16 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-sfL9TGWhHMZ8dHNlS5SvXYfm/rWvaTDvn6OW5qqjRY6+iluVm6SXbYpIhv79aSBsCi8SQB5Ctzu3rVX!ILbAg1MXD6N7chDK9gb3Mtl9DZ4TB0Y8d06iUcBKGiA/BW4s5VDpSKnN6bztjZpecTyWjwF+obka!Jw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: eternal-september.org comp.lang.vhdl:3949 On 7/28/2010 3:36 PM, Andy wrote: > This can be represented in two separate processes, one clocked by > in_a, and the other by in_b. > > I hope you are not planning on synthesizing this to an FPGA. > > Andy Why not? It's two D-flops with a 1 on the data input, clocked by two separate clocks, with an asynch clear from the and of the two outputs. You get some interesting dead band issues based on the routing delay of that clear path, but you can certainly make it work. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!v35g2000prn.googlegroups.com!not-for-mail From: niyander Newsgroups: comp.lang.vhdl Subject: is it possible to have a clockless design synthesizeable? Date: Wed, 28 Jul 2010 18:19:51 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <0589837d-ad34-466f-85be-c559341afd23@v35g2000prn.googlegroups.com> NNTP-Posting-Host: 59.95.102.17 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280366391 29368 127.0.0.1 (29 Jul 2010 01:19:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 01:19:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v35g2000prn.googlegroups.com; posting-host=59.95.102.17; posting-account=W-Z0OQoAAABTlmAqUoVxZybmc-jZmCQr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3950 hi, can any one please tell me that is it possible to synthesize a clockless design, 100% working? few days back i was reading a book on vhdl, there author quoted an example of floating point adder and in that example clock was not used. thanks From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!postnews.google.com!q21g2000prm.googlegroups.com!not-for-mail From: niyander Newsgroups: comp.lang.vhdl Subject: xilinx ise synthesis timing summary Date: Wed, 28 Jul 2010 20:43:11 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <184b3d64-8ebe-4155-b81e-a0824177b1be@q21g2000prm.googlegroups.com> NNTP-Posting-Host: 59.95.102.17 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280374991 6693 127.0.0.1 (29 Jul 2010 03:43:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 03:43:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q21g2000prm.googlegroups.com; posting-host=59.95.102.17; posting-account=W-Z0OQoAAABTlmAqUoVxZybmc-jZmCQr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3951 hi, i have made a floating point multiplier and after synthesis i get the following result. does the "No path found" message means that my design is not synthesized properly? Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 18.621ns please help me. thanks From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k8g2000prh.googlegroups.com!not-for-mail From: vipin lal Newsgroups: comp.lang.vhdl Subject: Re: xilinx ise synthesis timing summary Date: Wed, 28 Jul 2010 22:42:52 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <53d00493-c8fb-4fa2-9e7d-6ef5325e8781@k8g2000prh.googlegroups.com> References: <184b3d64-8ebe-4155-b81e-a0824177b1be@q21g2000prm.googlegroups.com> NNTP-Posting-Host: 203.199.213.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280382172 7027 127.0.0.1 (29 Jul 2010 05:42:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 05:42:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k8g2000prh.googlegroups.com; posting-host=203.199.213.66; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy2.iitm.ac.in:3128 (squid/2.7.STABLE7), 1.0 proxyp1.iitm.ac.in:3128 (squid/2.7.STABLE7) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.3 (KHTML, like Gecko) Chrome/5.0.360.0 Safari/533.3,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3952 On Jul 29, 8:43=A0am, niyander wrote: > hi, > > i have made a floating point multiplier and after synthesis i get the > following result. > does the "No path found" message means that my design is not > synthesized properly? > > =A0 =A0Minimum period: No path found > =A0 =A0Minimum input arrival time before clock: No path found > =A0 =A0Maximum output required time after clock: No path found > =A0 =A0Maximum combinational path delay: 18.621ns > > please help me. > > thanks No, "no path found" doesnt mean that your code is not synthesised properly. I found this answer from xilinx forum: "The PERIOD constraint only applies to internal signals which go from one flip-flop to another on the same clock." Your design doesnt use a clock,so no flip flops are generated. So the maximum operating frequency is not a function of internal timing and cannot be calculated during synthesis. Experts please verify this. --vipin From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i28g2000yqa.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: xilinx ise synthesis timing summary Date: Wed, 28 Jul 2010 23:23:42 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <24da3bcd-f727-4d85-8e94-7bebadce0dca@i28g2000yqa.googlegroups.com> References: <184b3d64-8ebe-4155-b81e-a0824177b1be@q21g2000prm.googlegroups.com> <53d00493-c8fb-4fa2-9e7d-6ef5325e8781@k8g2000prh.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280384623 27952 127.0.0.1 (29 Jul 2010 06:23:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 06:23:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i28g2000yqa.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.8) Gecko/20100723 Ubuntu/10.04 (lucid) Firefox/3.6.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3953 On 29 Jul., 07:42, vipin lal wrote: > On Jul 29, 8:43=A0am, niyander wrote: > > > hi, > > > i have made a floating point multiplier and after synthesis i get the > > following result. > > does the "No path found" message means that my design is not > > synthesized properly? > > > =A0 =A0Minimum period: No path found > > =A0 =A0Minimum input arrival time before clock: No path found > > =A0 =A0Maximum output required time after clock: No path found > > =A0 =A0Maximum combinational path delay: 18.621ns > > > please help me. > > > thanks > > No, "no path found" doesnt mean that your code is not synthesised > properly. I found this answer from xilinx forum: > > "The PERIOD constraint only applies to internal signals which go from > one flip-flop to another on the same clock." > > Your design doesnt use a clock,so no flip flops are generated. =A0So the > maximum operating frequency is not a function of internal timing and > cannot be calculated during synthesis. > > Experts please verify this. > > --vipin Hi, vipins interpretation is correct. It may make one wonder that a FP-multiplier has no FFs at all, but if it's intended, why not. 18 ns (including the slow I/O-buffers) allow operations up to 55 MHz. To be sure that everything went well you may check the amount of primitives (BELs) in the synthesis report, also check all the warnings and infos. A post translate/map/par simulation will show you quite fast wether the synthesized logic works as intended or not. Be prepared to see a lot of glitches. :-) Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!w30g2000yqw.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: is it possible to have a clockless design synthesizeable? Date: Wed, 28 Jul 2010 23:33:28 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0589837d-ad34-466f-85be-c559341afd23@v35g2000prn.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280385210 32744 127.0.0.1 (29 Jul 2010 06:33:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 06:33:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w30g2000yqw.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.8) Gecko/20100723 Ubuntu/10.04 (lucid) Firefox/3.6.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3954 On 29 Jul., 03:19, niyander wrote: > hi, > > can any one please tell me that is it possible to synthesize a > clockless design, 100% working? > few days back i was reading a book on vhdl, there author quoted an > example of floating point adder and in that example clock was not > used. > > thanks Hi, sure it is possible. I does not always make sense, but possible it is. When you are reading abooks on VHDL, keep in mind that there are now several target technologies that can be used for HDL designs. e.g. CPLDs, FPGAs and ASICs. Each has its special strengths and weaknesses. Large combinatorical blocks like the mentioned example are good for ASICs, where FFs are expensive and silicon is fast with a fine logic granulation (down to single gates). While in FPGAs FFs are cheap and logic granulation is higher (4 or 6 input LUTs). Best performance is acheived here by using pipelined architectures. Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:54:45 2010 Path: eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.64.134.MISMATCH!postnews.google.com!z10g2000yqb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Thu, 29 Jul 2010 08:38:30 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280417911 26567 127.0.0.1 (29 Jul 2010 15:38:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Jul 2010 15:38:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z10g2000yqb.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3955 It is the race condition on the clear signal that would concern me in an FPGA, making sure that the first flop is not cleared, thus removing the clear signal, before the second flop is cleared. It could be made to work reliably with a lot of fuss and analysis (assuming the FPGA vendor provides minimum delay specifications on async clear, routing, etc.) but it would not be a good idea for someone who needs basic help in synthesis. Andy From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!j8g2000yqd.googlegroups.com!not-for-mail From: dgreig Newsgroups: comp.lang.vhdl Subject: Re: Precision and VHDL2008 Date: Fri, 30 Jul 2010 03:28:38 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <98b4b1ae-fe31-4116-9ab3-b45c5ce54bb0@j8g2000yqd.googlegroups.com> References: <9004d975-2efe-466c-9a26-996fd2b9d14d@w30g2000yqw.googlegroups.com> <7b75e831-2124-408d-a4a3-00e2c4871c46@e30g2000vbl.googlegroups.com> NNTP-Posting-Host: 84.19.254.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280485719 32518 127.0.0.1 (30 Jul 2010 10:28:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 10:28:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j8g2000yqd.googlegroups.com; posting-host=84.19.254.82; posting-account=jWYCGAoAAACtdbpYfrlZ1GVzvYP1FIDc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.2; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 ( .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3956 On Jul 27, 2:23=A0pm, "M. Norton" wrote: > On Jul 20, 6:04=A0am, Tricky wrote: > > > Id say until Modelsim supports it people wont really start using > > VHDL2008 at all (apart from the 1993 versions of the float/fixed > > packages, that comes included with modelsim) > > Unfortunately this is true, though I understand Aldec's simulation > package has far better 2008 support. =A0I recently discussed the roadmap > with a Mentor support engineer and their implementation roadmap > stretches out to 2011a and 6.8. =A0The only support that I know is in > for certain right now is the encrypted source code. =A0Personally I > don't know why, of all the VHDL-2008 features, that was the one that > got the initial support, but there it is. =A0(Likely they had someone > pay them for it I suppose.) > > And while I was pleased to see Precision start implementing it, it > really doesn't make any sense to have different RTL for simulation and > synthesis. > > The VHDL-2008 support for Modelsim exists as an enhancement request > ticket. =A0If you feel strongly like you'd use it, call up Mentor and > ask to have your name and company added to the enhancement request. > With enough interest, perhaps they'll move up their implementation > timeline. > > Best regards, > Mark Norton SynplifyPro and Aldec both have seem to have complete 2008 support, the full set of IEEE libraries are provided and I have not yet found any problems. That being said I am working with a subset of new features that are pertinant to fixed point multi-dimensional DSP. Lattice now provide SynplifyPro(full blown Lattice version) and Aldec(slightly throttled Lattice version). Best Regards David Greig From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 15:35:40 +0200 Lines: 12 Message-ID: <8bg2pcF863U1@mid.individual.net> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net nMjfwHGIJf+RBthLB6z/2gMhLdG5nhCK6SvqU8VNgBeD155Vo= Cancel-Lock: sha1:IBuVvcushNjUQ8vIV0oVEWcZFNI= User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:3957 Andy schrieb: > It is the race condition on the clear signal that would concern me in > an FPGA, making sure that the first flop is not cleared, thus removing > the clear signal, before the second flop is cleared. It could be made > to work reliably with a lot of fuss and analysis (assuming the FPGA > vendor provides minimum delay specifications on async clear, routing, > etc.) but it would not be a good idea for someone who needs basic help > in synthesis. Ok, so what are the alternatives? The circuit from xapp028, which I found here? http://www.eettaiwan.com/ARTICLES/2000JUN/2000JUN29_AMD_PL_AN572.PDF?SOURCES=DOWNLOAD From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 15:36:39 +0200 Lines: 8 Message-ID: <8bg2r7F863U2@mid.individual.net> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net aJ1vqBo4NVI397zsBqntAAyo5F9N8SDbxIFrJa4olkCWV9/KA= Cancel-Lock: sha1:XvREk7Utaa9hbsPr8cg7Ls4ePpM= User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:3958 Andy schrieb: > This can be represented in two separate processes, one clocked by > in_a, and the other by in_b. Ok, so the answer to my real question seems to be: a verilog process, different from a VHDL process, can only have one edge-sensitive signal. Correct? From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f6g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 06:55:26 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <166403da-483f-4166-97d8-7523d8b559e6@f6g2000yqa.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280498126 10578 127.0.0.1 (30 Jul 2010 13:55:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 13:55:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f6g2000yqa.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3959 On Jul 30, 8:36=A0am, Thomas Heller wrote: > Andy schrieb: > > > This can be represented in two separate processes, one clocked by > > in_a, and the other by in_b. > > Ok, so the answer to my real question seems to be: a verilog process, > different from a VHDL process, can only have one edge-sensitive signal. > > Correct? No, I don't know what verilog will allow. I'm just pointing out that you don't need it to handle dual-clocked processes to handle this circuit. Andy From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.swapon.de!newsfeed.straub-nv.de!open-news-network.org!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 07:31:06 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <18b00172-dd8a-493d-8e1e-c5978b6c7ef4@d8g2000yqf.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2pcF863U1@mid.individual.net> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280500267 22807 127.0.0.1 (30 Jul 2010 14:31:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 14:31:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3960 A circuit designed for relatively slow FPGA families from 10 years ago may not work as well (or be as easily made to work well) in a modern, very fast FPGA. Quite frankly, I like the original design better than the xapp one. What does this phase detector drive, an external filter and VCO, or an internal synchronous NCO, or something else? Alternatives differ widely based on the answer. Consider whether you need an asynchronous phase detector, or whether a more synchronous design might work with whatever it needs to control. What the first design needs is a way to make sure the async clear does not go away as soon as one of the registers is cleared. You could do this with a third flop, set (clock in a '1') when the two flops are both set, and cleared when both are cleared. Use the output of this third flop to clear the first two. This may cause other problems though with dead-band issues, meta-stability, etc. However, I must also warn you: using combinatorial circuits (remember, these are LUTs, not ANDs and ORs) to drive causal signals (clocks and async resets) can be risky (glitchy), especially in cases where more than one input to the LUT is changing at a time. The muxes in the LUTS are very well balanced to minimize this, but "there ain't nothin' perfect". Generally speaking, the more synchronous the design, the fewer problems getting it to work reliably (across different die, power supply voltages, temperatures, aging, etc.). Andy From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 18:07:09 +0200 Lines: 46 Message-ID: <8bgbldFun7U1@mid.individual.net> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2pcF863U1@mid.individual.net> <18b00172-dd8a-493d-8e1e-c5978b6c7ef4@d8g2000yqf.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net 6dFLqlqdNw7hnnAtN1xB9wdhH7IbZjdwT1O4KeT7miL+F7VFE= Cancel-Lock: sha1:A0MSayASAIHO4hudJT/T4/NupeY= User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <18b00172-dd8a-493d-8e1e-c5978b6c7ef4@d8g2000yqf.googlegroups.com> Xref: eternal-september.org comp.lang.vhdl:3961 Andy schrieb: > A circuit designed for relatively slow FPGA families from 10 years ago > may not work as well (or be as easily made to work well) in a modern, > very fast FPGA. Quite frankly, I like the original design better than > the xapp one. And indeed, the circuit from xapp028 isn't recommended any more for newer devices. Here is a thread where this is discussed: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b42f882e2849011f/f89506f566d0568c#f89506f566d0568c > What does this phase detector drive, an external filter and VCO, or an > internal synchronous NCO, or something else? Alternatives differ > widely based on the answer. Consider whether you need an asynchronous > phase detector, or whether a more synchronous design might work with > whatever it needs to control. > > What the first design needs is a way to make sure the async clear does > not go away as soon as one of the registers is cleared. You could do > this with a third flop, set (clock in a '1') when the two flops are > both set, and cleared when both are cleared. Use the output of this > third flop to clear the first two. This may cause other problems > though with dead-band issues, meta-stability, etc. I'll think this idea over. > However, I must also warn you: using combinatorial circuits (remember, > these are LUTs, not ANDs and ORs) to drive causal signals (clocks and > async resets) can be risky (glitchy), especially in cases where more > than one input to the LUT is changing at a time. The muxes in the LUTS > are very well balanced to minimize this, but "there ain't nothin' > perfect". > > Generally speaking, the more synchronous the design, the fewer > problems getting it to work reliably (across different die, power > supply voltages, temperatures, aging, etc.). Thanks, Andy, for these tips. It seems that the AD9901 chip contains a phase-frequency detector that could be implemented inside an fpga without problems; however, I have to check if I can use it for my application (I fear I cannot ;-). > Andy Thomas From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.wiretrip.org!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!z15g2000prn.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 09:47:55 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280508476 29260 127.0.0.1 (30 Jul 2010 16:47:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 16:47:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z15g2000prn.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3962 On Jul 30, 6:36=A0am, Thomas Heller wrote: > Andy schrieb: > > > This can be represented in two separate processes, one clocked by > > in_a, and the other by in_b. > > Ok, so the answer to my real question seems to be: a verilog process, > different from a VHDL process, can only have one edge-sensitive signal. No, both Verilog and VHDL allow processes to be sensitive to the edges of any number of signals. Certainly for behavioral modeling this is perfectly OK. However, you have to realize that FPGA flip-flops are sensitive to the edge of only one signal, so the synthesis tools will likely barf on code that uses more than one signal's edge. -a From newsfish@newsfish Fri Dec 24 22:54:46 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 19:13:42 +0200 Lines: 30 Message-ID: <8bgfi6FlqkU1@mid.individual.net> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net EDvyEJw9GpJbRhkjKqaybgPJgdtHfZwinE/ldQa/huB+Ixsu0= Cancel-Lock: sha1:ob2sSgxIDOkZc3Fg4VC8sc+0tyY= User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Xref: eternal-september.org comp.lang.vhdl:3963 Andy Peters schrieb: > However, you have to realize that FPGA flip-flops are sensitive to the > edge of only one signal, so the synthesis tools will likely barf on > code that uses more than one signal's edge. I know this very well, having designed digital circuits since 35 years ;-) And not all clock signals have to go into the same flip-flop's clock input. Part of the question in my original post was: How would the below VHDL code look like in a single verilog process: process(in_a, in_b, up, down) begin if up = '1' and down = '1' then up <= '0'; down <= '0'; else if rising_edge(in_a) then up <= '1'; end if; if rising_edge(in_b) then down <= '1'; end if; end if; end process; Thomas From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!feeder.erje.net!feeder.news-service.com!postnews.google.com!f42g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 12:53:07 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <999749eb-6257-4dd8-b0e8-ddac7cc4c85b@f42g2000yqn.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280519587 3024 127.0.0.1 (30 Jul 2010 19:53:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 19:53:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f42g2000yqn.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3964 Many FPGA synthesis tools will allow more than one clock edge in a process. They usually won't allow assignments to the same signal/ variable on more than one clock, but that is not being done in this example. Some FPGAs have DDR flops in the IOBs. Not sure whether any tools will infer a DDR flop from a two clock process assigning the same var/sig on both clocks. Andy From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: Jan Decaluwe Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Fri, 30 Jul 2010 13:07:26 -0700 (PDT) Organization: http://groups.google.com Lines: 60 Message-ID: <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> NNTP-Posting-Host: 91.177.68.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280520446 3131 127.0.0.1 (30 Jul 2010 20:07:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Jul 2010 20:07:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=91.177.68.126; posting-account=WtMxSAoAAAD64fCvvWweI3gIe90Db4Yz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100401 Ubuntu/9.10 (karmic) Firefox/3.5.9,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3965 On Jul 30, 7:13=A0pm, Thomas Heller wrote: > Andy Peters schrieb: > > > However, you have to realize that FPGA flip-flops are sensitive to the > > edge of only one signal, so the synthesis tools will likely barf on > > code that uses more than one signal's edge. > > I know this very well, having designed digital circuits since 35 years ;-= ) > And not all clock signals have to go into the same flip-flop's clock inpu= t. > > Part of the question in my original post was: How would the below VHDL co= de > look like in a single verilog process: > > process(in_a, in_b, up, down) > begin > =A0 if up =3D '1' and down =3D '1' then > =A0 =A0 up <=3D '0'; > =A0 =A0 down <=3D '0'; > =A0 else > =A0 =A0 if rising_edge(in_a) then > =A0 =A0 =A0 up <=3D '1'; > =A0 =A0 end if; > =A0 =A0 if rising_edge(in_b) then > =A0 =A0 =A0 down <=3D '1'; > =A0 =A0 end if; > =A0 end if; > end process; > > Thomas Interesting, isn't it? You ask a question about modeling and everyone is immediately concerned about synthesis :-) What you need is way to check, in an if statement, which signal has just seen an event. I'm not aware of a way to do this in Verilog, although of course the proper forum to ask would be comp.lang.verilog. (Who knows what can be found in the dark corners of the standards...) It cannot be done in MyHDL either, although it would certainly be possible to support this, e.g. by a Signal.event attribute. I would be reluctant to add this, because it would add operations in the main simulation loop for an uncertain value, given that the whole Verilog community can perfectly live without it ... (not entirely sure about that argument either though :-)) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!5g2000yqz.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Connecting "signed" to "std_logic_vector" ports. Date: Fri, 30 Jul 2010 18:44:43 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: References: b24d152c-a1d2-4236-96f9-d28e14a2813e@u11g2000vbd.googlegroups.com <4b193e71-0b0b-45c0-abad-a6bb501f08ef@q22g2000yqm.googlegroups.com> <918f7754-8c55-4eb9-a77a-b8ed11157bdc@d8g2000yqf.googlegroups.com> <3fb3c836-0075-497a-9bd5-112b84637d94@d8g2000yqf.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280540684 16078 127.0.0.1 (31 Jul 2010 01:44:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 31 Jul 2010 01:44:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 5g2000yqz.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:11990 comp.lang.vhdl:3966 On Jul 30, 12:20=A0pm, rickman wrote: > On Jul 29, 6:43=A0am, Kolja Sulimma wrote: > > > On 29 Jul., 02:34, KJ wrote: > > > > Instead of this: > > > =A0 =A0 Some_slv_sig <=3D std_logic_vector(Some_unsigned); > > > Do this > > > =A0 =A0 Some_slv_sig <=3D std_ulogic_vector(Some_unsigned); > > > a package numeric_unresolved would be nice.... > > > Kolja > > There is no reason why unresolved can't be added to numeric_std is > there? I don't think you could really *add* the unresolved types to numeric_std because to do so you would have to create new types other than 'unsigned' and 'signed' that are based on std_ulogic. Then of course you would have to get all of the synthesis and simulation vendors on board with the change before you could really use the new types. In the mean time, the 'least common denominator' rule will apply and everyone would continue to use the more supported current data types that are based on the resolved std_logic type...which would then kill all momentum for any of the vendors to support the change and the proposal would likely die quietly. If instead, numeric_std was simply changed from this... type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; to this... type UNSIGNED is array (NATURAL range <>) of STD_ULOGIC; type SIGNED is array (NATURAL range <>) of STD_ULOGIC; Then the only ones the user community would have to beat on to get this implemented would be the simulation vendors. Synthesis vendors already flag multiple driver violations as a standard part of synthesis since they (for the most part) do not implement multiple net drivers. Changes to standard packages should of course not be taken lightly, but off the top of my head, I can't think of anyone that would be negatively impacted by this. I'll toss this out to the newsgroupies first to see if someone can come up with a use case where the change in the definition of 'unsigned' and 'signed' would negatively impact something. If not, then I'll submit it to the standards group for consideration...numeric_std was so close, they were only two letters short in the source code. Sooooo close. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Sat, 31 Jul 2010 10:09:23 +0100 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Sat, 31 Jul 2010 09:09:28 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="16841"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19szo+evuGji/yDG5tED8IwuKTXjgPaITQ=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:OE7jZ7no6RMMk1KRO5Ee/mzosE8= Xref: eternal-september.org comp.lang.vhdl:3967 On Fri, 30 Jul 2010 13:07:26 -0700 (PDT), Jan Decaluwe wrote: >What you need is way to check, in an if statement, which >signal has just seen an event. Ah. Like "rising_edge(sig)" or "sig'event" or something really silly like that? The kind of stuff that only dumb software wonks, writing a bloated language like VHDL, would think of? :-) >I'm not aware of a way to do this in Verilog It's not wildly hard, but it needs care. always @(sigA, sigB) begin reg old_sigA, old_sigB; if (sigA !== old_sigA) begin // sigA has changed end if (sigB !== old_sigB) begin // sigB has changed end old_sigA = sigA; old_sigB = sigB; end Note that you must keep the "old" values IN THE SAME SEQUENTIAL BLOCK as you used to do the test, otherwise you're exposed to all manner of race conditions. Tedious, because it means you must replicate the "old-keeper" code in each place you might need it. Note, too, the use of !== for comparison. The same code works fine for multi-bit signals too, although of course you must be careful to declare the "old_" variables to be the same size as the signals of interest. Needless to say, this is modelling code and won't synthesise correctly! SystemVerilog adds some alternative tricks for doing similar things, with its event variables and event .triggered property. cheers -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Sat, 31 Jul 2010 10:35:42 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280597742 22853 127.0.0.1 (31 Jul 2010 17:35:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 31 Jul 2010 17:35:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3968 Jan, So how is a DDR register (with two clocks and two data inputs) modeled in verilog or myhdl? Andy From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!news.mixmin.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t2g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Connecting "signed" to "std_logic_vector" ports. Date: Sat, 31 Jul 2010 10:50:50 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <9aba4bd4-a975-4a38-a6d7-36e893441223@t2g2000yqe.googlegroups.com> References: b24d152c-a1d2-4236-96f9-d28e14a2813e@u11g2000vbd.googlegroups.com <4b193e71-0b0b-45c0-abad-a6bb501f08ef@q22g2000yqm.googlegroups.com> <918f7754-8c55-4eb9-a77a-b8ed11157bdc@d8g2000yqf.googlegroups.com> <3fb3c836-0075-497a-9bd5-112b84637d94@d8g2000yqf.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280598650 30586 127.0.0.1 (31 Jul 2010 17:50:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 31 Jul 2010 17:50:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t2g2000yqe.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:11995 comp.lang.vhdl:3969 It would break existing code that used signed/unsigned like SLV, and needed the tri-state, multi-driver logic. Also, elements of unsigned would not be SL, with the same problem. Am I just dreaming, or wasn't there an effort to change the relationship between SLV and SULV such that they would become interchangeable subtypes like SUL and SL are? E.G. subtype SLV is resolved(SULV); or similar, with a new version of resolved() to match. It seems like the gotcha was that an element of such an SLV would no longer be SL, but SUL. But I thought they got around that. Andy From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l25g2000prn.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Duck Shoot Game Date: Sun, 1 Aug 2010 11:56:10 -0700 (PDT) Organization: http://groups.google.com Lines: 150 Message-ID: NNTP-Posting-Host: 217.171.129.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1280688971 1266 127.0.0.1 (1 Aug 2010 18:56:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 1 Aug 2010 18:56:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l25g2000prn.googlegroups.com; posting-host=217.171.129.74; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET4.0C; .NET4.0E),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3970 I have the following code which uses di, do duck in duck out to represent a duck in the sights of a gun. Load save provide loading and saving, run runs the process, rw, sel control selection as write gating, comde controls compute an reverses it, busy signals that do is not valid or r/w etc should not be done yrt. It simulates a duck in the sights from a duck pond. The fast 0 ducks are less likly to be in the sights than a 1 or slow duck. The bias of expected ducks fast being harder to target is the goal. It's BSD licence and free non comercial use. I'm looking to get a better bias to slow ducks in the sights. The process must be reversable for practical reasons. Any comments and suggestions are most welcome. -- (C)2008 K Ring Technologies Semiconductor -- BSD http://nibz.googlecode.com (no support) -- Comercial licencing available -- Tel: +44 796 797 3001 (a real space odessy) -- Maintained by Simon Jackson, BEng. -- E-mail: jackokring@gmail.com -- Hardware support kodek for nibz library ieee; -- library altera; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity k is port ( do : buffer std_Logic; di : in std_logic; busy : buffer std_logic; comde : std_logic; clk : in std_logic; -- a rising edge signal (run) run : in std_logic; -- for setting the prbs -- may be of use as a general prbs ... load : in std_logic_vector(15 downto 0); save : buffer std_logic_vector(15 downto 0); rw : in std_logic; sel : in std_logic ); end entity; architecture rtl of k is signal asymproc : std_logic; signal which : std_logic; type s is (action,motion); signal state : s; -- intermediates signal wind : std_logic_vector(4 downto 0); signal procp : std_logic_vector(1 downto 0); signal tapx : std_logic; signal ends : std_logic; -- process control flags signal procdo : std_logic; signal winddo : std_logic; signal modo : std_logic; signal runlast : std_logic; constant tap : natural := 3; signal pmux : std_logic_vector(15 downto 0); begin process(clk) -- prbs begin end process; procp <= pmux(1 downto 0); procdo <= procp(1) and procp(0); -- set motion velocities via probability switching modo <= procdo xor which xor do xor '1'; -- set sampling window wind <= pmux(7 downto 3); winddo <= wind(4) and wind(3) and wind(2) and wind(1) and wind(0); process(clk) -- k state machine begin if(rising_edge(clk)) then runlast <= run; end if; if(rising_edge(clk) and busy = '1') then case state is when motion => asymproc <= asymproc xor modo; state <= action; when action => if(asymproc = '0') then if(which = '0') then -- sample if(winddo = '1') then busy <= '0'; -- sample do end if; else -- random do <= do xor procp(0); end if; else which <= which xor procdo; end if; state <= motion; end case; -- NB. if 2nd rising edge run before busy zero -- then ignored elsif(rising_edge(clk) and runlast = '0' and run = '1') then -- set busy, cleared by kodek finish bit busy <= '1'; do <= di; end if; -- prbs if(comde = '1') then ends <= save(15); else ends <= save(0); end if; tapx <= save(tap) xor ends; if(rising_edge(clk) and busy = '1') then if(comde = '1') then save <= save(14 downto 0)&tapx; else save <= tapx&save(15 downto 1); end if; end if; if(comde = '1') then pmux <= save; else pmux <= tapx&save(15 downto 1); end if; -- load if(rising_edge(clk) and sel = '1' and rw = '0') then -- NB. a load while busy can be a random number gen -- but not much use in general operation -- do a kind of reset asymproc <= '0'; -- rand/samp side which <= '0'; -- samp side state <= motion; -- perform motion methods first -- (begin and end on them) -- assign essentials save <= load; end if; end process; end rtl; From newsfish@newsfish Fri Dec 24 22:54:47 2010 Path: eternal-september.org!feeder.erje.net!feeder2.news.elisa.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: New Version of Emacs vhdl-mode Available Date: Mon, 02 Aug 2010 18:12:00 +0300 Lines: 14 Message-ID: References: <1464e71d-b076-4721-86bc-f3bbbc8516ca@t35g2000vbb.googlegroups.com> NNTP-Posting-Host: pepper.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1280761920 11036 2001:708:310:3430:203:baff:fe7d:42dd (2 Aug 2010 15:12:00 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Mon, 2 Aug 2010 15:12:00 +0000 (UTC) User-Agent: Gnus/5.1006 (Gnus v5.10.6) XEmacs/21.4 (Constant Variable, usg-unix-v) Cancel-Lock: sha1:LSvrtTq+HCr4M/OnsMFMVPe3Wvg= Xref: eternal-september.org comp.lang.vhdl:3971 "M. Norton" writes: > Just wanted to let other emacs enthusiasts know that a new version of > the vhdl-mode.el is available. Changelog is available at > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html. Many, many > thanks to Reto Zimmerman for maintaining this excellent tool. Thanks to Reto seconded! And thanks for the tip, it seems Emacs 23 ships an old version (3.33.6) from 2005. Looks like the installation instructions for Windows are a little outdated. These days, you can just open ~/.emacs (or ~/.emacs.d/init.el) and update your load-path there, just like Linux or Unix. From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!nerim.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Connecting "signed" to "std_logic_vector" ports. Date: Tue, 3 Aug 2010 06:40:07 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <23d8dd43-1aad-474d-836d-90a58044afb6@l20g2000yqm.googlegroups.com> References: b24d152c-a1d2-4236-96f9-d28e14a2813e@u11g2000vbd.googlegroups.com <4b193e71-0b0b-45c0-abad-a6bb501f08ef@q22g2000yqm.googlegroups.com> <918f7754-8c55-4eb9-a77a-b8ed11157bdc@d8g2000yqf.googlegroups.com> <3fb3c836-0075-497a-9bd5-112b84637d94@d8g2000yqf.googlegroups.com> <9aba4bd4-a975-4a38-a6d7-36e893441223@t2g2000yqe.googlegroups.com> NNTP-Posting-Host: 24.180.106.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280842807 18124 127.0.0.1 (3 Aug 2010 13:40:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 3 Aug 2010 13:40:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=24.180.106.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:12028 comp.lang.vhdl:3972 On Jul 31, 1:50=A0pm, Andy wrote: > It would break existing code that used signed/unsigned like SLV, and > needed the tri-state, multi-driver logic. Also, elements of unsigned > would not be SL, with the same problem. > Actually, I intended my question more along the lines of if signed/ unsigned were changed to be collections of std_ulogic rather than std_logic, how many would really notice/care? I understand that those who use signed/unsigned with multiple drivers would be affected...but how many of those cases are actually out there? So, do *you* use multiple drivers on signed/unsigned signals? Is that actually important to you? KJ From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!q22g2000yqm.googlegroups.com!not-for-mail From: Jan Decaluwe Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Tue, 3 Aug 2010 06:58:20 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> NNTP-Posting-Host: 91.177.145.124 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280843900 14460 127.0.0.1 (3 Aug 2010 13:58:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 3 Aug 2010 13:58:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q22g2000yqm.googlegroups.com; posting-host=91.177.145.124; posting-account=WtMxSAoAAAD64fCvvWweI3gIe90Db4Yz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100401 Ubuntu/9.10 (karmic) Firefox/3.5.9,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3973 On Jul 31, 7:35=A0pm, Andy wrote: > Jan, > > So how is a DDR register (with two clocks and two data inputs) modeled > in verilog or myhdl? > > Andy With Jonathans's somewhat brute-force method I guess :-) Mm, perhaps I really should consider adding an .event attribute, or doing it like in SystemVerilog if someone can tell me how that is exactly ... -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!i31g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Connecting "signed" to "std_logic_vector" ports. Date: Tue, 3 Aug 2010 09:04:12 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: <5f28050c-749e-4a54-822b-97274bcaf96b@i31g2000yqm.googlegroups.com> References: b24d152c-a1d2-4236-96f9-d28e14a2813e@u11g2000vbd.googlegroups.com <4b193e71-0b0b-45c0-abad-a6bb501f08ef@q22g2000yqm.googlegroups.com> <918f7754-8c55-4eb9-a77a-b8ed11157bdc@d8g2000yqf.googlegroups.com> <3fb3c836-0075-497a-9bd5-112b84637d94@d8g2000yqf.googlegroups.com> <9aba4bd4-a975-4a38-a6d7-36e893441223@t2g2000yqe.googlegroups.com> <23d8dd43-1aad-474d-836d-90a58044afb6@l20g2000yqm.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280851455 28392 127.0.0.1 (3 Aug 2010 16:04:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 3 Aug 2010 16:04:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i31g2000yqm.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:12032 comp.lang.vhdl:3974 On Aug 3, 8:40=A0am, KJ wrote: > On Jul 31, 1:50=A0pm, Andy wrote: > > > It would break existing code that used signed/unsigned like SLV, and > > needed the tri-state, multi-driver logic. Also, elements of unsigned > > would not be SL, with the same problem. > > Actually, I intended my question more along the lines of if signed/ > unsigned were changed to be collections of std_ulogic rather than > std_logic, how many would really notice/care? =A0I understand that those > who use signed/unsigned with multiple drivers would be affected...but > how many of those cases are actually out there? =A0So, do *you* use > multiple drivers on signed/unsigned signals? =A0Is that actually > important to you? > > KJ Mostly in places where I have an inout port (or procedure argument) of a record type, and I need resolution functions to manage in and out elements more often than I actually use a bidirectional element. My test benches tend to have lots of procedures like read/write(bus, address, data) I have also used unsigned on tri-stated primary IOs of FPGAs (it is easy enough to convert them back to SLV if I need to use the gate level models). Internally, I have used them with a tri-state bus description, knowing full-well that the synthesis tool would convert them to muxes for me. The added benefit is that the synthesis tool can assume that the tri- state enables are mutually exclusive, which allows it to optimize the muxes. Sometimes it is just easier to describe an interface with a bus, than to create the mux and the plumbing for it. I don't usually do truly bi-directional busses, but sometimes... So, yes, I have used them in several areas. IMHO, changes to the language or standard packages must be backwards compatible (even though in rare cases in the past they have not been so), so that they don't break anyone's code, regardless of how common (or even "useful") a given usage is. The "prime directive" WRT changes to the standards should be "do no harm". If we need a different numeric_std-like package, so be it. Andy From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!feeder.erje.net!feeder.news-service.com!news.astraweb.com!border5.a.newsrouter.astraweb.com!feeder2.cambriumusenet.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!198.186.194.250.MISMATCH!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!x21g2000yqa.googlegroups.com!not-for-mail From: dgreig Newsgroups: comp.lang.vhdl Subject: Re: New Version of Emacs vhdl-mode Available Date: Wed, 4 Aug 2010 01:01:14 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <0bae59d3-5f11-42f0-921a-e2f6e1b768d0@x21g2000yqa.googlegroups.com> References: <1464e71d-b076-4721-86bc-f3bbbc8516ca@t35g2000vbb.googlegroups.com> NNTP-Posting-Host: 84.19.254.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280908874 9093 127.0.0.1 (4 Aug 2010 08:01:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 4 Aug 2010 08:01:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x21g2000yqa.googlegroups.com; posting-host=84.19.254.82; posting-account=jWYCGAoAAACtdbpYfrlZ1GVzvYP1FIDc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.2; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 ( .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3975 On Jul 27, 2:26=A0pm, "M. Norton" wrote: > Just wanted to let other emacs enthusiasts know that a new version of > the vhdl-mode.el is available. =A0Changelog is available athttp://www.iis= .ee.ethz.ch/~zimmi/emacs/vhdl-mode.html. =A0Many, many > thanks to Reto Zimmerman for maintaining this excellent tool. > > Mark I'll third that. Cant't help thinking that there is a 2008 version going around somewhere. Does anyone know how to create or modify a mode? David From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 04 Aug 2010 13:56:11 +0200 Lines: 40 Message-ID: <87r5iey4kk.fsf@harnisch.dyndns.org> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net LUqfNb64wvT4iMJr4LQUCwuuc1UxdRxofLTSqRRrZHn5hz30m6 Cancel-Lock: sha1:yZW9THxu+GSRyuZCkzzV0vSiCj8= sha1:q25ofbNC/VGUy649JECXTyY9wcM= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b29 (linux) Xref: eternal-september.org comp.lang.vhdl:3976 Jan Decaluwe writes: > On Jul 31, 7:35 pm, Andy wrote: >> So how is a DDR register (with two clocks and two data inputs) modeled >> in verilog or myhdl? > > With Jonathans's somewhat brute-force method I guess :-) But why has nobody asked about the rationale for the requirement(?) implementing the original function in one process? Nobody here seriously believes that this would simulate faster?! Regarding the DDR register above, just use two processes assigning to the same register. As opposed to VHDL concurrent drivers, in Verilog the last assignment wins. Should both clock edges occur simultaneously, it is undefined which assignment is effective. I guess that models the real world pretty well. always @(posedge clk0, posedge reset) begin if (reset) q <= 0; else q <= d0; end always @(posedge clk1, posedge reset) begin if (reset) q <= 0; else q <= d1; end -- Marcus note that "property" can also be used as syntactic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!d17g2000yqb.googlegroups.com!not-for-mail From: Jan Decaluwe Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 4 Aug 2010 07:33:40 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> <87r5iey4kk.fsf@harnisch.dyndns.org> NNTP-Posting-Host: 91.177.157.112 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280932420 5760 127.0.0.1 (4 Aug 2010 14:33:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 4 Aug 2010 14:33:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d17g2000yqb.googlegroups.com; posting-host=91.177.157.112; posting-account=ltnGpQgAAADxtXr5-Rt4cfPQkzupVM6C User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100401 Ubuntu/9.10 (karmic) Firefox/3.5.9,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3977 On Aug 4, 1:56=A0pm, Marcus Harnisch wrote: > Jan Decaluwe writes: > > On Jul 31, 7:35=A0pm, Andy wrote: > >> So how is a DDR register (with two clocks and two data inputs) modeled > >> in verilog or myhdl? > > > With Jonathans's somewhat brute-force method I guess :-) > > But why has nobody asked about the rationale for the requirement(?) > implementing the original function in one process? Nobody here > seriously believes that this would simulate faster?! > > Regarding the DDR register above, just use two processes assigning to > the same register. As opposed to VHDL concurrent drivers, in Verilog > the last assignment wins. Should both clock edges occur > simultaneously, it is undefined which assignment is effective. I guess > that models the real world pretty well. I suspect the reason is that VHDL designers tend to care about determinism. The fact that the real world is non-deterministic doesn't imply that it's a good idea to make your simulations non-deterministic also. Jan From newsfish@newsfish Fri Dec 24 22:54:48 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!f6g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 4 Aug 2010 07:48:03 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> <87r5iey4kk.fsf@harnisch.dyndns.org> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280933284 26352 127.0.0.1 (4 Aug 2010 14:48:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 4 Aug 2010 14:48:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f6g2000yqa.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3978 On Aug 4, 9:33=A0am, Jan Decaluwe wrote: > On Aug 4, 1:56=A0pm, Marcus Harnisch wrote: > > > > > > > Jan Decaluwe writes: > > > On Jul 31, 7:35=A0pm, Andy wrote: > > >> So how is a DDR register (with two clocks and two data inputs) model= ed > > >> in verilog or myhdl? > > > > With Jonathans's somewhat brute-force method I guess :-) > > > But why has nobody asked about the rationale for the requirement(?) > > implementing the original function in one process? Nobody here > > seriously believes that this would simulate faster?! > > > Regarding the DDR register above, just use two processes assigning to > > the same register. As opposed to VHDL concurrent drivers, in Verilog > > the last assignment wins. Should both clock edges occur > > simultaneously, it is undefined which assignment is effective. I guess > > that models the real world pretty well. > > I suspect the reason is that VHDL designers tend to care about > determinism. The fact that the real world is non-deterministic doesn't > imply that it's a good idea to make your simulations non-deterministic > also. > > Jan- Hide quoted text - > > - Show quoted text - To add to that, I would want my model to tell me if it could not determine what the modelled behavior (i.e. hardware) would/should do. This could be via an assertion failure and/or by assigning the output to 'X' if both clocks occurred at the same time. Maybe there's a way to do that in verilog and/or myhdl? Andy From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!m1g2000yqo.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 4 Aug 2010 08:05:53 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> <87r5iey4kk.fsf@harnisch.dyndns.org> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280934353 3249 127.0.0.1 (4 Aug 2010 15:05:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 4 Aug 2010 15:05:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000yqo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3979 On Aug 4, 6:56=A0am, Marcus Harnisch wrote: > Jan Decaluwe writes: > > On Jul 31, 7:35=A0pm, Andy wrote: > >> So how is a DDR register (with two clocks and two data inputs) modeled > >> in verilog or myhdl? > > > With Jonathans's somewhat brute-force method I guess :-) > > But why has nobody asked about the rationale for the requirement(?) > implementing the original function in one process? Nobody here > seriously believes that this would simulate faster?! > > Regarding the DDR register above, just use two processes assigning to > the same register. As opposed to VHDL concurrent drivers, in Verilog > the last assignment wins. Should both clock edges occur > simultaneously, it is undefined which assignment is effective. I guess > that models the real world pretty well. > > =A0 =A0 always @(posedge clk0, posedge reset) begin > =A0 =A0 =A0 =A0 if (reset) > =A0 =A0 =A0 =A0 =A0 q <=3D 0; > =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 q <=3D d0; > =A0 =A0 end > > =A0 =A0 always @(posedge clk1, posedge reset) begin > =A0 =A0 =A0 =A0 if (reset) > =A0 =A0 =A0 =A0 =A0 q <=3D 0; > =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 q <=3D d1; > =A0 =A0 end > > -- > Marcus > > note that "property" can also be used as syntactic sugar to reference > a property, breaking the clean design of verilog; [...] > > =A0 =A0 =A0 =A0 =A0 =A0 =A0(seen onhttp://www.veripool.com/verilog-mode_n= ews.html) Aha! I keep forgetting you can do that in verilog... Reasons a single process is desired in vhdl include that it would simulate faster, especially since it would allow using a variable instead of a signal. I suppose we all assume solutions in the forms we are most used to. Thanks for keeping us honest. Andy From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Marcus Harnisch Newsgroups: comp.lang.vhdl Subject: Re: VHDL vs. verilog question Date: Wed, 04 Aug 2010 19:16:27 +0200 Lines: 57 Message-ID: <87iq3qxpqs.fsf@harnisch.dyndns.org> References: <8bbdrnFdocU1@mid.individual.net> <3111de37-8cc9-47fa-a031-ca7d78e7260e@t10g2000yqg.googlegroups.com> <8bg2r7F863U2@mid.individual.net> <8bgfi6FlqkU1@mid.individual.net> <9a66dd6f-9a0d-4495-b890-5aa7d1adf33c@l20g2000yqm.googlegroups.com> <6d168d1c-89ac-4763-b79b-ed73bdb61b5e@d8g2000yqf.googlegroups.com> <87r5iey4kk.fsf@harnisch.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net fCcR2RIKEECv+D2gEbi5twH7T6ij2vXpkXrRdkI6lpfcLdxU2k Cancel-Lock: sha1:NPsL1Lxcx02tEu+H2bdlQai6qhY= sha1:Thzh3APLFgiYWjdTsROor4roD/c= User-Agent: Gnus/5.1008 (Gnus v5.10.8) XEmacs/21.5-b29 (linux) Xref: eternal-september.org comp.lang.vhdl:3980 Jan Decaluwe writes: > On Aug 4, 1:56 pm, Marcus Harnisch wrote: > I suspect the reason is that VHDL designers tend to care about > determinism. The fact that the real world is non-deterministic doesn't > imply that it's a good idea to make your simulations non-deterministic > also. But this objection only applies to the solution for Andy's problem. Thomas wants to drive individual signals which serve as their own asynchronous resets. BTW, at which minimal phase difference do you consider both edges simultaneous. Here is a solution which leaves q as unknown if both clock edges occur in the same time step and try to assign opposite values. For most practical purposes in simulation[1] the code (using blocking assignments) below should suffice: always @(posedge clk0, posedge reset) begin if (reset) q = 0; else begin q = d0; #0; if (q != d0) // the other block has been executed after this one in the // same time step and assigned a different value q = 1'bx; end end always @(posedge clk1, posedge reset) begin if (reset) q = 0; else begin q = d1; #0; if (q != d1) // the other block has been executed after this one in the // same time step and assigned a different value q = 1'bx; end end But we are drifting away from the original request. Footnotes: [1] Since most DDR flops are implemented using special cells you wouldn't want to synthesize this anyway. -- Marcus note that "property" can also be used as syntactic sugar to reference a property, breaking the clean design of verilog; [...] (seen on http://www.veripool.com/verilog-mode_news.html) From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i31g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Connecting "signed" to "std_logic_vector" ports. Date: Wed, 4 Aug 2010 17:59:37 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <8451477e-79db-4206-aae3-a226ea416c4b@i31g2000yqm.googlegroups.com> References: b24d152c-a1d2-4236-96f9-d28e14a2813e@u11g2000vbd.googlegroups.com <4b193e71-0b0b-45c0-abad-a6bb501f08ef@q22g2000yqm.googlegroups.com> <918f7754-8c55-4eb9-a77a-b8ed11157bdc@d8g2000yqf.googlegroups.com> <3fb3c836-0075-497a-9bd5-112b84637d94@d8g2000yqf.googlegroups.com> <9aba4bd4-a975-4a38-a6d7-36e893441223@t2g2000yqe.googlegroups.com> <23d8dd43-1aad-474d-836d-90a58044afb6@l20g2000yqm.googlegroups.com> <5f28050c-749e-4a54-822b-97274bcaf96b@i31g2000yqm.googlegroups.com> NNTP-Posting-Host: 24.180.106.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1280969977 7370 127.0.0.1 (5 Aug 2010 00:59:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 Aug 2010 00:59:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i31g2000yqm.googlegroups.com; posting-host=24.180.106.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: eternal-september.org comp.arch.fpga:12052 comp.lang.vhdl:3981 On Aug 3, 12:04=A0pm, Andy wrote: > On Aug 3, 8:40=A0am, KJ wrote: > IMHO, changes to the language or standard packages must be backwards > compatible (even though in rare cases in the past they have not been > so), Backwards compatibility should not be a 'must have'...although I certainly agree that it is something worth working for to get if you can. Examples of changes that are definitely more onerous to 'used to be working just fine' code were the changes to type 'FILE' and 'shared variables'. > so that they don't break anyone's code, regardless of how common > (or even "useful") a given usage is. I think the cost/benefit should be weighed although just how well one can weigh this with actual users is a bit of a question. > The "prime directive" WRT changes > to the standards should be "do no harm". 'Do no harm' applies to doctors, not engineering standards. If something needs to be improved and is 'worth it' to the users then it should be improved. The definition of whether something is 'worth it' or not is subjective. > If we need a different > numeric_std-like package, so be it. > Maybe just use the fixed point package. The documentation says it uses std_logic as the base, but the actual code says std_ulogic. Thanks for your input on how you use/need multi-driver signed/unsigned Kevin Jennings From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!t2g2000yqe.googlegroups.com!not-for-mail From: Sudoer Newsgroups: comp.lang.vhdl Subject: Is Partial Record Assignment Possible? Date: Fri, 6 Aug 2010 10:34:38 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281116078 12572 127.0.0.1 (6 Aug 2010 17:34:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Aug 2010 17:34:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t2g2000yqe.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.17.8 (KHTML, like Gecko) Version/5.0.1 Safari/533.17.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3983 I often use records within records, or records within records within records, ad nausea. It's nice that I can currently do the following: A.A.A <= X; A.A.B <= Y; A.A.C <= Z; However, there's a lot of repetition in my code, so I often prefer the following: A <= ( A => ( A => X, B => Y, C => Z ) ); The benefit is more noticeable with long and descriptive names for the elements, but the problem is that if my intention is to set only the A, B, and C leaf elements and leave any others unchanged it doesn't seem possible. Is there anything in the 2002 or 2008 standard that allows this, is there any reason this shouldn't be allowed, or is it time that I propose an overloaded use of the keyword unaffected, or another keyword all together (unchanged/same/handsoff?) A <= ( A => ( A => X, B => Y, C => Z, D => UNAFFECTED ) ); A <= ( A => ( A => X, B => Y, C => Z, OTHERS => UNAFFECTED ) ); Obviously it would be useful for slices as well. Since I haven't been able to play with 2008 yet, I'm wondering if left- side aggregates (not sure what they're called) would also simplify the above. Thanks! From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 06 Aug 2010 14:26:06 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 06 Aug 2010 20:33:22 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-lgDPxp3Qr525TwAs1AO4p9iydXRpt7cTgC/9z0dGqV8aJ2io3G1P060eLWkXPq1iimgimKr6DV7Gbgr!mB5D3Al/nuEX/lxGyXnskaCLH9po5oMhlZNxyD46VmwZuol2XZdEfoKotMFgCJmsmYnas1EbHj0D!dqpc X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: eternal-september.org comp.lang.vhdl:3984 On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer wrote: >I often use records within records, or records within records within >records, ad nausea. It's nice that I can currently do the following: > >A.A.A <= X; >A.A.B <= Y; >A.A.C <= Z; > >However, there's a lot of repetition in my code, so I often prefer the >following: > >A <= ( A => ( A => X, > B => Y, > C => Z ) ); > >The benefit is more noticeable with long and descriptive names for the >elements, but the problem is that if my intention is to set only the >A, B, and C leaf elements and leave any others unchanged it doesn't >seem possible. Funny, I would have expected A.A <= ( A => X, B => Y, C => Z ); or even A.A <= (X,Y,Z) ; to do the job. - Brian From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m1g2000yqo.googlegroups.com!not-for-mail From: Sudoer Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 6 Aug 2010 14:28:47 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> References: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281130127 4621 127.0.0.1 (6 Aug 2010 21:28:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Aug 2010 21:28:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000yqo.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.17.8 (KHTML, like Gecko) Version/5.0.1 Safari/533.17.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3985 On Aug 6, 3:33=A0pm, Brian Drummond wrote: > On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer > wrote: > > > > > > >I often use records within records, or records within records within > >records, ad nausea. It's nice that I can currently do the following: > > >A.A.A <=3D X; > >A.A.B <=3D Y; > >A.A.C <=3D Z; > > >However, there's a lot of repetition in my code, so I often prefer the > >following: > > >A <=3D ( A =3D> ( A =3D> X, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0B =3D> Y, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0C =3D> Z ) ); > > >The benefit is more noticeable with long and descriptive names for the > >elements, but the problem is that if my intention is to set only the > >A, B, and C leaf elements and leave any others unchanged it doesn't > >seem possible. > > Funny, I would have expected > > A.A <=3D ( A =3D> X, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 B =3D> Y, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 C =3D> Z ); > or even > > A.A <=3D (X,Y,Z) ; > > to do the job. > > - Brian Me too - in fact that was what I tried first. However, I get the following error when using XST: ERROR:HDLCompiler:790 - "*REDACTED*" Line 78: Some record elements are missing in this aggregate of A_TYPE Perhaps this is an XST thing and not a VHDL thing? Can anyone else get the above to work using different synthesis software? From newsfish@newsfish Fri Dec 24 22:54:49 2010 Path: eternal-september.org!feeder.news-service.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 06 Aug 2010 16:34:28 -0500 Date: Fri, 06 Aug 2010 14:34:28 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.11) Gecko/20100711 Thunderbird/3.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> In-Reply-To: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 58 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-nYs2duAl4lVxaFjjXVPq4V+IBcQgdtd81kXrlxwWjYQwst9RchpCZhfrLMj2L+TcphkBmrhism1dpZ2!3186TCoFZQMpq75aRBc++wf9xO/w01xyOjIlnB4l9u+lHrrqeEcIbNdYnBVyYnfJAvx/DJLR+3th!Jg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: eternal-september.org comp.lang.vhdl:3986 On 8/6/2010 2:28 PM, Sudoer wrote: > On Aug 6, 3:33 pm, Brian Drummond > wrote: >> On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer >> wrote: >> >> >> >> >> >>> I often use records within records, or records within records within >>> records, ad nausea. It's nice that I can currently do the following: >> >>> A.A.A<= X; >>> A.A.B<= Y; >>> A.A.C<= Z; >> >>> However, there's a lot of repetition in my code, so I often prefer the >>> following: >> >>> A<= ( A => ( A => X, >>> B => Y, >>> C => Z ) ); >> >>> The benefit is more noticeable with long and descriptive names for the >>> elements, but the problem is that if my intention is to set only the >>> A, B, and C leaf elements and leave any others unchanged it doesn't >>> seem possible. >> >> Funny, I would have expected >> >> A.A<= ( A => X, >> B => Y, >> C => Z ); >> or even >> >> A.A<= (X,Y,Z) ; >> >> to do the job. >> >> - Brian > > Me too - in fact that was what I tried first. However, I get the > following error when using XST: > > ERROR:HDLCompiler:790 - "*REDACTED*" Line 78: Some record elements are > missing in this aggregate of A_TYPE > > Perhaps this is an XST thing and not a VHDL thing? Can anyone else get > the above to work using different synthesis software? Ahhh, THAT old problem. The process in which you assign any elements of an aggregate signal (record, array, etc) has to be the one in which you assign all of the elements of it. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t2g2000yqe.googlegroups.com!not-for-mail From: Sudoer Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 6 Aug 2010 15:21:02 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: <9ce98c3f-e18c-4410-8c26-8742ca304d71@t2g2000yqe.googlegroups.com> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281133262 16401 127.0.0.1 (6 Aug 2010 22:21:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Aug 2010 22:21:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t2g2000yqe.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.17.8 (KHTML, like Gecko) Version/5.0.1 Safari/533.17.8,gzip(gfe) Xref: eternal-september.org comp.lang.vhdl:3987 On Aug 6, 5:34=A0pm, Rob Gaddi wrote: > On 8/6/2010 2:28 PM, Sudoer wrote: > > > > > > > On Aug 6, 3:33 pm, Brian Drummond > > wrote: > >> On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer > >> wrote: > > >>> I often use records within records, or records within records within > >>> records, ad nausea. It's nice that I can currently do the following: > > >>> A.A.A<=3D X; > >>> A.A.B<=3D Y; > >>> A.A.C<=3D Z; > > >>> However, there's a lot of repetition in my code, so I often prefer th= e > >>> following: > > >>> A<=3D ( A =3D> =A0( A =3D> =A0X, > >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 B =3D> =A0Y, > >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 C =3D> =A0Z ) ); > > >>> The benefit is more noticeable with long and descriptive names for th= e > >>> elements, but the problem is that if my intention is to set only the > >>> A, B, and C leaf elements and leave any others unchanged it doesn't > >>> seem possible. > > >> Funny, I would have expected > > >> A.A<=3D ( A =3D> =A0X, > >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0B =3D> =A0Y, > >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0C =3D> =A0Z ); > >> or even > > >> A.A<=3D (X,Y,Z) ; > > >> to do the job. > > >> - Brian > > > Me too - in fact that was what I tried first. However, I get the > > following error when using XST: > > > ERROR:HDLCompiler:790 - "*REDACTED*" Line 78: Some record elements are > > missing in this aggregate of A_TYPE > > > Perhaps this is an XST thing and not a VHDL thing? Can anyone else get > > the above to work using different synthesis software? > > Ahhh, THAT old problem. =A0The process in which you assign any elements o= f > an aggregate signal (record, array, etc) has to be the one in which you > assign all of the elements of it. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Well, that too is annoying, but I'm not quite seeing how that's related to the behavior I'm taking exception to today. I simply do not want to change the values of some elements in a record, only sometimes, and when assigning to the whole record. Frequently this will happen in some case statement - for some when's I want to assign some values, and for others I want to assign other values. If I assign to individual elements of a record I have no issue, but when I try to assign to the record itself it requires that I provide a value for every element. I'll admit right now that what I'm asking for here is pure swizzle- stick syntax sugar, but the difference between a language like C++ or Ada and a language like BF is exactly pure swizzle-stick syntax sugar (who needs named variables anyway?) I've found that unmanageable code tends to crop up most often when I have to do a lot of copying and pasting - this issue alone has caused me to create a new emacs macro that does nothing but copy the character directly above the point (cursor) to the point, but I do have my macro and so I'll survive if no one agrees with me that this would be a nice VHDL feature in future standards, or if no one can point out to me how to do it in any existing standard... From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 06 Aug 2010 23:30:49 +0100 Organization: A noiseless patient Spider Lines: 43 Message-ID: <653p56t025l60g7kr454n4tm7kncqthk9a@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Fri, 6 Aug 2010 22:30:52 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="28210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19LdOn1ysZO2QdFvHharTzFlMe8Yf6A0RQ=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:LDuDOHfsRYo7AxySpCaudjHd7fE= Xref: eternal-september.org comp.lang.vhdl:3988 On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer wrote: >I often use records within records, or records within records within >records, ad nausea. It's nice that I can currently do the following: > >A.A.A <= X; >A.A.B <= Y; >A.A.C <= Z; > >However, there's a lot of repetition in my code, so I often prefer the >following: > >A <= ( A => ( A => X, > B => Y, > C => Z ) ); > >The benefit is more noticeable with long and descriptive names for the >elements, but the problem is that if my intention is to set only the >A, B, and C leaf elements and leave any others unchanged it doesn't >seem possible. How about an alias? alias AA: ABC_record_type is A.A; ... AA.A <= X; Doesn't quite do what you asked for (I don't think that's possible) but it does simplify the naming problem somewhat. Functions and procedures might be useful too: procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is begin T.A <= X; ... end; ... tweakJustTheLeafParts(A.A); -- does A.A.A <= X; Watch out for multiple drivers, though, as Rob Gaddi points out. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 06 Aug 2010 23:31:20 +0100 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Fri, 6 Aug 2010 22:31:22 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="28239"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/EtdFm6OXb2BYTyhTMhbeOPg8uoK6vpe4=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:nR4lrMeQfzPngMfW4aKB7nLPGR0= Xref: eternal-september.org comp.lang.vhdl:3989 On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer wrote: >I often use records within records, or records within records within >records, ad nausea. It's nice that I can currently do the following: > >A.A.A <= X; >A.A.B <= Y; >A.A.C <= Z; > >However, there's a lot of repetition in my code, so I often prefer the >following: > >A <= ( A => ( A => X, > B => Y, > C => Z ) ); > >The benefit is more noticeable with long and descriptive names for the >elements, but the problem is that if my intention is to set only the >A, B, and C leaf elements and leave any others unchanged it doesn't >seem possible. How about an alias? alias AA: ABC_record_type is A.A; ... AA.A <= X; Doesn't quite do what you asked for (I don't think that's possible) but it does simplify the naming problem somewhat. Functions and procedures might be useful too: procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is begin T.A <= X; ... end; ... tweakJustTheLeafParts(A.A); -- does A.A.A <= X; Watch out for multiple drivers, though, as Rob Gaddi points out. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 06 Aug 2010 17:39:15 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Fri, 06 Aug 2010 23:46:32 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 44 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-pItxKOyk8AtShrlY20lLBCaDmmcXDmarhGEuNEpkRU3I/Bdslsp9rAQSBCZpTqcLl3Y9pXieEZuB8bP!ZkueQXdMQHyAVYkGn5FMvxKKNKRGakzL67iyIGqCdTHsXgKjixjCspnqVF8/L5PpcRaWknOpQDVt!m8id X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2649 Xref: eternal-september.org comp.lang.vhdl:3990 On Fri, 6 Aug 2010 14:28:47 -0700 (PDT), Sudoer wrote: >On Aug 6, 3:33 pm, Brian Drummond >wrote: >> On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer >> wrote: >> >However, there's a lot of repetition in my code, so I often prefer the >> >following: >> >A <= ( A => ( A => X, >> >                    B => Y, >> >                    C => Z ) ); >> >...if my intention is to set only the >> >A, B, and C leaf elements and leave any others unchanged it doesn't >> >seem possible. >> >> Funny, I would have expected >> A.A <= (X,Y,Z) ; >> to do the job. >Me too - in fact that was what I tried first. However, I get the >following error when using XST: > >ERROR:HDLCompiler:790 - "*REDACTED*" Line 78: Some record elements are >missing in this aggregate of A_TYPE First : if Modelsim accepts it, it's probably an XST-ism. If not, I have learned something about VHDL today... Maybe it's possible to work around the problem using a function? (or set of functions, overloaded by different parameters) e.g. A <= new_A (A, partA => (X,Y,Z)); function new_A (A : in A_type; partA : in partial_A_type) return A_type is variable temp_A := A; begin temp_A.A := partA; return temp; end new_A; - Brian From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t20g2000yqa.googlegroups.com!not-for-mail From: Sheetal Newsgroups: comp.lang.vhdl Subject: VHDL newbie- stuck just weeks before project submission :(..please help Date: Sat, 7 Aug 2010 10:16:00 -0700 (PDT) Organization: http://groups.google.com Lines: 97 Message-ID: <17d33efe-45a1-4d2f-a75d-71b88f8009e1@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.5.110.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281201361 2906 127.0.0.1 (7 Aug 2010 17:16:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 7 Aug 2010 17:16:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t20g2000yqa.googlegroups.com; posting-host=94.5.110.109; posting-account=-LVHLAoAAAALPk59dS_mpM_ksS51IT2V User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:3991 Hello, For my Masters project, I'm trying to implement a multiplier, and a MAC where the outputs are calculated per clock cycle and stored in a text file which can then be used for further processing. However, both these designs are giving out partial products(I guess they are partial products) at the output too, before they give the final result..I've tried changing the codes, changing clock frequency in testbench etc. but nothing seems to work... Is there any way to implement a output_ready signal for multipliers/ adders?(I saw a few codes using shifter for rdy, but could not understand the logic behind it) I'm using the embedded Mult18X18 in Spartan 3..but do not want to use the Core generator for MAC(which has a RDY signal) as the code has to be kept portable. Code for multiplier is-- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Single_Mul is Port ( Clk : in STD_LOGIC; Mul1 : in STD_LOGIC_VECTOR (17 downto 0); Mul2 : in STD_LOGIC_VECTOR(17 downto 0); Mul_Res : out STD_LOGIC_VECTOR(35 downto 0)); end Single_Mul; architecture Behavioral of Single_Mul is Signal Prod : Signed( 35 downto 0):="000000000000000000000000000000000000"; begin process(clk)is begin if rising_edge(Clk) then Prod<=signed(Mul1)*signed(Mul2); end if; end process; Prod_Process:Process(prod) begin Mul_Res<=STD_LOGIC_VECTOR(Prod);--here I was hoping this process is --invoked only when the --clocked process above is complete... end process; end Behavioral; Code for MAC-- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_STD.all; entity Mul_Adder is Port ( MulA : in STD_LOGIC_VECTOR (17 downto 0); MulB : in STD_LOGIC_VECTOR(17 downto 0); Multi_Res : in STD_LOGIC_VECTOR(35 downto 0); MulAdd_Res : out STD_LOGIC_VECTOR(35 downto 0); Clk : in STD_LOGIC); end Mul_Adder; architecture Behavioral of Mul_Adder is shared variable temp :SIGNED(35 downto 0);--:="000000000000000000000000000000000000"; Signal temp1:SIGNED(35 downto 0):="000000000000000000000000000000000000"; begin Process(Clk) is BEGIN If rising_edge(Clk) then temp:=signed(MulA)*signed(MulB); temp1<=signed(Multi_Res)+temp; end if; End Process; MulAdd_Res_process: Process(temp1) begin MulAdd_Res<=STD_LOGIC_VECTOR(temp1); end Process; end Behavioral; Am I doing anything wrong here? Any help in this direction would be useful From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!m1g2000yqo.googlegroups.com!not-for-mail From: Sudoer Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sat, 7 Aug 2010 10:30:41 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281202241 31352 127.0.0.1 (7 Aug 2010 17:30:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 7 Aug 2010 17:30:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000yqo.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.17.8 (KHTML, like Gecko) Version/5.0.1 Safari/533.17.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:3992 Neither aliasing nor use of a function quite capture what I want to do, if only because they require more code just assigning to each subelement now. The idea is to assign to some, but not all elements, without writing additional code to do so, in a single assignment statement. It also occurs to me that this could reduce the number of signal assignments in total (depending on how the EDA tool author implements it, and it at least serves as an obvious clue to the compiler), which is always a good thing for simulation run times. A very good thing. From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.lang.vhdl Subject: Re: VHDL newbie- stuck just weeks before project submission :(..please help Message-ID: From: Andreas Ehliar Date: 8 Aug 10 11:18:58 MET References: <17d33efe-45a1-4d2f-a75d-71b88f8009e1@t20g2000yqa.googlegroups.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 16 Xref: feeder.eternal-september.org comp.lang.vhdl:3993 On 2010-08-07, Sheetal wrote: > However, both these designs are giving out partial products(I guess > they are partial products) at the output too, before they give the > final result..I've tried changing the codes, changing clock frequency > in testbench etc. but nothing seems to work... I couldn't see anything extremely weird in your code after a cursory glance at it. Where did you observe this phenomenon? Is it in RTL simulation? Is it in post synthesis simulation? Is it in post place and route simulation? Is it in the real hardware? regards /Andreas From newsfish@newsfish Fri Dec 24 22:54:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sun, 08 Aug 2010 12:04:00 +0100 Organization: A noiseless patient Spider Lines: 59 Message-ID: <0n2t56pn5ob4k5hbo5orvdugnmk8svkp1g@4ax.com> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Sun, 8 Aug 2010 11:04:06 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="4804"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/6yZzlQo6Nb7y1wv8pKIhHTfwIZKgG9qk=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:PvxRZId114NRQQz4Y0RA82KdVO8= Xref: feeder.eternal-september.org comp.lang.vhdl:3994 On Sat, 7 Aug 2010 10:30:41 -0700 (PDT), Sudoer wrote: >The idea is to assign to some, but not all elements, >without writing additional code to do so, in a single assignment >statement. And, as you correctly surmise, the language has (as far as I know) no direct way to allow you to do that. You can, of course, use part of the original record in the aggregate expression: A <= (X=>55, Y=>'1', Z=>A.Z); but that still forces you to write out every element somewhere in the aggregate. I'm sure you can see why OTHERS=>UNCHANGED is problematic, because the aggregate doesn't know that it is going to be assigned to A, and so the aggregate can no longer be just an expression of the record type; it needs also to incorporate a bunch of "don't-write" flags. And what would be the meaning of OTHERS=>UNCHANGED if the aggregate were to appear in a context other than simple assignment? So your original question changes from being a language-syntax problem to being an application problem: how can you design your data (and code infrastructure) to do what you want in the clearest possible way? Your requirement is to update a set of (possibly sub-) record elements in the cleanest, most concise possible way. For a single element it's obviously very easy, and minimally verbose: R1.R2.R3.E <= value; But how do you plan to choose your set of record elements, and what drives that choice? If you have just a small number of distinct sets of elements, then I would argue that writing one "update this set" procedure per set of elements is by far the neatest approach. If, however, the set of elements you want to update is more fluid, then I perhaps question your choice of simple records as an implementation vehicle. Of course, records have the huge advantage of supporting elements of heterogeneous data type, so the choice may not be quite so simple; but I would still argue that the problem is one of data structure design. >It also occurs to me that this could reduce the number of >signal assignments in total (depending on how the EDA tool author >implements it, and it at least serves as an obvious clue to the >compiler), Maybe. But I don't see this as a strong argument in favour of adding a language feature. On the other hand, your arguments from code conciseness do seem to me to have some value. But there are many things that would come way higher up my VHDL wish-list. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sun, 08 Aug 2010 12:15:40 +0100 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> <0n2t56pn5ob4k5hbo5orvdugnmk8svkp1g@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Sun, 8 Aug 2010 11:15:45 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="7687"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GFWkI9mIrQ12mspOLhbb3RctMAIjNiNY=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:/rlAh7a6yPhdzpTEs6fqbelTBeM= Xref: feeder.eternal-september.org comp.lang.vhdl:3995 On Sun, 08 Aug 2010 12:04:00 +0100, Jonathan Bromley wrote: >So your original question changes from being a >language-syntax problem to being an application problem: A quick postscript: You *can* use OTHERS=> in a record aggregate, BUT this only works if all the elements specified by OTHERS are of the same type. My guess is that this is no use to you, because your record elements are of various types; and if the record elements are all of the same type, then it's probably easier to use an array anyhow. But I thought I'd mention it because it might make certain approaches possible in some special situations. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 08 Aug 2010 06:48:55 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sun, 08 Aug 2010 12:56:14 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: <3j5t56ttnmj6h9rrp9q1lkaas8joi7pk60@4ax.com> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 38 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-NA8Xwg4x1C61g4N7rz9nw3bj7R0EUekVZrahSCnDcreiMTDgTNxv1JS54YusGCnp+hguyKaugD4gu+J!Pfl1aNpsOo/7VQWi7bCFFCt9nxxRTSCB2TLcCunx0JSW7I8zposdu1cqWhA+CuF5ov270/de1gQZ!Ew== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:3996 On Sat, 7 Aug 2010 10:30:41 -0700 (PDT), Sudoer wrote: >Neither aliasing nor use of a function quite capture what I want to >do, if only because they require more code just assigning to each >subelement now. The idea is to assign to some, but not all elements, >without writing additional code to do so, in a single assignment >statement. As Jonathan points out, you can use a full assignment, re-using parts of the original record, to replace the partial assignment. It looks complex and confusing - as you say, by adding additional code - but it gets the job jone. A function can encapsulate that partial assignment via full assignment into a single - very clean - statement at the point of use, thus making your intention clear to the reader. What I don't understand is your objection to using a function because of the additional code necessary. The two frequent objections are that a larger program is more complex and harder to understand; and that adding code increases resource use and decreases performance. Using a function, the additional code is written once, and hidden in a package, so does not interfere with program clarity or understanding. If you have several patterns of selective update, the package contains several equally simple functions. They can share a name, overloaded by different parameter types; or have different names; whichever makes your intent clearer. The functions will not synthesise to extra hardware; they are just shorthand for their contents (inlined during synthesis, if you prefer). During simulation, you may actuallly be able to measure a small increase in simulation time but I'd be surprised if it was more than a couple of percent. So I don't believe your objection is either of these - perhaps you can clarify? - Brian From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: Sudoer Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sun, 8 Aug 2010 17:50:56 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <274c9729-74e0-4ca6-9cdb-7b29a8554b4a@y11g2000yqm.googlegroups.com> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> <3j5t56ttnmj6h9rrp9q1lkaas8joi7pk60@4ax.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281315056 8461 127.0.0.1 (9 Aug 2010 00:50:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Aug 2010 00:50:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.17.8 (KHTML, like Gecko) Version/5.0.1 Safari/533.17.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:3997 Jonathan Bromley pretty much nailed it, I was just looking for code clarity and conciseness, and in my case I do plan to use many variants in terms of which subelements I assign to. The code I started this topic while writing would need five different functions to do the partial assignments. Sometimes I forget that VHDL has a formal syntactic definition that causes even small changes like I suggested to have large consequences. That said, one way to do this would be to have "OTHERS => UNAFFECTED" (or UNCHANGED - I'm not sure of the policy of overloading keywords, or of introducing keywords that are very likely to be in existing code...) simply mean that each element "assigned" UNAFFECTED would be assigned it's current value. This does away with the "bit- flag" problem. As I'm a bit of a VHDL neophyte I was more hoping an expert would point out that I was missing an obvious way to do this more than I was hoping to propose a feature which would take years to ratify, further years to implement, and even innumerable years to make it into synthesis tools. From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sun, 08 Aug 2010 21:57:35 -0700 Lines: 23 Message-ID: <8c9g60FhfmU1@mid.individual.net> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> <3j5t56ttnmj6h9rrp9q1lkaas8joi7pk60@4ax.com> <274c9729-74e0-4ca6-9cdb-7b29a8554b4a@y11g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net SOY+9ysRw0SWSWzLavRZlAK8WnW9h4Yi+w9cYFQEJxITFBJTMH Cancel-Lock: sha1:BRZRnMiRQUFuEZRver1e5lWfIsA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100802 Lightning/1.0b2 Thunderbird/3.1.2 In-Reply-To: <274c9729-74e0-4ca6-9cdb-7b29a8554b4a@y11g2000yqm.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:3998 On 8/8/2010 5:50 PM, Sudoer wrote: > Jonathan Bromley pretty much nailed it, I was just looking for code > clarity and conciseness, and in my case I do plan to use many variants > in terms of which subelements I assign to. The code I started this > topic while writing would need five different functions to do the > partial assignments. I also prefer structures with descriptive element names -- if the dimensions are small enough that words don't confuse the issue. In this case, an array of records, where the array index is a type enumeration, often does the trick for me. > As I'm a bit of a VHDL neophyte I was more hoping an expert would > point out that I was missing an obvious way to do this more than I was > hoping to propose a feature which would take years to ratify, further > years to implement, and even innumerable years to make it into > synthesis tools. On the other hand, a question without an obvious answer is interesting. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!c10g2000yqi.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Mon, 9 Aug 2010 01:01:36 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <6e134c4d-b401-4e60-8363-2b5ba79c7d1f@c10g2000yqi.googlegroups.com> References: <7614777c-39ab-4417-9d3c-06020fc74069@m1g2000yqo.googlegroups.com> <3j5t56ttnmj6h9rrp9q1lkaas8joi7pk60@4ax.com> <274c9729-74e0-4ca6-9cdb-7b29a8554b4a@y11g2000yqm.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281340896 9111 127.0.0.1 (9 Aug 2010 08:01:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Aug 2010 08:01:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqi.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.2 (14893) 11j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:3999 On Aug 9, 1:50=A0am, Sudoer wrote: > one way to do this would be to have "OTHERS =3D> UNAFFECTED" > simply mean that each element "assigned" UNAFFECTED > would be assigned it's current value. This does away with the "bit- > flag" problem. As we all agree, this discussion is academic anyway, but.... It doesn't "do away with" any such problem. In a simple assignment TARGET:=3D(some aggregate), the notion of "its current value" makes some sense (although it would be a new idea in VHDL for a right-hand-side expression to obtain values from an assignment target). But I'm at a loss even to guess what UNAFFECTED might mean in any other context - for example, if you were passing the aggregate to a function as an input argument. There are other peripheral problems too. Should the UNAFFECTED assignment cause a transaction on the unaffected elements of a record signal? I do agree, though, that it is exceedingly tedious that you can't write a record aggregate with only a few of its elements specified, leaving the others with their default values. In fact, that would open the door to some neat approaches to solving your problem. But you can't do it, so I won't waste my time and yours by describing how it might be done! cheers Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: dgreig Newsgroups: comp.lang.vhdl Subject: Re: VHDL newbie- stuck just weeks before project submission :(..please help Date: Mon, 9 Aug 2010 01:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 109 Message-ID: <2716e9df-1684-4ec7-ab2c-12ca759c47dc@y11g2000yqm.googlegroups.com> References: <17d33efe-45a1-4d2f-a75d-71b88f8009e1@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 84.19.254.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281344151 1696 127.0.0.1 (9 Aug 2010 08:55:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 9 Aug 2010 08:55:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=84.19.254.82; posting-account=jWYCGAoAAACtdbpYfrlZ1GVzvYP1FIDc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.2; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4000 On Aug 7, 6:16=A0pm, Sheetal wrote: > Hello, > > For my Masters project, I'm trying to implement a multiplier, and a > MAC where the outputs are calculated per clock cycle and stored in a > text file which can then be used for further processing. > > However, both these designs are giving out partial products(I guess > they are partial products) at the output too, before they give the > final result..I've tried changing the codes, changing clock frequency > in testbench etc. but nothing seems to work... > > Is there any way to implement a output_ready signal for multipliers/ > adders?(I saw a few codes using shifter for rdy, but could not > understand the logic behind it) > > I'm using the embedded Mult18X18 in Spartan 3..but do not want to use > the Core generator for MAC(which has a RDY signal) as the code has to > be kept portable. > > Code for multiplier is-- > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Single_Mul is > =A0 =A0 Port ( Clk : in =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0Mul1 : in =A0STD_LOGIC_VECTOR (17 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0Mul2 : in =A0STD_LOGIC_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0Mul_Res : out =A0STD_LOGIC_VECTOR(35 downto 0)); > end Single_Mul; > > architecture Behavioral of Single_Mul is > Signal Prod : Signed( 35 downto > 0):=3D"000000000000000000000000000000000000"; > > begin > process(clk)is > begin > > if rising_edge(Clk) then > Prod<=3Dsigned(Mul1)*signed(Mul2); > end if; > end process; > > Prod_Process:Process(prod) > begin > > Mul_Res<=3DSTD_LOGIC_VECTOR(Prod);--here I was hoping this process is > --invoked only when the --clocked process above is complete... > > end process; > > end Behavioral; > > Code for MAC-- > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.numeric_STD.all; > > entity Mul_Adder is > =A0 =A0 Port ( MulA : in STD_LOGIC_VECTOR (17 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0MulB : in STD_LOGIC_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0Multi_Res : in STD_LOGIC_VECTOR(35 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0MulAdd_Res : out STD_LOGIC_VECTOR(35 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0Clk : in =A0STD_LOGIC); > end Mul_Adder; > > architecture Behavioral of Mul_Adder is > shared variable temp :SIGNED(35 downto > 0);--:=3D"000000000000000000000000000000000000"; > Signal temp1:SIGNED(35 downto > 0):=3D"000000000000000000000000000000000000"; > > begin > Process(Clk) is > BEGIN > > If rising_edge(Clk) > then > temp:=3Dsigned(MulA)*signed(MulB); > temp1<=3Dsigned(Multi_Res)+temp; > end if; > > End Process; > > MulAdd_Res_process: Process(temp1) > begin > MulAdd_Res<=3DSTD_LOGIC_VECTOR(temp1); > end Process; > > end Behavioral; > > Am I doing anything wrong here? Any help in this direction would be > useful use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; Use either the IEEE NUMERIC_STD numeric_std OR the Synopsis STD_LOGIC_UNSIGNED/STD_LOGIC_SIGNED, not both! Your code is compatable with NUMERIC_STD, so stay with a good thing an avoid the other libraries. Regards DG From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Is there a way to define different names to same signal in VHDL? Date: Tue, 10 Aug 2010 00:50:07 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281426607 4197 127.0.0.1 (10 Aug 2010 07:50:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 07:50:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4001 I'm looking for a method to use substitute names to same signal VHDL so the synthesis tool would use the same flops for all of them.... is there a way to do it right? Thanx From newsfish@newsfish Fri Dec 24 22:54:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!m1g2000yqo.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Tue, 10 Aug 2010 03:49:51 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281437391 27716 127.0.0.1 (10 Aug 2010 10:49:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 10:49:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000yqo.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4002 On 10 Aug, 08:50, Eli wrote: > I'm looking for a method to use substitute names to same signal VHDL > so the synthesis tool would use the same flops for all of them.... is > there a way to do it right? > > Thanx it should already do this, for example: signal reg : std_logic; signal a,b,c : std_logic; process(clk) begin if rising_edge(clk) then reg <= input; end if; end process; a <= reg; b <= reg; c <= reg; a, b and c are all just a registered version of the input. similarly, if you do this: process(clk) begin if rising_edge(clk) then reg1 <= input; reg2 <= input; end if; end process; a <= reg1; b <= reg2; c <= a; when it is synthesised, it will probably compress reg1 and reg2 into the same register (unless you specifically tell it not to). otherwise you can alias signals to avoid the delta delays (in simulation) from the above methods: signal reg1 : std_logic; alias a : std_logic is reg1; IS this what you wanted? From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f6g2000yqa.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Tue, 10 Aug 2010 05:11:33 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281442294 1955 127.0.0.1 (10 Aug 2010 12:11:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 12:11:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f6g2000yqa.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4003 On Aug 10, 1:49=A0pm, Tricky wrote: > On 10 Aug, 08:50, Eli wrote: > > > I'm looking for a method to use substitute names to same signal VHDL > > so the synthesis tool would use the same flops for all of them.... is > > there a way to do it right? > > > Thanx > > it should already do this, for example: > > signal reg : std_logic; > signal a,b,c : std_logic; > > process(clk) > begin > =A0 if rising_edge(clk) then > =A0 =A0 reg <=3D input; > =A0 end if; > end process; > > a <=3D reg; > b <=3D reg; > c <=3D reg; > > a, b and c are all just a registered version of the input. > > similarly, if you do this: > > process(clk) > begin > =A0 if rising_edge(clk) then > =A0 =A0 reg1 <=3D input; > =A0 =A0 reg2 <=3D input; > =A0 end if; > end process; > > a <=3D reg1; > b <=3D reg2; > c <=3D a; > > when it is synthesised, it will probably compress reg1 and reg2 into > the same register (unless you specifically tell it not to). > > otherwise you can alias signals to avoid the delta delays (in > simulation) from the above methods: > > signal reg1 : std_logic; > alias a : std_logic is reg1; > > IS this what you wanted? Thanx, but i'm looking for real substitute, like in C language. I'll write iot in pseudo-code: if i have signal defined: signal generic_register : integer range 0 to 1023l; and some statements like: up_counter IS SUBSTITUTE OF generic_register; down_counter IS SUBSTITUTE OF generic_register; so i can use statements like up_counter <=3D down_counter+1; and get the result as i wrote generic_register <=3D generic_register+1; i'm looking for a nice and readable way to use the same generic signal or variable which gets completely different meaning From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!news.mind.de!news.cs.uni-magdeburg.de!not-for-mail From: Paul Newsgroups: comp.lang.vhdl Subject: type computation Date: Tue, 10 Aug 2010 14:26:48 +0200 Organization: University of Magdeburg, Germany Lines: 53 Message-ID: NNTP-Posting-Host: imat46.mb.uni-magdeburg.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: fuerst.cs.uni-magdeburg.de 1281443208 8945 141.44.146.46 (10 Aug 2010 12:26:48 GMT) X-Complaints-To: abuse@cs.uni-magdeburg.de NNTP-Posting-Date: Tue, 10 Aug 2010 12:26:48 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de-DE; rv:1.9.2.8) Gecko/20100802 Lightning/1.0b2 Thunderbird/3.1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:4004 Hi, I'm porting a fixed point simulink (SL) model to vhdl. The SL type is fixdt(..., WORDLENGTH, FRACLENGTH) where sfixed does have a different notation. For convience I wrote a VHDL function to convert the type in a package: package body ... function fixdt_to_sfixed( constant WordLength : integer; constant FractionLength : integer) return UNRESOLVED_sfixed is constant left : integer := WordLength - FractionLength - 1; constant right : integer := -FractionLength; variable result : UNRESOLVED_sfixed(left downto right); begin return result; end; end ... to avoid type computations ans signal like: architecture .... constant COEFFICIENT_LEFT : integer := COEFFICIENT_WORDLENGTH - COEFFICIENT_FRACTIONLENGTH - 1; constant COEFFICIENT_RIGHT : integer := -COEFFICIENT_FRACTIONLENGTH; subtype coeefficient_type is sfixed(COEFFICIENT_LEFT downto COEFFICIENT_RIGHT); constant COEEFFICIENT_SIZER : coeefficient_type := (others => '0'); signal b0_coeff_s : coeefficient_type; begin b0_coeff_s <= to_sfixed( input_b0, COEEFFICIENT_SIZER); But this approach won't work: architecture behave OF df1tsos_tester is signal coeff_a0 : fixdt_to_sfixed(COEFFICIENT_WORDLENGTH, COEFFICIENT_FRACTIONLENGTH); is there such a way? How to? Thanks, Olaf From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z28g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Tue, 10 Aug 2010 05:50:56 -0700 (PDT) Organization: http://groups.google.com Lines: 81 Message-ID: References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281444656 20420 127.0.0.1 (10 Aug 2010 12:50:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 12:50:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z28g2000yqh.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4005 On Aug 10, 8:11=A0am, Eli wrote: > On Aug 10, 1:49=A0pm, Tricky wrote: > > > > > > > On 10 Aug, 08:50, Eli wrote: > > > > I'm looking for a method to use substitute names to same signal VHDL > > > so the synthesis tool would use the same flops for all of them.... is > > > there a way to do it right? > > > > Thanx > > > it should already do this, for example: > > > signal reg : std_logic; > > signal a,b,c : std_logic; > > > process(clk) > > begin > > =A0 if rising_edge(clk) then > > =A0 =A0 reg <=3D input; > > =A0 end if; > > end process; > > > a <=3D reg; > > b <=3D reg; > > c <=3D reg; > > > a, b and c are all just a registered version of the input. > > > similarly, if you do this: > > > process(clk) > > begin > > =A0 if rising_edge(clk) then > > =A0 =A0 reg1 <=3D input; > > =A0 =A0 reg2 <=3D input; > > =A0 end if; > > end process; > > > a <=3D reg1; > > b <=3D reg2; > > c <=3D a; > > > when it is synthesised, it will probably compress reg1 and reg2 into > > the same register (unless you specifically tell it not to). > > > otherwise you can alias signals to avoid the delta delays (in > > simulation) from the above methods: > > > signal reg1 : std_logic; > > alias a : std_logic is reg1; > > > IS this what you wanted? > > Thanx, but i'm looking for real substitute, like in C language. > I'll write iot in pseudo-code: > > if i have signal defined: > signal generic_register : integer range 0 to 1023l; > > and some statements like: > up_counter IS SUBSTITUTE OF generic_register; > down_counter IS SUBSTITUTE OF generic_register; > > so i can use statements like > > up_counter <=3D down_counter+1; > and get the result as i wrote generic_register <=3D generic_register+1; > > i'm looking for a nice and readable way to use the same generic signal > or variable which gets completely different meaning- Hide quoted text - > Look into the 'alias' statement. It does exactly what you're describing. KJ From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c10g2000yqi.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: type computation Date: Tue, 10 Aug 2010 05:55:06 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: <64a9708d-2a50-4d4b-9313-127d8dd86138@c10g2000yqi.googlegroups.com> References: NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281444906 3951 127.0.0.1 (10 Aug 2010 12:55:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 12:55:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqi.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4006 On Aug 10, 8:26=A0am, Paul wrote: > Hi, > > I'm porting a fixed point simulink (SL) model to vhdl. The SL type is > fixdt(..., WORDLENGTH, FRACLENGTH) where sfixed does have a different > notation. > > For convience I wrote a VHDL function to convert the type in a package: > > package body ... > > function fixdt_to_sfixed( > =A0 =A0 constant WordLength =A0 =A0 : integer; > =A0 =A0 constant FractionLength : integer) > =A0 return UNRESOLVED_sfixed > =A0 is > =A0 =A0 constant left : integer :=3D WordLength - FractionLength - 1; > =A0 =A0 constant right : integer :=3D -FractionLength; > =A0 =A0 variable result : UNRESOLVED_sfixed(left downto right); > =A0 begin > =A0 =A0 return result; > =A0 end; > > end ... > > to avoid type computations ans signal like: > > architecture .... > =A0 constant COEFFICIENT_LEFT =A0 =A0 : integer :=3D =A0COEFFICIENT_WORDL= ENGTH - > COEFFICIENT_FRACTIONLENGTH - 1; > =A0 constant COEFFICIENT_RIGHT =A0 =A0: integer :=3D -COEFFICIENT_FRACTIO= NLENGTH; > =A0 subtype coeefficient_type =A0 =A0 is sfixed(COEFFICIENT_LEFT downto > COEFFICIENT_RIGHT); > > =A0 constant COEEFFICIENT_SIZER =A0 : coeefficient_type =A0 =A0 :=3D (oth= ers =3D> '0'); > > =A0 signal b0_coeff_s =A0 =A0 =A0 =A0 =A0 =A0 : coeefficient_type; > > begin > =A0 b0_coeff_s =A0 =A0<=3D to_sfixed( input_b0, COEEFFICIENT_SIZER); > > But this approach won't work: > > architecture behave OF df1tsos_tester is > > =A0 signal coeff_a0 : fixdt_to_sfixed(COEFFICIENT_WORDLENGTH, > COEFFICIENT_FRACTIONLENGTH); > > is there such a way? How to? > > Thanks, > Olaf You need functions to compute the sfixed array bounds. What you've shown is declaring a signal that is of a type computed by a function...which is illegal. Once you get your two functions, the signal declarations will be something like this... signal coeff_a0 : sfixed(fixdt_to_sfixed_left(COEFFICIENT_WORDLENGTH, COEFFICIENT_FRACTIONLENGTH) downto fixdt_to_sfixed_right(COEFFICIENT_WORDLENGTH, COEFFICIENT_FRACTIONLENGTH)); KJ From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x21g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: type computation Date: Tue, 10 Aug 2010 07:01:35 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: <1d3c5bad-103b-4ff1-a93d-187c80a43ec0@x21g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281448895 5658 127.0.0.1 (10 Aug 2010 14:01:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 14:01:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x21g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4007 On 10 Aug, 13:26, Paul wrote: > Hi, > > I'm porting a fixed point simulink (SL) model to vhdl. The SL type is > fixdt(..., WORDLENGTH, FRACLENGTH) where sfixed does have a different > notation. > > For convience I wrote a VHDL function to convert the type in a package: > > package body ... > > function fixdt_to_sfixed( > =A0 =A0 constant WordLength =A0 =A0 : integer; > =A0 =A0 constant FractionLength : integer) > =A0 return UNRESOLVED_sfixed > =A0 is > =A0 =A0 constant left : integer :=3D WordLength - FractionLength - 1; > =A0 =A0 constant right : integer :=3D -FractionLength; > =A0 =A0 variable result : UNRESOLVED_sfixed(left downto right); > =A0 begin > =A0 =A0 return result; > =A0 end; > > end ... > > to avoid type computations ans signal like: > > architecture .... > =A0 constant COEFFICIENT_LEFT =A0 =A0 : integer :=3D =A0COEFFICIENT_WORDL= ENGTH - > COEFFICIENT_FRACTIONLENGTH - 1; > =A0 constant COEFFICIENT_RIGHT =A0 =A0: integer :=3D -COEFFICIENT_FRACTIO= NLENGTH; > =A0 subtype coeefficient_type =A0 =A0 is sfixed(COEFFICIENT_LEFT downto > COEFFICIENT_RIGHT); > > =A0 constant COEEFFICIENT_SIZER =A0 : coeefficient_type =A0 =A0 :=3D (oth= ers =3D> '0'); > > =A0 signal b0_coeff_s =A0 =A0 =A0 =A0 =A0 =A0 : coeefficient_type; > > begin > =A0 b0_coeff_s =A0 =A0<=3D to_sfixed( input_b0, COEEFFICIENT_SIZER); > > But this approach won't work: > > architecture behave OF df1tsos_tester is > > =A0 signal coeff_a0 : fixdt_to_sfixed(COEFFICIENT_WORDLENGTH, > COEFFICIENT_FRACTIONLENGTH); > > is there such a way? How to? > > Thanks, > Olaf I am currently in the process of getting simulink algorithms working in VHDL, and doing a lot of co-simulation. I think the approach you have may be the wrong way round. When we started, we looked at the limitations the FPGA was going to impose on the algorithm, rather than letting simulink run the show completly. Things like multiplier widths (normally 18 bits) and available memory at given points. This all fed back and put fixed limits on the word widths at the start (after some testing was done on the algorithm to ensure it didnt degrade performance). So I have a "setup package" that defines all of the word widths throughout the algorithm via sub types. I have the following: subtype filter_word_t is sfixed(11 downto -4); --16 bits because the memories are 18 bits and we need to store a couple of status bits with each word subtype coeff_t is sfixed(1 downto -16); --18 bit multiplers. then you can start doing all the stuff VHDL is good for: type coeff_array_t is array(-1 to 1, -1 to 1) of coeff_t; type filter_array_t is array(natural range <>) of coeff_array_t; -- Will co-simulation support 3+D arrays any time soon? The good thing about this is, if we really need to change the widths, all I need to do is change the setup package manually and the whole thing still works - make sure you use the 'length/'high/'low attributes all over the place. Whether it will still fit, and whether the algorithm guys will understand this is another question! From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder.news-service.com!postnews.google.com!f6g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL newbie- stuck just weeks before project submission :(..please help Date: Tue, 10 Aug 2010 11:59:09 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <17d33efe-45a1-4d2f-a75d-71b88f8009e1@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281466750 25188 127.0.0.1 (10 Aug 2010 18:59:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 10 Aug 2010 18:59:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f6g2000yqa.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4008 How is this different from: architecture Behavioral of Mul_Adder is -- no shared variables or signals needed begin Process(Clk) is -- local (not shared) variable declaration for -- combinatorial results from multiplier variable temp :SIGNED(multi_res'range) := (others => '0'); BEGIN If rising_edge(Clk) then temp := signed(MulA) * signed(MulB); MulAdd_Res <= STD_LOGIC_VECTOR(signed(Multi_Res) + temp; end if; End Process; end Behavioral; If this is giving you intermediate results on some clock cycles, it is only because your inputs are intermediate values on some clock cycles. In other words, the problem is not in this code, but in the code that instantiates this entity/architecture. Andy From newsfish@newsfish Fri Dec 24 22:54:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i13g2000yqd.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Wed, 11 Aug 2010 00:14:09 -0700 (PDT) Organization: http://groups.google.com Lines: 97 Message-ID: <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281510849 24968 127.0.0.1 (11 Aug 2010 07:14:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Aug 2010 07:14:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i13g2000yqd.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4009 On Aug 10, 3:50=A0pm, KJ wrote: > On Aug 10, 8:11=A0am, Eli wrote: > > > > > On Aug 10, 1:49=A0pm, Tricky wrote: > > > > On 10 Aug, 08:50, Eli wrote: > > > > > I'm looking for a method to use substitute names to same signal VHD= L > > > > so the synthesis tool would use the same flops for all of them.... = is > > > > there a way to do it right? > > > > > Thanx > > > > it should already do this, for example: > > > > signal reg : std_logic; > > > signal a,b,c : std_logic; > > > > process(clk) > > > begin > > > =A0 if rising_edge(clk) then > > > =A0 =A0 reg <=3D input; > > > =A0 end if; > > > end process; > > > > a <=3D reg; > > > b <=3D reg; > > > c <=3D reg; > > > > a, b and c are all just a registered version of the input. > > > > similarly, if you do this: > > > > process(clk) > > > begin > > > =A0 if rising_edge(clk) then > > > =A0 =A0 reg1 <=3D input; > > > =A0 =A0 reg2 <=3D input; > > > =A0 end if; > > > end process; > > > > a <=3D reg1; > > > b <=3D reg2; > > > c <=3D a; > > > > when it is synthesised, it will probably compress reg1 and reg2 into > > > the same register (unless you specifically tell it not to). > > > > otherwise you can alias signals to avoid the delta delays (in > > > simulation) from the above methods: > > > > signal reg1 : std_logic; > > > alias a : std_logic is reg1; > > > > IS this what you wanted? > > > Thanx, but i'm looking for real substitute, like in C language. > > I'll write iot in pseudo-code: > > > if i have signal defined: > > signal generic_register : integer range 0 to 1023l; > > > and some statements like: > > up_counter IS SUBSTITUTE OF generic_register; > > down_counter IS SUBSTITUTE OF generic_register; > > > so i can use statements like > > > up_counter <=3D down_counter+1; > > and get the result as i wrote generic_register <=3D generic_register+1; > > > i'm looking for a nice and readable way to use the same generic signal > > or variable which gets completely different meaning- Hide quoted text - > > Look into the 'alias' statement. =A0It does exactly what you're > describing. > > KJ looks like this is the solution, thanx. Are the following statements valid and supported by various synthesis tools for FPGA? signal misc_register : integer range 0 to 511; -- general alias pid_tick_count_value_ALIAS: integer range 0 to 511 IS misc_register integer range 0 to 511; alias scan_channel_params_ALIAS: integer range 0 to 31 IS misc_register integer range 0 to 31; alias i_buff_remain_values_ALIAS: integer range 0 to 127 IS misc_register integer range 0 to 127; alias d_buff_remain_values_ALIAS: integer range 0 to 127 IS misc_register integer range 0 to 63; From newsfish@newsfish Fri Dec 24 22:54:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!news.buerger.net!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 Aug 2010 21:38:22 -0500 Date: Thu, 12 Aug 2010 12:39:23 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> In-Reply-To: <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> Lines: 22 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-2n37F1H9Wuf4Ylql22H9Mlv4df/Ns0DSpV8dC83aWRcru6Uj7c2/kPxh36tFTSJcNRjPQX+5Uc4um3P!IPD8YkU5LfVvCvF27lRZ4syiMBI6f/finOwLZ3L+KyrPT8iVj2tBpbNU5vZiJnpvojT7fRCflyd2!Zz8wXfjA2qfspDa4UjML X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2213 Xref: feeder.eternal-september.org comp.lang.vhdl:4011 Eli wrote: > Are the following statements valid and supported by various synthesis > tools for FPGA? > > signal misc_register : integer range 0 to 511; -- general > alias pid_tick_count_value_ALIAS: integer range 0 to 511 IS > misc_register integer range 0 to 511; Nope, at least not in Quartus. subtype int512_t is integer range 0 to 511; signal misc_register : int512_t; alias pid_tick_count_value_ALIAS : int512_t is misc_register; Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 Aug 2010 21:50:33 -0500 Date: Thu, 12 Aug 2010 12:51:34 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: in the absence of a pre-processor... Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 30 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-P7yuBfwVYDgiq8avj7ii0QiqrECll0URW8pU+/bUEBpkNXWcTpm/keE0QJAJQ5mf0D+kH0r2i+q576A!wCDOzeC8HVVOsT/HlJ04oOK1YI/DwyneQJmK0ABSgL1z+4Fl4GMhn/WZv1rthI01dHKcdTqq1NXf!tyF+O64Qy02U4filuxr+ X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4012 Hi gurus, I have a bunch of constants that can change from build to build, depending on what I'm targeting. Right now I'm simply commenting/out a whole set of lines each time. eg: --constant A : std_logic_vector(3 downto 0) := X"0"; --constant B : std_logic_vector(3 downto 0) := X"1"; --constant C : std_logic_vector(3 downto 0) := X"2"; --constant D : std_logic_vector(3 downto 0) := X"3"; constant A : std_logic_vector(3 downto 0) := X"3"; constant B : std_logic_vector(3 downto 0) := X"4"; constant C : std_logic_vector(3 downto 0) := X"5"; constant D : std_logic_vector(3 downto 0) := X"6"; Short of diving into configurations etc, does anyone have a handy trick they use in these sorts of situations? The idea is to be able to change/comment only 1/2 lines to achieve the above... I can think of some rather horrible & convoluted ways that might work with, say, std_logic_vector using and/or, but it's not pretty... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Wed, 11 Aug 2010 21:45:41 -0700 Lines: 28 Message-ID: <8chcjgFmd4U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net unjoehanuZPgap1/egWj1A2ljlyouiZ0ImQkeOBYcVuRlEnkh5 Cancel-Lock: sha1:oftYHpT/FD46oJWcd1BfKTz2HuA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100802 Lightning/1.0b2 Thunderbird/3.1.2 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4013 On 8/11/2010 7:51 PM, Mark McDougall wrote: > I have a bunch of constants that can change from build to build, depending > on what I'm targeting. Right now I'm simply commenting/out a whole set of > lines each time. eg: > > --constant A : std_logic_vector(3 downto 0) := X"0"; > --constant B : std_logic_vector(3 downto 0) := X"1"; > --constant C : std_logic_vector(3 downto 0) := X"2"; > --constant D : std_logic_vector(3 downto 0) := X"3"; > > constant A : std_logic_vector(3 downto 0) := X"3"; > constant B : std_logic_vector(3 downto 0) := X"4"; > constant C : std_logic_vector(3 downto 0) := X"5"; > constant D : std_logic_vector(3 downto 0) := X"6"; > > Short of diving into configurations etc, does anyone have a handy trick > they use in these sorts of situations? The idea is to be able to > change/comment only 1/2 lines to achieve the above... I would declare an array: bunch_o_constants_t That might give me only one line to comment. If the values are computable from a parameter, as in the example, I might use a function on the right side. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:54:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Wed, 11 Aug 2010 22:18:28 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281590316 19979 127.0.0.1 (12 Aug 2010 05:18:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 05:18:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4014 On Aug 11, 10:51=A0pm, Mark McDougall wrote: > Hi gurus, > > I have a bunch of constants that can change from build to build, dependin= g > on what I'm targeting. Right now I'm simply commenting/out a whole set of > lines each time. eg: > > --constant A : std_logic_vector(3 downto 0) :=3D X"0"; > --constant B : std_logic_vector(3 downto 0) :=3D X"1"; > --constant C : std_logic_vector(3 downto 0) :=3D X"2"; > --constant D : std_logic_vector(3 downto 0) :=3D X"3"; > > constant A : std_logic_vector(3 downto 0) :=3D X"3"; > constant B : std_logic_vector(3 downto 0) :=3D X"4"; > constant C : std_logic_vector(3 downto 0) :=3D X"5"; > constant D : std_logic_vector(3 downto 0) :=3D X"6"; > > Short of diving into configurations etc, does anyone have a handy trick > they use in these sorts of situations? The idea is to be able to > change/comment only 1/2 lines to achieve the above... > > I can think of some rather horrible & convoluted ways that might work > with, say, std_logic_vector using and/or, but it's not pretty... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Define a type which contains the set of things that you'll be selecting from (i.e. A, B, C, D each of type std_logic_vector) type t_abcd is record a: std_logic_vector(3 downto 0); b: std_logic_vector(3 downto 0); ... end record; Next define a type that is an array of that type type arr_t_abcd is array (natural range<>) of t_abcd; And now a constant array of the universe of those choices... constant All_abcds: arr_t_abcd :=3D (x"0", x"1"..., x"3"), (x"3", x"4"..., x"6"); Now have either a generic input to the entity or a constant in the architecture to select which set you want to use for a particular build and define the A, B, C, D constants like this... constant A: std_logic_vector(3 downto 0) :=3D All_abcds(Sel).A; constant B: std_logic_vector(3 downto 0) :=3D All_abcds(Sel).B; ... None of your code that right now refers to A, B, C, D needs to change since you still eventually end up with those constants defined. The top level generic can be selected at build time, or simply defined as a constant in the architecture. Either way you only change one thing, either the top level generic or the selection constant in the code. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:54:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k10g2000yqa.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Wed, 11 Aug 2010 23:47:11 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <92a72b68-54c4-4d24-ada5-26b79b0808c6@k10g2000yqa.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281595632 31684 127.0.0.1 (12 Aug 2010 06:47:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 06:47:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000yqa.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4015 On Aug 12, 5:39=A0am, Mark McDougall wrote: > Eli wrote: > > Are the following statements valid and supported by various synthesis > > tools for FPGA? > > > signal misc_register : integer range 0 to 511; -- general > > alias pid_tick_count_value_ALIAS: integer range 0 to 511 IS > > misc_register integer range 0 to 511; > > Nope, at least not in Quartus. > > subtype int512_t is integer range 0 to 511; > signal misc_register : int512_t; > alias pid_tick_count_value_ALIAS : int512_t is misc_register; > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 so if they integer type they must be the same range exactly? what about std_logic_vector type? may they be partial set of bits like this? misc_register : std_logic_vector (15 downto 0); alias pid_tick_count_value_ALIAS : std_logic_vector (4 downto 0) misc_register (15 downto 12); From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Thu, 12 Aug 2010 09:49:37 +0100 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> <92a72b68-54c4-4d24-ada5-26b79b0808c6@k10g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Aug 2010 08:49:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="16676"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/2jbV1fgZedFLCE2K3JyoXmuWkDQ1mS0I=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:NTGrhnBHv36LOHj3NwtO9uwceSI= Xref: feeder.eternal-september.org comp.lang.vhdl:4016 On Wed, 11 Aug 2010 23:47:11 -0700 (PDT), Eli wrote: >so if they integer type they must be the same range exactly? An alias is exactly that: a different name for the same thing. So it is no great surprise that the subtype of alias and thing must be the same. >what about std_logic_vector type? may they be partial set of bits like >this? Yes, provided you get the length right. In this case the alias can have a subtype that is different from the thing's, but the lengths must match so that the alias and the thing can participate in exactly the same operations. So your example is flawed: >misc_register : std_logic_vector (15 downto 0); >alias pid_tick_count_value_ALIAS : > std_logic_vector (4 downto 0) -- that's 5 elements > is misc_register (15 downto 12); -- oops, only 4 -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 11:14:18 +0100 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Aug 2010 10:14:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="30252"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+go1oULdIyGj6/p65FrFdElIvnn7/5bpE=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:Unzms17JhFXPU0Oh57MdooqioEc= Xref: feeder.eternal-september.org comp.lang.vhdl:4017 On Thu, 12 Aug 2010 12:51:34 +1000, Mark McDougall wrote: >I have a bunch of constants that can change from build to build Great advice from Mike and KJ. A couple of other thoughts: - Kevin's "universe of possible sets of values" could possibly be a moving target as you port the design to a big variety of platforms. Using a function to construct the record, and passing some interesting selector values to that function, may be a cleaner approach if you can compute your constants based on the value of a few vital statistics of the platform. - If the set of constants truly is a horrible platform-specific mishmash of values, it may be cleaner *not* to maintain one big collection of them, but rather to create a collection of package files each of which defines the same-named package, which contains all your constants. Each file is then the description of a single platform, and by compiling the correct file you get the correct values in your platform descriptor package. Now you can adjust the platform-specific build simply by writing a new package file, and tweaking your build script to use that file. - Oftentimes it is quite sucky to be forced to use std_logic_vector values for these constants. Don't be ashamed of using integer constants in the package, and then constructing s-l-v constants from them using a function in the architecture. I've often done this when describing, for example, the layout of a bunch of registers in an address space - it's far easier to describe the addresses using integers, and then fabricate appropriate vector values from those integers for use in the decoder or whatever logic. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 05:29:26 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 11:36:49 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <8chcjgFmd4U1@mid.individual.net> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-pyaA/OrljVbwfVcjBMLar2aH334HLTkNg8spOhj2Pdar6GI7MAfdTMe8qwJv+ANTHmxafjDrjyjRw8k!llsGUrfLl4pd8P/4NePiDStk18ZKDCmzot+MQfMfQZ+ogzSkhwHCSpNXA/CcJPWYrZOXg4xIiDax!E3o= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4018 On Wed, 11 Aug 2010 21:45:41 -0700, Mike Treseler wrote: >On 8/11/2010 7:51 PM, Mark McDougall wrote: > >> I have a bunch of constants that can change from build to build, depending >> on what I'm targeting. Right now I'm simply commenting/out a whole set of >> lines each time. eg: >> >> --constant A : std_logic_vector(3 downto 0) := X"0"; >> --constant B : std_logic_vector(3 downto 0) := X"1"; >> constant A : std_logic_vector(3 downto 0) := X"3"; >> constant B : std_logic_vector(3 downto 0) := X"4"; >I would declare an array: bunch_o_constants_t >That might give me only one line to comment. I've used this for an array of constants defining LUT widths and internal word widths. The index came from an integer subrange denoting the precision I wanted to achieve. >If the values are computable from a parameter, >as in the example, I might use a function on the right side. The same index controlled functions to truncate the LUT entries to the correct size to initialise the LUTs themselves. One design created a family of function generators with tunable precision and resource usage. I should have made it a generic, but in this instance I didn't bother. - Brian From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!u26g2000yqu.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Thu, 12 Aug 2010 08:45:05 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <9787580a-afcd-4a5b-a05e-7be6edbfa3e9@u26g2000yqu.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> <92a72b68-54c4-4d24-ada5-26b79b0808c6@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281627905 11033 127.0.0.1 (12 Aug 2010 15:45:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 15:45:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000yqu.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4019 On Aug 12, 11:49=A0am, Jonathan Bromley wrote: > On Wed, 11 Aug 2010 23:47:11 -0700 (PDT), Eli wrote: > >so if they integer type they must be the same range exactly? > > An alias is exactly that: a different name for the same thing. > So it is no great surprise that the subtype of alias and thing > must be the same. > > >what about std_logic_vector type? may they be partial set of bits like > >this? > > Yes, provided you get the length right. =A0In this case the > alias can have a subtype that is different from the thing's, > but the lengths must match so that the alias and the thing > can participate in exactly the same operations. =A0So your > example is flawed: > > >misc_register : std_logic_vector (15 downto 0); > >alias pid_tick_count_value_ALIAS : > > =A0 std_logic_vector (4 downto 0) =A0 -- that's 5 elements > > is misc_register (15 downto 12); =A0 -- oops, only 4 > > -- > Jonathan Bromley OK, OK, it was just my mistake. It should be this way: std_logic_vector (4 downto 0) is misc_register (15 downto 11); From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!p7g2000yqa.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Thu, 12 Aug 2010 08:45:19 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <72141b9e-f5ed-44d8-8fd0-463bf979ae9c@p7g2000yqa.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> <92a72b68-54c4-4d24-ada5-26b79b0808c6@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281627920 10062 127.0.0.1 (12 Aug 2010 15:45:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 15:45:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p7g2000yqa.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4020 On Aug 12, 11:49=A0am, Jonathan Bromley wrote: > On Wed, 11 Aug 2010 23:47:11 -0700 (PDT), Eli wrote: > >so if they integer type they must be the same range exactly? > > An alias is exactly that: a different name for the same thing. > So it is no great surprise that the subtype of alias and thing > must be the same. > > >what about std_logic_vector type? may they be partial set of bits like > >this? > > Yes, provided you get the length right. =A0In this case the > alias can have a subtype that is different from the thing's, > but the lengths must match so that the alias and the thing > can participate in exactly the same operations. =A0So your > example is flawed: > > >misc_register : std_logic_vector (15 downto 0); > >alias pid_tick_count_value_ALIAS : > > =A0 std_logic_vector (4 downto 0) =A0 -- that's 5 elements > > is misc_register (15 downto 12); =A0 -- oops, only 4 > > -- > Jonathan Bromley OK, OK, it was just my mistake. It should be this way: std_logic_vector (4 downto 0) is misc_register (15 downto 11); From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!c10g2000yqi.googlegroups.com!not-for-mail From: Eli Newsgroups: comp.lang.vhdl Subject: Re: Is there a way to define different names to same signal in VHDL? Date: Thu, 12 Aug 2010 08:47:39 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <57f66165-27d0-4d25-a7b4-6e514a9adbb1@c10g2000yqi.googlegroups.com> References: <6c489369-723f-42b3-973a-0be4c40341b0@y11g2000yqm.googlegroups.com> <11dabc9c-a424-48fd-b49b-f41184ab49b0@f6g2000yqa.googlegroups.com> <3e091042-3a4f-446d-9044-e5b0eba5f0a3@i13g2000yqd.googlegroups.com> <4vCdna37PpoCw_7RnZ2dnUVZ_uadnZ2d@westnet.com.au> <92a72b68-54c4-4d24-ada5-26b79b0808c6@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.159.243.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281628059 12124 127.0.0.1 (12 Aug 2010 15:47:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 15:47:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqi.googlegroups.com; posting-host=94.159.243.222; posting-account=lpjKpgoAAAAVoaV_0XCqQUiHyNGX-ZLE User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 GTB7.1 ( .NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4021 On Aug 12, 11:49=A0am, Jonathan Bromley wrote: > On Wed, 11 Aug 2010 23:47:11 -0700 (PDT), Eli wrote: > >so if they integer type they must be the same range exactly? > > An alias is exactly that: a different name for the same thing. > So it is no great surprise that the subtype of alias and thing > must be the same. > > >what about std_logic_vector type? may they be partial set of bits like > >this? > > Yes, provided you get the length right. =A0In this case the > alias can have a subtype that is different from the thing's, > but the lengths must match so that the alias and the thing > can participate in exactly the same operations. =A0So your > example is flawed: > > >misc_register : std_logic_vector (15 downto 0); > >alias pid_tick_count_value_ALIAS : > > =A0 std_logic_vector (4 downto 0) =A0 -- that's 5 elements > > is misc_register (15 downto 12); =A0 -- oops, only 4 > > -- > Jonathan Bromley my mistake. it should be: alias pid_tick_count_value_ALIAS : std_logic_vector (4 downto 0) is misc_register (15 downto 11); From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!transit3.readnews.com!transit4.readnews.com!news-out.readnews.com!postnews3.readnews.com!not-for-mail Date: Thu, 12 Aug 2010 12:06:48 -0400 From: Jeff Cunningham User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.4; en-US; rv:1.9.1.11) Gecko/20100711 Thunderbird/3.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 79 Message-ID: <4c641c08$0$2370$4d3efbfe@news.sover.net> Organization: SoVerNet (sover.net) NNTP-Posting-Host: a10b52d8.news.sover.net X-Trace: DXC=96\:LI54kIG]dI?8hh>1UOK6_LM2JZB_CEC65gDJ6W[JCbR`gJ`=gUCOHT37@C1P`B1\i_6Lcco?H X-Complaints-To: abuse@sover.net Xref: feeder.eternal-september.org comp.lang.vhdl:4022 On 8/12/10 6:14 AM, Jonathan Bromley wrote: > - If the set of constants truly is a horrible > platform-specific mishmash of values, it may be > cleaner *not* to maintain one big collection of > them, but rather to create a collection of package > files each of which defines the same-named package, > which contains all your constants. Each file > is then the description of a single platform, > and by compiling the correct file you get the > correct values in your platform descriptor package. > Now you can adjust the platform-specific build > simply by writing a new package file, and > tweaking your build script to use that file. I've done a similar thing but using a single package file with deferred constant types. This works great with modelsim and synplicity but not XST. Funny thing is, it used to work with XST then back around version 7 or 8 of the tools it suddenly broke. When I opened a webcase on it I was told it was my fault for using "illegal syntax". -Jeff library ieee; use ieee.std_logic_1164.all; package datapathSetup is -- enumerate the different datapath configurations. type t_datapath_configuration is ( toolkit, gen3 ); -- select a datapath configuration: constant datapath_configuration: t_datapath_configuration := toolkit; -- constants I want to be a function of datapath configuration constant WORDS_PER_SORT: integer; constant SORTS_PER_RASTER: integer; constant BURSTS_PER_MODULE: integer; end datapathSetup; package body datapathSetup is function get_words_per_sort (mode: t_datapath_configuration) return integer is begin case mode is when toolkit=> return 16; when gen3=> return 19; end case; end get_words_per_sort; constant WORDS_PER_SORT: integer := get_words_per_sort(datapath_configuration); function get_sorts_per_raster (mode: t_datapath_configuration) return integer is begin case mode is when toolkit=> return 1; when gen3=> return 1; end case; end get_sorts_per_raster; constant SORTS_PER_RASTER: integer := get_sorts_per_raster(datapath_configuration); function get_bursts_per_module (mode: t_datapath_configuration) return integer is begin case mode is when toolkit=> return 2; when gen3=> return 3; end case; end get_bursts_per_module; constant BURSTS_PER_MODULE: integer := get_bursts_per_module(datapath_configuration); end datapathSetup; From newsfish@newsfish Fri Dec 24 22:54:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 11:35:54 -0500 Date: Fri, 13 Aug 2010 02:36:54 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: <8chcjgFmd4U1@mid.individual.net> In-Reply-To: <8chcjgFmd4U1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-dhM+twUX+EMoUWzRrOqNGkWYQt7CTfEvcH4cFMwpxB+PNNkQsJzjoVe8svADTkWHoTeKo9go54Y6JY8!wLYbHLqri8s91rdmfDD2rsRZvRZIJ2aNDeKU9pWTNQR8coHPATQBcDoIXar2L8VtvuIVhGVehzLp!djSj9MUFxTYa2shgdvoS X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4023 Mike Treseler wrote: > I would declare an array: bunch_o_constants_t > That might give me only one line to comment. I should've used a better example. There's a mixture of types involved. > If the values are computable from a parameter, > as in the example, I might use a function on the right side. Nope, not in this case. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 11:43:52 -0500 Date: Fri, 13 Aug 2010 02:44:52 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 34 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-eG9S9zy6GvOHEswHRTWgHGBZ/J+qe0sEX1/ez8zIUdZlg+VokTKUIFQ5nYJsBsloxgRaurbWZwrxxwn!LP5Cz08J4h7S0aPu9KTBUiCVQKSugKVL4PZZtO3fYHiiiWP3YSdSVR66T36k71mhm4XH0d49v090!DHU/JtALvQl1ztJZadL5 X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4024 KJ wrote: > And now a constant array of the universe of those choices... > constant All_abcds: arr_t_abcd := > (x"0", x"1"..., x"3"), > (x"3", x"4"..., x"6"); This I like, except for one thing. It groups values for each constant together in the source, which wouldn't be a problem except I need to be able to see the relationship between some of the constants for a given "configuration". In the example above, you can easily see 0 goes with 3, 1 goes with 4 etc, but when you have different types and longer names, it makes it quite difficult... :( eg. constant All_acbds: arr_t_abcd := ( some_value_for_type_a, another_value_for_type_a, yet_another_value_for_type_a...and_finally_another_for_type_a), ( true, true, false...true), ( a_value_of_c, another_value_of_c, yet_another_value_of_c... and_a_last_value_for_c_which_has_a_long_name), etc... But food for thought... thanks! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!s9g2000yqd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 09:45:45 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: References: NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281631545 9233 127.0.0.1 (12 Aug 2010 16:45:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 16:45:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000yqd.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4025 On Aug 12, 5:14=A0am, Jonathan Bromley wrote: > On Thu, 12 Aug 2010 12:51:34 +1000, Mark McDougall wrote: > >I have a bunch of constants that can change from build to build > > Great advice from Mike and KJ. > > A couple of other thoughts: > > - Kevin's "universe of possible sets of values" could > possibly be a moving target as you port the design > to a big variety of platforms. =A0Using a function to > construct the record, and passing some interesting > selector values to that function, may be a cleaner > approach if you can compute your constants based on > the value of a few vital statistics of the platform. > > - If the set of constants truly is a horrible > platform-specific mishmash of values, it may be > cleaner *not* to maintain one big collection of > them, but rather to create a collection of package > files each of which defines the same-named package, > which contains all your constants. =A0Each file > is then the description of a single platform, > and by compiling the correct file you get the > correct values in your platform descriptor package. > Now you can adjust the platform-specific build > simply by writing a new package file, and > tweaking your build script to use that file. > > - Oftentimes it is quite sucky to be forced to > use std_logic_vector values for these constants. > Don't be ashamed of using integer constants in > the package, and then constructing s-l-v > constants from them using a function in the > architecture. =A0I've often done this when > describing, for example, the layout of a bunch > of registers in an address space - it's far > easier to describe the addresses using integers, > and then fabricate appropriate vector values > from those integers for use in the decoder or > whatever logic. > > -- > Jonathan Bromley Integers and other types work especially well to provide some built-in sanity checking, such as limiting a constant's value to between 1 and 100 (decimal). Or a color to be red, blue, green, etc. Sure these checks can be handled with extra functions called by extra assertion statements, but you get it for free by constraining the type/subtype etc. SLV works well when you are trying to describe a set of digital electronic signals, not so well when you want to describe information (e.g. add some context to the signals). Andy From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 11:49:13 -0500 Date: Fri, 13 Aug 2010 02:50:12 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 39 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-VFhQkiUbUF3IJ21lhd0pTTG00D9xw1YmxILS/amLjt536voRVg6Bm9dSRF8hXOaw772JCT4CFFuVk5w!r2LlK1C8tlAmjigjQ0N8NI2OS7fsck/Y8PIvGdXnU+G5eAhkYZGFc/YjhrMMomG+eURlLcRXSBmv!KONNXrahrbH09U8L6nBG X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4026 Jonathan Bromley wrote: > - Kevin's "universe of possible sets of values" could possibly be a > moving target as you port the design to a big variety of platforms. > Using a function to construct the record, and passing some interesting > selector values to that function, may be a cleaner approach if you can > compute your constants based on the value of a few vital statistics of > the platform. Good idea for some applications, but see my comments in response to Kevin's - and this is one step worse again. :( > - If the set of constants truly is a horrible platform-specific > mishmash of values, it may be cleaner *not* to maintain one big > collection of them, but rather to create a collection of package files > each of which defines the same-named package, which contains all your > constants. Heh, this is exactly what I do *as well*, one step up the ladder of 'abstraction'. The constants I have are a mish-mash, but even within the same project there are several build options. But I see where you're coming from. > - Oftentimes it is quite sucky to be forced to use std_logic_vector > values for these constants. Don't be ashamed of using integer constants > in the package, Don't worry, I've never been afraid to use integers or other non-slv types. I frequently use integer subtypes for counters, for example. Thanks guys for your tips. Much appreciated! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 09:53:14 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <87dce1f7-6685-47e3-836f-f443b019ad39@y11g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281631994 12798 127.0.0.1 (12 Aug 2010 16:53:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 Aug 2010 16:53:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4027 On 12 Aug., 04:51, Mark McDougall wrote: > I have a bunch of constants that can change from build to build, depending > on what I'm targeting. Right now I'm simply commenting/out a whole set of > lines each time. eg: > > --constant A : std_logic_vector(3 downto 0) := X"0"; > --constant B : std_logic_vector(3 downto 0) := X"1"; > --constant C : std_logic_vector(3 downto 0) := X"2"; > --constant D : std_logic_vector(3 downto 0) := X"3"; > > constant A : std_logic_vector(3 downto 0) := X"3"; > constant B : std_logic_vector(3 downto 0) := X"4"; > constant C : std_logic_vector(3 downto 0) := X"5"; > constant D : std_logic_vector(3 downto 0) := X"6"; Is there a reason why you don't want to solve this with generics or configurations? I've seen that Synplicty even allows you to pass generics in the synthesis you need no top level wrapper, that you would use otherwise. bye Thomas From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 11:54:15 -0500 Date: Fri, 13 Aug 2010 02:55:14 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <-_WdncpoWb2quvnRnZ2dnUVZ_jGdnZ2d@westnet.com.au> Lines: 20 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-fjmLoXx0XME2HyWZvOhAjCVPUqGV7rl6I6qW+sqkKwsMARurdBDkoJKcpoI8GailGZXOr4K6FKkah3z!FTubIiA+TKcNqD404TQj50eXvhMJL1rE6SgySzsAz3rRotUNmVIDRxWPsvkLTEhSc2MQaO2Qnv3B!hqbCor746S4FzVPIqzCo X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4028 Mark McDougall wrote: > Heh, this is exactly what I do *as well*, one step up the ladder of > 'abstraction'. The constants I have are a mish-mash, but even within the > same project there are several build options. But I see where you're > coming from. FWIW I suspect my situation is a little different than most!?! I have a collection of projects that all build on a cross-section of hardware targets. And each project itself may have different build options for each hardware target. So I'm trying to manage 'p' projects on 't' targets with 'b' build options... pxtxb=arrghh!!! ;) Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!news2.google.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 11:56:51 -0500 Date: Fri, 13 Aug 2010 02:57:52 +1000 From: Mark McDougall Reply-To: markm@vl.com.au Organization: Virtual Logic Pty Ltd User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: <87dce1f7-6685-47e3-836f-f443b019ad39@y11g2000yqm.googlegroups.com> In-Reply-To: <87dce1f7-6685-47e3-836f-f443b019ad39@y11g2000yqm.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <-_WdncVoWb1OuvnRnZ2dnUVZ_jGdnZ2d@westnet.com.au> Lines: 16 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 124.170.70.98 X-Trace: sv3-NtOSKqOnH5ADtBiD7Rzq4S3Q+QDvzXBy110hizJjFM9pCjk3u9fzUWcOT/11ND0N5R8TQ/2Im7r+7qn!nqf3H0CnVrKQKgm5rmQwAaUVsskfwnZ4fymWM1r3F9tnleuEGZZHxxspiVe6lBNPnrzgcRAcHi4r!CGYLzN5d3yhKk4mkGF86 X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4029 Thomas Stanka wrote: > Is there a reason why you don't want to solve this with generics or > configurations? Generics won't solve my problem. Just move it. Configurations - I've never been able to get them to solve this problem. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 20:51:35 +0100 Organization: A noiseless patient Spider Lines: 48 Message-ID: <1rj8665hdgosbk7bi9kq6ole0e0r5ch3i2@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Aug 2010 19:51:47 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="21567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/+9P52ed7+U+oTXvu9Mm62VoBd1k6Y+5w=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:uBzz3rWa0w6xTLVSt9sfpX3/vlA= Xref: feeder.eternal-september.org comp.lang.vhdl:4030 On Fri, 13 Aug 2010 02:44:52 +1000, Mark McDougall wrote: >KJ wrote: > >> And now a constant array of the universe of those choices... >> constant All_abcds: arr_t_abcd := >> (x"0", x"1"..., x"3"), >> (x"3", x"4"..., x"6"); > >This I like, except for one thing. It groups values for each constant >together in the source, which wouldn't be a problem except I need to be >able to see the relationship between some of the constants for a given >"configuration". In the example above, you can easily see 0 goes with 3, 1 >goes with 4 etc, but when you have different types and longer names, it >makes it quite difficult... :( > >eg. > >constant All_acbds: arr_t_abcd := >( some_value_for_type_a, another_value_for_type_a, > yet_another_value_for_type_a...and_finally_another_for_type_a), >( true, true, false...true), >( a_value_of_c, another_value_of_c, yet_another_value_of_c... > and_a_last_value_for_c_which_has_a_long_name), I'm not sure you and KJ are on the same page here. Kevin's idea (as I read it) is to construct a type that is a record, collecting all the assorted constants relating to a single build. And then an array of those records, one array element for each possible build. So each record, written as an aggregate expression, clearly shows "what goes with what". I don't really understand why that presents the problem I think you're describing. But I could have missed the point - it wouldn't be the first time :-) Regardless of the details (and point taken about your rather large configuration space) it should be possible to build a data structure that clearly captures the set of constants that define a build. Once that's done, you can create an array of those things and choose one of them by a suitable index, or write a function that constructs such an object from argument values that specify the build's properties. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 14:59:42 -0500 Date: Thu, 12 Aug 2010 12:59:41 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.11) Gecko/20100711 Thunderbird/3.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 34 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-Ze1SmS6MLs402BbA1gweHwRHqfwwDIVRzf5y2nBqMfU1j4yywtlb0OmNolnugrUuEonCQ3w/oCHqKLn!KeImRpl4o6Hwwzy2Mz/QhUxeAq50JgEbZcl8rmJeAShN15mxPaB+Qp41HwTAJaZC26bVPvHAGArB!0w== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4031 On 8/11/2010 7:51 PM, Mark McDougall wrote: > Hi gurus, > > I have a bunch of constants that can change from build to build, depending > on what I'm targeting. Right now I'm simply commenting/out a whole set of > lines each time. eg: > > --constant A : std_logic_vector(3 downto 0) := X"0"; > --constant B : std_logic_vector(3 downto 0) := X"1"; > --constant C : std_logic_vector(3 downto 0) := X"2"; > --constant D : std_logic_vector(3 downto 0) := X"3"; > > constant A : std_logic_vector(3 downto 0) := X"3"; > constant B : std_logic_vector(3 downto 0) := X"4"; > constant C : std_logic_vector(3 downto 0) := X"5"; > constant D : std_logic_vector(3 downto 0) := X"6"; > > Short of diving into configurations etc, does anyone have a handy trick > they use in these sorts of situations? The idea is to be able to > change/comment only 1/2 lines to achieve the above... > > I can think of some rather horrible& convoluted ways that might work > with, say, std_logic_vector using and/or, but it's not pretty... > > Regards, > Put each set of constants in their own file, give them all the same package name, and make your Makefile responsible for picking which of the files to actually include in the build? -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 12 Aug 2010 16:47:14 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Thu, 12 Aug 2010 22:54:38 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: <1br866t64i1r9ufj0c3qoomm93abletpq8@4ax.com> References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 14 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-JaRTKwrz2Eu3l3/ZsoLcLIahwyP/t19By8Ec5IcNLuxs4JupUyNLuS2prHvzF6/s7w+Fn2PcSLuSQU7!Ic3NBZPO+bo0vFmTmZamLZaDxo4+qXUYuD+icIEvNi+ObC8x3KujaQmQLrQThVuXVBJU+XeeZFCx!3/E= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1797 Xref: feeder.eternal-september.org comp.lang.vhdl:4032 On Fri, 13 Aug 2010 02:44:52 +1000, Mark McDougall wrote: >constant All_acbds: arr_t_abcd := >( some_value_for_type_a, another_value_for_type_a, > yet_another_value_for_type_a...and_finally_another_for_type_a), >( true, true, false...true), >( a_value_of_c, another_value_of_c, yet_another_value_of_c... > and_a_last_value_for_c_which_has_a_long_name), It may be useful to alias short names (for the array) onto the long names you need elsewhere for clarity. - Brian From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!c10g2000yqi.googlegroups.com!not-for-mail From: Ruud Newsgroups: comp.lang.vhdl Subject: Newbee in VHDL Date: Fri, 13 Aug 2010 01:17:12 -0700 (PDT) Organization: http://groups.google.com Lines: 139 Message-ID: NNTP-Posting-Host: 85.158.139.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281687432 27391 127.0.0.1 (13 Aug 2010 08:17:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Aug 2010 08:17:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqi.googlegroups.com; posting-host=85.158.139.228; posting-account=CkGlpgkAAACtq9RzAXYWt4fWCwsxq6Ug User-Agent: G2/1.0 X-HTTP-Via: 1.1 WINSV616, 1.1 squid-16 (squid/3.1.0.13) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.0.3705; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4033 Hallo allemaal, I think I'm new here. If not, then it was quite some years back, when I was fiddling with CPLDs. But that didn't get off the ground; I preferred the real 74-stuff above the CPLDs (it is just hobby for me, not my profession). But lately I was pointed to the Godil, < http://www.oho-elektronik.de/ >, a module with a big FPGA plus some extras that can replace (IMHO) any 40/48 pins DIL-IC. Some guys already used it in a BBC Master to replace the onboard 65C102, < http://sites.google.com/site/beeb816/project-updates/firstbytefromthetube-on-fpgahimemis32768 >. I bought the header version because I already had several ideas for its use and and almost none included direct IC replacement. One of the ideas is replacing the 6510 of my Commodore 64 with an, as compatible as possible, improved CPU. I have been busy with building my own 6502, < http://www.baltissen.org/newhtm/ttl6502.htm >, and I decided to use an updated, not yet published design as base for my own VHDL design. Yes, I know, there are some free 6502 VHDL designs around. I studied T65, available at OpenCores. The T65 core is used in many reliable working designs < http://www.fpgaarcade.com/library.htm >. I understood (mostly of) its parts but not the whole. And this has to do with the concepts of concurrency, sequential and event-driven. I program in Pascal and Delphy and therefore are familiar with sequential and event-driven code. You can say that, by working with TTL-ICs, I'm familiar concurrency, but also with things like delay and glitches. I'll give you an example where things go wrong in my vision. According the docs the RDY signal stops the 6502 when pulled low and there is no write going on. RDY is checked at the end of the upper part of the clock. Here is an excerpt from the T65 code: architecture rtl of T65 is signal really_rdy : std_logic; ... begin really_rdy <= Rdy or not(R_W_n_i); [1] R_W_n <= R_W_n_i; .... process (Clk) [2] begin if Clk'event and Clk = '1' then [3] if (Enable = '1') then if (really_rdy = '1') then [4] ..... IRQ_n_o <= IRQ_n; NMI_n_o <= NMI_n; end if; end if; end if; end process; I interprete it as that the signal really_rdy at [1] is updated _all_ the time. The process [2] is only handled if Clk has changed. I interprete [3] as: "handle the following lines if Clk has become '1'". And I interprete [4] as: "and do it only if RDY is not active". I can imagine that RDY has been activated moments before CLK became '1' but also that this situation can change half-way the upper Clk cycle, well before the cycle of Clk. Inthat case the 6502 is stopped while it shouldn't. IRQ is level triggered. IMHO now it it checked at the beginning of the upper part of Clk while IMHO it should be at the end. NMI is edge triggered and should have its own process IMHO. To make sure my TTL6502 is 6502 compatible, it must use both phases of Clk. AFAIK T65 only uses the phase Clk = '1', as in above example. IMHO this could only be done because a big FPGA enables you to execute some tasks parallel, tasks I have to do sequential because I only have an 8 bits wide internal data bus. Of course I have been programming myself already and want to show you the base so you can shoot at it: begin IRQ_in <= not(IRQ) when (PHI0 = '1'); RDY_in <= not(RDY) when ((PHI0 = '1') and (PHI_in = '1')); [1] process(NMI) [2] begin if (RESET = '0') then NMI_in <= '1'; -- set internal NMI flag end if; end process; process(RESET, PHI0) begin if (RESET = '0') then ..... NMI_in <= '0'; -- reset internal NMI flag elsif PHI0'event then if (RDY_in = '1') then [3] if (PHI0 = '0') then PHI_in <= '0'; ..... else PHI_in <= '1'; .... end if; end if; end if; end process; end; [1]: RDY_in can be set only during the upper half of PHI0 and only after the event of the process has been executed; [2] makes sure that NMI is edge triggered. [3] this RDY_in can only have been set in previous upper half of PHI0 IMHO. Two questions: - please comment my above thoughts. - just popped up: how can I test my design as best as possible? FYI: i have an ISA card with 96 I/O lines connected to my Godil. So I can use Turbo Pascal under DOS to address every in- or outpu of the Godil. Any hint is welcome! Many thanks in advance !!! Kind regards, Ruud Baltissen www.Baltissen.org From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!p7g2000yqa.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Fri, 13 Aug 2010 05:34:25 -0700 (PDT) Organization: http://groups.google.com Lines: 105 Message-ID: <1fefe4af-9073-4b33-85aa-8dfa3ed8a59e@p7g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281702866 19341 127.0.0.1 (13 Aug 2010 12:34:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 Aug 2010 12:34:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p7g2000yqa.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4034 On Aug 12, 12:44=A0pm, Mark McDougall wrote: > KJ wrote: > > And now a constant array of the universe of those choices... > > constant All_abcds: arr_t_abcd :=3D > > (x"0", x"1"..., x"3"), > > (x"3", x"4"..., x"6"); KJ note: There was a set of () missing above. Should have been constant All_abcds: arr_t_abcd :=3D ( -- Twas missing this (x"0", x"1"..., x"3"), (x"3", x"4"..., x"6")); -- Twas missing the outer ) > > This I like, except for one thing. It groups values for each constant > together in the source, which wouldn't be a problem except I need to be > able to see the relationship between some of the constants for a given > "configuration". In the example above, you can easily see 0 goes with 3, = 1 > goes with 4 etc, but when you have different types and longer names, it > makes it quite difficult... :( > > > constant All_acbds: arr_t_abcd :=3D > ( some_value_for_type_a, another_value_for_type_a, > =A0 yet_another_value_for_type_a...and_finally_another_for_type_a), > ( true, true, false...true), > ( a_value_of_c, another_value_of_c, yet_another_value_of_c... > =A0 and_a_last_value_for_c_which_has_a_long_name), > > etc... > As I mentioned above, I had a bit of a typo and probably should have used name associations when showing the final constant, and I think you may be misinterpreting the groupings. Just to clear this up, using your now longer named things, and trying to be a bit more explicit, the constant would be declared as constant All_acbds: arr_t_abcd(1 to 4) :=3D ( 1 =3D> ( A =3D> some_value_for_type_a, B =3D> true, C =3D> a_value_of_c, D =3D> some_value_for_type_d ), 2 =3D> ( A =3D> another_value_for_type_a, B =3D> true, C =3D> another_value_of_c, D =3D> another_value_for_type_d ), 3 =3D> ( A =3D> yet_another_value_for_type_a B =3D> false, C =3D> yet_another_value_of_c, D =3D> yet_another_value_for_type_d ), 4=3D> ( A =3D> and_finally_another_for_type_a, B =3D> true, C =3D> and_a_last_value_for_c_which_has_a_long_name D =3D> and_a_last_value_for_type_d ) ); There are two sets of aggregates (now explicitly named, rather than implicit as before). The 'outer' set is the array of the record types, the inner set of aggregates defines the elements of each record. The set of constants for a given configuration are clearly all together. If for some of the constants you really would like to see all of the 'b' for the different configurations together in the source like this... constant The_b_types: arr_boolean(1 to 4) :=3D (true, true, false, true); Then either use that new constant in the bigger constant like this... constant All_acbds: arr_t_abcd :=3D ( 1 =3D> (A =3D> some_value_for_type_a, B =3D> The_b_types(1), C =3D> a_value_of_c, D =3D> some_value_for_type_d), ... Or simply remove the 'b' element from the record and use this new 'b' array since ultimately you want to select a particular set to use and there is no particular advantage (other than to thosse who are picky about consistency) to either of these two forms All_acbds(Sel).B The_b_types(Sel) Kevin Jennings From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.lindneronline.de!news.uni-stuttgart.de!news.cs.uni-magdeburg.de!not-for-mail From: Paul Newsgroups: comp.lang.vhdl Subject: Re: type computation Date: Mon, 16 Aug 2010 07:51:06 +0200 Organization: University of Magdeburg, Germany Lines: 32 Message-ID: References: <1d3c5bad-103b-4ff1-a93d-187c80a43ec0@x21g2000yqa.googlegroups.com> NNTP-Posting-Host: imat46.mb.uni-magdeburg.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: fuerst.cs.uni-magdeburg.de 1281937866 11400 141.44.146.46 (16 Aug 2010 05:51:06 GMT) X-Complaints-To: abuse@cs.uni-magdeburg.de NNTP-Posting-Date: Mon, 16 Aug 2010 05:51:06 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de-DE; rv:1.9.2.8) Gecko/20100802 Lightning/1.0b2 Thunderbird/3.1.2 In-Reply-To: <1d3c5bad-103b-4ff1-a93d-187c80a43ec0@x21g2000yqa.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4035 > I am currently in the process of getting simulink algorithms working > in VHDL, and doing a lot of co-simulation. > I think the approach you have may be the wrong way round. When we > started, we looked at the limitations the FPGA was going to impose on > the algorithm, rather than letting simulink run the show completly. > Things like multiplier widths (normally 18 bits) and available memory > at given points. This all fed back and put fixed limits on the word > widths at the start (after some testing was done on the algorithm to > ensure it didnt degrade performance). Bitwidth is 16bit due to the DSP48 macro. BTW, why are there 18 bits? I would expect 17 for overflow calculation. > So I have a "setup package" that defines all of the word widths > throughout the algorithm via sub types. I have the following: > > subtype filter_word_t is sfixed(11 downto -4); --16 bits because the > memories are 18 bits and we need to store a couple of status bits with > each word > subtype coeff_t is sfixed(1 downto -16); --18 bit multiplers. This is my tb_pkg at this time, the entity is parametrized by this. I only perform some type/width calculation. At this time I have the problem that in the TB's tester fixed points calculations are correct, inside the dut isn't .... Thanks, Olaf From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!5g2000yqz.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: All are unsigned but wrong type is output? Date: Sun, 15 Aug 2010 23:58:05 -0700 (PDT) Organization: http://groups.google.com Lines: 165 Message-ID: <6d07c576-d5f1-452b-a242-c951f4baf505@5g2000yqz.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1281941885 7544 127.0.0.1 (16 Aug 2010 06:58:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 Aug 2010 06:58:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 5g2000yqz.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.125 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4037 Hello, I was wondering if anyone could help. I've included the code for 4 files of my project. If anyone has the Altera DE2, It's from Lab6 Part 1. My problem is that in full8bitadder.vhd, i'm getting an error that says: Error (10381): VHDL Type Mismatch error at full8bitadder.vhd(17): indexed name returns a value whose type does not match "UNSIGNED", the type of the target expression this error occurs on the line where fa0 is instantiated. I don't understand why the type would not match unsigned when EVERYTHING in my project is unsigned. Does anyone here have an idea of what's happening? Thanks, Malik ------------------------------------------------- Lab1_6.vhd ---------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity Lab1_6 is port( SW : in unsigned(15 downto 0); KEY : in unsigned(1 downto 0); LEDR : out unsigned(7 downto 0); LEDG : out unsigned(8 downto 8); HEX7, HEX6, HEX5, HEX4, HEX1, HEX0 : out unsigned(6 downto 0) ); end Lab1_6; architecture behavior of Lab1_6 is signal ci0 : unsigned; signal S : unsigned(7 downto 0); signal R : unsigned(7 downto 0); begin ci0 <= to_unsigned(1,1); fa : work.full8bitadder port map(ci0, SW(15 downto 8), SW(7 downto 0), LEDG, R); h7 : work.HEX port map(SW(15 downto 12), HEX7); h6 : work.HEX port map(SW(11 downto 8), HEX6); h5 : work.HEX port map(SW(7 downto 4), HEX5); h4 : work.HEX port map(SW(3 downto 0), HEX4); h1 : work.HEX port map(S(7 downto 4), HEX1); h0 : work.HEX port map(S(3 downto 0), HEX0); process(KEY) begin if(KEY = "01") then S <= to_unsigned(0,8); end if; if(KEY = "10") then S <= R; end if; end process; end behavior; ------------------------------------------------- full8bitadder.vhd ---------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity full8bitadder is port( ci : in unsigned(7 downto 0); a, b : in unsigned(7 downto 0); co : out unsigned(8 downto 0); s : out unsigned(7 downto 0) ); end full8bitadder; architecture behavior of full8bitadder is begin fa0 : work.fulladder port map(ci(0), a(0), b(0), co(1), s(0)); fa1 : work.fulladder port map(ci(1), a(1), b(1), co(2), s(1)); fa2 : work.fulladder port map(ci(2), a(2), b(2), co(3), s(2)); fa3 : work.fulladder port map(ci(3), a(3), b(3), co(4), s(3)); fa4 : work.fulladder port map(ci(4), a(4), b(4), co(5), s(4)); fa5 : work.fulladder port map(ci(5), a(5), b(5), co(6), s(5)); fa6 : work.fulladder port map(ci(6), a(6), b(6), co(7), s(6)); fa7 : work.fulladder port map(ci(7), a(7), b(7), co(8), s(7)); end behavior; ------------------------------------------------- fulladder.vhd ---------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity fulladder is port( ci, a, b : in unsigned; co, s : out unsigned ); end fulladder; architecture behavior of fulladder is begin s <= a xor b xor ci; co <= (a and b) or (b and ci) or (a and ci); end behavior; ------------------------------------------------- HEX.vhd ---------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity HEX is port( HEXcnt : in unsigned(3 downto 0); HEXOut : out unsigned(6 downto 0) ); end HEX; architecture behavioral of HEX is signal HEXInt : integer; type SegROM is array (0 to 15) of unsigned(6 downto 0); constant segStates : SegROM := ( 0 => "1000000", 1 => "1111001", 2 => "0100100", 3 => "0110000", 4 => "0011001", 5 => "0010010", 6 => "0000010", 7 => "1111000", 8 => "0000000", 9 => "0010000", 10 => "0001000", 11 => "0000011", 12 => "1000110", 13 => "0100001", 14 => "0000110", 15 => "0001110"); begin process(HEXcnt, HEXInt) begin HEXInt <= to_integer(unsigned(HEXcnt)); HEXOut <= segStates(HEXInt); end process; end behavioral; From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.freenet.ag!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Date: Mon, 16 Aug 2010 09:04:38 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: All are unsigned but wrong type is output? References: <6d07c576-d5f1-452b-a242-c951f4baf505@5g2000yqz.googlegroups.com> In-Reply-To: <6d07c576-d5f1-452b-a242-c951f4baf505@5g2000yqz.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 16 Message-ID: <4c68e307$0$22941$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 195.242.97.150 X-Trace: 1281942279 news.xs4all.nl 22941 phulshof/[::ffff:195.242.97.150]:54091 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4038 > this error occurs on the line where fa0 is instantiated. I don't > understand why the type would not match unsigned when EVERYTHING in my > project is unsigned. > entity fulladder is > port( > ci, a, b : in unsigned; > co, s : out unsigned > ); > end fulladder; Try using std_logic here in stead of unsigned vectors of undetermined length. Kind regards, Pieter Hulshoff From newsfish@newsfish Fri Dec 24 22:54:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.64.134.MISMATCH!postnews.google.com!i13g2000yqd.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: All are unsigned but wrong type is output? Date: Mon, 16 Aug 2010 00:57:20 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <0fccb573-291c-437a-bf73-9aade6ad0e23@i13g2000yqd.googlegroups.com> References: <6d07c576-d5f1-452b-a242-c951f4baf505@5g2000yqz.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1281945441 21034 127.0.0.1 (16 Aug 2010 07:57:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 Aug 2010 07:57:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i13g2000yqd.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4039 On 16 Aug., 08:58, laserbeak43 wrote: > I was wondering if anyone could help. I've included the code for 4 > files of my project. If anyone has the Altera DE2, It's from Lab6 Part > 1. [..] > =A0 =A0 =A0 =A0 fa0 : work.fulladder port map(ci(0), a(0), b(0), co(1), s= (0)); [..] > entity fulladder is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ci, a, b =A0 =A0 =A0 =A0: in unsigned; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 co, s =A0 =A0 =A0 =A0 =A0 : out unsigned I think the problem is, that numeric_std defines unsigned as array of std_logic which means the single element is std_logic not unsigned. If you change the type of these 5 IOs to std_logic, everything should work. bye Thomas From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!v41g2000yqv.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: in the absence of a pre-processor... Date: Mon, 16 Aug 2010 23:45:08 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <87dce1f7-6685-47e3-836f-f443b019ad39@y11g2000yqm.googlegroups.com> <-_WdncVoWb1OuvnRnZ2dnUVZ_jGdnZ2d@westnet.com.au> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282027509 10231 127.0.0.1 (17 Aug 2010 06:45:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 Aug 2010 06:45:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v41g2000yqv.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4042 On 12 Aug., 18:57, Mark McDougall wrote: > Thomas Stanka wrote: > > Is there a reason why you don't want to solve this with generics or > > configurations? > > Generics won't solve my problem. Just move it. Some tools like Modelsim or Synplify accept Generics as tool input. So you avoid commenting of code by passing Generics from the tools. > Configurations - I've never been able to get them to solve this problem. You can use Generics and set them in the configuration. Each build would use a different top level configuration setting the Generics, while the complete other code is identical for the design. Unfortunately not every tool supports Configurations on top level properly although it is pure and legal vhdl. bye Thomas From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!ecngs!feeder.ecngs.de!feeder.news-service.com!postnews.google.com!z10g2000yqb.googlegroups.com!not-for-mail From: CP Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: vMAGIC 0.3.9 released Date: Wed, 18 Aug 2010 04:24:14 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <138fc07f-9021-421f-be69-8d364d2de97c@z10g2000yqb.googlegroups.com> NNTP-Posting-Host: 62.159.14.62 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282130660 27468 127.0.0.1 (18 Aug 2010 11:24:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Aug 2010 11:24:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z10g2000yqb.googlegroups.com; posting-host=62.159.14.62; posting-account=gJPJ3AoAAAC1Zi231vILwkMZpBrMz6Tk User-Agent: G2/1.0 X-HTTP-Via: 1.1 NT-PROXY03 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4043 comp.arch.fpga:12173 Hi folks! We are proud to announce version 0.3.9 of the vMAGIC libraries with a number of improvements. Most importantly, this will be the last alpha release as we want to keep the API stable from beta release 0.4.0 onwards. The current release particularly improves the handling of scopes, thus extending the code analysis features of vMAGIC. Also we have re-added the documentation to the binary release, and introduced a complete overhaul of the output framework. This last item is as yet transparent to the user, but it will be very important for the extension of the vMAGIC output options, i.e., the generation of XML code or Java code using vMAGIC (cf. http://vmagic.sf.net > Coming up next). Get it at SourceForge: http://vmagic.sf.net Looking forward to your feedback on http://sourceforge.net/projects/vmagic/forums/forum/880445 Ralf and christopher From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!z10g2000yqb.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: All are unsigned but wrong type is output? Date: Wed, 18 Aug 2010 14:06:00 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: <6d07c576-d5f1-452b-a242-c951f4baf505@5g2000yqz.googlegroups.com> <0fccb573-291c-437a-bf73-9aade6ad0e23@i13g2000yqd.googlegroups.com> NNTP-Posting-Host: 12.18.245.219 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282165560 12361 127.0.0.1 (18 Aug 2010 21:06:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 18 Aug 2010 21:06:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z10g2000yqb.googlegroups.com; posting-host=12.18.245.219; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4044 Hi guys, Thanks for the replies, that did work, I have to remember that unsigned is an array of std_logic. very tricky stuff! Thanks, Malik From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 18 Aug 2010 16:58:49 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Wed, 18 Aug 2010 23:06:21 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 32 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-eyNVh7JbBAQzS7GzO8VgfxNYen2OSH/adZ2O4fXSvqKYRbvG+oMKi3/kUA80tzAK4JvZuK50dqZvND/!f+NlbLrVAPStl0+rrEhqneE9chsQpB6ecAm12zaxKhtytcnyTIH5SHHeSW4GPqw+uJw6T6CFTVH7!/g== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4045 On Wed, 18 Aug 2010 14:11:14 -0700 (PDT), laserbeak43 wrote: >Hello, >I'm writting some code(lab 6 part 1 of the Altera DE2 VHDL exercises) >and i keep getting this warning, that some of my signals and I/O are >going to be latched. I don't understand what makes >this happen, could someone please explain? Because you didn't complete the if statement. So it means... > if(KEY = "00") then > S <= to_unsigned(0,8); > elsif(KEY = "01") then > S <= R; else latch the old value of S; > end if; If you don't want storage elements here, fill in the correct action in "else"... If you want registers instead of latches. make this a clocked process... process (clk) begin if rising_edge(clk) then if (KEY ... end if; end if; end process; - Brian From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.eweka.nl!feeder3.eweka.nl!81.171.88.15.MISMATCH!eweka.nl!lightspeed.eweka.nl!postnews.google.com!j18g2000yqd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Thu, 19 Aug 2010 10:12:34 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282237957 1093 127.0.0.1 (19 Aug 2010 17:12:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 Aug 2010 17:12:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000yqd.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4046 Avoiding latches comes from understanding what causes them. Anytime a process is required to remember the value of a signal through an execution of that process, that implied memory becomes a storage element in synthesis. A signal that is not assigned any value during an execution of the process must "remember" it's previous value, thus that creates a memory element. If the process is clocked, then the memory element is an edge-triggered flip-flop. If the process is combinatorial, then the memory element is a latch, or combinatorial feedback creating a latch out of gates. The easiest, surest way to avoid latches is to, for all combinatorial processes, include default assignments to all outputs ever driven by the process, right up front, before anything else. That way there are no execution paths through the process that avoid the assignments. Of course, if you can avoid combinatorial processes altogether, then you won't get latches in the first place. But sometimes you just can't avoid a combinatorial process. This same "remembering" analogy also governs whether a reference to a variable in a clocked process causes a register, or just combinatorial logic. Andy From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.swapon.de!feedme.ziplink.net!border2.nntp.dca.giganews.com!nntp.giganews.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!nx01.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!postnews3.readnews.com!not-for-mail Date: Thu, 19 Aug 2010 18:08:02 -0400 From: Jeff Cunningham User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.4; en-US; rv:1.9.1.11) Gecko/20100711 Thunderbird/3.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> In-Reply-To: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 22 Message-ID: <4c6dab48$0$2388$4d3efbfe@news.sover.net> Organization: SoVerNet (sover.net) NNTP-Posting-Host: 6e2908c0.news.sover.net X-Trace: DXC=;a=G]BGjXIM25]V9k:[LPCK6_LM2JZB_C5a4cYH7B7HH:WUUlR<856O:C0bTWIZ^;OPD2i4]?S3;C X-Complaints-To: abuse@sover.net Xref: feeder.eternal-september.org comp.lang.vhdl:4047 On 8/18/10 5:11 PM, laserbeak43 wrote: ... > process(KEY, R, S, sigSW, co0) > begin > if(KEY = "00") then > S<= to_unsigned(0,8); > elsif(KEY = "01") then > S<= R; > LEDG8<= co0(7); > LEDR(15 downto 8)<= sigSW(15 downto 8); > LEDR(7 downto 0)<= sigSW(7 downto 0); > end if; > end process; In addition to the latch problem due to not covering all cases of KEY, you really should not have S in the sensitivity list. You are telling the model to run the process again when S changes. But because you change it in the process itself, it sort of doesn't make sense and will cause wasteful rerunning of the process whenever you update S. This doesn't affect your synthesis result - it just slows the simulation. -Jeff From newsfish@newsfish Fri Dec 24 22:54:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!h19g2000yqb.googlegroups.com!not-for-mail From: bybell Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: gtkwave 3.3.11 is available Date: Thu, 19 Aug 2010 22:19:50 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: <34ddf724-b33a-4f58-a358-ed30f0ef7599@5g2000yqz.googlegroups.com> NNTP-Posting-Host: 75.189.205.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282281590 29989 127.0.0.1 (20 Aug 2010 05:19:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Aug 2010 05:19:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h19g2000yqb.googlegroups.com; posting-host=75.189.205.40; posting-account=v6D4ZAkAAAATVRs0rkKAnftIlV5GVUb8 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.11) Gecko/20100701 Firefox/3.5.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:2499 comp.lang.vhdl:4048 Most of the new features in this version revolve around Tcl support enhancements, the main new feature being the addition of Tcl callback procedures which can triggered by various GUI and viewer operations. This will provide far tighter integration with external tools. -Tony From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!g17g2000yqe.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Alias of two std_logic_vector elements of an array Date: Fri, 20 Aug 2010 03:19:29 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <27695cf2-6a12-4c1c-b7ba-b1a8456d0ff1@g17g2000yqe.googlegroups.com> NNTP-Posting-Host: 134.102.219.52 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282299569 423 127.0.0.1 (20 Aug 2010 10:19:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Aug 2010 10:19:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g17g2000yqe.googlegroups.com; posting-host=134.102.219.52; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; de; rv:1.9.2.8) Gecko/20100723 Ubuntu/10.04 (lucid) Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4049 Hello! I declared the following type and the corresponding signal: type sd_card_data_a is array (natural range 527 downto 0) of std_logic_vector(7 downto 0); signal sd_card_data_as : sd_card_data_a; What I can do now is create an alias for a single element of the signal: alias data_start_block_s : std_logic_vector(7 downto 0) is sd_card_data_as(0); What I can NOT do is defining an alias that spans several elements of the array: alias data_stuff_bytes_s : std_logic_vector(15 downto 0) is sd_card_data_as(10 downto 9); Even when I define a type for the alias: type data_stuff_bytes_a is array (514 downto 513) of std_logic_vector(7 downto 0); alias data_stuff_bytes_s : data_stuff_bytes_a is sd_card_data_as(2 downto 1); My questions are: Did anybody understand my promblem? Can anybody present a solution? Greetings, /h From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: "Maurice" Newsgroups: comp.lang.vhdl Subject: free software for synthetising popular PAL/GALs? Date: Fri, 20 Aug 2010 13:42:44 +0300 Organization: Aioe.org NNTP Server Lines: 8 Message-ID: NNTP-Posting-Host: 5ZsCg3GJldp2bdyKynAM+w.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Notice: Filtered by postfilter v. 0.8.2 X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4050 Hello: is there any free software for synthetising popular PAL/GAL devices (like 22V10) from a VHDL code ? thanks From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Alias of two std_logic_vector elements of an array Date: Fri, 20 Aug 2010 13:20:19 +0100 Organization: A noiseless patient Spider Lines: 72 Message-ID: References: <27695cf2-6a12-4c1c-b7ba-b1a8456d0ff1@g17g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Fri, 20 Aug 2010 12:20:22 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="22710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18iKkqnY8SFAKM/+UtewnyAUHK+nrZoruE=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:EkjhLEayFlLui9u5ntU16Raq0PI= Xref: feeder.eternal-september.org comp.lang.vhdl:4051 On Fri, 20 Aug 2010 03:19:29 -0700 (PDT), hhanff wrote: >type sd_card_data_a is array (natural range 527 downto 0) of >std_logic_vector(7 downto 0); >signal sd_card_data_as : sd_card_data_a; > >What I can do now is create an alias for a single element of the >signal: > >alias data_start_block_s : std_logic_vector(7 downto 0) is >sd_card_data_as(0); > >What I can NOT do is defining an alias that spans several elements of >the array: > >alias data_stuff_bytes_s : std_logic_vector(15 downto 0) is >sd_card_data_as(10 downto 9); No, you can't - your alias must be an array of the same element types as were in the original array. >Even when I define a type for the alias: > >type data_stuff_bytes_a is array (514 downto 513) of >std_logic_vector(7 downto 0); >alias data_stuff_bytes_s : data_stuff_bytes_a is sd_card_data_as(2 >downto 1); Different problem here. The alias must have the same base type as the real object, I think. So you would need something like this... --- This one is just to reduce finger strain: subtype byte is std_logic_vector(7 downto 0); --- Generalised array type type byte_array_t is array(natural) of byte; --- Specialise it for your card_data array: signal sd_card_data_as: byte_array_t(527 downto 0); --- Now make your alias: alias data_stuff: byte_array_t(514 downto 513) is sd_card_data_as(2 downto 1); I *think* that will work.... no time to check. >Can anybody present a solution? You will probably find it easier to write functions and procedures to access groups of elements of the array. For example, to read and write several adjacent elements as if they were a single wide vector: function get_Nbytes(data: byte_array_t; first_adrs: natural; num_bytes: positive) return std_logic_vector is variable result: std_logic_vector(8*num_bytes-1 downto 0); begin for i in 0 to num_bytes-1 loop result(8*i+7 downto 8*i) := data(first_adrs+i); --- puts first address into rightmost 8 bits end loop; return result; end function; The matching "put" procedure is left as an exercise... -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: free software for synthetising popular PAL/GALs? Date: Fri, 20 Aug 2010 10:14:00 -0700 Lines: 9 Message-ID: <8d7rc0FgplU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net DrKMUkd8BFCkyUN5gbyqogrxt77r9NJkgJPMgT9vZY6rQg0cgi Cancel-Lock: sha1:00N6HXM7W/FbY5VyrZ0SnjWmMxY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4052 On 8/20/2010 3:42 AM, Maurice wrote: > is there any free software for synthetising popular PAL/GAL devices (like > 22V10) from a VHDL code ? Don't know, but for $2.55 I can get 64 flops instead of 22 and free software. http://www.altera.com/literature/ds/m3000a.pdf -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!v8g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: free software for synthetising popular PAL/GALs? Date: Fri, 20 Aug 2010 10:42:57 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <95b78a6d-e315-4a63-bec2-479731e428e4@v8g2000yqe.googlegroups.com> References: NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282326177 14905 127.0.0.1 (20 Aug 2010 17:42:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Aug 2010 17:42:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v8g2000yqe.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4053 On Aug 20, 5:42=A0am, "Maurice" wrote: > Hello: > > is there any free software for synthetising popular PAL/GAL devices (like > 22V10) =A0from a VHDL code ? > > thanks I think Cypress used to have such a free tool; maybe they still do? Andy From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!news2.glorb.com!news-in-01.newsfeed.easynews.com!easynews!core-easynews-01!easynews.com!en-nntp-11.dc1.easynews.com.POSTED!not-for-mail From: Rich Webb Newsgroups: comp.lang.vhdl Subject: Re: free software for synthetising popular PAL/GALs? Organization: Line Eater Memorial Fund Message-ID: References: X-Newsreader: Forte Agent 6.00/32.1186 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hamster-Pg/1.25.2.0 X-Antivirus: avast! (VPS 100820-0, 08/20/2010), Outbound message X-Antivirus-Status: Clean Lines: 14 X-Complaints-To: abuse@easynews.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 20 Aug 2010 13:33:19 -0400 Xref: feeder.eternal-september.org comp.lang.vhdl:4054 On Fri, 20 Aug 2010 13:42:44 +0300, "Maurice" wrote: >Hello: > >is there any free software for synthetising popular PAL/GAL devices (like >22V10) from a VHDL code ? Not VHDL but WinCUPL isn't a bad fit for PAL/GAL-sized devices, and it is free from Atmel. http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759 -- Rich Webb Norfolk, VA From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.wiretrip.org!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!p22g2000pre.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: free software for synthetising popular PAL/GALs? Date: Fri, 20 Aug 2010 11:24:11 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <26cbe7bc-cd42-4c21-8180-9a207dd03afb@p22g2000pre.googlegroups.com> References: <95b78a6d-e315-4a63-bec2-479731e428e4@v8g2000yqe.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282328652 3286 127.0.0.1 (20 Aug 2010 18:24:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Aug 2010 18:24:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p22g2000pre.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4055 On Aug 20, 10:42=A0am, Andy wrote: > On Aug 20, 5:42=A0am, "Maurice" wrote: > > > Hello: > > > is there any free software for synthetising popular PAL/GAL devices (li= ke > > 22V10) =A0from a VHDL code ? > > > thanks > > I think Cypress used to have such a free tool; maybe they still do? > > Andy It was called "warp"; I found it very useful for VHDL->22V10. I found a couple defects transliterating CUPL to VHDL and then simulating. Last time I checked, it was discontinued by Cypress, but still available from distributors. Not free however. I recommend a google for "Cypress Warp". RK From newsfish@newsfish Fri Dec 24 22:54:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t3g2000vbb.googlegroups.com!not-for-mail From: MBodnar Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Fri, 20 Aug 2010 12:28:20 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> NNTP-Posting-Host: 75.147.109.134 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282332500 2830 127.0.0.1 (20 Aug 2010 19:28:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Aug 2010 19:28:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t3g2000vbb.googlegroups.com; posting-host=75.147.109.134; posting-account=er1mVAoAAACeGcBwCiEuZAmH5XJGQKa5 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4056 On Aug 19, 1:12=A0pm, Andy wrote: > Avoiding latches comes from understanding what causes them. Anytime a > process is required to remember the value of a signal through an > execution of that process, that implied memory becomes a storage > element in synthesis. A signal that is not assigned any value during > an execution of the process must "remember" it's previous value, thus > that creates a memory element. If the process is clocked, then the > memory element is an edge-triggered flip-flop. If the process is > combinatorial, then the memory element is a latch, or combinatorial > feedback creating a latch out of gates. > > The easiest, surest way to avoid latches is to, for all combinatorial > processes, include default assignments to all outputs ever driven by > the process, right up front, before anything else. That way there are > no execution paths through the process that avoid the assignments. > > Of course, if you can avoid combinatorial processes altogether, then > you won't get latches in the first place. But sometimes =A0you just > can't avoid a combinatorial process. > > This same "remembering" analogy also governs whether a reference to a > variable in a clocked process causes a register, or just combinatorial > logic. > > Andy This was a very good, thorough, and correct explanation. In every possible execution path through a combinatorial process, the outputs of that process MUST be assigned to avoid latches. Like Andy said, the easiest is to initialize everything upfront: process(KEY, R, sigSW, co0) begin -- all outputs assigned regardless of 'KEY' S <=3D (others =3D> '0'); LEDG8 <=3D '0'; LEDR <=3D (others =3D> '0'); -- conditional assignments now do not have to be exhaustive if(KEY =3D "00") then S <=3D to_unsigned(0,8); elsif(KEY =3D "01") then S <=3D R; LEDG8 <=3D co0(7); LEDR(15 downto 8) <=3D sigSW(15 downto 8); LEDR(7 downto 0) <=3D sigSW(7 downto 0); end if; end process; From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!v41g2000yqv.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Fri, 20 Aug 2010 22:13:00 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: <74ceb263-2a5e-467e-963b-5e0e48800081@v41g2000yqv.googlegroups.com> References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282367581 3278 127.0.0.1 (21 Aug 2010 05:13:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 05:13:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v41g2000yqv.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4057 Thanks for all of the advice, I've read this about twice so far and it's starting to become a bit more clear. My process has become more stable and I've made a minor adjustment to my 8bit adder. everything seems to be working but, 1 - R is supposed to be sent to S when KEY(1) is high, but nothing happens when I press KEY(1). But Key(0) does what KEY(1) is supposed to do. 2 - When KEY(1) and KEY(0) are pressed together, everything is cleared, the way that KEY(0) is supposed to behave when pressed by itself 3 - LEDG never lights up. I don't see why this is happening, do you? If anyone is using quartus, are there any tools that could help me figure out this problem? Like maybe a schematic of my design? ************************************** top-level.vhd ******************************************** LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity Lab1_6 is port( SW : in unsigned(15 downto 0); KEY : in unsigned(1 downto 0); LEDR : out unsigned(15 downto 0); LEDG8 : out std_logic; HEX7, HEX6, HEX5, HEX4, HEX1, HEX0 : out unsigned(6 downto 0) ); end Lab1_6; architecture behavior of Lab1_6 is signal ci0 : std_logic; signal co0 : std_logic; signal S : unsigned(7 downto 0); signal R : unsigned(7 downto 0); begin ci0 <= '0'; fa : work.full8bitadder port map(ci0, SW(15 downto 8), SW(7 downto 0), co0, R); h7 : work.HEX port map(SW(15 downto 12), HEX7); h6 : work.HEX port map(SW(11 downto 8), HEX6); h5 : work.HEX port map(SW(7 downto 4), HEX5); h4 : work.HEX port map(SW(3 downto 0), HEX4); h1 : work.HEX port map(S(7 downto 4), HEX1); h0 : work.HEX port map(S(3 downto 0), HEX0); process(KEY, SW) begin if(KEY(0) = '1') then S <= (others => '0'); LEDR <= (others => '0'); elsif(KEY(1) = '1') then S <= R; LEDG8 <= co0; LEDR(15 downto 8) <= SW(15 downto 8); LEDR(7 downto 0) <= SW(7 downto 0); else S <= (others => '0'); LEDG8 <= '0'; LEDR <= (others => '0'); S <= (others => '0'); end if; end process; end behavior; ********************************************************************************************8 Thanks, Malik From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!n11g2000yqk.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Fri, 20 Aug 2010 23:24:49 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <5cf0762e-5f1a-4151-94b4-8562ffd89385@n11g2000yqk.googlegroups.com> References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> <74ceb263-2a5e-467e-963b-5e0e48800081@v41g2000yqv.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282371889 18925 127.0.0.1 (21 Aug 2010 06:24:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 06:24:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n11g2000yqk.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4058 Here's an RTL Image. I've just looked through it and the MUXs seem fine to me... http://picpaste.com/pics/Lab1_6.1282371847.png Thanks, Malik From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!x25g2000yqj.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Fri, 20 Aug 2010 23:41:03 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> <74ceb263-2a5e-467e-963b-5e0e48800081@v41g2000yqv.googlegroups.com> <5cf0762e-5f1a-4151-94b4-8562ffd89385@n11g2000yqk.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282372863 26700 127.0.0.1 (21 Aug 2010 06:41:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 06:41:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x25g2000yqj.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4059 It turns out my KEYs are logic low. I'll have to test it when I have a chance. I'll let you know what happens! Thanks, Malik From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!f20g2000pro.googlegroups.com!not-for-mail From: niyander Newsgroups: comp.lang.vhdl Subject: need help, synthesizable vhdl Date: Sat, 21 Aug 2010 08:27:52 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> NNTP-Posting-Host: 59.95.110.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282404472 20332 127.0.0.1 (21 Aug 2010 15:27:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 15:27:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000pro.googlegroups.com; posting-host=59.95.110.109; posting-account=W-Z0OQoAAABTlmAqUoVxZybmc-jZmCQr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4060 Hi, I have written some vhdl code which uses internal multiplier present in spartan-3 device. Can someone check if this code is synthesizable, i would appreciate if someone can help me in this. I am getting desired results in simulation, but i am not sure if this code is 100% synthesizable. code:http://anceop.com/vhdl.txt Thanks From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!weretis.net!feeder4.news.weretis.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp14-2.free.fr!not-for-mail Date: Sat, 21 Aug 2010 18:00:10 +0200 Return-Path: deboutv@free.fr From: Vince Subject: Re: need help, synthesizable vhdl Message-ID: X-Priority: 3 User-Agent: NewsReader Newsgroups: comp.lang.vhdl References: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="ISO-8859-15" Lines: 12 Organization: Guest of ProXad - France NNTP-Posting-Date: 21 Aug 2010 18:00:10 MEST NNTP-Posting-Host: 78.227.109.149 X-Trace: 1282406410 news-1.free.fr 640 78.227.109.149:33115 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4061 niyander a écrit : > Hi, > > I have written some vhdl code which uses internal multiplier present > in spartan-3 device. Can someone check if this code is synthesizable, > i would appreciate if someone can help me in this. > I am getting desired results in simulation, but i am not sure if this > code is 100% synthesizable. > > code:http://anceop.com/vhdl.txt A synthesis tool will answer to your question... From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: need help, synthesizable vhdl Date: Sat, 21 Aug 2010 09:53:55 -0700 Lines: 21 Message-ID: <8daeibFifnU1@mid.individual.net> References: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net hG8kk8XJRNKiK/bqKHA9hAnstHAvfcYu0GuXSOzdsVNRBEeA9W Cancel-Lock: sha1:g/3DR+YGTn7vx8MGOWExX9cYwCc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 In-Reply-To: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4062 On 8/21/2010 8:27 AM, niyander wrote: > I have written some vhdl code which uses internal multiplier present > in spartan-3 device. Can someone check if this code is synthesizable, > i would appreciate if someone can help me in this. I would suggest nothing but reset and clock in the sensitivity list. Something like the template below. -- Mike Treseler main : process(reset, clock) is begin -- process template if reset = '1' then -- init_regs; elsif rising_edge(clock) then -- update_regs; end if; -- update_ports; end process main; end architecture synth; From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c10g2000yqi.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Sat, 21 Aug 2010 10:41:51 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> <74ceb263-2a5e-467e-963b-5e0e48800081@v41g2000yqv.googlegroups.com> <5cf0762e-5f1a-4151-94b4-8562ffd89385@n11g2000yqk.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282412511 22857 127.0.0.1 (21 Aug 2010 17:41:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 17:41:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqi.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.126 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4063 It turns out that i did need some latches, but not in the configuration I had originally used. ****************** process block **************************** process(KEY, SW) begin if(KEY(1) = '0') then S <= R; LEDG8 <= co0; LEDR(15 downto 8) <= SW(15 downto 8); LEDR(7 downto 0) <= SW(7 downto 0); elsif(KEY(0) = '0') then S <= (others => '0'); LEDR <= (others => '0'); else LEDR(15 downto 8) <= SW(15 downto 8); LEDR(7 downto 0) <= SW(7 downto 0); end if; end process; ***************************************************************************** Thanks a lot for your help guys. You're life savers :) Malik From newsfish@newsfish Fri Dec 24 22:54:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i31g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: need help, synthesizable vhdl Date: Sat, 21 Aug 2010 10:57:37 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: <46414831-f33b-4f09-b6a6-c69182049e4d@i31g2000yqm.googlegroups.com> References: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282413458 23205 127.0.0.1 (21 Aug 2010 17:57:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 21 Aug 2010 17:57:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i31g2000yqm.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4064 On Aug 21, 11:27=A0am, niyander wrote: > Hi, > > I have written some vhdl code which uses internal multiplier present > in spartan-3 device. Can someone check if this code is synthesizable, > i would appreciate if someone can help me in this. > I am getting desired results in simulation, but i am not sure if this > code is 100% synthesizable. > > code:http://anceop.com/vhdl.txt > > Thanks Synthesis tools are downloadable from the supplier's web site, consider downloading one. In both the short and long run you'll be more productive. Using Quartus, the warnings reported below (*1) represent conditions under which the logic that gets generated will *not* match simulation results. (*2) You should also consider getting rid of the first process and just use concurrent signals assignments as you did when you commented out the process portions of your second group. As a general rule you should try to not use combinatorial (i.e. non-clocked processes) they lead to design errors such as the ones being reported below as well as latches if you miss an assignment to a signal under some condition in the process. Sometimes one really likes to use statements such as 'if' and 'case' that are not available in concurrent assignment statements (such as in your last process). In those cases, if making the process clocked is not an option, then peruse the synthesis warnings for statements like the ones listed below since they are actually potential design errors waiting to trap you. Alternatively, consider implemeting your 'process' code as a function or a procedure instead. At least then any compiler will flag usage of some signal (such as 'lead0') that is not formally listed as an input parameter. Kevin Jennings (*1) Warning (10492): VHDL Process Statement warning at Junk.vhd(509): signal "lead0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Junk.vhd(511): signal "lead0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning: Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "clk" (*2) The synthesized result will behave as if 'lead0' was listed in the sensitivity list. Since it is not, then your simulation will differ if 'lead0' changes but none of the other signals does not happen to simultaneously transition. In your case, 'lead0' will change one simulation delta cycle after product_mantissa(47 or 46) changes so it won't be simultaneous. Your process for computing 'final_mantissa' will wake up because of the change in 'product_mantissa' (with a soon to be out of date value for 'lead0') but will not wake up again on the next simulation delta when 'lead0' actually gets updated. From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y32g2000prc.googlegroups.com!not-for-mail From: Pranav Pareek Newsgroups: comp.lang.vhdl Subject: Re: need help, synthesizable vhdl Date: Sun, 22 Aug 2010 10:05:54 -0700 (PDT) Organization: http://groups.google.com Lines: 63 Message-ID: <5124d57e-feb8-4f4b-abfc-a807b529a987@y32g2000prc.googlegroups.com> References: <887300f0-790c-4187-a8a1-9320aa80883b@f20g2000pro.googlegroups.com> <46414831-f33b-4f09-b6a6-c69182049e4d@i31g2000yqm.googlegroups.com> NNTP-Posting-Host: 59.95.104.217 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282496760 31714 127.0.0.1 (22 Aug 2010 17:06:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 22 Aug 2010 17:06:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y32g2000prc.googlegroups.com; posting-host=59.95.104.217; posting-account=q4WpvwoAAADnuTEFSQPsg0zyl0_s4oww User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4066 On Aug 21, 10:57=A0pm, KJ wrote: > On Aug 21, 11:27=A0am, niyander wrote: > > > Hi, > > > I have written some vhdl code which uses internal multiplier present > > in spartan-3 device. Can someone check if this code is synthesizable, > > i would appreciate if someone can help me in this. > > I am getting desired results in simulation, but i am not sure if this > > code is 100% synthesizable. > > > code:http://anceop.com/vhdl.txt > > > Thanks > > Synthesis tools are downloadable from the supplier's web site, > consider downloading one. =A0In both the short and long run you'll be > more productive. =A0Using Quartus, the warnings reported below (*1) > represent conditions under which the logic that gets generated will > *not* match simulation results. (*2) > > You should also consider getting rid of the first process and just use > concurrent signals assignments as you did when you commented out the > process portions of your second group. =A0As a general rule you should > try to not use combinatorial (i.e. non-clocked processes) they lead to > design errors such as the ones being reported below as well as latches > if you miss an assignment to a signal under some condition in the > process. > > Sometimes one really likes to use statements such as 'if' and 'case' > that are not available in concurrent assignment statements (such as in > your last process). =A0In those cases, if making the process clocked is > not an option, then peruse the synthesis warnings for statements like > the ones listed below since they are actually potential design errors > waiting to trap you. =A0Alternatively, consider implemeting your > 'process' code as a function or a procedure instead. =A0At least then > any compiler will flag usage of some signal (such as 'lead0') that is > not formally listed as an input parameter. > > Kevin Jennings > > (*1) > Warning (10492): VHDL Process Statement warning at Junk.vhd(509): > signal "lead0" is read inside the Process Statement but isn't in the > Process Statement's sensitivity list > Warning (10492): VHDL Process Statement warning at Junk.vhd(511): > signal "lead0" is read inside the Process Statement but isn't in the > Process Statement's sensitivity list > Warning: Design contains 1 input pin(s) that do not drive logic > =A0 =A0 =A0 =A0 Warning (15610): No output dependent on input pin "clk" > > (*2) The synthesized result will behave as if 'lead0' was listed in > the sensitivity list. =A0Since it is not, then your simulation will > differ if 'lead0' changes but none of the other signals does not > happen to simultaneously transition. =A0In your case, 'lead0' will > change one simulation delta cycle after product_mantissa(47 or 46) > changes so it won't be simultaneous. =A0Your process for computing > 'final_mantissa' will wake up because of the change in > 'product_mantissa' (with a soon to be out of date value for 'lead0') > but will not wake up again on the next simulation delta when 'lead0' > actually gets updated. Thank you ever one for your valuable comments. From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p3g2000yqp.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Not understanding what makes my code turn to latches. Date: Mon, 23 Aug 2010 00:45:47 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: References: <1b387f68-6d77-4ed2-add9-17ce3015ab56@z10g2000yqb.googlegroups.com> <42mo669spn33258va6f1bb4v90m0c0difn@4ax.com> <80bdb780-dac8-4b2d-b32a-afbb6f45cb9c@j18g2000yqd.googlegroups.com> <4b0bc0dc-52de-4ff9-abf4-12dce6efdbd3@t3g2000vbb.googlegroups.com> <74ceb263-2a5e-467e-963b-5e0e48800081@v41g2000yqv.googlegroups.com> <5cf0762e-5f1a-4151-94b4-8562ffd89385@n11g2000yqk.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282549547 30607 127.0.0.1 (23 Aug 2010 07:45:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Aug 2010 07:45:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p3g2000yqp.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4067 On 21 Aug, 18:41, laserbeak43 wrote: > It turns out that i did need some latches, but not in the > configuration I had originally used. > > ****************** process block **************************** > > =A0 =A0 =A0 =A0 process(KEY, SW) > =A0 =A0 =A0 =A0 begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(KEY(1) =3D '0') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 S <=3D R; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDG8 <=3D co0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR(15 downto 8) <=3D SW= (15 downto 8); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR(7 downto 0) <=3D SW(= 7 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif(KEY(0) =3D '0') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 S <=3D (others =3D> '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR <=3D (others =3D> '0= '); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR(15 downto 8) <=3D SW= (15 downto 8); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR(7 downto 0) <=3D SW(= 7 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end process; > > *************************************************************************= **** > > Thanks a lot for your help guys. You're life savers :) > Malik You're missing co0 and R from the sensitivity list! So simulation wont match real hardware. From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y11g2000yqm.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: Alias of two std_logic_vector elements of an array Date: Mon, 23 Aug 2010 05:00:00 -0700 (PDT) Organization: http://groups.google.com Lines: 99 Message-ID: References: <27695cf2-6a12-4c1c-b7ba-b1a8456d0ff1@g17g2000yqe.googlegroups.com> NNTP-Posting-Host: 134.102.219.52 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282564800 16466 127.0.0.1 (23 Aug 2010 12:00:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Aug 2010 12:00:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y11g2000yqm.googlegroups.com; posting-host=134.102.219.52; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; de; rv:1.9.2.8) Gecko/20100723 Ubuntu/10.04 (lucid) Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4068 On Aug 20, 2:20=A0pm, Jonathan Bromley wrote: > On Fri, 20 Aug 2010 03:19:29 -0700 (PDT), hhanff wrote: > >type sd_card_data_a is array (natural range 527 downto 0) of > >std_logic_vector(7 downto 0); > >signal sd_card_data_as : sd_card_data_a; > > >What I can do now is create an alias for a single element of the > >signal: > > >alias data_start_block_s : std_logic_vector(7 downto 0) is > >sd_card_data_as(0); > > >What I can NOT do is defining an alias that spans several elements of > >the array: > > >alias data_stuff_bytes_s =A0 =A0: std_logic_vector(15 downto 0) is > >sd_card_data_as(10 downto 9); > > No, you can't - your alias must be an array of the same > element types as were in the original array. > > >Even when I define a type for the alias: > > >type data_stuff_bytes_a is array (514 downto 513) of > >std_logic_vector(7 downto 0); > >alias data_stuff_bytes_s : data_stuff_bytes_a is sd_card_data_as(2 > >downto 1); > > Different problem here. =A0The alias must have the same > base type as the real object, I think. =A0So you would > need something like this... > > =A0 --- This one is just to reduce finger strain: > =A0 subtype byte is std_logic_vector(7 downto 0); > > =A0 --- Generalised array type > =A0 type byte_array_t is array(natural) of byte; > > =A0 --- Specialise it for your card_data array: > =A0 signal sd_card_data_as: byte_array_t(527 downto 0); > > =A0 --- Now make your alias: > =A0 alias data_stuff: byte_array_t(514 downto 513) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 is sd_card_data_as(2 downto 1); > > I *think* that will work.... no time to check. > > >Can anybody present a solution? > > You will probably find it easier to write functions > and procedures to access groups of elements of the > array. =A0For example, to read and write several > adjacent elements as if they were > a single wide vector: > > =A0 function get_Nbytes(data: byte_array_t; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 first_adrs: natural; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 num_bytes: positive) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return std_logic_vector is > =A0 =A0 variable result: > =A0 =A0 =A0 =A0 =A0std_logic_vector(8*num_bytes-1 downto 0); > =A0 begin > =A0 =A0 for i in 0 to num_bytes-1 loop > =A0 =A0 =A0 result(8*i+7 downto 8*i) :=3D data(first_adrs+i); > =A0 =A0 =A0 --- puts first address into rightmost 8 bits > =A0 =A0 end loop; > =A0 =A0 return result; > =A0 end function; > > The matching "put" procedure is left as an exercise... > -- > Jonathan Bromley Dear Jonathan! Thanks for your quick reply. You were right in all points. I implemented your advises today and exerything is fine now. The solution to your exercise ahould be: function put_Nbytes_f(data : std_logic_vector; first_adrs : natural; num_bytes : positive) return byte_array_t is variable result : byte_array_t(512 -1 downto 0); begin for i in 0 to num_bytes-1 loop result(first_adrs+i) :=3D data(8*i+7 downto 8*i); --- puts 8 bit into rightmost rightmos byte end loop; return result(num_bytes-1 downto 0); end function; end package body sd_card_spi_wrapper_pack; Yours, /h From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x25g2000yqj.googlegroups.com!not-for-mail From: sakr Newsgroups: comp.lang.vhdl Subject: Configure component inside generate block Date: Mon, 23 Aug 2010 05:53:16 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <1b29a5d1-e6ce-49a2-a086-5ead370720b4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 196.219.88.203 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282567996 9927 127.0.0.1 (23 Aug 2010 12:53:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Aug 2010 12:53:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x25g2000yqj.googlegroups.com; posting-host=196.219.88.203; posting-account=YzDk_QkAAABWN3LEAuQwC48p3Lhr_BOl User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.8.0.12) Gecko/20080208 CentOS/1.5.0.12-0.10.el4.centos Firefox/1.5.0.12 pango-text,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4069 I was trying to write a configuration declaration to certain component; when compiling that configuration, I had a warning that the Component configuration "all : myComp" applies to no component instantiation statements. This an example of how my configuration declaration looks like; direct and simple: for myArch for all : myComp use entity myLib.myComp(myCompArch); end for; end for; I could attribute the problem to the fact that the myComp is instintaited inside a generate block. genLabel : for i in 0 to i_max generate myCompInst : component myComp port map ( ... ... ... ); end generate genLabel; Just to make sure I have no typos, I moved the component instintiation outside the generate block, then compiled the configuration, and I received no errors, or warnings, and the component binding was as I expected. So, my question is how to configure a compenet, when it is instintaited inside a generate block. Best Regards, Mostafa Sakr From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4c729bc6$0$22936$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Configure component inside generate block Newsgroups: comp.lang.vhdl Date: Mon, 23 Aug 2010 18:03:18 +0200 References: <1b29a5d1-e6ce-49a2-a086-5ead370720b4@x25g2000yqj.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 67 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1282579398 news.xs4all.nl 22936 puiterl/[::ffff:195.242.97.150]:35518 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4070 sakr wrote: > I was trying to write a configuration declaration to certain > component; when compiling that configuration, I had a warning that the > Component configuration "all : myComp" applies to no component > instantiation statements. > > This an example of how my configuration declaration looks like; direct > and simple: > > for myArch > for all : myComp > use entity myLib.myComp(myCompArch); > end for; > end for; > > I could attribute the problem to the fact that the myComp is > instintaited inside a generate block. > > genLabel : for i in 0 to i_max generate > myCompInst : component myComp > port map ( > ... > ... > ... > ); > > end generate genLabel; > > Just to make sure I have no typos, I moved the component instintiation > outside the generate block, then compiled the configuration, and I > received no errors, or warnings, and the component binding was as I > expected. > > So, my question is how to configure a compenet, when it is > instintaited inside a generate block. The for-generate loop acts like an extra level of hierarchy, for configurations. So your configuration declaration should contain: for myArch for genLabel for all : myComp use entity myLib.myComp(myCompArch); end for; end for; end for; Additionally, your instantiation should be: genLabel : for i in 0 to i_max generate myCompInst : myComp port map ( ... ... ... ); end generate genLabel; So without the word "component" after "myCompInst :". -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!w30g2000yqw.googlegroups.com!not-for-mail From: Poojan Wagh Newsgroups: comp.lang.vhdl Subject: Equivalent of SystemVerilog Interface in VHDL? Date: Mon, 23 Aug 2010 11:12:45 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: <2c99f706-6e4c-44f6-9106-349d9a3af83d@w30g2000yqw.googlegroups.com> NNTP-Posting-Host: 8.19.192.12 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282587165 30871 127.0.0.1 (23 Aug 2010 18:12:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 23 Aug 2010 18:12:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w30g2000yqw.googlegroups.com; posting-host=8.19.192.12; posting-account=UH45tAoAAABAc0Vwx6sDvQQty2LC8oqk User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4071 I was wondering if VHDL-2008 (or newer) includes an equivalent of the SystemVerilog interface. From newsfish@newsfish Fri Dec 24 22:55:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Equivalent of SystemVerilog Interface in VHDL? Date: Mon, 23 Aug 2010 19:57:04 +0100 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: <2c99f706-6e4c-44f6-9106-349d9a3af83d@w30g2000yqw.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Aug 2010 18:57:12 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="4207"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NEpT1WlFY8rflsURCC2YBaFm/XsrmuQc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:IY4HEDak7/y2Qyiec8rmhGVAN88= Xref: feeder.eternal-september.org comp.lang.vhdl:4072 On Mon, 23 Aug 2010 11:12:45 -0700 (PDT), Poojan Wagh wrote: > I was wondering if VHDL-2008 (or newer) includes an > equivalent of the SystemVerilog interface. hi Poojan, No, I don't think it does. Signals of record type have always been available, and allow you to do some of the simpler things you can do with SV interfaces, but you typically need to pass them through "inout" ports which rather messes things up. There have been various discussions in the past about adding directions to individual elements of a record, but (to the best of my knowledge) that never came to anything - it doesn't sound very nice anyway. I don't think it is a good idea to be excessively envious of SV's interfaces. They look like a really good idea on the surface, and they have some very interesting potential applications, but in SV as it stands today they are so badly broken that it's pretty much impossible to do anything really creative with them. (Yes, I can hear the mumblings in the back row even now... here goes Jonathan ranting about interfaces for the Nth time.... yawn, yawn...) -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Alias of two std_logic_vector elements of an array Date: Mon, 23 Aug 2010 22:57:21 +0100 Organization: A noiseless patient Spider Lines: 80 Message-ID: References: <27695cf2-6a12-4c1c-b7ba-b1a8456d0ff1@g17g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Aug 2010 21:57:29 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="27124"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QSiA4esn/GNcst29t2RAZs/rL0MWMVeg=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:4b56yBOMA7K9/ECTZVUsXRwDnhA= Xref: feeder.eternal-september.org comp.lang.vhdl:4073 On Mon, 23 Aug 2010 05:00:00 -0700 (PDT), hhanff wrote: >The solution to your exercise ahould be: > > function put_Nbytes_f(data : std_logic_vector; > first_adrs : natural; > num_bytes : positive) > return byte_array_t is > variable result : byte_array_t(512 -1 downto 0); > begin > for i in 0 to num_bytes-1 loop > result(first_adrs+i) := data(8*i+7 downto 8*i); > --- puts 8 bit into rightmost rightmos byte > end loop; > return result(num_bytes-1 downto 0); > end function; Yes, but that's probably a little inefficient - it constructs the whole of "result" even if you use only a tiny part of it. More important, though, it has unnecessary arguments. As an example, consider mySig: byte_array_t(511 downto 0); ... --- now we update just 2 words of it mySig(5 downto 4) <= put_Nbytes(some_data, 4, 2); Note how you are tempted to repeat the "start address" on both sides. Indeed, the '4' argument to put_Nbytes doesn't really do anything useful at all, and the '2' length argument is unnecessary too. You could mightily simplify it... function to_bytes(data:std_logic_vector) return byte_array_t is constant nBytes: integer := data'length/8; variable result: byte_array_t(nBytes-1 downto 0); constant normalised: std_logic_vector(data'length-1 downto 0) := data; begin assert (data'length mod 8) = 0 report "Data should be a multiple of 8 bits" severity error; for i in 0 to nBytes-1 loop result(i) := data(8*i+7 downto 8*i); end loop; return result; end; Now you could do mySig(5 downto 4) <= to_bytes(X"CAFE"); mySig(13 downto 10) <= to_bytes(X"BAD4F00D"); Originally I was thinking, rather, of passing the target array as an out or inout argument to a procedure, so that it is passed by reference, and then having the procedure update just the necessary elements. However, this is less convenient than the function because you need two versions of the procedure - one to update a signal result, and one to update a variable [*]. And you can't call any procedure from within a function [**]. So, on balance, I like the function version better. [*] VHDL wishlist item: Some way of overloading subprograms based on the class (signal vs other things) of their arguments, so that you can write identical procedures to update signals and variables. Today you must create two procedures with different names. [**] Another VHDL wishlist item: void functions to encapsulate non-time-consuming activity whilst permitting input, output and inout arguments. Did that make it into VHDL-2008? I don't think so. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z10g2000yqb.googlegroups.com!not-for-mail From: Poojan Wagh Newsgroups: comp.lang.vhdl Subject: Re: Equivalent of SystemVerilog Interface in VHDL? Date: Tue, 24 Aug 2010 05:57:13 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <1e17a4a6-f543-4d73-9608-5cd820ebe542@z10g2000yqb.googlegroups.com> References: <2c99f706-6e4c-44f6-9106-349d9a3af83d@w30g2000yqw.googlegroups.com> NNTP-Posting-Host: 72.97.7.152 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282654633 1175 127.0.0.1 (24 Aug 2010 12:57:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Aug 2010 12:57:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z10g2000yqb.googlegroups.com; posting-host=72.97.7.152; posting-account=UH45tAoAAABAc0Vwx6sDvQQty2LC8oqk User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4074 On Aug 23, 1:57=A0pm, Jonathan Bromley wrote: > I don't think it is a good idea to be excessively > envious of SV's interfaces. =A0They look like a really > good idea on the surface, and they have some very > interesting potential applications, but in SV as it > stands today they are so badly broken that it's > pretty much impossible to do anything really > creative with them. =A0(Yes, I can hear the mumblings > in the back row even now... here goes Jonathan > ranting about interfaces for the Nth time.... > yawn, yawn...) > -- > Jonathan Bromley Apparently, I missed the last N-1 times. What's broken about SV interfaces? (Feel free to reply directly if this line of questioning is off-topic for this list.) From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Equivalent of SystemVerilog Interface in VHDL? Date: Tue, 24 Aug 2010 11:27:29 -0700 Lines: 8 Message-ID: <8dih8fF3obU1@mid.individual.net> References: <2c99f706-6e4c-44f6-9106-349d9a3af83d@w30g2000yqw.googlegroups.com> <1e17a4a6-f543-4d73-9608-5cd820ebe542@z10g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Se6e9RXAL95HW0dpDVp8EAmMmE5ChZ7CzM7HBYP8U4Gg+S98x3 Cancel-Lock: sha1:Z7uB9Sr5nnaQlxVrq66noke+vko= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 In-Reply-To: <1e17a4a6-f543-4d73-9608-5cd820ebe542@z10g2000yqb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4075 On 8/24/2010 5:57 AM, Poojan Wagh wrote: > Apparently, I missed the last N-1 times. What's broken about SV > interfaces? That was in comp.lang.verilog -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z28g2000yqh.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 02:19:18 -0700 (PDT) Organization: http://groups.google.com Lines: 69 Message-ID: NNTP-Posting-Host: 82.59.217.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282727958 31168 127.0.0.1 (25 Aug 2010 09:19:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Aug 2010 09:19:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z28g2000yqh.googlegroups.com; posting-host=82.59.217.130; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4076 Hi, Here below a stupid code to show a problem that I can't understand. I have a 8 bit register (myReg) and a clk. On each rising edge of clk a process should set myReg(0 to 1) to '0' using a for loop and another process (always on each ris. edge) set the other bits to '0' as well (remind, it's a STUPID code just for understanding). When I simulate (tried more simulators) I get zeroes on myReg(0 to 1) (ok) but U on the others (2 to 7). WHY? If I don't use the for loop (and I simply use assignments) it works. If I move the assignments done by the second process, after the end loop line of the first process it works. Thnaks Pupillo library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity user_logic is end entity user_logic; architecture myArch of user_logic is signal myReg : std_logic_vector(0 to 7); signal myClk :std_logic; begin REG_0_1_WRITE_PROC : process( myClk ) is begin if myClk'event and myClk = '1' then for index in 0 to 1 loop myReg(index)<='0'; end loop; end if; end process REG_0_1_WRITE_PROC; REG_2_7_WRITE_PROC : process( myClk ) is begin if myClk'event and myClk = '1' then myReg(2 to 7) <= (others => '0'); end if; end process REG_2_7_WRITE_PROC; gen_clkrocess begin while (true) loop myClk<='0'; wait for 5 ns; myClk<='1'; wait for 5 ns; end loop; end process; end myArch; From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 25 Aug 2010 05:16:43 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 11:24:25 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 68 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-jZ13xQkiGQTNIOQPhqkOih4vDfGTYG6XlsuV2DWcW03xJq5lPGPXz5Tw41EmPTqmRgmedA2R4uZIVMv!aTKgLhy97kPWExjzAoqwMzD5B3Znywvpe6u8stGPOIZsmRg4L8vpPrvxvAsDaMyDhEmLX9HcElkr!DVYR X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4077 On Wed, 25 Aug 2010 02:19:18 -0700 (PDT), pupillo wrote: > > >Hi, >If I don't use the for loop (and I simply use assignments) it works. >If I move the assignments done by the second process, after the end >loop line of the first process it works. > >library ieee; >use ieee.std_logic_1164.all; -- use ieee.std_logic_arith.all; -- use ieee.std_logic_unsigned.all; -- Don't use these! You don't need them for this example. -- When you need signed or unsigned types, use ieee.numeric_std; -- instead -- if myClk'event and myClk = '1' then -- If you want a rising edge detector, use this... if rising_edge(clk) -- then pathological testbenches that alternate between "H" and "1" -- won't clock your circuit when they shouldn't! Both the above defects come from following design guidelines that have been obsolete for well over 15 years. But the basic problem is that both processes drive "myreg" and without a complete analysis (especially of the loop, which could compute the loop bounds in much more complex ways) it's impossible for the compiler to detect that you have got it right (driving all the bits, exactly once each). So the language simplifies by saying that each process potentially drives all of "myreg". Solutions: (1) Drive "myreg" from exactly one process. As you confirmed, that works. It's also less verbose, and probably clearer. (2) Drive a separate signal from each process, and combine them externally myreg <= myreg_2 & myreg_1; -- from process 2 and 1 respectively (Naturally you have declared myreg_1 as 2 bits wide, etc) This involves an extra signal assignment. People will tell you that your sim runs slower, but I'll be damned if I can measure the difference in the context of a whole project. It'll certainly be faster than trying to find an obscure bug introduced by being too clever. The only problem worth mentioning is that if you use any signals from "myreg" as clocks to other logic, they will appear one delta cycle later (i.e. zero time later but in a different order from the original design) and that can cause different simulation results (race conditions) downstream. But using them as clocks would be bad design practice anyway. (3) Drive a separate signal from each process, and use an alias to rename them to "myreg" i.e. in the signal declaration section, alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; Avoids the extra delta cycle. I haven't tested this and there may be an obscure rule why an alias won't work in this situation, but I believe it should. - Brian From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!ecngs!feeder.ecngs.de!feeder.news-service.com!postnews.google.com!z10g2000yqb.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 04:42:38 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282736558 12342 127.0.0.1 (25 Aug 2010 11:42:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Aug 2010 11:42:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z10g2000yqb.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.2 (14893) 14j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4078 On Aug 25, 11:24=A0am, Brian Drummond wrote: > alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; Brian, I don't think you can do this. What then happens if you attempt to assign to myreg??? Remember that "&" is simply a function that returns a result. OTOH there may be some way to do it using aggregates. Where is Jim Lewis when you need him? :-) alias myreg : std_logic_vector(7 downto 0) is (7 =3D> myreg_2(5) ,6 =3D> myreg_2(4) , .... ad nauseam .... ,2 =3D> myreg_2(0) ,1 =3D> myreg_1(1) ,0 =3D> myreg_1(0) ); Even if it works (which I doubt) it's pretty nasty! -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.190.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!postnews.google.com!k10g2000yqa.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 08:52:18 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> NNTP-Posting-Host: 87.17.245.214 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282751538 1431 127.0.0.1 (25 Aug 2010 15:52:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Aug 2010 15:52:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000yqa.googlegroups.com; posting-host=87.17.245.214; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4079 On 25 Ago, 13:42, Jonathan Bromley wrote: > On Aug 25, 11:24=A0am, Brian Drummond wrote: > > > alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; > > Brian, I don't think you can do this. =A0What then happens > if you attempt to assign to myreg??? =A0Remember that "&" > is simply a function that returns a result. > > OTOH there may be some way to do it using aggregates. > Where is Jim Lewis when you need him? :-) > > =A0alias myreg : std_logic_vector(7 downto 0) is > =A0 =A0(7 =3D> myreg_2(5) > =A0 =A0,6 =3D> myreg_2(4) > =A0 =A0, =A0.... ad nauseam .... > =A0 =A0,2 =3D> myreg_2(0) > =A0 =A0,1 =3D> myreg_1(1) > =A0 =A0,0 =3D> myreg_1(0) ); > > Even if it works (which I doubt) it's pretty nasty! > -- > Jonathan Bromley I think that the best thing is driving all the bus within the same process, however I wonder why a compiler should try to suppose that only one process drives all the signals. It looks like going against the semantic of vhdl. From newsfish@newsfish Fri Dec 24 22:55:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 09:05:39 -0700 Lines: 20 Message-ID: <8dktahFe7tU1@mid.individual.net> References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net MV6gyE6MNU4dpS7TZRKd+gFu/PyofEk4hZkwZxJalxoiTNCxxS Cancel-Lock: sha1:rlTFGXlQDatJ5Q+BTC4Bq6qEqUY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4080 On 8/25/2010 8:52 AM, pupillo wrote: > I think that the best thing is driving all the bus within the same > process, True. > however I wonder why a compiler should try to suppose that > only one process drives all the signals. It looks like going against > the semantic of vhdl. But there is only one signal: signal myReg : std_logic_vector(0 to 7); Use use two vectors or std_ulogic for bits. It is easier to combine than slice in vhdl. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp15-2.free.fr!not-for-mail Subject: New Application Note: Multiple configuration for Altera FPGAs. From: Bert_Paris Newsgroups: comp.lang.vhdl Keywords: altera remote update multiple configuration Organization: ALSE X-Newsreader: MesNews/1.08.03.00 Date: Wed, 25 Aug 2010 18:21:56 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15"; format=flowed Content-Transfer-Encoding: 8bit Lines: 18 Message-ID: <4c754329$0$4407$426a74cc@news.free.fr> NNTP-Posting-Date: 25 Aug 2010 18:22:01 MEST NNTP-Posting-Host: 82.66.120.181 X-Trace: 1282753321 news-3.free.fr 4407 82.66.120.181:4583 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4081 Hi, After seeing a number of customers struggling with this issue, I have written a detailed ApNote showing how to implement a multiple configuration system for Altera FPGAs. The example is a Cyclone III using Active Serial mode / EPCS (on a DE0 board), but it is easily translatable to any other Altera FPGA/board. It is not complex, but getting everything right from the documentation is not absolutely obvious. The ApNote and the design files are available at the top of the list at: http://www.alse-fr.com/apnotes.php Anyone spotting a discrepancy, please let me know. Hope this helps, Bert. From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!q22g2000yqm.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 10:31:54 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> <8dktahFe7tU1@mid.individual.net> NNTP-Posting-Host: 87.17.245.214 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282757515 19716 127.0.0.1 (25 Aug 2010 17:31:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Aug 2010 17:31:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q22g2000yqm.googlegroups.com; posting-host=87.17.245.214; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4082 I think that you're right. For VHDL it'is ONE signal (even though it's a bus), thus driving one signal in two process can lead to a undefined behaviour. Pupillo On 25 Ago, 18:05, Mike Treseler wrote: > On 8/25/2010 8:52 AM, pupillo wrote: > > > I think that the best thing is driving all the bus within the same > > process, > > True. > > > however I wonder why a compiler should try to suppose that > > only one process drives all the signals. It looks like going against > > the semantic of vhdl. > > But there is only one signal: > signal myReg : std_logic_vector(0 to 7); > > Use use two vectors or std_ulogic for bits. > It is easier to combine than slice in vhdl. > > =A0 =A0 =A0-- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 19:45:38 +0100 Organization: A noiseless patient Spider Lines: 46 Message-ID: <8joa76t7os2u4p2vb8adh8nfl1jnv2p3tr@4ax.com> References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Wed, 25 Aug 2010 18:45:49 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6594"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/8PxPIJ3K6ayBkW6nzrHs+4FGgr9X5G5U=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:5owSRoCi4QhvR39zKP/FfYqNwgU= Xref: feeder.eternal-september.org comp.lang.vhdl:4083 On Wed, 25 Aug 2010 08:52:18 -0700 (PDT), pupillo wrote: >I think that the best thing is driving all the bus within the same >process, Yes. Very good for your sanity. > however I wonder why a compiler should try to suppose that >only one process drives all the signals. It looks like going against >the semantic of vhdl. Two issues here: - all the 'U' values you saw were precisely because you had two processes driving the same signa; the problem was that one process was unexpectedly driving 'U's, because..... - a 'for' loop in VHDL is "dynamically elaborated", so the for-loop range cannot be used to determine which of a set of signals the process drives. Consequently, if you drive even one bit of the vector from within that for-loop, the whole vector is driven by the process. Search the VHDL LRM for the phrase "longest static prefix" to find more detail on why this is so. The for-loop thing is often quite irritating, especially to people who use for-loops for synthesis and expect the loop to be statically unrolled. In VHDL that is not what happens. For-generate loops, on the other hand, ARE statically elaborated and you can use them to drive selected bits of a vector while leaving other bits undriven - bear in mind that the for-generate is actually constructing separate processes for each pass of the loop, and each process statically knows which part of the vector it's driving. Not so with a procedural for-loop; there's just one process, but if you use the loop counter as an index into the vector then the process doesn't know statically which bits it will drive, and must conclude that it's driving the whole vector. No easy answers, I'm afraid (apart from the sensible "just one process" advice). Most people (me included) find the LRM description of longest-static-prefix quite hard to follow, although it's very precise. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 25 Aug 2010 15:43:04 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Wed, 25 Aug 2010 21:50:47 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 17 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-i2Z/nh0aaJZ1sy4H+ZvN0CSLvs8IE2F5EnFTqAuTGJ15O1eWlwqgQcO+/530vcq7mZi1gTM5vqRAeXZ!XsL1gI5ycgNTLyqNGUX+p0rwwWk/zix0qwl0q4q/jtYdaSXGJh5jy4IAryznBF/yX7yJo+B/z6Sx!dfue X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4084 On Wed, 25 Aug 2010 04:42:38 -0700 (PDT), Jonathan Bromley wrote: >On Aug 25, 11:24 am, Brian Drummond wrote: > >> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; > >Brian, I don't think you can do this. What then happens >if you attempt to assign to myreg??? Remember that "&" >is simply a function that returns a result. I was assuming that there would only be assignments to its component parts. But my posting machine doesn't do VHDL, and my work machine isn't on the internet, so this approach remains untested (here)... - Brian From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v8g2000yqe.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Thu, 26 Aug 2010 00:15:17 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <7b340e3d-a5d4-4406-bb61-c4f9ebdab6b7@v8g2000yqe.googlegroups.com> References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> NNTP-Posting-Host: 86.111.223.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282806917 18040 127.0.0.1 (26 Aug 2010 07:15:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 26 Aug 2010 07:15:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v8g2000yqe.googlegroups.com; posting-host=86.111.223.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.2 (14893) 05j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4085 >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; > But my posting machine doesn't do VHDL, and my work machine isn't on the > internet, so this approach remains untested (here)... ModelSim won't compile it, but I haven't had time to trawl the LRM to work out exactly what to do instead. Given that "A&B" is not a reference-able thing, but rather is just the value-result of a function's execution, I don't think it will ever be possible to make that happen. Aggregates don't seem to work either. Once again, I haven't had a chance to work out precisely why, or what you could do about it. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!news.glorb.com!postnews.google.com!k10g2000yqa.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Thu, 26 Aug 2010 00:21:55 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> <7b340e3d-a5d4-4406-bb61-c4f9ebdab6b7@v8g2000yqe.googlegroups.com> NNTP-Posting-Host: 87.11.244.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282807315 13996 127.0.0.1 (26 Aug 2010 07:21:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 26 Aug 2010 07:21:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000yqa.googlegroups.com; posting-host=87.11.244.151; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4086 On 26 Ago, 09:15, Jonathan Bromley wrote: > >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; > > But my posting machine doesn't do VHDL, and my work machine isn't on th= e > > internet, so this approach remains untested (here)... > > ModelSim won't compile it, but I haven't had time to > trawl the LRM to work out exactly what to do instead. > Given that "A&B" is not a reference-able thing, but rather > is just the value-result of a function's execution, I > don't think it will ever be possible to make that happen. > > Aggregates don't seem to work either. =A0Once again, I haven't > had a chance to work out precisely why, or what you could > do about it. > -- > Jonathan Bromley OK, thanks to all, I will keep in mind your advices Pupillo From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m1g2000yqo.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Where did the Null array come from? Date: Fri, 27 Aug 2010 03:56:37 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1282906597 25737 127.0.0.1 (27 Aug 2010 10:56:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Aug 2010 10:56:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000yqo.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4087 Just wondering if this is something Ive done wrong, or if its a modelsim bug. Here is the problem code: process variable uf : ufixed(7 downto -7) := to_ufixed( 1, 7, -7); variable sf : sfixed(8 downto -7) := to_sfixed(-2, 8, -7); variable op : sfixed(17 downto -14); begin op := sf * sfixed('0' & uf); wait; end process; and here is the error: # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a literal used? # Time: 0 ps Iteration: 0 Instance: /play_tb # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf # File in use by: 113007238 Hostname: IND-JJYK03JG1 ProcessID: 9164 # Attempting to use alternate WLF file "./wlftrh7wd7". # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf # Using alternate file: ./wlftrh7wd7 # ** Fatal: (vsim-3420) Array lengths do not match. Left is 30 (15 downto -14). Right is 0 (0 downto 1 (null array)). # Time: 0 ps Iteration: 0 Process: /play_tb/line__21 File: play_tb.vhd # Fatal error in Process line__21 at play_tb.vhd line 26 If I take the type conversion out of the assignment line and have a temporary variable for just the type conversion, there is no error: temp := sfixed('0' & uf); op := sf * temp; From newsfish@newsfish Fri Dec 24 22:55:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe25.ams2.POSTED!7564ea0f!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> Subject: Re: Where did the Null array come from? Lines: 84 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5931 X-RFC2646: Format=Flowed; Original Organization: virginmedia.com Message-ID: NNTP-Posting-Date: Fri, 27 Aug 2010 15:18:58 UTC Date: Fri, 27 Aug 2010 16:18:41 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4088 Might be a bug, seems fine with default optimisation but if enable full visibility I get the same error as you (I also tried -novopt) D:\Modelsim>vsim -c -quiet test_tb Reading D:/modeltech_SE_6.6b/tcl/vsim/pref.tcl # 6.6b # vsim -c -quiet test_tb # // ModelSim SE 6.6b May 21 2010 # // # // Copyright 1991-2010 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. # // VSIM 1> vsim -quiet test_tb # vsim -quiet test_tb VSIM 2> run 1 us VSIM 3> vsim -quiet -voptargs=+acc test_tb # vsim -voptargs=+acc -quiet test_tb VSIM 4> run 1 us # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a literal used? # Time: 0 ns Iteration: 0 Instance: /test_tb # ** Fatal: (vsim-3420) Array lengths do not match. Left is 32 (17 downto -14). Right is 0 (0 downto 1 (null array)). # Time: 0 ns Iteration: 0 Process: /test_tb/line__17 File: test_ufix.vhd # Fatal error in Process line__17 at test_ufix.vhd line 22 VSIM 5> Pass it on to Mentor, if you are lucky it might still make 6.6c :-) Hans. www.ht-lab.com "Tricky" wrote in message news:873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com... > Just wondering if this is something Ive done wrong, or if its a > modelsim bug. > > Here is the problem code: > > process > variable uf : ufixed(7 downto -7) := to_ufixed( 1, 7, -7); > variable sf : sfixed(8 downto -7) := to_sfixed(-2, 8, -7); > variable op : sfixed(17 downto -14); > begin > > op := sf * sfixed('0' & uf); > wait; > end process; > > and here is the error: > > # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a > literal used? > # Time: 0 ps Iteration: 0 Instance: /play_tb > # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf > # File in use by: 113007238 Hostname: IND-JJYK03JG1 > ProcessID: 9164 > # Attempting to use alternate WLF file "./wlftrh7wd7". > # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf > # Using alternate file: ./wlftrh7wd7 > # ** Fatal: (vsim-3420) Array lengths do not match. Left is 30 (15 > downto -14). Right is 0 (0 downto 1 (null array)). > # Time: 0 ps Iteration: 0 Process: /play_tb/line__21 File: > play_tb.vhd > # Fatal error in Process line__21 at play_tb.vhd line 26 > > > If I take the type conversion out of the assignment line and have a > temporary variable for just the type conversion, there is no error: > > temp := sfixed('0' & uf); > op := sf * temp; > > From newsfish@newsfish Fri Dec 24 22:55:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!q2g2000yqq.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Fri, 27 Aug 2010 08:49:13 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <65e5e9fb-d00a-4e0a-98fe-437c7985f93e@q2g2000yqq.googlegroups.com> References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> <7b340e3d-a5d4-4406-bb61-c4f9ebdab6b7@v8g2000yqe.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282924154 20074 127.0.0.1 (27 Aug 2010 15:49:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Aug 2010 15:49:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000yqq.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4089 On Aug 26, 2:15=A0am, Jonathan Bromley wrote: > >>> alias myreg : std_logic_vector(7 downto 0) is myreg_2 & myreg_1; > > But my posting machine doesn't do VHDL, and my work machine isn't on th= e > > internet, so this approach remains untested (here)... > > ModelSim won't compile it, but I haven't had time to > trawl the LRM to work out exactly what to do instead. > Given that "A&B" is not a reference-able thing, but rather > is just the value-result of a function's execution, I > don't think it will ever be possible to make that happen. > > Aggregates don't seem to work either. =A0Once again, I haven't > had a chance to work out precisely why, or what you could > do about it. > -- > Jonathan Bromley I tend to think of aliases as just a different handle to the same object. It does not and cannot rely upon any movement of data. Thus you cannot just create an alias that is a vector of disassociated bits because those bits are not located together where a vector reference will work. Andy From newsfish@newsfish Fri Dec 24 22:55:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i13g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Fri, 27 Aug 2010 09:12:04 -0700 (PDT) Organization: http://groups.google.com Lines: 90 Message-ID: <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1282925525 31816 127.0.0.1 (27 Aug 2010 16:12:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Aug 2010 16:12:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i13g2000yqd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4090 On 27 Aug, 16:18, "HT-Lab" wrote: > Might be a bug, seems fine with default optimisation but if enable full > visibility I get the same error as you (I also tried -novopt) > > D:\Modelsim>vsim -c -quiet test_tb > Reading D:/modeltech_SE_6.6b/tcl/vsim/pref.tcl > > # 6.6b > > # vsim -c -quiet test_tb > # // =A0ModelSim SE 6.6b May 21 2010 > # // > # // =A0Copyright 1991-2010 Mentor Graphics Corporation > # // =A0 =A0 =A0 =A0 =A0 =A0 =A0All Rights Reserved. > # // > # // =A0THIS WORK CONTAINS TRADE SECRET AND > # // =A0PROPRIETARY INFORMATION WHICH IS THE PROPERTY > # // =A0OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS > # // =A0AND IS SUBJECT TO LICENSE TERMS. > # // > VSIM 1> vsim -quiet test_tb > # vsim -quiet test_tb > VSIM 2> run 1 us > VSIM 3> vsim -quiet -voptargs=3D+acc test_tb > # vsim -voptargs=3D+acc -quiet test_tb > VSIM 4> run 1 us > # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a litera= l used? > # =A0 =A0Time: 0 ns =A0Iteration: 0 =A0Instance: /test_tb > # ** Fatal: (vsim-3420) Array lengths do not match. Left is 32 (17 downto= -14). > Right is 0 (0 downto 1 (null array)). > # =A0 =A0Time: 0 ns =A0Iteration: 0 =A0Process: /test_tb/line__17 File: t= est_ufix.vhd > # Fatal error in Process line__17 at test_ufix.vhd line 22 > VSIM 5> > > Pass it on to Mentor, if you are lucky it might still make 6.6c :-) > > Hans.www.ht-lab.com > > "Tricky" wrote in message > > news:873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com... > > > Just wondering if this is something Ive done wrong, or if its a > > modelsim bug. > > > Here is the problem code: > > > process > > =A0 =A0variable uf : ufixed(7 downto =A0 -7) :=3D to_ufixed( 1, 7, -7); > > =A0 =A0variable sf : sfixed(8 downto =A0 -7) :=3D to_sfixed(-2, 8, -7); > > =A0 =A0variable op : sfixed(17 downto -14); > > =A0begin > > > =A0 =A0op :=3D sf * sfixed('0' & uf); > > =A0wait; > > =A0end process; > > > and here is the error: > > > # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a > > literal used? > > # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Instance: /play_tb > > # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf > > # =A0 =A0 =A0 =A0 =A0 File in use by: 113007238 =A0Hostname: IND-JJYK03= JG1 > > ProcessID: 9164 > > # =A0 =A0 =A0 =A0 =A0 Attempting to use alternate WLF file "./wlftrh7wd= 7". > > # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf > > # =A0 =A0 =A0 =A0 =A0 Using alternate file: ./wlftrh7wd7 > > # ** Fatal: (vsim-3420) Array lengths do not match. Left is 30 (15 > > downto -14). Right is 0 (0 downto 1 (null array)). > > # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Process: /play_tb/line__21 File: > > play_tb.vhd > > # Fatal error in Process line__21 at play_tb.vhd line 26 > > > If I take the type conversion out of the assignment line and have a > > temporary variable for just the type conversion, there is no error: > > > temp :=3D sfixed('0' & uf); > > =A0 =A0op :=3D sf * temp; > > Its a confirmed bug - Defect report raised. That makes 3 outstanding for me! From newsfish@newsfish Fri Dec 24 22:55:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL simple process - loop problem Date: Fri, 27 Aug 2010 17:41:41 +0100 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <71q976p891tlpq2mj58lmv0nfah2qqn7k8@4ax.com> <7b340e3d-a5d4-4406-bb61-c4f9ebdab6b7@v8g2000yqe.googlegroups.com> <65e5e9fb-d00a-4e0a-98fe-437c7985f93e@q2g2000yqq.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Aug 2010 16:41:44 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="11426"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18mXjh0Ewg0L53tpRBCt7awuA0NzpmHSIw=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:qkQRr/KZGx1pYz5aPGjXx5Pz+B4= Xref: feeder.eternal-september.org comp.lang.vhdl:4091 On Fri, 27 Aug 2010 08:49:13 -0700 (PDT), Andy wrote: >you cannot just create an alias that is a vector of disassociated bits >because those bits are not located together where a vector reference >will work. Agreed, that makes perfect sense, and I've no doubt it's what actually happens. _A_fortiori_ you can't alias to the value (result) of an expression, such as A&B. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!l32g2000prn.googlegroups.com!not-for-mail From: kjkjkjk Newsgroups: comp.lang.vhdl Subject: Looking Donors for world wide Date: Sat, 28 Aug 2010 12:31:31 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: NNTP-Posting-Host: 111.119.166.219 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283023892 11410 127.0.0.1 (28 Aug 2010 19:31:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 28 Aug 2010 19:31:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000prn.googlegroups.com; posting-host=111.119.166.219; posting-account=o82hPgoAAADSkq3L_r8wm3_N8E17WPWh User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4093 Looking Donors for world wide http://fatimaz-foundation-ngo.blogspot.com From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4c7ae536$0$22920$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Where did the Null array come from? Newsgroups: comp.lang.vhdl Date: Mon, 30 Aug 2010 00:54:45 +0200 References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 12 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1283122486 news.xs4all.nl 22920 puiterl/[::ffff:195.242.97.150]:45545 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4094 Tricky wrote: > Its a confirmed bug - Defect report raised. > > That makes 3 outstanding for me! And sadly 13 for me... -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!l20g2000yqe.googlegroups.com!not-for-mail From: bybell Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: gtkwave 3.3.12 is available Date: Mon, 30 Aug 2010 12:19:25 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <34ddf724-b33a-4f58-a358-ed30f0ef7599@5g2000yqz.googlegroups.com> NNTP-Posting-Host: 129.33.49.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283195965 13971 127.0.0.1 (30 Aug 2010 19:19:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Aug 2010 19:19:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqe.googlegroups.com; posting-host=129.33.49.251; posting-account=v6D4ZAkAAAATVRs0rkKAnftIlV5GVUb8 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.9) Gecko/20100315 (CK-IBM) Firefox/3.5.9 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:2522 comp.lang.vhdl:4096 New for 3.3.12 is better feature parity between the MinGW (Windows) and Linux versions in areas dealing with creation of external processes. Windows now supports process and transaction filters. -Tony From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s15g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 00:17:24 -0700 (PDT) Organization: http://groups.google.com Lines: 114 Message-ID: <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283239044 29944 127.0.0.1 (31 Aug 2010 07:17:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 07:17:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s15g2000yqm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4097 On 27 Aug, 17:12, Tricky wrote: > On 27 Aug, 16:18, "HT-Lab" wrote: > > > > > Might be a bug, seems fine with default optimisation but if enable full > > visibility I get the same error as you (I also tried -novopt) > > > D:\Modelsim>vsim -c -quiet test_tb > > Reading D:/modeltech_SE_6.6b/tcl/vsim/pref.tcl > > > # 6.6b > > > # vsim -c -quiet test_tb > > # // =A0ModelSim SE 6.6b May 21 2010 > > # // > > # // =A0Copyright 1991-2010 Mentor Graphics Corporation > > # // =A0 =A0 =A0 =A0 =A0 =A0 =A0All Rights Reserved. > > # // > > # // =A0THIS WORK CONTAINS TRADE SECRET AND > > # // =A0PROPRIETARY INFORMATION WHICH IS THE PROPERTY > > # // =A0OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS > > # // =A0AND IS SUBJECT TO LICENSE TERMS. > > # // > > VSIM 1> vsim -quiet test_tb > > # vsim -quiet test_tb > > VSIM 2> run 1 us > > VSIM 3> vsim -quiet -voptargs=3D+acc test_tb > > # vsim -voptargs=3D+acc -quiet test_tb > > VSIM 4> run 1 us > > # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a lite= ral used? > > # =A0 =A0Time: 0 ns =A0Iteration: 0 =A0Instance: /test_tb > > # ** Fatal: (vsim-3420) Array lengths do not match. Left is 32 (17 down= to -14). > > Right is 0 (0 downto 1 (null array)). > > # =A0 =A0Time: 0 ns =A0Iteration: 0 =A0Process: /test_tb/line__17 File:= test_ufix.vhd > > # Fatal error in Process line__17 at test_ufix.vhd line 22 > > VSIM 5> > > > Pass it on to Mentor, if you are lucky it might still make 6.6c :-) > > > Hans.www.ht-lab.com > > > "Tricky" wrote in message > > >news:873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com... > > > > Just wondering if this is something Ive done wrong, or if its a > > > modelsim bug. > > > > Here is the problem code: > > > > process > > > =A0 =A0variable uf : ufixed(7 downto =A0 -7) :=3D to_ufixed( 1, 7, -7= ); > > > =A0 =A0variable sf : sfixed(8 downto =A0 -7) :=3D to_sfixed(-2, 8, -7= ); > > > =A0 =A0variable op : sfixed(17 downto -14); > > > =A0begin > > > > =A0 =A0op :=3D sf * sfixed('0' & uf); > > > =A0wait; > > > =A0end process; > > > > and here is the error: > > > > # ** Error: :floatfixlib:fixed_pkg: Unbounded number passed, was a > > > literal used? > > > # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Instance: /play_tb > > > # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf > > > # =A0 =A0 =A0 =A0 =A0 File in use by: 113007238 =A0Hostname: IND-JJYK= 03JG1 > > > ProcessID: 9164 > > > # =A0 =A0 =A0 =A0 =A0 Attempting to use alternate WLF file "./wlftrh7= wd7". > > > # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf > > > # =A0 =A0 =A0 =A0 =A0 Using alternate file: ./wlftrh7wd7 > > > # ** Fatal: (vsim-3420) Array lengths do not match. Left is 30 (15 > > > downto -14). Right is 0 (0 downto 1 (null array)). > > > # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Process: /play_tb/line__21 Fil= e: > > > play_tb.vhd > > > # Fatal error in Process line__21 at play_tb.vhd line 26 > > > > If I take the type conversion out of the assignment line and have a > > > temporary variable for just the type conversion, there is no error: > > > > temp :=3D sfixed('0' & uf); > > > =A0 =A0op :=3D sf * temp; > > Its a confirmed bug - Defect report raised. > > That makes 3 outstanding for me! Apparently it might not be a modelsim bug. Here is their latest response: I had a few suspicions about this error, so first wanted to check with R&D before raising any DR. Here is what they said about the error: >>>> This is definitely not a ModelSim implementation issue. The fixed package uses array indexes in a critical way. uf has indexes 7 downto -7. When you concatenate a '0' to the left of this value you get the correct bit pattern, but the wrong index values. specifically, you do not get 8 downto -7. The workaround is OK because it takes the desired bit pattern, and assigns it to a variable which has the correct index values. <<<< BTW, I should add this is a shortcoming in the fixed package. From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 08:45:06 +0100 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 Aug 2010 07:45:14 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="21332"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/YcFEgEh3uyW4B0eSPo/ovHICLBIpbGIw=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:+Q0Wg97AEE/6lYoH9sVaWlWFGHs= Xref: feeder.eternal-september.org comp.lang.vhdl:4098 On Tue, 31 Aug 2010 00:17:24 -0700 (PDT), Tricky wrote: [from Mentor] > The fixed package uses array indexes in a critical way. >uf has indexes 7 downto -7. >When you concatenate a '0' to the left of this value you get the >correct bit pattern, but the wrong index values. specifically, you do >not get 8 downto -7. >The workaround is OK because it takes the desired bit pattern, and >assigns it to a variable which has the correct index values. [Tricky] >BTW, I should add this is a shortcoming in the fixed package. I agree; I was under the impression that all the FP operators complain if given arrays with the wrong range direction. You could work around it without the temporary variable, by using a subtype to do the conversion: subtype sfix9f7 is sfixed(8 downto -7); .. op := sf * sfix9f7('0' & uf); Now the constrained subtype sfix9f7 coerces the result to have the right array range. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.41.MISMATCH!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feeder3.cambriumusenet.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!x25g2000yqj.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Did VHDL-2008 get lost ? Date: Tue, 31 Aug 2010 06:51:55 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283262718 24012 127.0.0.1 (31 Aug 2010 13:51:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 13:51:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x25g2000yqj.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4099 http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/38842723232ac99/bd632ce31865faf9?lnk=gst&q=VHDL-2008#bd632ce31865faf9 http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/5bc5e269ca718480/98a26bf8abc952dc?lnk=gst&q=VHDL2008#98a26bf8abc952dc Are there any news on VHDL-2008 ? Whether simulation nor synthesis tools do support it considerably. Do we users have to draw some kind of chain letter to convince Mentor, Aldec, Synplicity etc. ? Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f6g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 08:28:02 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283268487 18056 127.0.0.1 (31 Aug 2010 15:28:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 15:28:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f6g2000yqa.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4100 On Aug 31, 2:45=A0am, Jonathan Bromley wrote: > On Tue, 31 Aug 2010 00:17:24 -0700 (PDT), Tricky wrote: > >BTW, I should add this is a shortcoming in the fixed package. > > I agree; I was under the impression that all the FP operators > complain if given arrays with the wrong range direction. Am I missing something? op :=3D sf * to_sfixed(uf); to_sfixed() automatically pads the ufixed with the sign bit for you, and it is much more readable. Before assuming the package has a shortcoming, make sure you know (and use) what's already available in the package. The concatenation result range issue is with vhdl, not fixed point. Avoid concatenating fixed point values. Andy From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!tudelft.nl!txtfeed1.tudelft.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!s15g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Tue, 31 Aug 2010 09:07:48 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283270868 5562 127.0.0.1 (31 Aug 2010 16:07:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 16:07:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s15g2000yqm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4101 On 31 Aug, 14:51, hssig wrote: > http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/38... > > http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/5b... > > Are there any news on VHDL-2008 ? > Whether simulation nor synthesis tools do support it considerably. Do > we users have to draw some kind of chain letter to convince Mentor, > Aldec, Synplicity etc. ? > > Cheers, > hssig Altera started to support VHDL 2008 features in Quartus 9.1, but these are mostly syntactical support (no built in fixed point library yet, not even in Q10) But the big problem is Mentor. Without their support, 2008 wont be used much for a while, especially as modelsim is the altera simulator of choice (given its what altera bundle with quartus). I thought ActiveHDL was supports 2008? From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i4g2000prf.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Tue, 31 Aug 2010 09:23:53 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 98.246.140.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283271833 13709 127.0.0.1 (31 Aug 2010 16:23:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 16:23:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i4g2000prf.googlegroups.com; posting-host=98.246.140.7; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4102 Hi Hssig, > Are there any news on VHDL-2008 ? > Whether simulation nor synthesis tools do support it considerably. Do > we users have to draw some kind of chain letter to convince Mentor, > Aldec, Synplicity etc. ? I think letters are always a good idea as they help vendors assign priority to tasks they are working on. As a result, be sure to prioritize the features that mean something to you. OTOH, I think the 3 you mentioned have been actively working on their implementation of VHDL-2008. You can see evidence of this in their documentation. In release 10.0, Altera mentions VHDL-2008. Xilinx does not seem to mention implementing anything in VHDL-2008 other than the fixed and floating point packages. It would be better to test things out rather than relying on documentation. I have some of my and David Bishop's examples that I intend to load so that people can do that. Again, letters will encourage them further and help them justify their investment into the language. Best, Jim SynthWorks VHDL Training From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe27.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> Subject: Re: Did VHDL-2008 get lost ? Lines: 45 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5931 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe27.ams2 1283272747 213.105.6.183 (Tue, 31 Aug 2010 16:39:07 UTC) NNTP-Posting-Date: Tue, 31 Aug 2010 16:39:07 UTC Organization: virginmedia.com Date: Tue, 31 Aug 2010 17:38:56 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4103 "Tricky" wrote in message news:dedab77c-f7ca-47df-ae81-7c26cd0c542a@s15g2000yqm.googlegroups.com... > On 31 Aug, 14:51, hssig wrote: >> http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/38... >> >> http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/5b... >> >> Are there any news on VHDL-2008 ? >> Whether simulation nor synthesis tools do support it considerably. Do >> we users have to draw some kind of chain letter to convince Mentor, >> Aldec, Synplicity etc. ? >> >> Cheers, >> hssig > > Altera started to support VHDL 2008 features in Quartus 9.1, but these > are mostly syntactical support (no built in fixed point library yet, > not even in Q10) > > But the big problem is Mentor. Without their support, 2008 wont be > used much for a while, especially as modelsim is the altera simulator > of choice (given its what altera bundle with quartus). The problem here is not just Mentor, I have been told on several occasions that Mentor gets very few VHDL2008 request so the lack of support is partly(?) our fault! I also believe that a contributing factor is that Mentor underestimates the number of VHDL users and perhaps more worrying they believe we are all slowly migrating to SystemVerilog...... If you are using VHDL and you are paying maintenance then let Mentor know you want VHDL2008 support!! It only takes a minute, go to your supportnet page, raise an SR and say you want VHDL2008 support. Alternatively, email your distributor and say can I have VHDL2008 support in Modelsim 6.7 please! > > I thought ActiveHDL was supports 2008? > Yes they do for more than a year now. Hans www.ht-lab.com From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 17:50:58 +0100 Organization: A noiseless patient Spider Lines: 38 Message-ID: References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Aug 2010 16:51:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="4736"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+RrTyHp3FDVvTfaXLYFNbiSAXwbjQ+4Ak=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:msVHXr2LCVTJjRaIBTeMMo8ZrQA= Xref: feeder.eternal-september.org comp.lang.vhdl:4104 On Tue, 31 Aug 2010 08:28:02 -0700 (PDT), Andy wrote: >On Aug 31, 2:45 am, Jonathan Bromley wrote: >> I was under the impression that all the FP operators >> complain if given arrays with the wrong range direction. >Am I missing something? > op := sf * to_sfixed(uf); >to_sfixed() automatically pads the ufixed with the sign bit for you, >and it is much more readable Whoops, that'll teach me not to discuss things I don't use actively. Didn't know that, thanks Andy. Yes, of course that's the right way to get that effect. >Before assuming the package has a shortcoming, make sure you know (and >use) what's already available in the package. The concatenation result >range issue is with vhdl, not fixed point. That's a bit harsh. Since the FP package absolutely requires that vector ranges all be "downto", and the language cannot enforce that, it's kinda disappointing that the package doesn't assert the check whenever it gets the chance. The concat rules are indeed weird, but it's hard to see what the language could have done to make them better in ALL useful cases. > Avoid concatenating fixed point values. Probably very good advice, but not as important as ** avoid using VHDL assignment to copy ** ** one fixed-point vector into another ** violation of which simply gives wrong answers, with no possibility whatsoever of any checking. Thanks again -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!f42g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 10:49:16 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <51484e47-6989-4f9d-ac79-53e0ec5499de@f42g2000yqn.googlegroups.com> References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283276956 24928 127.0.0.1 (31 Aug 2010 17:49:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Aug 2010 17:49:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f42g2000yqn.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4105 Just like other operators, the language could have chosen a specific range result based on the operands (like extending the range of the largest operand, or if equal, picking L or R consistently). Instead, it defaults to something not particularly useful for any application. I suspect the original authors did not expect that indices would be used for specific purposes as in the fixed and floating point languages. The fixed point user guide says: 'A negative or =93to=94 index is flagged as an error by the fixed-point routines. Thus, if you define a number as =93ufixed (1 to 5)=94 the routines will automatically error out.' Apparently that did not make it into the package? BTW, surely this was not intended to prevent usage of e.g. ufixed(-4 downto -7)? The only way to fix the assignment issue is to add overloaded assignment operators to the language, which IMHO should have been added a long time ago. In the meantime, it would be beneficial to get into the habit of always using resize() prior to assignment. op :=3D resize(sf * to_sfixed(uf), op); Since op might be the right size, while not of the right "shape". Andy From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Where did the Null array come from? Date: Tue, 31 Aug 2010 19:04:18 +0100 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <873cd548-dd7f-4188-b9f0-f33a900c2ae0@m1g2000yqo.googlegroups.com> <8d1ef150-24b0-4912-93bb-b1f0aba33065@i13g2000yqd.googlegroups.com> <81f5f707-890a-424e-b6f9-c2b483fa645d@s15g2000yqm.googlegroups.com> <51484e47-6989-4f9d-ac79-53e0ec5499de@f42g2000yqn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Aug 2010 18:04:26 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="30724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Oq2ELJPQmNRU1t+6MNyJ53Qd3muLjcXQ=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:uIk7XFzGtJauKbOExzAAjyLCbqM= Xref: feeder.eternal-september.org comp.lang.vhdl:4106 On Tue, 31 Aug 2010 10:49:16 -0700 (PDT), Andy wrote: >The fixed point user guide says: >'A negative or “to” index is flagged as an error by the fixed-point >routines. Thus, if you define a number as “ufixed (1 to 5)” the >routines will automatically error out.' Yes, I thought I had a folk-memory of something like that. >Apparently that did not make it into the package? Maybe it's been taken out of some versions for performance reasons? The problem, of course, is that an assertion on every function call is likely to perform very many redundant checks. On the other hand it's a pretty cheap check, so I would still prefer to see it in place. >BTW, surely this was not intended to prevent usage of >e.g. ufixed(-4 downto -7)? I guess that's a documentation slip-up. >The only way to fix the assignment issue is to add overloaded >assignment operators to the language, which IMHO should have been >added a long time ago. Couldn't agree with you more; I've even put in a request for exactly that. >In the meantime, it would be beneficial to get >into the habit of always using resize() prior to assignment. > op := resize(sf * to_sfixed(uf), op); That was a brilliant trick of Dave Bishop's, to add the "shape-only" argument to resize(). Much nicer to use than the copy procedures that I created when I did a FP package... copyV(variable_target, source); copyS(signal_target, source); Apart from the syntactic clumsiness, their being procedures precludes their use in a function. (Cue complaint #N+1 about VHDL: we need void-functions with output arguments, like procedures but not time-consuming). Ah me. You got me all wound up again.... sorry! -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.mixmin.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Charles Gardiner Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Tue, 31 Aug 2010 23:00:03 +0200 Organization: T-Online Lines: 16 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1283288404 00 n27265 ErstBLHrAhtbSCEp 100831 21:00:04 X-Complaints-To: usenet-abuse@t-online.de X-ID: TtBeqTZareU5v8kxCVKqNMzm2IwEfrpwZB9u1ScqOOubUD6d027zrg User-Agent: Thunderbird 2.0.0.23 (X11/20090817) In-Reply-To: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4107 hssig schrieb: > http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/38842723232ac99/bd632ce31865faf9?lnk=gst&q=VHDL-2008#bd632ce31865faf9 > > http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/5bc5e269ca718480/98a26bf8abc952dc?lnk=gst&q=VHDL2008#98a26bf8abc952dc > > > Are there any news on VHDL-2008 ? > Whether simulation nor synthesis tools do support it considerably. Do > we users have to draw some kind of chain letter to convince Mentor, > Aldec, Synplicity etc. ? > > Cheers, > hssig Aldec Riviera already supports it pretty well. I'm slowly migrating whereever it makes sense and haven't encountered any difficulties so far. From newsfish@newsfish Fri Dec 24 22:55:05 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!o7g2000prg.googlegroups.com!not-for-mail From: vipin lal Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 1 Sep 2010 01:08:48 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 117.206.12.126 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283328528 32408 127.0.0.1 (1 Sep 2010 08:08:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Sep 2010 08:08:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o7g2000prg.googlegroups.com; posting-host=117.206.12.126; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4108 Is it possible to create some vote/public letter to convince Mentor, Aldec and Synplicity. The VHDL-2008 language develop team can start such a public voting so that people can show that they want VHDL-2008 support. It will be much easier this way than individually mailing the above three. just wondering,is it possible? From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!g17g2000yqe.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 1 Sep 2010 02:46:21 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <11620a4c-f0b2-4254-8c28-ebab7ba7f359@g17g2000yqe.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283334382 16071 127.0.0.1 (1 Sep 2010 09:46:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Sep 2010 09:46:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g17g2000yqe.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4109 On 1 Sep., 10:08, vipin lal wrote: > Is it possible to create some vote/public letter to convince Mentor, > Aldec and Synplicity. > The VHDL-2008 language develop team can start such a public voting so > that people can show that they want VHDL-2008 support. It will be much > easier this way than individually mailing the above three. > > just wondering,is it possible? Excellent idea. Anybody participating in that voting should indicate her/his function, VHDL affiliation and tool, I think Mentor is the first vendor to push. Of course anybody participating should outline the most important features to be supported. There should be more public courses offered. In Germany for example there would be much interest in seeing those courses for VHDL-2008. Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!l6g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 1 Sep 2010 05:52:34 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283345554 11732 127.0.0.1 (1 Sep 2010 12:52:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Sep 2010 12:52:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000yqb.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4110 On Sep 1, 4:08=A0am, vipin lal wrote: > Is it possible to create some vote/public letter to convince Mentor, > Aldec and Synplicity. That vote already occurred. The vote was when the standard was approved. Mentor and other companies are represented on that public forum and are participants in the standards development process. > The VHDL-2008 language develop team can start such a public voting so > that people can show that they want VHDL-2008 support. Petitions are easy and in this case likely to be ineffective. Simply contact Mentor (and others) directly through their support page and request implementation of whatever VHDL-2008 features you need the most and ask them when they're scheduling release of full VHDL-2008. To gather public interest that might be similar to yours, simply take whatever you've posted with Mentor and whatever their response is to this group as well. That may spur others to do so similar requests. > It will be much > easier this way than individually mailing the above three. > I seriously doubt some public vote would be easier than directly contacting a few companies. I also doubt that it would be effective. The power of stating "company xyz's tool supports this feature" is also a useful prod since it potentially is lost revenue then to a competitor if they can't say they have the feature also. > just wondering,is it possible? Sure...many things are possible. KJ From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!z7g2000yqg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 1 Sep 2010 06:22:08 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <1514034b-c57d-4e17-8452-d6a47d9cc514@z7g2000yqg.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283347329 13345 127.0.0.1 (1 Sep 2010 13:22:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Sep 2010 13:22:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z7g2000yqg.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4111 On Sep 1, 7:52=A0am, KJ wrote: > The power of stating "company xyz's tool supports this feature" is > also a useful prod since it potentially is lost revenue then to a > competitor if they can't say they have the feature also. This has always been my most effective means of getting a vendor to support a language capability. Andy From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe22.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> Subject: Re: Did VHDL-2008 get lost ? Lines: 62 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5931 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe22.ams2 1283348423 213.105.6.183 (Wed, 01 Sep 2010 13:40:23 UTC) NNTP-Posting-Date: Wed, 01 Sep 2010 13:40:23 UTC Organization: virginmedia.com Date: Wed, 1 Sep 2010 14:40:15 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4112 I agree with KJ, as I wrote before, raising an SR (by maintenance paying customers) is more effective than a petition since the only thing that counts is $$$. I just spoke to a Mentor engineer and there is some good, bad and worrying news. The good news is that Modelsim 6.7 (expected around Xmas) will have additional VHDL-2008 support including "case with don't cares", "simplified conditional expression (if , ?(=,<,....)", "Array/Scalar Logic Operators" to name a few. The bad news is that some constructs are not expected until 6.8 (2012?) such as "generic types on packages" but the worrying one is that constructs like "simplified case statements", "slices in array aggregates" and "conditional and selected assignment in sequential code" have no release date at all. Of course this is all subject to change! So if you raise an SR you might want to ask for some of the none-release date constructs :-) Hans www.ht-lab.com "KJ" wrote in message news:57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com... On Sep 1, 4:08 am, vipin lal wrote: > Is it possible to create some vote/public letter to convince Mentor, > Aldec and Synplicity. That vote already occurred. The vote was when the standard was approved. Mentor and other companies are represented on that public forum and are participants in the standards development process. > The VHDL-2008 language develop team can start such a public voting so > that people can show that they want VHDL-2008 support. Petitions are easy and in this case likely to be ineffective. Simply contact Mentor (and others) directly through their support page and request implementation of whatever VHDL-2008 features you need the most and ask them when they're scheduling release of full VHDL-2008. To gather public interest that might be similar to yours, simply take whatever you've posted with Mentor and whatever their response is to this group as well. That may spur others to do so similar requests. > It will be much > easier this way than individually mailing the above three. > I seriously doubt some public vote would be easier than directly contacting a few companies. I also doubt that it would be effective. The power of stating "company xyz's tool supports this feature" is also a useful prod since it potentially is lost revenue then to a competitor if they can't say they have the feature also. > just wondering,is it possible? Sure...many things are possible. KJ From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!h19g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 1 Sep 2010 06:56:51 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283349411 29591 127.0.0.1 (1 Sep 2010 13:56:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Sep 2010 13:56:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h19g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4113 I think I got the same copy/paste reply, 5 mins after raising the support request. It is all marked as a "tentative" release schedule: Read out ports Targeted release: 6.7 Simplified Case Statements Targeted release: No target release at this time. Case with don't care (-) Targeted release: 6.7 Simplified conditional expression (if , ?(=,<,....) Targeted release: 6.7 Expressions in port maps Questa/ModelSim supports conv funcs, globally static expressions in port maps today. Targeted release: 6.7 (remaining functionality). Conditional and Selected assignment in sequential code Targeted release: Questa/ModelSim still investigating Unary Reduction Operators Partial support in Questa/ModelSim today. std_ulogic_vector is not yet supported. Targeted release: 6.7 (std_ulogic_vector). Array/Scalar Logic Operators Partial support in Questa/ModelSim today. std_ulogic_vector is not yet supported. Targeted release: 6.7 (std_ulogic_vector). Slices in array aggregates Targeted release: No target release at this time. Source code encryption Supported today in Questa/ModelSim. Fixed Point Packages Questa/ModelSim supports the non-generic version of the packages in 6.5. Targeted release: 6.8 (requires generic type capability). generic type Targeted release: 6.8. From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.osn.de!diablo1.news.osn.de!ecngs!feeder.ecngs.de!feeder.news-service.com!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Thu, 2 Sep 2010 05:14:54 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <36d34872-b458-4fb1-8278-d86ecb001b4b@e14g2000yqe.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283429694 27551 127.0.0.1 (2 Sep 2010 12:14:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Sep 2010 12:14:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4114 KJ wrote: >Simply contact Mentor (and others) directly through their support page and >request implementation of whatever VHDL-2008 features you need Here we go round in circles, I mean before I am not able to try a new feature out I can whether assess it nor request it rationally. Or I request all features and try them out afterwards. Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!postnews.google.com!j18g2000yqd.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Mon, 6 Sep 2010 01:31:18 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <473049b2-31b5-44b3-ac3f-215775049b89@j18g2000yqd.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> <36d34872-b458-4fb1-8278-d86ecb001b4b@e14g2000yqe.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283761878 24483 127.0.0.1 (6 Sep 2010 08:31:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Sep 2010 08:31:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000yqd.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4115 Some additional info to Tricky's road map (from answer to my support request) : * Modelsim 6.8 will see full VHDL-2008 support * Modelsim 6.7 will be available end of this year. * Support of process(ALL) in ModelSim 6.7, maybe 6.8 * "The point is that one of the several essential factors that can prioritize the implementation of such enhancement requests implies the number of customers that requested these. That is why any feedback on this matter is appreciated so we can continually improve the quality of our releases." Cheers, Heinze From newsfish@newsfish Fri Dec 24 22:55:06 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k10g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Extracting type - Not possible or would it be useful in a future standard? Date: Tue, 7 Sep 2010 01:42:08 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <8e2bc19f-867d-4b34-ab89-9d16f3a697aa@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283848928 3609 127.0.0.1 (7 Sep 2010 08:42:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Sep 2010 08:42:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4116 I have just come across a situation where it might be beneficial to return the type of something so another type can be created. For example: I have this type defined in a package. type rec_t is record num : ufixed(7 downto 0); end record rec; type rec_array_t is array(integer range <>) of rec_t; then in a design file I want to create an array. The purpose of this array is simply to extract the "num" elements from a rec_array_t. At the moment I have to define: type local_array_t is array(integer range <>) of ufixed(rec_t.num'range); the problem comes when the "num" element is changed from a ufixed to a sfixed. I then have to manually redefine the local_array_t to cope with the type change. Am I overthinking a problem that might be worked around with a function (and by-passing the need for a local_array_t) or would this prove useful in the language? From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Extracting type - Not possible or would it be useful in a future standard? Date: Tue, 7 Sep 2010 07:13:43 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <2a09e5a6-5c5a-41ed-a907-b58dfa8251ac@e14g2000yqe.googlegroups.com> References: <8e2bc19f-867d-4b34-ab89-9d16f3a697aa@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283868823 32050 127.0.0.1 (7 Sep 2010 14:13:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Sep 2010 14:13:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4117 Just shooting from the hip, but I suppose you already tried: type local_array_t is array(integer range <>) of rec_t.num; One would think that 'base should be usable for this, but the spec clearly says that the attribute is only usable as a prefix for another attribute. Still seems like a reasonable enhancement request, especially if the above does not work (not sure why they limited 'base to use as a prefix in the first place). As a work-around, if you defined a named subtype for use in the record definition, and referenced that subtype in the local array definition, that would solve your problem. Then you could change the base type of the subtype definition, and both the record and the local array would be updated. Andy From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!b34g2000yqm.googlegroups.com!not-for-mail From: "Dr. Giovanni Squillero" Newsgroups: comp.lang.vhdl Subject: CFP: EvoHOT 2011 Date: Tue, 7 Sep 2010 10:32:17 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <8bc871cf-6b88-43b1-804f-03effd423f6e@b34g2000yqm.googlegroups.com> NNTP-Posting-Host: 151.48.78.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1283880737 29728 127.0.0.1 (7 Sep 2010 17:32:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 7 Sep 2010 17:32:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b34g2000yqm.googlegroups.com; posting-host=151.48.78.169; posting-account=wDgnTQkAAAAxWbsVNyuWtiZ5iM59iBkz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.127 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4118 We would like to invite you to submit a paper to EvoHOT 2011, the 6th European Workshop on Hardware Optimization Techniques. EvoHOT focuses on innovative heuristics, game theory and bio-inspired techniques (eg. EA, SA, AIS, NN, ants) applied to the Electronic Design Automation. The workshop goal is to show the latest developments; industrial experiences; successful attempts to /evolve/ rather than /design/ new solutions; hybridizations of traditional methodologies. EvoHOT topics include, but are not limited to: * Analog circuit design * Automatic test pattern generation * Built-in self test * Evolutionary design of electronic circuits * Evolutionary hardware design methodologies * Evolutionary robotics * Evolvable hardware * Floorplanning * Hardware/Software co-design * Hybrid evolutionary/exact approach * Hardware accelerated methodologies * Logic synthesis * Routing * Test program generation Submissions should be formatted according to the LNCS guidelines and must not be longer than 10 pages. EvoHOT is part of EvoStar (Evo*), the premier co-located conferences in the field of Evolutionary Computing. The website http://www.evostar.org/ offers updated information about EvoHOT and all other Evo* events, including call for papers, organising committees and detailed submission requirements. Evo* 2011 will be held in Torino, Italy. In 2011, Italy will celebrate the 150th anniversary of its unification. Torino, as the first Italian capital, will be the center of all the celebrations. The investments made to host the 2006 Winter Olympics made the city of Torino and the region Piemonte very attractive and an ideal location to host international events. Important dates common to all Evo* events: * Submission deadline: 22 november 2010 * Notification to authors: 7 january 2011 * Camera-ready deadline: 1 february 2011 * Conference: 27-29 April 2011 Thanks for your patience and interest Rolf Drechsler & Giovanni Squillero (EvoHOT chairs) -- Giovanni Squillero, Ph.D. Politecnico di Torino - Dip. Automatica e Informatica C.so Duca degli Abruzzi 24 - 10129 Torino - ITALY Tel: +39-011564.7186 - Fax: +39-011564.7099 WWW: http://www.cad.polito.it/staff/squillero/ -- The time you enjoy wasting is not wasted time. -- Bertrand Russell (1872-1970) From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Extracting type - Not possible or would it be useful in a future standard? Date: Tue, 7 Sep 2010 21:50:50 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: <4f63b42a-47cf-4f38-b771-a7f4fdbe30c1@l20g2000yqm.googlegroups.com> References: <8e2bc19f-867d-4b34-ab89-9d16f3a697aa@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283921450 19154 127.0.0.1 (8 Sep 2010 04:50:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Sep 2010 04:50:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4119 On Sep 7, 4:42=A0am, Tricky wrote: > I have just come across a situation where it might be beneficial to > return the type of something so another type can be created. > > For example: I have this type defined in a package. > > type rec_t is record > =A0 num : ufixed(7 downto 0); > end record rec; > > type rec_array_t is array(integer range <>) of rec_t; > > then in a design file I want to create an array. The purpose of this > array is simply to extract the "num" elements from a rec_array_t. At > the moment I have to define: > > type local_array_t is array(integer range <>) of > ufixed(rec_t.num'range); > > the problem comes when the "num" element is changed from a ufixed to a > sfixed. I then have to manually redefine the local_array_t to cope > with the type change. > Well, that's just the start of it though. You would then also have to change the type of any signals that are using the local array also. > Am I overthinking a problem that might be worked around with a > function (and by-passing the need for a local_array_t) In this particular case, one might be able to say that your package that defines the type should also have a function that returns an array of particular elements since that apparently may be a generally useful function to have when using your package. That would avoid having to do some editing in the area that you mentioned, but as I pointed out, you must have signals that want to use the local array so those declarations would be affected as well, you'll still be editing multiple places when you change a data type. However, it's probably not difficult to imagine there could also be much more 'nichy' functions that are useful in only very limited areas. One could say that those 'nichy' functions probably should not be cluttering up the package, but there really isn't a good argument for 'Why not?'. What looks like 'clutter' to one person is 'consolidation' to somebody else. Why not have 'nichy' as well as 'generally useful' functions that work with a type in the same package? In other words all functions that work with that type go in the same package...one stop shopping. Over time that package grows to pick up more 'generally useful' functions as well as 'nichy' functions that might end up finding other niches to fill. If you think it looks 'cluttered', that is most likely a commentary on your editing skills rather than the idea of packaging all functions together. Of course, in the end, there will be functions that really want to work with things of two different types and then the question about which package to put those functions in will rear its head. > or would this > prove useful in the language? Probably useful...but... At some point as you start to parameterize your design to make it more self-documenting you create the situation where it becomes difficult to look at the code and answer a simple question like "What type is signal xyz?" because the declaration becomes buried under mounds of 'self-documenting code' that refers to something here that refers to something there... Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Wed, 8 Sep 2010 01:00:02 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <66a74cd9-580d-48b4-b94f-49aa89fd6f03@l20g2000yqm.googlegroups.com> References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> <36d34872-b458-4fb1-8278-d86ecb001b4b@e14g2000yqe.googlegroups.com> <473049b2-31b5-44b3-ac3f-215775049b89@j18g2000yqd.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283932802 15110 127.0.0.1 (8 Sep 2010 08:00:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Sep 2010 08:00:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.6.30 Version/10.60,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4120 On Sep 6, 9:31=A0am, hssig wrote: > Some additional info to Tricky's road map (from answer to my support > request) : > > * Modelsim 6.8 will see full VHDL-2008 support Does "full VHDL-2008 support" include VHPI? Somehow, I doubt it. From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nf02.dk.telia.net!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!v35g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Equivalent of SystemVerilog Interface in VHDL? Date: Wed, 8 Sep 2010 15:21:59 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <2c99f706-6e4c-44f6-9106-349d9a3af83d@w30g2000yqw.googlegroups.com> NNTP-Posting-Host: 98.246.140.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1283984520 9031 127.0.0.1 (8 Sep 2010 22:22:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Sep 2010 22:22:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v35g2000prn.googlegroups.com; posting-host=98.246.140.7; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4121 On Aug 23, 11:12=A0am, Poojan Wagh wrote: > I was wondering if VHDL-2008 (or newer) includes an equivalent of the > SystemVerilog interface. I use records with resolved elements. I have written resolution functions for integer, real, and time to facilitate this. Not for RTL. Use it extensively in testbench models. Also cover it in our VHDL Testbenches and Verification class. Cheers, Jim SynthWorks VHDL Training From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.osn.de!diablo1.news.osn.de!ecngs!feeder.ecngs.de!feeder.news-service.com!postnews.google.com!l32g2000prn.googlegroups.com!not-for-mail From: chandrakant birajdar Newsgroups: comp.lang.vhdl Subject: Reading image file Date: Mon, 13 Sep 2010 01:56:38 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: <19df055d-6fbe-4699-843c-e3f660115629@l32g2000prn.googlegroups.com> NNTP-Posting-Host: 121.242.76.214 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284368198 18807 127.0.0.1 (13 Sep 2010 08:56:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 08:56:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000prn.googlegroups.com; posting-host=121.242.76.214; posting-account=Rtw5FwoAAAD3lswdAwoOSfOUmWWKGlDR User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.3) Gecko/20100403 Fedora/3.6.3-4.fc13 Firefox/3.6.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4122 I am trying to implement 2D filter using VHDL for this i have to give input as image. So how can i read image file? From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.69.MISMATCH!feeder.news-service.com!postnews.google.com!v6g2000prd.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Latch inference when default is missing in case statement Date: Mon, 13 Sep 2010 03:37:42 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> NNTP-Posting-Host: 139.181.143.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284374262 3783 127.0.0.1 (13 Sep 2010 10:37:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 10:37:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v6g2000prd.googlegroups.com; posting-host=139.181.143.34; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.55 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4123 Dear Group, It is said that if default statement is missing in case statement, then a latch is inferred. But I am not able to understand this. What is meant by latch inference? and why would a latch be inferred if case statement does not have default statement. If some cases are missed and default is also not there in a case statement, then it should simply read 'x' or '-' for those cases. Why is this latch inference coming into picture? Please help. Thanks From newsfish@newsfish Fri Dec 24 22:55:07 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!h37g2000pro.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Mon, 13 Sep 2010 03:38:51 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> NNTP-Posting-Host: 139.181.143.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284374331 20714 127.0.0.1 (13 Sep 2010 10:38:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 10:38:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h37g2000pro.googlegroups.com; posting-host=139.181.143.34; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.55 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4124 I also found a related article : http://www.asic-world.com/verilog/verilog_one_day2.html But it does not explain WHY? :( From newsfish@newsfish Fri Dec 24 22:55:08 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!h25g2000vba.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Reading image file Date: Mon, 13 Sep 2010 04:03:56 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <363eed87-ef39-4e1a-a095-0ab9e37ffa8a@h25g2000vba.googlegroups.com> References: <19df055d-6fbe-4699-843c-e3f660115629@l32g2000prn.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284375837 17456 127.0.0.1 (13 Sep 2010 11:03:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 11:03:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h25g2000vba.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.9) Gecko/20100824 Firefox/3.6.9,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4125 On 13 Sep, 09:56, chandrakant birajdar wrote: > I am trying to implement 2D filter using VHDL for this i have to give > input as image. So how can i read image file? Are you talking about for testbench or for real hardware. For testbenches, you can use the read function to read files char by char (in modelsim at least, other simulators want specific file headers). This way you can read in file data and do whatever you want with it. In real hardware, you will need to send the dataa through the filter pixel by pixel. so not as straightforward as above. From newsfish@newsfish Fri Dec 24 22:55:09 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v23g2000vbi.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Mon, 13 Sep 2010 04:09:52 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284376194 2698 127.0.0.1 (13 Sep 2010 11:09:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 11:09:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v23g2000vbi.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.9) Gecko/20100824 Firefox/3.6.9,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4126 On 13 Sep, 11:38, We Ech Dee Ell wrote: > I also found a related article :http://www.asic-world.com/verilog/verilog_one_day2.html > > But it does not explain WHY? > :( This is only a problem if you have asynchronous logic. Synchronous logic will never create latches (because you are always creating registers). the problem comes because if you dont define what happens in all states, then you are asking the circuit to remember a state. look at the following code: process(ip, a) begin if ip = '1' then op <= a; end if; end process; now, the output only changes when "ip" = '1'. when "ip" = '0' then op holds it's state. This is a latch. to prevent the formation of latches, you must provide paths for all states: process(ip,a,b) begin if ip = '1' then op <= a; else op <= b; end if; end process; Here we have created a mux, so no latches are required. From newsfish@newsfish Fri Dec 24 22:55:09 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!u13g2000vbo.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: process with two clks in sensitivity list problem Date: Mon, 13 Sep 2010 04:13:26 -0700 (PDT) Organization: http://groups.google.com Lines: 163 Message-ID: <20ad70e3-7776-4c96-b3b1-f859c57f0dd6@u13g2000vbo.googlegroups.com> NNTP-Posting-Host: 213.209.217.77 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284376406 21950 127.0.0.1 (13 Sep 2010 11:13:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 11:13:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u13g2000vbo.googlegroups.com; posting-host=213.209.217.77; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.9) Gecko/20100824 Firefox/3.6.9,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4127 Hi, in the code below there are two 2 bit free running counters (cnta and cntb). The o output is generated inside oprc process sampling alternatively cnta on the rising edge of clk and cntb on the rising edge of clkn (that is not clk). The output o1 is generated in the same way, except that it uses a copy of clk (lck1) and a copy of clkn (clk1n). The poroblem is: o and o1 are different. WHY? This code comes from an implementation of a DDR IO pad mux from an FPGA manufacturer. In my opinion the problem has something to do with the fact that those processes use a sensitivity list with two clocks. Thanks Pupillo ------------------------------------------------------------------------------------------------------------------------ ---------------- ENTITY myff ------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity myff is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; o,o1: out STD_LOGIC_VECTOR (1 downto 0)); end myff; architecture Behavioral of myff is signal clkn,clk1,clkn1:std_logic; signal cnta,cntb:std_logic_vector(1 downto 0); begin clkn<=not clk; clk1<=clk; clkn1<=clkn; ---- counter cnta ---------- cntaprc:process(clk) begin if (rising_edge(clk)) then if (rst='1') then cnta<="00"; else cnta<=cnta+1; end if; end if; end process; ---- counter cntb ------------- cntbprc:process(clk) begin if (rising_edge(clk)) then if (rst='1') then cntb<="10"; else cntb<=cntb+1; end if; end if; end process; ----- DDR sampling of cnta / cntb using clk / clkn --------- oprc:process(clk,clkn) begin if (rising_edge(clk)) then o<=cnta; end if; if (rising_edge(clkn)) then o<=cntb; end if; end process; ----- DDR sampling of cnta / cntb using clk1 / clkn1 --------- o1prc:process(clk1,clkn1) begin if (rising_edge(clk1)) then o1<=cnta; end if; if (rising_edge(clkn1)) then o1<=cntb; end if; end process; end Behavioral; ------------------------------------------------------------------------------------------------------------------------ ----------------------------------- TEST BENCH ------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY myff_TB IS END myff_TB; ARCHITECTURE behavior OF myff_TB IS COMPONENT myff PORT( clk : IN std_logic; rst : IN std_logic; o,o1 : OUT std_logic_vector(1 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; --Outputs signal o,o1: std_logic_vector(1 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN uut: myff PORT MAP ( clk => clk, rst => rst, o => o, o1 => o1 ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. rst<='1'; wait for 100 ns; rst<='0'; wait; end process; END; From newsfish@newsfish Fri Dec 24 22:55:09 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m1g2000vbh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Mon, 13 Sep 2010 05:42:38 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284381759 1201 127.0.0.1 (13 Sep 2010 12:42:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 12:42:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000vbh.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4128 On Sep 13, 6:37=A0am, We Ech Dee Ell wrote: > > What is meant by latch inference? It means that a transparent latch will be created based on the logic in the source code. A transparent latch is something of the form... process(C, D) begin if (C=3D '1') then Q <=3D D; end if; end process; This is just one example > and why would a latch be inferred if > case statement does not have default statement. Because the definition of the VHDL language (and most others) is that unless specifically assigned, a signal does not change values. In the above example, if 'C' is not equal to '1' then signal 'Q' will not be updated because the 'Q <=3D D' statement will not be executed. > If some cases are missed and default is also not there in a case > statement, then it should simply read 'x' or '-' for those cases. What should 'read' 'x' or '-'? Then ask yourself why? If the last value that was assigned to signal 'Q' in the above was '1', and now 'C' is no longer equal to '1', then wouldn't you expect 'Q' to retain the value of '1'? Not 'x' or '-'. KJ From newsfish@newsfish Fri Dec 24 22:55:09 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.64.134.MISMATCH!postnews.google.com!j2g2000vbo.googlegroups.com!not-for-mail From: "Niv (KP)" Newsgroups: comp.lang.vhdl Subject: Writing & reading same file Date: Mon, 13 Sep 2010 06:29:59 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <41737b4b-c186-49cb-a77a-2db2334bc97b@j2g2000vbo.googlegroups.com> NNTP-Posting-Host: 81.110.164.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284384600 25154 127.0.0.1 (13 Sep 2010 13:30:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 13:30:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j2g2000vbo.googlegroups.com; posting-host=81.110.164.109; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4129 In my testbench, is it possible to write to a file, then read that file, then write to the file again, then read the file again, etc etc. It doesn't matter if the file is re-opened and destrots the previous data written. Seem to be having trouble doing this. i.e. in my tb, unit 1 writes several lines of binary data (as text) to file A, then unit 2 needs to read this file A before it then writes out other data to file B. This is then repeated several times/ From newsfish@newsfish Fri Dec 24 22:55:09 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!t3g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Mon, 13 Sep 2010 08:31:13 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <57bfc1bd-372e-47ad-a71c-07a614c6bf15@t3g2000vbb.googlegroups.com> References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284391873 20654 127.0.0.1 (13 Sep 2010 15:31:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 15:31:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t3g2000vbb.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4130 The idea of an HDL description that requires "remembering" the state of a signal will generate a latch is spot-on. Anytime a combinatorial process executes but somehow avoids assigning an output, it must remember the previous value of the output. Rather than focusing on defaults in case statements and else's for every if, there are two simple coding rules for avoiding latches: 1. Avoid combinatorial processes; use clocked processes instead. Clocked processes cannot create latches. 2. If you have to use a combinatorial process, create default assignments to every signal/variable driven by the process right up front, before any conditional statements, etc., so that every execution will result in assigning a value to them, and nothing needs remembering. This is far simpler to remember, write, and review than rules about else's for every if, defaults for every case, etc. Taking the example provided, and applying rule #2: process(ip,a,b) begin op <= b; -- default assignment if ip = '1' then op <= a; end if; end process; In this trivial example, the benefits of this approach may not be apparent. But how difficult would it be if you had multiple outputs, and multiple levels of if-statement logic, to determine whether or not there was an execution path that avoided assigning something to one of those outputs? Note that the default assignment could be to '0', '1', b, 'X', etc. Do not use op <= op, for obvious reasons. Note also that assignments to 'X' or '-' may not simulate as expected (or like the hardware may behave) if you are subsequently checking to see if op = '1' or similar. Andy From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k11g2000vbf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: process with two clks in sensitivity list problem Date: Mon, 13 Sep 2010 08:44:32 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <20ad70e3-7776-4c96-b3b1-f859c57f0dd6@u13g2000vbo.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284392672 27351 127.0.0.1 (13 Sep 2010 15:44:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 15:44:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k11g2000vbf.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4131 Your assignments between clocks consume a delta delay cycle. While their edges coincide in simulation time, they do not coincide in execution time, and therefore you get different results. If data is clocked out by the un-delayed clock, then clocked in by the delayed clock, the date will ripple through both registers in one clock cycle, which is not what you expected (or what the synthesized hardware will do). If the clock gets delta delayed, the input data needs to be delta delayed too. But if the input data is delta delayed, the clock does not need to be delta delayed, since the next clock edge will occur long after delta delays have passed. You can also use rising_edge() and falling_edge() to avoid having to invert the clocks. Andy From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!j19g2000vbh.googlegroups.com!not-for-mail From: pupillo Newsgroups: comp.lang.vhdl Subject: Re: process with two clks in sensitivity list problem Date: Mon, 13 Sep 2010 11:36:02 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <20ad70e3-7776-4c96-b3b1-f859c57f0dd6@u13g2000vbo.googlegroups.com> NNTP-Posting-Host: 87.11.2.102 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284402962 22279 127.0.0.1 (13 Sep 2010 18:36:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Sep 2010 18:36:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j19g2000vbh.googlegroups.com; posting-host=87.11.2.102; posting-account=LmDBwwoAAAAQS8Wm0aRDX_lMNOhQ8Bs- User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; it; rv:1.9.2.9) Gecko/20100824 Firefox/3.6.9,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4132 On 13 Set, 17:44, Andy wrote: > Your assignments between clocks consume a delta delay cycle. While > their edges coincide in simulation time, they do not coincide in > execution time, and therefore you get different results. If data is > clocked out by the un-delayed clock, then clocked in by the delayed > clock, the date will ripple through both registers in one clock cycle, > which is not what you expected (or what the synthesized hardware will > do). > > If the clock gets delta delayed, the input data needs to be delta > delayed too. But if the input data is delta delayed, the clock does > not need to be delta delayed, since the next clock edge will occur > long after delta delays have passed. > > You can also use rising_edge() and falling_edge() to avoid having to > invert the clocks. > > Andy Ok very helpfull! Thanks From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Writing & reading same file Date: Mon, 13 Sep 2010 21:05:55 +0100 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <41737b4b-c186-49cb-a77a-2db2334bc97b@j2g2000vbo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Sep 2010 20:06:03 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="2856"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PFbu5JCMoSoTGy81NmSwUwkB0q0RZrQc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:0mb12JeKsySxqQ6bVo4RBp7Bkb8= Xref: feeder.eternal-september.org comp.lang.vhdl:4133 On Mon, 13 Sep 2010 06:29:59 -0700 (PDT), "Niv (KP)" wrote: >In my testbench, is it possible to write to a file, then read that >file, then write to the file again, then read the file again, etc etc. >It doesn't matter if the file is re-opened and destrots the previous >data written. > >Seem to be having trouble doing this. > >i.e. in my tb, unit 1 writes several lines of binary data (as text) to >file A, then unit 2 needs to read this file A before it then writes >out other data to file B. hi Kevin Did you close file A before attempting to re-open and then read from it? (Of course this requires using the -93 form of file declaration, and FILE_OPEN and FILE_CLOSE procedures.) When you write new data to a file, I don't think there is any guarantee of that file's contents until it's closed. While we're thinking about this, it's worth mentioning that you need to be very careful when multiple processes access the same file. The file is in effect a shared variable with no kind of interlock or scheduling, so it is quite easy to get indeterminacy - one of the very few places this can happen in VHDL. Unless you have really huge amounts of data (many tens of megabytes) it may be better to use shared variables of protected type. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 13 Sep 2010 15:16:21 -0500 Date: Mon, 13 Sep 2010 13:16:23 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.9) Gecko/20100825 Thunderbird/3.1.3 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Writing & reading same file References: <41737b4b-c186-49cb-a77a-2db2334bc97b@j2g2000vbo.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <3_udnbo1SegIGxPRnZ2dnUVZ_judnZ2d@lmi.net> Lines: 39 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-GdflDw4dXZMX2uaBVw5o69dFJhWm1czjRefv+tP+nwy7syeS+2ViPqpIX3rh0/PmZVPSaxY8JG9urSH!iBkMsT/sbx30XnzRDH3P4jsbCQuQ4aCJ4AJx6+H8e/KRYqY4br8JkrTrVsntlUUvNnEzOT8xJCTc!Gg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4134 On 9/13/2010 1:05 PM, Jonathan Bromley wrote: > On Mon, 13 Sep 2010 06:29:59 -0700 (PDT), "Niv (KP)" wrote: > >> In my testbench, is it possible to write to a file, then read that >> file, then write to the file again, then read the file again, etc etc. >> It doesn't matter if the file is re-opened and destrots the previous >> data written. >> >> Seem to be having trouble doing this. >> >> i.e. in my tb, unit 1 writes several lines of binary data (as text) to >> file A, then unit 2 needs to read this file A before it then writes >> out other data to file B. > > hi Kevin > > Did you close file A before attempting to re-open and then > read from it? (Of course this requires using the -93 > form of file declaration, and FILE_OPEN and FILE_CLOSE > procedures.) > > When you write new data to a file, I don't think there is > any guarantee of that file's contents until it's closed. > > While we're thinking about this, it's worth mentioning > that you need to be very careful when multiple processes > access the same file. The file is in effect a shared > variable with no kind of interlock or scheduling, so it > is quite easy to get indeterminacy - one of the very few > places this can happen in VHDL. Unless you have really > huge amounts of data (many tens of megabytes) it may be > better to use shared variables of protected type. And if you do, it may be better to use a protected type as a wrapper around that file to manage transactions against it. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e20g2000vbn.googlegroups.com!not-for-mail From: Calvin C Newsgroups: comp.lang.vhdl Subject: Noise Filter on Master Reset ? Date: Tue, 14 Sep 2010 11:58:06 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 99.23.83.114 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284490687 6213 127.0.0.1 (14 Sep 2010 18:58:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Sep 2010 18:58:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbn.googlegroups.com; posting-host=99.23.83.114; posting-account=iZLPrwkAAAAL1qrPY86jsmNym9HayHeZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; (R1 1.5); .NET CLR 1.1.4322; .NET CLR 2.0.50727; WWTClient2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4135 Hi all, Are there any pros and cons in VHDL for placing noise filter on master reset, i.e. inserting noise filter between ASIC/FPGA master reset input and reset pins on internal FFs ? Thanks, Calvin From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!c32g2000vbq.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Noise Filter on Master Reset ? Date: Tue, 14 Sep 2010 14:03:07 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: References: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284498187 28908 127.0.0.1 (14 Sep 2010 21:03:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Sep 2010 21:03:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c32g2000vbq.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4136 I assume you mean a digital filter? Generally speaking, you want as little logic between master reset and the FPGA flops as possible. Inserting a filter would also assume that you had a dependable clock source to run the filter (our master resets are asynchronous because we need to control the state even with no clock). We synchronize the trailing edge of reset to each destination clock domain in order to avoid metastability problems, but it still works without a clock to get the chip into reset (it just won't come out of reset until you have a clock, which is not a bad thing.) Andy From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u13g2000vbo.googlegroups.com!not-for-mail From: Calvin C Newsgroups: comp.lang.vhdl Subject: Re: Noise Filter on Master Reset ? Date: Tue, 14 Sep 2010 14:20:42 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284499242 9760 127.0.0.1 (14 Sep 2010 21:20:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Sep 2010 21:20:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u13g2000vbo.googlegroups.com; posting-host=192.91.172.36; posting-account=iZLPrwkAAAAL1qrPY86jsmNym9HayHeZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322; .NET CLR 1.0.3705; InfoPath.2; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4137 Yes, I meant digital filter. Normally, a master reset should be asynchronous asserted and synchronous de-asserted, i.e. by clock edge as you mentioned. Will we deviate from IEEE standards by placing digital filter on master reset line ? What could be the drawback for doing so ? Thx, Calvin On Sep 14, 2:03=A0pm, Andy wrote: > I assume you mean a digital filter? > > Generally speaking, you want as little logic between master reset and > the FPGA flops as possible. Inserting a filter would also assume that > you had a dependable clock source to run the filter (our master resets > are asynchronous because we need to control the state even with no > clock). We synchronize the trailing edge of reset to each destination > clock domain in order to avoid metastability problems, but it still > works without a clock to get the chip into reset (it just won't come > out of reset until you have a clock, which is not a bad thing.) > > Andy From newsfish@newsfish Fri Dec 24 22:55:10 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feed.news.qwest.net!mpls-nntp-04.inet.qwest.net!news.glorb.com!postnews.google.com!m1g2000vbh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Noise Filter on Master Reset ? Date: Tue, 14 Sep 2010 17:23:16 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <296034d5-834f-4fba-95fa-e1f80b339d13@m1g2000vbh.googlegroups.com> References: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284510196 31112 127.0.0.1 (15 Sep 2010 00:23:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Sep 2010 00:23:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m1g2000vbh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4138 On Sep 14, 5:20=A0pm, Calvin C wrote: > > Will we deviate from IEEE standards by placing digital filter on > master reset line ? > What IEEE standards are you referring to? > What could be the drawback for doing so ? > You won't have found and fixed the cause of the noise on your master reset, just attempted to cover it up. Probably will come back to haunt you. KJ From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Reading image file Date: Wed, 15 Sep 2010 12:05:04 +0000 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <19df055d-6fbe-4699-843c-e3f660115629@l32g2000prn.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Date: Wed, 15 Sep 2010 11:04:16 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="18009"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/R2rBIYtOLaWFd8Nh5Stx74e2ZJHqJlUJewW/ViI9mQg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <19df055d-6fbe-4699-843c-e3f660115629@l32g2000prn.googlegroups.com> Cancel-Lock: sha1:IqbYG15knzKTblv/6Bux/92aBD0= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4139 Chandrakant Birajdar sent: |----------------------------------------------------------------------| |"I am trying to implement 2D filter using VHDL for this i have to give| |input as image. So how can i read image file?" | |----------------------------------------------------------------------| Use an image file in a bitmap format. (So for example, not in JPEG format.) Each pixel would be stored as a number, so load each pixel as a number. It might be useful for you to read relevant parts of a book which covers at least one graphical file format. From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Extracting type - Not possible or would it be useful in a future standard? Date: Wed, 15 Sep 2010 12:20:35 +0000 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <8e2bc19f-867d-4b34-ab89-9d16f3a697aa@k10g2000yqa.googlegroups.com> <2a09e5a6-5c5a-41ed-a907-b58dfa8251ac@e14g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Date: Wed, 15 Sep 2010 11:19:47 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="20698"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19B9K9JlAymunHUcEl7ha8A5PcrEaVEH82AkMckLBeOlw==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <2a09e5a6-5c5a-41ed-a907-b58dfa8251ac@e14g2000yqe.googlegroups.com> Cancel-Lock: sha1:x1p4cKKtzVnfVbRdkotYU1v+KkU= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4140 Andy sent on September 7th, 2010: |---------------------------------------| |"[..] | | | |[..] | |[..] (not sure why they limited 'base | |to use as a prefix in the first place).| | | |[..]" | |---------------------------------------| Not in the first place. 'Base can be liberally used in Ada. Regards, Paul Colin From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!a30g2000vbt.googlegroups.com!not-for-mail From: JB Newsgroups: comp.lang.vhdl Subject: Re: Reading image file Date: Wed, 15 Sep 2010 05:09:43 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <4e6ebecc-60f4-431f-b26c-37aa9c6ea546@a30g2000vbt.googlegroups.com> References: alpine.LNX.2.00.1009151201470.3650@Bluewhite64.example.net NNTP-Posting-Host: 80.14.138.198 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284552583 26309 127.0.0.1 (15 Sep 2010 12:09:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Sep 2010 12:09:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a30g2000vbt.googlegroups.com; posting-host=80.14.138.198; posting-account=S4wEMQoAAADRjpmXQT29euLGCs6HM3WR User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0b6) Gecko/20100101 Firefox/4.0b6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4141 > Use an image file in a bitmap format. (So for example, not in JPEG > format.) Each pixel would be stored as a number, so load each pixel as > a number. PGM is a good file format to start with as it is very easy to handle. From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!u31g2000pru.googlegroups.com!not-for-mail From: Calvin C Newsgroups: comp.lang.vhdl Subject: Re: Noise Filter on Master Reset ? Date: Wed, 15 Sep 2010 05:46:04 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <7697202b-f9c0-491b-a7c9-8ccc6570985f@u31g2000pru.googlegroups.com> References: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> <296034d5-834f-4fba-95fa-e1f80b339d13@m1g2000vbh.googlegroups.com> NNTP-Posting-Host: 99.23.83.114 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284554789 29525 127.0.0.1 (15 Sep 2010 12:46:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Sep 2010 12:46:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u31g2000pru.googlegroups.com; posting-host=99.23.83.114; posting-account=iZLPrwkAAAAL1qrPY86jsmNym9HayHeZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; (R1 1.5); .NET CLR 1.1.4322; .NET CLR 2.0.50727; WWTClient2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4142 I'd rather say common standard practice, not IEEE standards, are to avoid logic on master reset line. Due to its nature, i.e. at much higher frequency, the clock line is supposed to be more sensitive to noise than the reset line. However, if digital filter were to be placed on the master reset line, would that be enough to take care of noise concerns ? CC On Sep 14, 5:23=A0pm, KJ wrote: > On Sep 14, 5:20=A0pm, Calvin C wrote: > > > > > Will we deviate from IEEE standards by placing digital filter on > > master reset line ? > > What IEEE standards are you referring to? > > > What could be the drawback for doing so ? > > You won't have found and fixed the cause of the noise on your master > reset, just attempted to cover it up. =A0Probably will come back to > haunt you. > > KJ From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c16g2000vbp.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Noise Filter on Master Reset ? Date: Wed, 15 Sep 2010 09:49:27 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <567c5af8-de4f-47d6-9908-1a289b7c2c5c@c16g2000vbp.googlegroups.com> References: <0d1f03b3-ac60-40df-8f64-d4e038d58c12@e20g2000vbn.googlegroups.com> <296034d5-834f-4fba-95fa-e1f80b339d13@m1g2000vbh.googlegroups.com> <7697202b-f9c0-491b-a7c9-8ccc6570985f@u31g2000pru.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284569367 3480 127.0.0.1 (15 Sep 2010 16:49:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Sep 2010 16:49:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c16g2000vbp.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4143 On Sep 15, 8:46=A0am, Calvin C wrote: > Due to its nature, i.e. at much higher frequency, the clock line is > supposed to be more sensitive to noise than the reset line. > By that logic, you should be asking about noise filters on the clock, not reset. > However, if digital filter were to be placed on the master reset line, > would that be enough to take care of noise concerns ? > Sure...if your design has only input and that input is the master reset. But filtering also assumes that you have an understanding of the nature of the noise you are filtering so that you can design a proper filter...and for whatever reason, you are unable to eliminate the noise source in the first place and can only apply filter band-aids. KJ From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e20g2000vbn.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: How to create a directory in VHDL Simulation Date: Thu, 16 Sep 2010 07:33:04 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284647584 21226 127.0.0.1 (16 Sep 2010 14:33:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Sep 2010 14:33:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbn.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.55 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4144 Hi everyone, Out of curiosity, I was wondering if there is a way to create a directory in VHDL? I can create files with the WRITE procedure. However, this procedure will not work if the directory specified does not exist so I was wondering if there was a way in VHDL itself to create the missing directory. Best regards From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j19g2000vbh.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: How to create a directory in VHDL Simulation Date: Thu, 16 Sep 2010 08:25:20 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <14cbb02a-1970-41e4-b83e-2da1006ff2b2@j19g2000vbh.googlegroups.com> References: NNTP-Posting-Host: 86.111.223.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284650726 14336 127.0.0.1 (16 Sep 2010 15:25:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Sep 2010 15:25:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j19g2000vbh.googlegroups.com; posting-host=86.111.223.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.2 (14893) 06j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4145 On Sep 16, 3:33=A0pm, Benjamin Couillard wrote: > Out of curiosity, I was wondering if there is a way to create a > directory in VHDL? I can create files with the WRITE procedure. > However, this procedure will not work if the directory specified does > not exist so I was wondering if there was a way in VHDL itself to > create the missing directory. Nothing in the language or its standard libraries, no. There may be vendor extensions to do it, and you can do it through VHPI/FLI/DirectC or whatever foreign-language interface is provided by your preferred simulator. Suggestion: Don't even try it. VHDL's tools for exploring the file system are hopeless. Instead, run the sim from a script that first sets up all the desired input data IN THE SIMULATOR'S WORKING DIRECTORY, with simple filenames that you can put into your VHDL as literals. Then get the VHDL sim to write files, with simple fixed names, IN THE SIMULATOR'S WORKING DIRECTORY. And then, when simulation is done, the script moves those files to a sensible place. Scripting languages are brilliant for all this sort of thing; VHDL is garbage for it. Use the right tool for the job. In a script you can also easily arrange for output log files to have unique names based on time-of-day, for example. Try doing that in VHDL - no, I don't think so. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:11 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder5.xlned.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!x20g2000pro.googlegroups.com!not-for-mail From: Swapnajit Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Subject: Announcement: 'Verification Management' LinkedIn group Date: Thu, 16 Sep 2010 13:17:53 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 70.231.134.215 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284668274 12726 127.0.0.1 (16 Sep 2010 20:17:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Sep 2010 20:17:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x20g2000pro.googlegroups.com; posting-host=70.231.134.215; posting-account=bDLsBQkAAAB3tCuLYhxyPevTa4ZY2yB2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; OfficeLiveConnector.1.3; OfficeLivePatch.0.0; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:2578 comp.lang.vhdl:4146 comp.arch.fpga:12457 SUMMARY: Discussion, Q&A and sharing of thoughts related to management of functional verification of digital designs. DESCRIPTION: Functional verification is often touted as the big bottleneck in a digital design. This forum is a for everyone involved in the management of functional verification. Share your thoughts, ideas, problems, suggestions and even job opportunities with the group. HOW TO JOIN: www.linkedin.com/groups?gid=3403447 From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!l32g2000prn.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Fri, 17 Sep 2010 01:09:44 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> <57bfc1bd-372e-47ad-a71c-07a614c6bf15@t3g2000vbb.googlegroups.com> NNTP-Posting-Host: 122.177.161.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284710984 6622 127.0.0.1 (17 Sep 2010 08:09:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Sep 2010 08:09:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000prn.googlegroups.com; posting-host=122.177.161.197; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.59 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4147 Thanks All, your answers made it very clear to me. But I just had one more doubt while reading the replies above. Why do only asynchronous logic create latches and not the synchronous ones? A small example like the ones above would be really appreciated. From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!feeder4.news.weretis.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!j30g2000vbr.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Fri, 17 Sep 2010 06:38:28 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> <57bfc1bd-372e-47ad-a71c-07a614c6bf15@t3g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284730713 10693 127.0.0.1 (17 Sep 2010 13:38:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Sep 2010 13:38:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j30g2000vbr.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4148 On 17 Sep, 09:09, We Ech Dee Ell wrote: > Thanks All, your answers made it very clear to me. > But I just had one more doubt while reading the replies above. > > Why do only asynchronous logic create latches and not the synchronous > ones? > A small example like the ones above would be really appreciated. Techincally, a synchronous register is a latch. Just in this case the data is remembered when the clock changes from 0 to 1 (or vice versa if its falling edge). But because this is such a useful concept FPGAs are filled with them. Other types of latches are more custom but are made out of logic gates and therefore timing between them cannot be analysed (like it can from register to register) A D-type can be made from 4x nand gates. See here: http://www.play-hookey.com/digital/d_nand_latch.html From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!s17g2000prh.googlegroups.com!not-for-mail From: Parvathi c Newsgroups: comp.lang.vhdl Subject: Xilinx fft core simulation Date: Fri, 17 Sep 2010 08:18:07 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <876c28a2-0da4-464a-b7a0-486a5b664e49@s17g2000prh.googlegroups.com> NNTP-Posting-Host: 122.167.131.207 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1284736692 28172 127.0.0.1 (17 Sep 2010 15:18:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Sep 2010 15:18:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s17g2000prh.googlegroups.com; posting-host=122.167.131.207; posting-account=TIshbgoAAAAwCIUoIrBvOTzhrcngKo1x User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.9) Gecko/20100824 Firefox/3.6.9,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4149 Hi, I am trying to simulate fft of a sinewave of certain frequency with Modelsim. To simulate the fft code, first we have to find the Bin size. I have found that. Bin size = ( i/p freq*point fft)/sampling rate. (point fft = 1024) For a sine wave of i/p freq 10Hz, and Fs = 50Hz, bin size is 204.8. FFT of a sine wave is a delta at a frequency same as that of the input frequency. Now how do i view this in the simulator. Please guide me. thanks in advance. Parvathi. From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!postnews.google.com!c32g2000vbq.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Fri, 17 Sep 2010 20:19:56 -0700 (PDT) Organization: http://groups.google.com Lines: 89 Message-ID: <477f04af-209e-4ca2-acd9-98790012d774@c32g2000vbq.googlegroups.com> References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> <57bfc1bd-372e-47ad-a71c-07a614c6bf15@t3g2000vbb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284779996 3144 127.0.0.1 (18 Sep 2010 03:19:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 18 Sep 2010 03:19:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c32g2000vbq.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4150 On Sep 17, 4:09=A0am, We Ech Dee Ell wrote: > Thanks All, your answers made it very clear to me. > But I just had one more doubt while reading the replies above. > > Why do only asynchronous logic create latches and not the synchronous > ones? Well, as Tricky mentioned, registers can also be considered latches as well...but I think what you're looking for is a bit more practical answer for why. The short answer though is that what you've stated is somewhat backwards. The answer to the question "Why do only asynchronous logic create latches and not the synchronous ones?" is "Latches are used to implement combinatorial processes that feedback on themselves whereas registers are used to implement edge sensitive processes." The more detailed answer is coming up. > A small example like the ones above would be really appreciated. The following code might not be the typical form one sees for a latch or a register, but it was chosen to illustrate the point. [1] y <=3D x when (C =3D '1'); -- Example of code that creates a latch: [2] y <=3D x when (C =3D '1' and C'event); -- Example of code that creats a flip flop: Obviously, the only source code difference between [1] and [2] is the inclusion of "C'event". VHDL defines that C'event equates to 'any time signal C changes'. Focusing just on synthesis of digital logic here, the phrase 'any time signal C changes' means that signal C must have - Changed from a high to low (i.e. 1 to 0) - Changed from a low to high (i.e. 0 to 1) So now one can say that "C =3D '1' and C'event" equates to "C is 1 and C has changed from either low to high or from high to low". But if "C is 1" is true, then obviously C must have changed from low to high. So now you can look at the condition "C =3D '1' and C'event" and conclude that C must have had an a rising edge occur. Now look at the condition in [1]. Here you don't have the "C'event" condition, it is simply "C =3D '1'". This is true whenever signal C is high (i.e. a logic 1). This condition *starts* at the rising edge of C, but it is not a small interval of time, rather it is true frmo the rising edge of C up to the point where the falling edge of C occurs. Now look at the left part of the assignment in [2], "y <=3D x" in addition to what you now now about the "C =3D '1' and C'event" logic. What this means is that the signal x will only be copied over to y during the small interval of time when the rising edge of signal C is occurring. The digital logic primitive that samples a signal at the rising edge of some other input signal and stores that result is a flip flop (also known as register). Now look at the left part of the assignment in [1], "y <=3D x" in addition to what you now now about the "C =3D '1'" logic. What this means is that the signal x will only be copied over to y during the interval when signal C is high. In particular, if C is high, then any change to x will immediately show up on y, you don't need to wait for a rising edge on C. The digital logic primitive that samples a signal as long as some other input signal is high and stores that result is a transparent latch (or simply a latch). To bring it all around to wrap it up then, it is simply the appearance of the C'event in an outermost "if" statement in a process [3] that causes the synthesis software to say "Ah ha! I need to put in a flip flop here". Since a flip flop is chosen, the process is a synchronous process. If a process does not have a C'event in an outermost "if" statement, rather just a "C =3D '1'" form that causes the synthesis software to say "Ah ha! I need to put in (or cobble together from logic) a transparent latch here". Since a latch is chosen, the process is a combinatorial process. The pattern matching on the source code by the synthesis tool that results in what I called "Ah ha!..." is typically called inferring. Therefore, one can look at things like [1] and say something like "synthesis will infer a latch to implement [1]" and "synthesis will infer a flip flop to implement [2]" Kevin Jennings [3] The C'event can also be obscured somewhat. The preferred form for writing a clocked process would use "if rising_edge(C) then...". The IEEE standard libraries define the function "rising_edge" and that definition includes the C'event. It is slightly more complicated than just "C =3D '1' and C'event" but that complication has to do with simulation (where metavalues of 'X', '-', 'Z' are valid) not synthesis (where the value of any signal is either 0 or 1. From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 18 Sep 2010 17:47:54 -0500 Date: Sat, 18 Sep 2010 18:47:48 -0400 From: David Bishop User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> <36d34872-b458-4fb1-8278-d86ecb001b4b@e14g2000yqe.googlegroups.com> <473049b2-31b5-44b3-ac3f-215775049b89@j18g2000yqd.googlegroups.com> <66a74cd9-580d-48b4-b94f-49aa89fd6f03@l20g2000yqm.googlegroups.com> In-Reply-To: <66a74cd9-580d-48b4-b94f-49aa89fd6f03@l20g2000yqm.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 13 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-zhwipNZGrarMDW5ezqFICoNHJW1zGtBvB/yPTBM/SWBF1ecF4JCShQUrBnmtjz3okQAzjKZeYW3dSNt!FvDtG9TGg3UEMysZafRvC8fJs8zcXrZ4Arm9OVJyq5OaR+yP4jEOs6HOakzcxigQ X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4151 On 9/8/2010 4:00 AM, Chris Higgs wrote: > On Sep 6, 9:31 am, hssig wrote: >> Some additional info to Tricky's road map (from answer to my support >> request) : >> >> * Modelsim 6.8 will see full VHDL-2008 support > > Does "full VHDL-2008 support" include VHPI? Somehow, I doubt it. > Mentor for some strange reason thinks that their FLI "will work" for this. Personally I'd rather see a real PLI that is more standard. From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 18 Sep 2010 17:51:27 -0500 Date: Sat, 18 Sep 2010 18:51:20 -0400 From: David Bishop User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 18 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-MTFEwfPFsBSXE1h/7Wf7a0sjBpDJfUgWqPeLIMC3O+KDEk3DgPhz7Ka0B0HEbQ3gA2b05HDcWm1xyBW!mX0/CTfRrvHeYCPrwooKEMfGzxcv0ULl54VsPtQiJu7fcGsdcrrEwwzuSm2jAwQV X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Xref: feeder.eternal-september.org comp.lang.vhdl:4152 On 9/1/2010 9:56 AM, Tricky wrote: > I think I got the same copy/paste reply, 5 mins after raising the > support request. It is all marked as a "tentative" release schedule: > Fixed Point Packages > Questa/ModelSim supports the non-generic version of the packages > in 6.5. > Targeted release: 6.8 (requires generic type capability). > generic type I think I've talk MGC into supporting the base packages before 6.8. We'll see how it goes. On: http://www.vhdl.org/fphdl I have the source code for an "ieee_proposed" library (as many of the new functions as I could). These are all work with synthesis. From newsfish@newsfish Fri Dec 24 22:55:12 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!border2.nntp.ams2.giganews.com!border2.nntp.ams.giganews.com!nntp.giganews.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!w4g2000vbh.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Did VHDL-2008 get lost ? Date: Mon, 20 Sep 2010 01:55:12 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: References: <0e449497-ec7b-40d5-b8f3-19057ae883e4@x25g2000yqj.googlegroups.com> <57811fbb-81cf-4028-b4d7-28fc6e00b137@l6g2000yqb.googlegroups.com> <36d34872-b458-4fb1-8278-d86ecb001b4b@e14g2000yqe.googlegroups.com> <473049b2-31b5-44b3-ac3f-215775049b89@j18g2000yqd.googlegroups.com> <66a74cd9-580d-48b4-b94f-49aa89fd6f03@l20g2000yqm.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1284972912 1486 127.0.0.1 (20 Sep 2010 08:55:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Sep 2010 08:55:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w4g2000vbh.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.6.30 Version/10.62,gzip(gfe) X-Original-Bytes: 2112 Xref: feeder.eternal-september.org comp.lang.vhdl:4153 On Sep 18, 11:47=A0pm, David Bishop wrote: > > Does "full VHDL-2008 support" include VHPI? Somehow, I doubt it. > > Mentor for some strange reason thinks that their FLI "will work" for > this. =A0 Personally I'd rather see a real PLI that is more standard. VHPI is included in the VHDL-2008 standard and is now _the_ PLI standard. For a vendor to claim full VHDL-2008 support but not implement VHPI is a total misnomer. From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!a30g2000vbt.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Latch inference when default is missing in case statement Date: Mon, 20 Sep 2010 10:29:18 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: References: <98808f41-f189-4a61-a7cd-7669ef85150f@v6g2000prd.googlegroups.com> <712bd222-605b-46e5-b00c-26c927725ad8@v23g2000vbi.googlegroups.com> <57bfc1bd-372e-47ad-a71c-07a614c6bf15@t3g2000vbb.googlegroups.com> <477f04af-209e-4ca2-acd9-98790012d774@c32g2000vbq.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285003764 25918 127.0.0.1 (20 Sep 2010 17:29:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Sep 2010 17:29:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a30g2000vbt.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4154 Well said, with enough detail to show how things really work. To simplify it a little, a "clocked" or "Synchronous" process only updates on the edge of a clock signal (with the possible addition of an asynchronous reset). Therefore any "memory device" the process infers is of an edge-sensitive type, which is a flip flop. A combinatorial process updates when any of the inputs change (assuming they are correctly included in the sensitivity list), and therefore memory elements that the process infers are level-sensitive, which are latches. Andy From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!f20g2000pro.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Extracting type - Not possible or would it be useful in a future standard? Date: Mon, 20 Sep 2010 20:03:21 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: References: <8e2bc19f-867d-4b34-ab89-9d16f3a697aa@k10g2000yqa.googlegroups.com> NNTP-Posting-Host: 67.169.204.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285038201 23273 127.0.0.1 (21 Sep 2010 03:03:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Sep 2010 03:03:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000pro.googlegroups.com; posting-host=67.169.204.228; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.9) Gecko/20100824 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4155 As mentioned in the other posts, subtypes are probably the way to go now. VHDL-2008 adds a new attribute: O'SUBTYPE Kind: Subtype. Prefix: Any prefix O that is appropriate for an object, or an alias thereof. Result: The fully constrained subtype that is the subtype of O, together with constraints defining any index ranges that are determined by application of the rules of 5.3.2.2. (If O is an alias for an object, then the result is determined by the declaration of O, not that of the object.) From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!i17g2000vbq.googlegroups.com!not-for-mail From: Cesar Newsgroups: comp.lang.vhdl Subject: Variables instead of signals: what about constraints? Date: Tue, 21 Sep 2010 00:26:34 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> NNTP-Posting-Host: 80.35.205.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285053994 24743 127.0.0.1 (21 Sep 2010 07:26:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Sep 2010 07:26:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i17g2000vbq.googlegroups.com; posting-host=80.35.205.165; posting-account=EEVxEwoAAACf3fdSJ3peBkvx71DdidZM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.1.6) Gecko/20091201 Firefox/3.5.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4156 It's some months since I've been coding my VHDL modules within a single process. It's being a good experience but I've come across with a problem. When I try to attach a constraint like KEEP or IOB to a net, I've realized that there is no way to assign it to a variable, you can only do it to signals. Any solution? Regards, C=E9sar From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!q2g2000vbk.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Tue, 21 Sep 2010 04:24:48 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> NNTP-Posting-Host: 76.100.125.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285068289 13195 127.0.0.1 (21 Sep 2010 11:24:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Sep 2010 11:24:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbk.googlegroups.com; posting-host=76.100.125.106; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.8) Gecko/20100722 Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4157 On Sep 21, 3:26=A0am, Cesar wrote: > It's some months since I've been coding my VHDL modules within a > single process. It's being a good experience but I've come across with > a problem. When I try to attach a constraint like KEEP or IOB to a > net, I've realized that there is no way to assign it to a variable, > you can only do it to signals. > Any solution? To bring a value out of a process you have to use signals. To reach an IOB then you would have a signal to attach the constraint to, right? If you are using a constraint like KEEP, the question is why? The other question is, why not use a signal? You are not forced to use variables in processes. Rick From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!feedme.ziplink.net!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Tue, 21 Sep 2010 08:00:44 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <2fb37235-710b-493b-84c2-463553bb7174@k13g2000vbq.googlegroups.com> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285081249 24592 127.0.0.1 (21 Sep 2010 15:00:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Sep 2010 15:00:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) X-Original-Bytes: 2930 Xref: feeder.eternal-september.org comp.lang.vhdl:4158 Other than simply a limitation of the synthesis tool, I can see some potential problems with having some constraints applied to a variable. In a clocked process, multiple accesses to the same variable may imply combinatorial and registered data, which are mapped to different resources. If you applied a constraint to the variable, to which resource would you want to apply the constraint? In a clocked process, any signal that is assigned always becomes a register, and the constraint applied would map to the same resource. Are you needing to keep a combinatorial signal, or a register? If the former, you may need to fall back to a combinatorial process (or concurrent assignment) and use a vhdl signal for it. If you need to keep a register, you can create a duplicate of the register with a signal (or just code it with the signal instead of the variable), and keep that. If the item you need to keep is a combinatorial function of registered values within the same process, some tools allow you so specify output signals in clocked processes that are combinatorial functions of registered variables. process (clk) is variable myvar : natural range 0 to 7; begin if rising_edge(clk) then myvar := (myvar + 1) mod 8; outputa <= myfunc(myvar); end if; outputb <= myfunc(myvar); end process; In the above, outputa becomes the registered function of the combinatorial version of myvar. Outputb becomes the combinatorial function of the registered version of myvar. If both functions are the same, some synthesis tools will optimize both into one output (I've seen simplify choose the registered output) Andy From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j30g2000vbr.googlegroups.com!not-for-mail From: Cesar Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Tue, 21 Sep 2010 23:43:12 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <1b75d36d-cb04-4047-942f-bbae0effa332@j30g2000vbr.googlegroups.com> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> NNTP-Posting-Host: 80.35.205.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285137792 5708 127.0.0.1 (22 Sep 2010 06:43:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 22 Sep 2010 06:43:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j30g2000vbr.googlegroups.com; posting-host=80.35.205.165; posting-account=EEVxEwoAAACf3fdSJ3peBkvx71DdidZM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.1.6) Gecko/20091201 Firefox/3.5.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4159 On Sep 21, 1:24=A0pm, rickman wrote: > On Sep 21, 3:26=A0am, Cesar wrote: > > > It's some months since I've been coding my VHDL modules within a > > single process. It's being a good experience but I've come across with > > a problem. When I try to attach a constraint like KEEP or IOB to a > > net, I've realized that there is no way to assign it to a variable, > > you can only do it to signals. > > Any solution? > > To bring a value out of a process you have to use signals. =A0To reach > an IOB then you would have a signal to attach the constraint to, > right? Right. > If you are using a constraint like KEEP, the question is why? =A0 I'm double-flopping an input signal and I want to avoid implementing it as a LUT shift-register, because a LUT shift-register has a longer clock-to-output than a CLB flip-flop. The way to do it is to apply a KEEP or NOMERGE constraint to the first flip-flop output. > The other question is, why not use a signal? =A0You are not forced to use > variables in processes. Just to be style consistent. Regards, C=E9sar From newsfish@newsfish Fri Dec 24 22:55:13 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!g10g2000vbc.googlegroups.com!not-for-mail From: Cesar Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Tue, 21 Sep 2010 23:52:02 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> <2fb37235-710b-493b-84c2-463553bb7174@k13g2000vbq.googlegroups.com> NNTP-Posting-Host: 80.35.205.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285138322 12374 127.0.0.1 (22 Sep 2010 06:52:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 22 Sep 2010 06:52:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g10g2000vbc.googlegroups.com; posting-host=80.35.205.165; posting-account=EEVxEwoAAACf3fdSJ3peBkvx71DdidZM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.1.6) Gecko/20091201 Firefox/3.5.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4160 On Sep 21, 5:00=A0pm, Andy wrote: > Other than simply a limitation of the synthesis tool, I can see some > potential problems with having some constraints applied to a variable. > > In a clocked process, multiple accesses to the same variable may imply > combinatorial and registered data, which are mapped to different > resources. If you applied a constraint to the variable, to which > resource would you want to apply the constraint? In a clocked process, > any signal that is assigned always becomes a register, and the > constraint applied would map to the same resource. > > Are you needing to keep a combinatorial signal, or a register? If the > former, you may need to fall back to a combinatorial process (or > concurrent assignment) and use a vhdl signal for it. > > If you need to keep a register, you can create a duplicate of the > register with a signal (or just code it with the signal instead of the > variable), and keep that. This is my case. I'll do that. Any way, it's not nice to modify the VHDL code to assign a constraint. From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Wed, 22 Sep 2010 13:02:47 -0700 Lines: 25 Message-ID: <8fv5l9F31uU1@mid.individual.net> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> <1b75d36d-cb04-4047-942f-bbae0effa332@j30g2000vbr.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net l1BRt/InHlJHvlMyf9OdMA0yBRbnpXaFF6GK6nMj7zLkWr3VIG Cancel-Lock: sha1:MXD3AK+f2mDky4l5oDRACyD0seM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.9) Gecko/20100915 Lightning/1.0b2 Thunderbird/3.1.4 In-Reply-To: <1b75d36d-cb04-4047-942f-bbae0effa332@j30g2000vbr.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4161 On 9/21/2010 11:43 PM, Cesar wrote: > I'm double-flopping an input signal and I want to avoid implementing > it as a LUT shift-register, because a LUT shift-register has a longer > clock-to-output than a CLB flip-flop. > The way to do it is to apply a KEEP or NOMERGE constraint to the first > flip-flop output. An Fmax timing constraint would cover all the internal registers, including those input registers. To avoid fanout duplication on the second synchronization register, I code for three input registers. >-[DQ]--[DQ]-.-[DQ]-> | .-[DQ]-> Otherwise, I have to somehow verify no register duplication on the second stage. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!j30g2000vbr.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Thu, 23 Sep 2010 15:02:59 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <3fd41b63-0a74-41a6-97f2-ad0be11d22cb@j30g2000vbr.googlegroups.com> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> <1b75d36d-cb04-4047-942f-bbae0effa332@j30g2000vbr.googlegroups.com> <8fv5l9F31uU1@mid.individual.net> NNTP-Posting-Host: 173.72.222.152 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285279379 21412 127.0.0.1 (23 Sep 2010 22:02:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Sep 2010 22:02:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j30g2000vbr.googlegroups.com; posting-host=173.72.222.152; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4162 On Sep 22, 4:02=A0pm, Mike Treseler wrote: > On 9/21/2010 11:43 PM, Cesar wrote: > > > I'm double-flopping an input signal and I want to avoid implementing > > it as a LUT shift-register, because a LUT shift-register has a longer > > clock-to-output than a CLB flip-flop. > > The way to do it is to apply a KEEP or NOMERGE constraint to the first > > flip-flop output. > > An Fmax timing constraint would cover > all the internal registers, including > those input registers. > > To avoid fanout duplication on the > second synchronization register, > I code for three input registers. > > =A0>-[DQ]--[DQ]-.-[DQ]-> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > =A0 =A0 =A0 =A0 =A0 =A0 =A0 .-[DQ]-> > > Otherwise, I have to somehow verify > no register duplication on the second stage. > > =A0 =A0 =A0 =A0 =A0-- Mike Treseler You lost me somewhere. The first flop "sees" the async signal. The second flop sees a stable, sync signal. Why can't the second flop be duplicated? As long as there is adequate slack time in all paths between the first flop and the second rank of flops, how would it make a problem to have multiple flops in the second rank? I agree that the first flop must not be duplicated or you have lost the value of the exercise. Also, how does the third rank of flops prevent duplication of the first? Did I miss something in metastability 101? Rick From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Thu, 23 Sep 2010 15:56:12 -0700 Lines: 18 Message-ID: <8g246cF19dU1@mid.individual.net> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> <1b75d36d-cb04-4047-942f-bbae0effa332@j30g2000vbr.googlegroups.com> <8fv5l9F31uU1@mid.individual.net> <3fd41b63-0a74-41a6-97f2-ad0be11d22cb@j30g2000vbr.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 3AthSWR8+WBWhl3z5Vmv3AdFNeE3IQg9HtD6IY+prsnDIqGxeW Cancel-Lock: sha1:uwubtMhj67SeuV/LokdSei2iw+M= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.9) Gecko/20100915 Lightning/1.0b2 Thunderbird/3.1.4 In-Reply-To: <3fd41b63-0a74-41a6-97f2-ad0be11d22cb@j30g2000vbr.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4163 On 9/23/2010 3:02 PM, rickman wrote: > You lost me somewhere. The first flop "sees" the async signal. The > second flop sees a stable, sync signal. Often this is true, but sometimes there isn't enough slack time without a special constraint. The second flop always provides enough slack time. My goal is bomb-proof synchronization using only an Fmax constraint. > Also, how does the third rank of flops prevent duplication of the > first? The point is that if the third flop *is* duplicated, I still have two flops dedicated to synchronization. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.lang.vhdl Subject: Re: Variables instead of signals: what about constraints? Date: Sun, 26 Sep 2010 14:11:23 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <1b910e58-9b42-4c04-bd4f-d16ce3f2f20b@26g2000yqv.googlegroups.com> References: <4ff1517e-c82f-4acd-bf07-1d2907f65cd7@i17g2000vbq.googlegroups.com> NNTP-Posting-Host: 213.185.243.227 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285535483 5599 127.0.0.1 (26 Sep 2010 21:11:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 26 Sep 2010 21:11:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=213.185.243.227; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4165 On Sep 21, 9:26=A0am, Cesar wrote: > It's some months since I've been coding my VHDL modules within a > single process. It's being a good experience but I've come across with > a problem. When I try to attach a constraint like KEEP or IOB to a > net, I've realized that there is no way to assign it to a variable, > you can only do it to signals. > Any solution? > > Regards, > C=E9sar If you mean you want to "decorate" a signal with an attribute of some type, you must do so in the declarative part of your signals. Since your architecture is free of any signal declarations, you cant declare or "attach" the attributes there. However you can both declare and attach attributes to signals in the entity ports within the entity declaration itself. Untested code: entity e is port ( my_out : out bit); begin attribute syn_allow_retiming : boolean; attribute syn_allow_retiming of my_out : signal is false; end entity e; HTH -- Pontus From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!x42g2000yqx.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Integer with leading zeros to string Date: Tue, 28 Sep 2010 06:59:09 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285682349 22335 127.0.0.1 (28 Sep 2010 13:59:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Sep 2010 13:59:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x42g2000yqx.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4166 Hi, I have the following integer declaration: signal test_num : integer := 0555; Now I want to make a string out of it: signal test_string : string (1 to 4); begin test_string <= integer'image(test_num); Modelsim complains "Array lengths do not match. Left is 4 (1 to 4). Right is 3 (1 to 3)." How can I convert test_num (ranging from 0001 to 9999) to a string correctly taking into account the leading zeros? Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!fu-berlin.de!postnews.google.com!t20g2000yqa.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Tue, 28 Sep 2010 07:39:16 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285684857 12140 127.0.0.1 (28 Sep 2010 14:40:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Sep 2010 14:40:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t20g2000yqa.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4167 The following should be displayed: report "This should be displayed " & integer'image(test_num) severity note; -> This should be displayed 0555 cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t20g2000yqa.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Tue, 28 Sep 2010 09:36:39 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <7fc1bfe6-da79-4b87-aa1f-acf1e3f090d7@t20g2000yqa.googlegroups.com> References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285691800 1855 127.0.0.1 (28 Sep 2010 16:36:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 28 Sep 2010 16:36:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t20g2000yqa.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 19j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4168 On Sep 28, 2:59=A0pm, hssig wrote: > How can I convert test_num (ranging from 0001 to 9999) to a string > correctly taking into account the leading zeros? Don't forget that the integer doesn't know about leading zeros. You are entitled to write them in the integer literal, but they are of course NOT stored in the integer itself. So you need a format mechanism: function format( value : natural; --- the numeric value width : positive; -- number of characters leading : character :=3D ' ') return string --- guarantees to return "width" chars is constant img: string :=3D integer'image(value); variable str: string(1 to width) :=3D (others =3D> leading); begin if img'length > width then report "Format width " & integer'image(width) & " is too narrow for value " & img severity warning; str :=3D (others =3D> '*'); else str(width+1-img'length to width) :=3D img; end if; return str; end; ... ---- this line should give "0055" constant N: integer :=3D 55; report "value is " & format(integer'image(N), 4, '0'); Any use? Dealing with negative integers is left as an exercise :-) -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:14 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Tue, 28 Sep 2010 19:55:45 +0100 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> <7fc1bfe6-da79-4b87-aa1f-acf1e3f090d7@t20g2000yqa.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Sep 2010 18:55:47 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="1135"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+iegq0fcnlz4xW1cQkr0JhxZ8m1F5TJLs=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:fsvgxGnGPC9mJ7q2Y/Z7eq1QNIc= Xref: feeder.eternal-september.org comp.lang.vhdl:4169 On Tue, 28 Sep 2010 09:36:39 -0700 (PDT), Jonathan Bromley wrote: >function format( > value : natural; --- the numeric value > width : positive; -- number of characters > leading : character := ' ') >return string --- guarantees to return "width" chars [...] >constant N: integer := 55; >report "value is " & format(integer'image(N), 4, '0'); oops, obviously the first argument should be N rather than integer'image(N). Hasty end-of-working-day post. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Tue, 28 Sep 2010 20:04:03 +0100 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Sep 2010 19:04:08 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="3457"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/HPUHguejLSClW+QJSh6JpO+UWqEOUe/k=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:kTImicN18Ls5voFASKiBrbJ4imw= Xref: feeder.eternal-september.org comp.lang.vhdl:4170 On Tue, 28 Sep 2010 06:59:09 -0700 (PDT), hssig wrote: >How can I convert test_num (ranging from 0001 to 9999) to a string >correctly taking into account the leading zeros? One final afterthought: take a look at http://www.easics.com/webtools/freesics for a more general (and very cunning) solution. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!k10g2000yqa.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Wed, 29 Sep 2010 06:23:29 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <396bd130-acd8-4e28-b381-79ca5d0a557c@k10g2000yqa.googlegroups.com> References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1285766609 13435 127.0.0.1 (29 Sep 2010 13:23:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Sep 2010 13:23:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000yqa.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4171 Hi Jonathan, I like you proposals. Thank you very much. Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!t20g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Wed, 29 Sep 2010 07:44:42 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <384cec47-7323-4929-b68e-d53703419186@t20g2000yqa.googlegroups.com> References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> <7fc1bfe6-da79-4b87-aa1f-acf1e3f090d7@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285771482 23591 127.0.0.1 (29 Sep 2010 14:44:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Sep 2010 14:44:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t20g2000yqa.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4172 On Sep 28, 11:36=A0am, Jonathan Bromley wrote: > Don't forget that the integer doesn't know about leading > zeros. =A0You are entitled to write them in the integer literal, > but they are of course NOT stored in the integer itself. =A0So > you need a format mechanism: > -- > Jonathan Bromley VHDL integers do store leading zeroes, up to at least 32 binary bits total. However, as you stated, standard output formats do not display them. Just because you initialize an integer with a literal which happens to be formatted with leading zeroes does not mean that the display output from that same integer will automatically be formatted with leading zeroes. Andy From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!x42g2000yqx.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Integer with leading zeros to string Date: Wed, 29 Sep 2010 08:02:19 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <0fe427fd-d992-4cf8-9224-fab904c775c1@x42g2000yqx.googlegroups.com> References: <5c01ca59-10c1-44cb-a954-d567c1a44a65@x42g2000yqx.googlegroups.com> <7fc1bfe6-da79-4b87-aa1f-acf1e3f090d7@t20g2000yqa.googlegroups.com> <384cec47-7323-4929-b68e-d53703419186@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1285772539 30329 127.0.0.1 (29 Sep 2010 15:02:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Sep 2010 15:02:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x42g2000yqx.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 07j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4173 On Sep 29, 3:44=A0pm, Andy wrote: > VHDL integers do store leading zeroes, up to at least 32 binary bits > total. However, as you stated, standard output formats do not display > them. Just because you initialize an integer with a literal which > happens to be formatted with leading zeroes does not mean that the > display output from that same integer will automatically be formatted > with leading zeroes. yeah, guess I didn't say very clearly what I meant :-) let's try again: there is no information stored in the integer variable that indicates whether or not its original textual representation had leading zeros (and, indeed, no information about any other aspect of its original textual representation except the integer's numeric value). Ho hum.... Jonathan From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe22.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl Subject: VHDL2008 & Modelsim Lines: 11 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Original Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe22.ams2 1285924146 213.105.6.183 (Fri, 01 Oct 2010 09:09:06 UTC) NNTP-Posting-Date: Fri, 01 Oct 2010 09:09:06 UTC Organization: virginmedia.com Date: Fri, 1 Oct 2010 10:09:04 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4175 For those that didn't get the email from Mentor, Modelsim 10.0 (yes I know) is now in beta and one of the highlights is: "Support for significant portions of VHDL 2008" You can download the beta from Mentor's supportnet. Hans www.ht-lab.com From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: assert of generic, during synthesis Date: Sun, 03 Oct 2010 22:05:47 +0200 Organization: Aioe.org NNTP Server Lines: 21 Message-ID: NNTP-Posting-Host: can+QHQsjHCwZAnhYtgNcg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4176 Hello, I am trying to write some portable code where one generic parameter, if wrong, gives a synthesis error that is difficult to understand. More precisely, i have a constant table that is addressed by the generic and i want to stop synthesis when the value in the table is 0, or something like that, with a clear message. I wand to use "assert" but it does not seem to be evaluated by the synthesiser. Some googling told me that it is not abnormal. I use synplify, by the way, and i wonder if most synthesizers behave the same way. Any hint or clue ? yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:15 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!feeder.erje.net!216.196.110.150.MISMATCH!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 03 Oct 2010 15:56:04 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Sun, 03 Oct 2010 22:04:40 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-YYx4QMCrEopwmI10gNROcL4hQtnM/UbqK8s0kP7KiIUiQdtwTZ+RGJWUaVmjZsrsF2Afbt79ZCrIO9D!gR/c55+7Aye97lg/69qklJDg6Z9Kkmp/wA/xxkL54lgOUXrxmnzUs6N7D7umFSAj2na+6a6lQ60t!izOq X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1927 Xref: feeder.eternal-september.org comp.lang.vhdl:4177 On Sun, 03 Oct 2010 22:05:47 +0200, whygee wrote: >Hello, > >I am trying to write some portable code where >one generic parameter, if wrong, gives a >synthesis error that is difficult to understand. > >More precisely, i have a constant table that >is addressed by the generic and i want to stop >synthesis when the value in the table is 0, >or something like that, with a clear message. > >I wand to use "assert" but it does not seem to >be evaluated by the synthesiser. >Some googling told me that it is not abnormal. >I use synplify, by the way, and i wonder if most >synthesizers behave the same way. > >Any hint or clue ? >yg Xilinx XST can handle certain forms of assert (statically determinable conditions) during synthesis. Others it ignores, but with a warning. - Brian. From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.mixmin.net!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Sun, 03 Oct 2010 22:56:42 +0200 Organization: Aioe.org NNTP Server Lines: 24 Message-ID: References: NNTP-Posting-Host: can+QHQsjHCwZAnhYtgNcg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4178 Hi Brian ! Thank you for the express answer ! Brian Drummond wrote: >> Any hint or clue ? >> yg > > Xilinx XST can handle certain forms of assert (statically determinable > conditions) during synthesis. Others it ignores, but with a warning. ok, so i guess that the best thing to do is forget the asserts for synthesis, i leave some for the simulation, and I put a comment close to where the synth says "out of range access"... I don't expect the code to be synthesised without a proper simulation but you never know :-D thanks again, > - Brian. yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Sun, 3 Oct 2010 16:47:22 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286149647 659 127.0.0.1 (3 Oct 2010 23:47:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 3 Oct 2010 23:47:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4179 On Oct 3, 4:05=A0pm, whygee wrote: > More precisely, i have a constant table that > is addressed by the generic and i want to stop > synthesis when the value in the table is 0, > or something like that, with a clear message. If you have a generic that shouldn't be 0, then it should be defined as a 'postive', not 'natural' or 'integer'...either that or define the range to be '1 to ??' KJ From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Mon, 4 Oct 2010 00:56:03 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: References: NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286178971 15310 127.0.0.1 (4 Oct 2010 07:56:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 Oct 2010 07:56:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 18j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4180 On Oct 4, 12:47=A0am, KJ wrote: > On Oct 3, 4:05=A0pm, whygee wrote: > > More precisely, i have a constant table that > > is addressed by the generic and i want to stop > > synthesis when the value in the table is 0, > > or something like that, with a clear message. > If you have a generic that shouldn't be 0, then it should be defined > as a 'postive', not 'natural' or 'integer'...either that or define the > range to be '1 to ??' I don't think that's terribly helpful, for two reasons. First, an integer subtype defines only one single contiguous range of legal values. Real-world parameterization problems often have much more complicated constraints on parameter values than a simple range constraint. Second, it's the wrong weapon. A subtype range violation suggests that someone is abusing the datatype system - things like trying to specify a vector with a negative number of bits, for example. That's a rather different idea than "the value is inappropriate given the set of other parameter values", which is much more application-specific and needs specific diagnostic messages such as can only be had from custom assertions. One of the great joys of VHDL over Verilog is its very clear-headed elaboration semantics, allowing you to write assertions over constant values and be assured that they will be checked at elaboration time, before simulation begins. By contrast, Verilog has only in the most recent version of the standard (1800-2009) gained elaboration-time assertions, and of course the tool support isn't there yet. In standard Verilog you can't check parameter values until simulation begins at time zero, which is usually too late - by that time, your bad parameter values are likely to have caused other fatal errors in the simulator. One point worth checking: some synth tools don't trip on assertions unless they are FATAL severity. Generally, I would regard it as a bug if a VHDL synth tool does not honour assertions over constant (elaboration-time) values such as generics. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe28.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: assert of generic, during synthesis Lines: 35 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe28.ams2 1286182698 213.105.6.183 (Mon, 04 Oct 2010 08:58:18 UTC) NNTP-Posting-Date: Mon, 04 Oct 2010 08:58:18 UTC Organization: virginmedia.com Date: Mon, 4 Oct 2010 09:58:10 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4181 "whygee" wrote in message news:i8aq3n$eal$1@speranza.aioe.org... > Hello, .. > Some googling told me that it is not abnormal. > I use synplify, by the way, and i wonder if most > synthesizers behave the same way. Hi Yg, Precision does report the assertion but only as a warning: GENERIC( CNTRESET : std_logic_vector(7 downto 0):="00000000"); assert ( CNTRESET /= "00000000" ) report "Count must not be zero" severity failure; # Warning: [45547]: Assertion Failed: failure : Count must not be zero As Jonathan mentioned it only works for failure. Regards, Hans. www.ht-lab.com > > Any hint or clue ? > yg > -- > http://ygdes.com / http://yasep.org > From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!l6g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Mon, 4 Oct 2010 02:24:29 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: <81ac6dfb-8eca-4205-975a-13df5ac33a95@l6g2000yqb.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286184277 20683 127.0.0.1 (4 Oct 2010 09:24:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 Oct 2010 09:24:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4182 On 4 Oct, 09:58, "HT-Lab" wrote: > "whygee" wrote in messagenews:i8aq3n$eal$1@speranza.aioe.org... > > Hello, > .. > > Some googling told me that it is not abnormal. > > I use synplify, by the way, and i wonder if most > > synthesizers behave the same way. > > Hi Yg, > > Precision does report the assertion but only as a warning: > > GENERIC( > CNTRESET : std_logic_vector(7 downto 0):="00000000"); > > assert ( CNTRESET /= "00000000" ) > report "Count must not be zero" severity failure; > > # Warning: [45547]: Assertion Failed: failure : Count must not be zero > > As Jonathan mentioned it only works for failure. > > Regards, > Hans.www.ht-lab.com > > > > > Any hint or clue ? > > yg > > -- > >http://ygdes.com/http://yasep.org > > This was discussed a while back - but Quartus Handles asserts properly (and quits if it fails or errors) From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!transit4.hitnews.eu!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 04 Oct 2010 04:44:50 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Mon, 04 Oct 2010 10:53:27 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-5WkBOV2+Z7P2eGY+2/JC8cpHBpuc1lnxzTM2w6rUGVXvJ6atYuBbV7BCbPWtWI4G2u+GInxeR5S/qMu!LQaq8DDUQ6egqpKzeBkcBGHyPtABZYief04rkztRPFm8eIFlBjgdlB+E9K8YtRCOyrcmEeIXZc9k!0xs= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2335 Xref: feeder.eternal-september.org comp.lang.vhdl:4183 On Sun, 03 Oct 2010 22:56:42 +0200, whygee wrote: >Hi Brian ! >Thank you for the express answer ! > >Brian Drummond wrote: >>> Any hint or clue ? >>> yg >> >> Xilinx XST can handle certain forms of assert (statically determinable >> conditions) during synthesis. Others it ignores, but with a warning. > >ok, so i guess that the best thing to do is >forget the asserts for synthesis, i leave some >for the simulation, and I put a comment >close to where the synth says "out of range access"... I think in your case, XST would catch the error - try it if you can. (I was using assertions in ISE7.1 so it need not be the latest version. If XST can do it and Synplify can't, I agree with Jonathan and would encourage you to supply a testcase to Synplify support... >I don't expect the code to be synthesised without >a proper simulation but you never know :-D The important thing is to ensure your process can always catch the error. Either via simulation, or perhaps using XST just as a syntax/sanity check - if you need Synplify for actual synthesis. (ditto Quartus according to Tricky) - Brian From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!feeds.news.ox.ac.uk!news.ox.ac.uk!zen.net.uk!hamilton.zen.co.uk!feeder2-2.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!c10g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Mon, 4 Oct 2010 05:32:18 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <4e8d265a-af7a-4c9b-885e-7831b364d385@c10g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286195543 3781 127.0.0.1 (4 Oct 2010 12:32:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 Oct 2010 12:32:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqh.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4184 On Oct 3, 7:47=A0pm, KJ wrote: > On Oct 3, 4:05=A0pm, whygee wrote: > > > More precisely, i have a constant table that > > is addressed by the generic and i want to stop > > synthesis when the value in the table is 0, > > or something like that, with a clear message. > > If you have a generic that shouldn't be 0, then it should be defined > as a 'postive', not 'natural' or 'integer'...either that or define the > range to be '1 to ??' > > KJ Woops, I retract the above. I misread "when the value in the table is 0" as "the address specified by the generic is 0" KJ From newsfish@newsfish Fri Dec 24 22:55:16 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed.velia.net!newsfeed01.sul.t-online.de!t-online.de!proxad.net!feeder1-2.proxad.net!74.125.46.134.MISMATCH!postnews.google.com!i13g2000yqd.googlegroups.com!not-for-mail From: zidong Newsgroups: comp.lang.vhdl Subject: Can you give some idea about the question? Date: Mon, 4 Oct 2010 23:10:17 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <4478b077-fac5-45b6-8677-608b315e4b2a@i13g2000yqd.googlegroups.com> NNTP-Posting-Host: 83.166.25.224 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286259018 32616 127.0.0.1 (5 Oct 2010 06:10:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Oct 2010 06:10:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i13g2000yqd.googlegroups.com; posting-host=83.166.25.224; posting-account=TWV0FQoAAACZ-d7Xs6yh06n4d7sxGkOw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.2; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.63 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4185 Design a circuit that has the following function: If C=3D00: shift A one step to the left (=93shift in=94 =920=92 on LSB) If C=3D01: shift A one step to the right (=93shift in=94 =920=92 on MSB) If C =3D10: rotate A one step left If C=3D11: rotate A one step right Input: A (std_logic_vector(7 downto 0)) C (std_logic_vector(1 downto 0) Output: Z (std_logic_vector(7 downto 0)) =96 the result of the shifting or rotation of A thanks in advance. From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x7g2000yqg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Can you give some idea about the question? Date: Tue, 5 Oct 2010 01:00:58 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <84a78844-5ff5-4ff1-ba5a-4261d9d76743@x7g2000yqg.googlegroups.com> References: <4478b077-fac5-45b6-8677-608b315e4b2a@i13g2000yqd.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286265658 13829 127.0.0.1 (5 Oct 2010 08:00:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Oct 2010 08:00:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x7g2000yqg.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4186 On 5 Oct, 07:10, zidong wrote: > Design a circuit that has the following function: > > If C=3D00: shift A one step to the left (=93shift in=94 =920=92 on LSB) > > If C=3D01: shift A one step to the right (=93shift in=94 =920=92 on MSB) > > If C =3D10: rotate A one step left > > If C=3D11: rotate A one step right > > Input: A (std_logic_vector(7 downto 0)) > > C (std_logic_vector(1 downto 0) > > Output: Z (std_logic_vector(7 downto 0)) =96 the result of the shifting > or rotation of > > A > > thanks in advance. Heres a good start: library ieee; use ieee.std_logic_1164.all; entity some_bloke_on_the_internet_did_my_assignment_for_me is port ( A : in std_logic_vector(7 downto 0); C : in std_logic_vector(1 downto 0); Z : out std_logic_vector(7 downto 0) ); end entity some_bloke_on_the_internet_did_my_assignment_for_me; architecture I_wrote_this_bit of some_bloke_on_the_internet_did_my_assignment_for_me is begin --place your code here - come back when you get stuck end architecture I_wrote_this_bit; From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe29.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl Subject: Functional Coverage without using SystemVerilog Lines: 10 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Original Message-ID: <9yFqo.18668$kL4.1742@newsfe29.ams2> NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe29.ams2 1286284549 213.105.6.183 (Tue, 05 Oct 2010 13:15:49 UTC) NNTP-Posting-Date: Tue, 05 Oct 2010 13:15:49 UTC Organization: virginmedia.com Date: Tue, 5 Oct 2010 14:15:38 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:4187 For those who are not on the Doulos mailing list: http://www.doulos.com/knowhow/vhdl_designers_guide/DVCon10_coverage_paper/fc_without_sv_downloads.php This is great stuff, Hans www.ht-lab.com From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nuzba.szn.dk!pnx.dk!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!postnews.google.com!j5g2000yqh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Can you give some idea about the question? Date: Tue, 5 Oct 2010 06:30:32 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <2e6b7319-8f44-4cf5-ad0f-b7f2e64a8a7c@j5g2000yqh.googlegroups.com> References: <4478b077-fac5-45b6-8677-608b315e4b2a@i13g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286285434 32516 127.0.0.1 (5 Oct 2010 13:30:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Oct 2010 13:30:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j5g2000yqh.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4188 I think it is a very nice question. Andy From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Can you give some idea about the question? Date: Tue, 5 Oct 2010 08:07:11 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <4478b077-fac5-45b6-8677-608b315e4b2a@i13g2000yqd.googlegroups.com> <2e6b7319-8f44-4cf5-ad0f-b7f2e64a8a7c@j5g2000yqh.googlegroups.com> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286291233 11977 127.0.0.1 (5 Oct 2010 15:07:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Oct 2010 15:07:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4189 On Oct 5, 9:30=A0am, Andy wrote: > I think it is a very nice question. > > Andy Except for the subject line, I didn't see any question. A bait-and- switch from my view. But maybe a question could have been a very nice question. I wonder if the OP is simulating new dance moves? KJ From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: VHDL2008 & Modelsim Date: Wed, 06 Oct 2010 22:31:20 +0200 Organization: T-Online Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1286397081 02 n30881 JV58BIfJfVTmwCU 101006 20:31:21 X-Complaints-To: usenet-abuse@t-online.de X-ID: E2akRuZQreSA0Zf+T9Hy0gpDqT-Ujaa33Sn534P2F+xQZmtYIECac2 User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100915 Thunderbird/3.0.8 In-Reply-To: X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4190 Am 01.10.2010 11:09, schrieb HT-Lab: > For those that didn't get the email from Mentor, Modelsim 10.0 (yes I know) is > now in beta and one of the highlights is: Why is it suddenly version 10? Are they doing a major rework of the simulator, like new GUI and decent multi-core support? I just wonder, because we are going to switch from Modelsim to Aldec's Riviera PRO. When coming from ModelSim you just have to love that tool because the GUI is so nice, quick, and feature-rich! Also, many features of VHDL-2008 are supported since a long time now. Matthias From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!feeder.news-service.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 08 Oct 2010 12:45:14 -0500 Date: Fri, 08 Oct 2010 13:45:13 -0400 From: David Bishop User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Fixed and floating point packages Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 12 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-RD4W4l5SRG+zlVOqUP7Qtv5y+uxs9pFnovk64m+1G6dFYA3xWc5PxyqVDgYRM0foXlqjDHdQAt0CiKS!sVtHc2Y2ybVmQKDwOp96HwU6JSfkLp6vspHwnObeaU0WpvOb+V7xaHVeh1ykvQl4 X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1364 Xref: feeder.eternal-september.org comp.lang.vhdl:4191 I took some time to updated the VHDL-93 compatible source code for the Fixed and floating point packages: http://www.vhdl.org/fphdl I also created a FAQ for these packages: http://www.vhdl.org/fphdl/fpfaq.html If I missed something, please let me know. These are in the new Modelsim Beta (I tested them). From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!w15g2000pro.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Reset Logic Function Date: Fri, 8 Oct 2010 01:53:47 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <930fff1d-4641-46db-ba30-d792e00c04d7@w15g2000pro.googlegroups.com> NNTP-Posting-Host: 139.181.143.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286563580 3194 127.0.0.1 (8 Oct 2010 18:46:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 18:46:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w15g2000pro.googlegroups.com; posting-host=139.181.143.34; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.63 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4192 Hi All, I have some code that consistently gives the problem of "Reset Logic Function", "Multiple Resets" etc. with some design checking tool for synthesis. The code is: ------------------ write_enable : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF ( Reset = '1' ) THEN register_we_REG1_i1 <= '0'; Wack <= '0'; ELSIF (WStrobe = '1') THEN register_we_REG1_i1 <= register_select(0); Wack <= '1'; END IF; END IF; END PROCESS write_enable; ---------------------------------------------------------------- reg_REG1_field16_i1 : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF Reset = '1' THEN field16_i1 <= '1'; ELSIF ( register_we_REG1_i1 = '1' ) THEN field16_i1 <= Wdata(16); END IF; END IF; END PROCESS reg_REG1_field16_i1; Can someone please help? Change is sensitivity lists is not allowed. Only synchronous processes are allowed. Thanks a lot in advance! From newsfish@newsfish Fri Dec 24 22:55:17 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!nntp.club.cc.cmu.edu!micro-heart-of-gold.mit.edu!bloom-beacon.mit.edu!4.24.21.218.MISMATCH!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Reset Logic Function Date: Fri, 8 Oct 2010 03:00:33 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: <1bd19229-1f8b-4308-8996-640416ffa780@e14g2000yqe.googlegroups.com> NNTP-Posting-Host: 122.177.215.186 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286563689 4299 127.0.0.1 (8 Oct 2010 18:48:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 18:48:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=122.177.215.186; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.63 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4193 write_enable : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF ( Reset = '1' ) THEN register_we_REG1_i1 <= '0'; Wack <= '0'; ELSIF (WStrobe = '1') THEN register_we_REG1_i1 <= register_select(0); Wack <= '1'; END IF; END IF; END PROCESS write_enable; ---------------------------------------------------------------- -- FIELD: field16 , ACCESS: write-only -- WIDTH: 1 , OFFSET: 16 ---------------------------------------------------------------- reg_REG1_field16_i1 : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF Reset = '1' THEN field16_i1 <= '1'; ELSIF ( register_we_REG1_i1 = '1' ) THEN field16_i1 <= Wdata(16); END IF; END IF; END PROCESS reg_REG1_field16_i1 From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!t5g2000prd.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Reset Logic Function Date: Fri, 8 Oct 2010 01:51:29 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <7f66195c-53ce-4642-b98c-322c2841df12@t5g2000prd.googlegroups.com> NNTP-Posting-Host: 139.181.143.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286563783 5345 127.0.0.1 (8 Oct 2010 18:49:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 18:49:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t5g2000prd.googlegroups.com; posting-host=139.181.143.34; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.63 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4194 Hi All, I have some code that consistently gives the problem of "Reset Logic Function", "Multiple Resets" etc. with some design checking tool for synthesis. The code is: ------------------ write_enable : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF ( Reset = '1' ) THEN register_we_REG1_i1 <= '0'; Wack <= '0'; ELSIF (WStrobe = '1') THEN register_we_REG1_i1 <= register_select(0); Wack <= '1'; END IF; END IF; END PROCESS write_enable; ---------------------------------------------------------------- reg_REG1_field16_i1 : PROCESS (Clock) BEGIN IF (Clock'EVENT) AND (Clock = '1') THEN IF Reset = '1' THEN field16_i1 <= '1'; ELSIF ( register_we_REG1_i1 = '1' ) THEN field16_i1 <= Wdata(16); END IF; END IF; END PROCESS reg_REG1_field16_i1; Can someone please help? Change is sensitivity lists is not allowed. Only synchronous processes are allowed. Thanks a lot in advance! From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!h7g2000yqn.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga,comp.arch.embedded Subject: ANN: Multi-port register-file (memory) generator Date: Thu, 7 Oct 2010 10:58:47 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <9d5a8b55-a972-4aa8-9afb-8d9ac53c5414@h7g2000yqn.googlegroups.com> NNTP-Posting-Host: 94.67.214.67 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286564127 9424 127.0.0.1 (8 Oct 2010 18:55:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 18:55:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h7g2000yqn.googlegroups.com; posting-host=94.67.214.67; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4195 comp.lang.verilog:2630 comp.arch.fpga:12716 comp.arch.embedded:16619 "mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx- specific (through component instantiation) multi-port memories. "mprfgen" was written during the course of a few days back in 2007. I guess I'm releasing this now since it is still useful and relevant. I would appreciate any comments and suggestions regarding its improvement. You can find this little tool at this website: http://www.nkavvadias.co.cc Direct link is: http://www.nkavvadias.co.cc/misc/mprfgen.zip "mprfgen" is licensed under the LGPL, version 3. Kind regards Nikolaos Kavvadias (nikolaoskavvadias#at#gmail.com) Adjunct lecturer - Research scientist Website: http://www.nkavvadias.co.cc From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Can you give some idea about the question? Date: Thu, 7 Oct 2010 23:38:56 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <838fb698-62d3-4504-ac9f-7c9803a34940@l20g2000yqm.googlegroups.com> References: <4478b077-fac5-45b6-8677-608b315e4b2a@i13g2000yqd.googlegroups.com> <2e6b7319-8f44-4cf5-ad0f-b7f2e64a8a7c@j5g2000yqh.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286564175 9937 127.0.0.1 (8 Oct 2010 18:56:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 18:56:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.10) Gecko/20100915 Ubuntu/10.04 (lucid) Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4196 On 5 Okt., 17:07, KJ wrote: > On Oct 5, 9:30=A0am, Andy wrote: > > > I think it is a very nice question. > > > Andy > > Except for the subject line, I didn't see any question. =A0A bait-and- > switch from my view. =A0But maybe a question could have been a very nice > question. =A0I wonder if the OP is simulating new dance moves? > > KJ Hi KJ, dance move generator, what a brilliant idea! Take four of these connected to random generators (two legs * x/y position), and don't forget the twister(tm)-detector to avoid impossible moves. With some input (3x3 step mat) and output stuff(3x3 LED) you can put a dance game into a single CPLD. More simple minds would suspect this assignment to be an implementation of the shift execution block of some simple processor core. The two bits of C could be part of the opcode, so all rotate/shift commands can use a common opcode, that differs only by these two bits. But how boring sounds that.... :-) Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q2g2000vbk.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: VHDL Combinatorial + Sequential + Timing? Date: Thu, 7 Oct 2010 10:55:42 -0700 (PDT) Organization: http://groups.google.com Lines: 174 Message-ID: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286564509 13717 127.0.0.1 (8 Oct 2010 19:01:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 19:01:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000vbk.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4197 Technical specifications first: I'm using the most recent Xilinx tools (12.2, 12.3), ISE/XST/Timing Analyzer, and I'm designing for the Virtex-6. As per the XST documentation I've inferred a single port Read-First Block RAM which, of course, is clock triggered. It looks a lot like this (some variable names and code that can't possibly be part of the critical path have been changed or removed): ConvertedAddress <= CONV_INTEGER( UNSIGNED( AddressConversion( AddressIn, ConversionFactor ) ) ); PROCESS(CLK) IS VARIABLE ReadRecord, WriteRecord : BRAMRecord; VARIABLE ReadRaw, WriteRaw : BRAMRaw; BEGIN IF RISING_EDGE(CLK) AND RESET = '0' THEN Result <= Ready; ReadRaw := BRAM(ConvertedAddress); WriteRaw := RecordToRaw( ( Field1 => Field1In, Field2 => Field2In, Field3 => Field3Generator( Field3In ) ) ); IF Operation = Write THEN BRAM(ConvertedAddress) <= WriteRaw; END IF; ReadRecord := RawToRecord( ReadRaw ); Field1Out <= ReadRecord.Field1; Field2Out <= ReadRecord.Field2; IF ReadRecord.Field3 = '0' THEN Result <= Result1; ELSIF ReadRecord.Field1 = Field1In THEN Result <= Result2; ELSE Result <= Result3; END IF; END IF; END PROCESS; Because it won't let me infer a block ram using records (it inferred distributed RAM when I tried that) I convert my record to and from an SLV using the RawToRecord and RecordToRaw functions. Now when I wrote this I thought the following would happen: 1. Before the clock cycle begins the consumer of the entity would input AddressIn and would set the enumeration typed Operation signal to either Read or Write. Before the clock cycle begins AddressIn would have AddressConversion applied to it and ConvertedAddress would be stable. 2. Rising edge of clock cycle - as long as RESET is low (inactive) the inferred Block RAM would begin work on ConvertedAddress for reading, and if Operation = Write it would write in a value as well. The Block RAM is significantly faster than my clock cycle which is set to 8 nanoseconds, so this should complete well before the clock cycle ends. 3. BEFORE the end of this clock cycle, Field1 and Field2 are set, and Result is set to one of three values based on the priority encoder in the process. Now when I synthesize this it fails timing, and the analysis gives me the following critical path: Timing constraint: TS_clk125 = PERIOD TIMEGRP "clk125" 8 ns HIGH 50%; 147168714 paths analyzed, 210840 endpoints analyzed, 3006 failing endpoints 3006 timing errors detected. (3006 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 11.172ns. -------------------------------------------------------------------------------- Slack: -3.172ns (requirement - (data path - clock path skew + uncertainty)) Source: Project/ValueOverride_19_15_BRB1 (FF) Destination: Project/RAM_GEN[7].RAM_inst/Result_1 (FF) Requirement: 8.000ns Data Path Delay: 11.022ns (Levels of Logic = 8) Clock Path Skew: -0.044ns (1.591 - 1.635) Source Clock: clk125 rising at 0.000ns Destination Clock: clk125 rising at 8.000ns Clock Uncertainty: 0.106ns Clock Uncertainty: 0.106ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.199ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: Project/ ValueOverride_19_15_BRB1 to Project/RAM_GEN[7].RAM_inst/Result_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X74Y187.CQ Tcko 0.337 Project/ ValueOverride_19_15_BRB4 Project/ ValueOverride_19_15_BRB1 SLICE_X118Y213.C3 net (fanout=526) 2.781 Project/ ValueOverride_19_15_BRB1 SLICE_X118Y213.CMUX Tilo 0.192 N4638 Project/ _n1876_inv1_rstpot SLICE_X103Y211.D6 net (fanout=96) 0.959 N5118 SLICE_X103Y211.D Tilo 0.068 Project/ RAMTableField1In<28> Project/ Mmux_Field1In<7>211 SLICE_X115Y216.D4 net (fanout=10) 0.903 Project/ Field1In<7><28> SLICE_X115Y216.D Tilo 0.068 Project/ RAM_GEN[7].RAM_inst/Mxor_ConvertedAddress<1>_xo<0>2 Project/ RAM_GEN[7].RAM_inst/Mxor_ConvertedAddress<1>_xo<0>3 SLICE_X127Y220.C4 net (fanout=1) 0.922 Project/ RAM_GEN[7].RAM_inst/Mxor_ConvertedAddress<1>_xo<0>2 SLICE_X127Y220.C Tilo 0.068 N29019 Project/ RAM_GEN[7].RAM_inst/Mxor_ConvertedAddress<1>_xo<0>6 SLICE_X138Y220.C2 net (fanout=520) 1.352 Project/ RAM_GEN[7].RAM_inst/ConvertedAddress<1> SLICE_X138Y220.BMUX Topcb 0.417 Project/ RAM_GEN[7].RAM_inst/N242 Project/ RAM_GEN[7].RAM_inst/Mram_BRAM120/C Project/ RAM_GEN[7].RAM_inst/Mram_BRAM120/F7.B Project/ RAM_GEN[7].RAM_inst/Mram_BRAM120/F8 SLICE_X133Y223.D2 net (fanout=1) 0.895 Project/ RAM_GEN[7].RAM_inst/N242 SLICE_X133Y223.DMUX Tilo 0.191 Project/ RAM_GEN[7].RAM_inst/Field1Out<43> Project/ RAM_GEN[7].RAM_inst/inst_LPM_MUX5911 SLICE_X125Y223.C6 net (fanout=2) 0.565 Project/ RAM_GEN[7].RAM_inst/_n0484<59> SLICE_X125Y223.DMUX Topcd 0.538 Project/ RAM_GEN[7].RAM_inst/BUS_0001_Field1In[47]_equal_16_o Project/ RAM_GEN[7].RAM_inst/Mcompar_BUS_0001_Field1In[47]_equal_16_o_lut<14> Project/ RAM_GEN[7].RAM_inst/Mcompar_BUS_0001_Field1In[47]_equal_16_o_cy<15> SLICE_X113Y221.D5 net (fanout=2) 0.696 Project/ RAM_GEN[7].RAM_inst/BUS_0001_Field1In[47]_equal_16_o SLICE_X113Y221.CLK Tas 0.070 Project/ RAM_GEN[7].RAM_inst/Result<1> Project/ RAM_GEN[7].RAM_inst/Mmux_PWR_500_o_GND_2830_o_mux_17_OUT21 Project/ RAM_GEN[7].RAM_inst/Result_1 ------------------------------------------------- --------------------------- Total 11.022ns (1.949ns logic, 9.073ns route) (17.7% logic, 82.3% route) Now in reality this path should be two clock cycles. The first path should begin at "Project/ValueOverride_19_15_BRB1 (FF) " and end at when ConvertedAddress is being applied to the Block RAM, and the second should be from where the Block RAM starts until "Project/ RAM_GEN[7].RAM_inst/Result_1 (FF) ". The block RAM clearly starts on the rising edge of a block cycle... So the question is am I fundamentally misunderstanding VHDL, or did I simply do something silly so that it's actually trying to infer an asynchronous Block RAM? I have a synth running where I don't include RESET in my if statement where I check for a RISING_EDGE, but that will take several hours before I find out if it worked or not... From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: We Ech Dee Ell Newsgroups: comp.lang.vhdl Subject: Reset Logic Function Date: Fri, 8 Oct 2010 03:01:41 -0700 (PDT) Organization: http://groups.google.com Lines: 1 Message-ID: <23cff1c9-9d37-4983-997e-b6edae650c8f@j25g2000yqa.googlegroups.com> NNTP-Posting-Host: 122.177.215.186 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286565219 21098 127.0.0.1 (8 Oct 2010 19:13:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 19:13:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=122.177.215.186; posting-account=XoFecQoAAACNfTPTKneNety-jtBEm9Sp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.3 (KHTML, like Gecko) Chrome/6.0.472.63 Safari/534.3,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4198 good is better From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!g8g2000yqa.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga,comp.arch.embedded Subject: ANN: Multi-port register-file (memory) generator Date: Thu, 7 Oct 2010 16:27:42 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <93b60b8c-74f8-44ee-9cb6-f3f874e437a8@g8g2000yqa.googlegroups.com> NNTP-Posting-Host: 94.67.214.67 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286568087 17068 127.0.0.1 (8 Oct 2010 20:01:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Oct 2010 20:01:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g8g2000yqa.googlegroups.com; posting-host=94.67.214.67; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4199 comp.lang.verilog:2634 comp.arch.fpga:12722 comp.arch.embedded:16623 "mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx- specific (through component instantiation) multi-port memories. "mprfgen" was written during the course of a few days back in 2007. I guess I'm releasing this now since it is still useful and relevant. I would appreciate any comments and suggestions regarding its improvement. You can find this little tool at this website: http://www.nkavvadias.co.cc Direct link is: http://www.nkavvadias.co.cc/misc/mprfgen.zip "mprfgen" is licensed under the LGPL, version 3. Kind regards Nikolaos Kavvadias (nikolaoskavvadias#at#gmail.com) Adjunct lecturer - Research scientist Website: http://www.nkavvadias.co.cc From newsfish@newsfish Fri Dec 24 22:55:18 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!28g2000yqm.googlegroups.com!not-for-mail From: Leon Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga,comp.arch.embedded Subject: Re: ANN: Multi-port register-file (memory) generator Date: Sat, 9 Oct 2010 07:56:36 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <045ede12-2f75-433b-8310-0f6aab128ac4@28g2000yqm.googlegroups.com> References: <9d5a8b55-a972-4aa8-9afb-8d9ac53c5414@h7g2000yqn.googlegroups.com> NNTP-Posting-Host: 109.155.237.46 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286636196 12733 127.0.0.1 (9 Oct 2010 14:56:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 Oct 2010 14:56:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 28g2000yqm.googlegroups.com; posting-host=109.155.237.46; posting-account=QWZLZQkAAADFmB_RJlmk3T-GvINRaZti User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10 GTB7.1 ( .NET CLR 3.5.30729; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4200 comp.lang.verilog:2637 comp.arch.fpga:12728 comp.arch.embedded:16633 On 7 Oct, 18:58, Nikolaos Kavvadias wrote: > "mprfgen" is a simple-minded multi-port memory generator that you can > use for your VHDL designs. It can generate either generic or Xilinx- > specific (through component instantiation) multi-port memories. > > "mprfgen" was written during the course of a few days back in 2007. I > guess I'm releasing this now since it is still useful and relevant. I > would appreciate any comments and suggestions regarding its > improvement. > > You can find this little tool at this website:http://www.nkavvadias.co.cc > Direct link is:http://www.nkavvadias.co.cc/misc/mprfgen.zip > > "mprfgen" is licensed under the LGPL, version 3. > > Kind regards > Nikolaos Kavvadias (nikolaoskavvadias#at#gmail.com) > Adjunct lecturer - Research scientist > Website:http://www.nkavvadias.co.cc Thanks. It built OK with gcc on my Win7 x64 laptop. I've just installed the latest Xilinx ISE, and I'll see how it behaves with that. Leon From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!g21g2000prn.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Why is this code persnickety? Date: Sun, 10 Oct 2010 09:38:00 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286728681 17875 127.0.0.1 (10 Oct 2010 16:38:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 Oct 2010 16:38:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g21g2000prn.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4201 I'm a software guy with a decent hardware understanding, just beginning to teach myself VHDL and FPGAs. I've got a Nexys2 board and in playing with the multiplexed 7-seg displays I've run across a situation where my code to delay and switch between digits runs for some count values and doesn't run for others. Here's the code section in question: prescale_to_100us: process (clk_50M) variable counter : natural range 0 to 2500 := 1; begin if (rising_edge(clk_50M)) then counter := counter - 1; if (counter = 0) then counter := 2500; clk_100us <= not clk_100us; end if; end if; end process; drive_digits: process (clk_100us, sw) constant Scan_Count : natural := 300; variable counter : natural range 0 to Scan_Count := 1; variable digs7_var : std_logic_vector (3 downto 0) := "1110"; begin if (rising_edge(clk_100us)) then counter := counter - 1; if (counter = 0) then case sw is when "001" => counter := Scan_Count / 8; when "010" => counter := Scan_Count / 4; when "100" => counter := Scan_Count / 2; when others => counter := Scan_Count; end case; case digs7_var is when "1110" => digs7_var := "1101"; when "1101" => digs7_var := "1011"; when "1011" => digs7_var := "0111"; when "0111" => digs7_var := "1110"; when others => digs7_var := "1110"; end case; digs7 <= digs7_var; end if; end if; end process; This code consistently works for e.g. Scan_Count = 300, 302 or 305, but fails (no multiplexing, just a solid 0 in the LSD position) for 301, 303 and 304. Nothing else is changed, just the value of Scan_Count. Naturally I assume that the problem lies in my code, but I have no idea what it might be. Any ideas? Thanks. BTW, do I need "sw" in the sensitivity list for drive_digits? Mike From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Sun, 10 Oct 2010 19:46:46 +0100 Organization: A noiseless patient Spider Lines: 99 Message-ID: <5524b65l6pamsmqrhvp8vun412koqvdguu@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Sun, 10 Oct 2010 18:46:56 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="30548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Zxek3sHDpp0ZyXmrTkCb8bFoqGyR0/rc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:5bxLSCoZ1+FkZyVWSFz2mHr13ZE= Xref: feeder.eternal-september.org comp.lang.vhdl:4202 On Sun, 10 Oct 2010 09:38:00 -0700 (PDT), KK6GM wrote: >I'm a software guy with a decent hardware understanding, just >beginning to teach myself VHDL and FPGAs. I've got a Nexys2 board and >in playing with the multiplexed 7-seg displays I've run across a >situation where my code to delay and switch between digits runs for >some count values and doesn't run for others. Here's the code section >in question: > > prescale_to_100us: process (clk_50M) > variable counter : natural range 0 to 2500 := 1; > begin > if (rising_edge(clk_50M)) then > counter := counter - 1; > if (counter = 0) then > counter := 2500; > clk_100us <= not clk_100us; > end if; > end if; > end process; > > > drive_digits: process (clk_100us, sw) > constant Scan_Count : natural := 300; > variable counter : natural range 0 to Scan_Count := 1; > variable digs7_var : std_logic_vector (3 downto 0) := "1110"; > begin > if (rising_edge(clk_100us)) then > counter := counter - 1; > if (counter = 0) then ........ reload scan counter, update multiplex output > end if; > end if; > end process; > >This code consistently works for e.g. Scan_Count = 300, 302 or 305, >but fails (no multiplexing, just a solid 0 in the LSD position) for >301, 303 and 304. Nothing else is changed, just the value of >Scan_Count. Naturally I assume that the problem lies in my code, but >I have no idea what it might be. Any ideas? Thanks. Your code looks broadly OK to me (have you simulated it?). It's good that you hide locals inside the processes as variables. Symbolic names for the various constants would help readability and maintainability, I'd suggest, and (see your latter question) no, you don't want 'sw' in the clocked process's sensitivity list - but it shouldn't do any harm, because the whole body of the process runs only on rising_edge. Carefully check out the synthesis report. My first suspicion would be that the clk_100us signal is not being routed on a clock net. Possibly it hasn't been recognized as a clock because of that bad sensitivity list - I don't know - but if the tools didn't recognise the clock then the results you see are not too surprising because you'll get clock skew between the various FFs of the second process's counter and this can give rise to hold time violations. As a sanity check on this, consider reworking the clock divider to generate a clock enable so that you can clock both processes from the common 50MHz. Also, note that your "if counter=0" tests (in both processes) are testing NEXT-STATE values of the counter, and therefore will give slower logic than if you had tested "counter" before decrementing it. Try this: prescale_to_100us: process (clk_50M) variable counter: natural range 0 to 2500 := 1; begin if counter=1 then -- test first, tests current state counter := 2500; enable_100us <= '1'; else counter := counter-1; enable_100us <= '0'; end if; end process; drive_digits: process (clk_50M) constant Scan_Count : natural := 300; variable counter : natural range 0 to Scan_Count := 1; variable digs7_var : std_logic_vector (3 downto 0) := "1110"; begin if (rising_edge(clk_50M)) then if (enable_100us) then -- same logic as before. Don't try to roll the two "if" tests into a single test; some synthesis tools are rather picky about keeping the rising_edge test in a separate statement. >BTW, do I need "sw" in the sensitivity list for drive_digits? No, definitely not - see above. Hope this helps, but I fear it may not... -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!c21g2000vba.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Sun, 10 Oct 2010 13:40:46 -0700 (PDT) Organization: http://groups.google.com Lines: 115 Message-ID: <9d336d82-5244-41ad-9f4b-605a4efa0290@c21g2000vba.googlegroups.com> References: <5524b65l6pamsmqrhvp8vun412koqvdguu@4ax.com> NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286743246 12683 127.0.0.1 (10 Oct 2010 20:40:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 Oct 2010 20:40:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c21g2000vba.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4203 On Oct 10, 11:46=A0am, Jonathan Bromley wrote: > On Sun, 10 Oct 2010 09:38:00 -0700 (PDT), KK6GM wrote: > >I'm a software guy with a decent hardware understanding, just > >beginning to teach myself VHDL and FPGAs. =A0I've got a Nexys2 board and > >in playing with the multiplexed 7-seg displays I've run across a > >situation where my code to delay and switch between digits runs for > >some count values and doesn't run for others. =A0Here's the code section > >in question: > > > =A0 =A0prescale_to_100us: process (clk_50M) > > =A0 =A0 =A0 =A0 =A0 =A0variable counter : natural range 0 to 2500 :=3D = 1; > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (rising_edge(clk_50M)) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0counter :=3D counter - 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (counter =3D 0) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0counter :=3D 250= 0; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clk_100us <=3D n= ot clk_100us; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > > =A0 =A0drive_digits: process (clk_100us, sw) > > =A0 =A0 =A0 =A0 =A0 =A0constant Scan_Count : natural :=3D 300; > > =A0 =A0 =A0 =A0 =A0 =A0variable counter : natural range 0 to Scan_Count= :=3D 1; > > =A0 =A0 =A0 =A0 =A0 =A0variable digs7_var : std_logic_vector (3 downto = 0) :=3D "1110"; > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (rising_edge(clk_100us)) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0counter :=3D counter - 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (counter =3D 0) then > > ........ reload scan counter, update multiplex output > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > >This code consistently works for e.g. Scan_Count =3D 300, 302 or 305, > >but fails (no multiplexing, just a solid 0 in the LSD position) for > >301, 303 and 304. =A0Nothing else is changed, just the value of > >Scan_Count. =A0Naturally I assume that the problem lies in my code, but > >I have no idea what it might be. =A0Any ideas? =A0Thanks. > > Your code looks broadly OK to me (have you simulated it?). =A0 > It's good that you hide locals inside the processes as variables. =A0 > Symbolic names for the various constants would help readability > and maintainability, I'd suggest, and (see your latter question) > no, you don't want 'sw' in the clocked process's sensitivity > list - but it shouldn't do any harm, because the whole body > of the process runs only on rising_edge. > > Carefully check out the synthesis report. =A0My first suspicion > would be that the clk_100us signal is not being routed on a > clock net. =A0Possibly it hasn't been recognized as a clock > because of that bad sensitivity list - I don't know - but > if the tools didn't recognise the clock then the results > you see are not too surprising because you'll get clock > skew between the various FFs of the second process's > counter and this can give rise to hold time violations. > > As a sanity check on this, consider reworking the clock > divider to generate a clock enable so that you can clock > both processes from the common 50MHz. > > Also, note that your "if counter=3D0" tests (in both > processes) are testing NEXT-STATE values of the counter, > and therefore will give slower logic than if you had > tested "counter" before decrementing it. =A0Try this: > > =A0 prescale_to_100us: process (clk_50M) > =A0 =A0 variable counter: natural range 0 to 2500 :=3D 1; > =A0 begin > =A0 =A0 if counter=3D1 then =A0-- test first, tests current state > =A0 =A0 =A0 counter :=3D 2500; > =A0 =A0 =A0 enable_100us <=3D '1'; > =A0 =A0 else > =A0 =A0 =A0 counter :=3D counter-1; > =A0 =A0 =A0 enable_100us <=3D '0'; > =A0 =A0 end if; > =A0 end process; > > =A0 drive_digits: process (clk_50M) > =A0 =A0 constant Scan_Count : natural :=3D 300; > =A0 =A0 variable counter : natural range 0 to Scan_Count :=3D 1; > =A0 =A0 variable digs7_var : std_logic_vector (3 downto 0) :=3D "1110"; > =A0 begin > =A0 =A0 if (rising_edge(clk_50M)) then > =A0 =A0 =A0 if (enable_100us) then > =A0 =A0 =A0 =A0 -- same logic as before. > > Don't try to roll the two "if" tests into a single test; > some synthesis tools are rather picky about keeping the > rising_edge test in a separate statement. > > >BTW, do I need "sw" in the sensitivity list for drive_digits? > > No, definitely not - see above. > > Hope this helps, but I fear it may not... > -- > Jonathan Bromley- Hide quoted text - > > - Show quoted text - That did indeed solve the problem - many thanks! Clearly I need to get a better understanding of the proper idioms for good, reliable clocking. Guess I'm lucky to have stumbled across this whole issue early on. Mike From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!t7g2000vbj.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Reset Logic Function Date: Sun, 10 Oct 2010 23:19:03 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: References: <930fff1d-4641-46db-ba30-d792e00c04d7@w15g2000pro.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286777943 14321 127.0.0.1 (11 Oct 2010 06:19:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Oct 2010 06:19:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t7g2000vbj.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.10) Gecko/20100915 Ubuntu/10.04 (lucid) Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4204 On 8 Okt., 10:53, We Ech Dee Ell wrote: > Hi All, > > I have some code that consistently gives the problem of "Reset Logic > Function", "Multiple Resets" etc. with some design checking tool for > synthesis. > > The code is: > ------------------ > > =A0write_enable : PROCESS (Clock) > =A0 BEGIN > =A0 =A0 IF (Clock'EVENT) AND (Clock =3D '1') THEN > =A0 =A0 =A0 IF ( Reset =3D '1' ) THEN > =A0 =A0 =A0 =A0 =A0 register_we_REG1_i1 <=3D '0'; > =A0 =A0 =A0 =A0 =A0 Wack <=3D '0'; > =A0 =A0 =A0 ELSIF (WStrobe =3D '1') THEN > =A0 =A0 =A0 =A0 =A0 register_we_REG1_i1 <=3D register_select(0); > =A0 =A0 =A0 =A0 =A0 Wack <=3D '1'; > =A0 =A0 =A0 END IF; > =A0 =A0 END IF; > =A0 END PROCESS write_enable; > > =A0---------------------------------------------------------------- > =A0 reg_REG1_field16_i1 : PROCESS (Clock) > =A0 BEGIN > =A0 =A0 IF (Clock'EVENT) AND (Clock =3D '1') THEN > =A0 =A0 =A0 IF Reset =3D '1' THEN > =A0 =A0 =A0 =A0 field16_i1 <=3D '1'; > =A0 =A0 =A0 ELSIF ( register_we_REG1_i1 =3D '1' ) THEN > =A0 =A0 =A0 =A0 field16_i1 <=3D Wdata(16); > =A0 =A0 =A0 END IF; > =A0 =A0 END IF; > =A0 END PROCESS reg_REG1_field16_i1; > > Can someone please help? > Change is sensitivity lists is not allowed. Only synchronous processes > are allowed. > > Thanks a lot in advance! Hi, the code shows some nice examples for FFs with sync. Reset and Clock Enable functions. Only thing that looks strange to me is the Wack signal, that never returns to '0', unless the FF gets resetted. Once written to the FF, the write acknowledge never becomes inactive? If not really intended an else branch could fix this. So, what about the mentioned reset problem? What messages do you see, printed by what kind of tool? I can't see a connection between your code fragments and the very common prased problems. Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j19g2000vbh.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Mon, 11 Oct 2010 05:48:10 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <4225d09b-5a2f-481d-9f59-a8967f9c74f2@j19g2000vbh.googlegroups.com> References: NNTP-Posting-Host: 188.28.208.227 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286801290 17946 127.0.0.1 (11 Oct 2010 12:48:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Oct 2010 12:48:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j19g2000vbh.googlegroups.com; posting-host=188.28.208.227; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.62,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4205 In some of my code I had a divided clock. I found that it was easier to detect and latch the end count 1 cycle before into a single bit and then use that single bit on the next cycle to do the clock inversion. This speeded up the design by over 4 times. I think this is because the clock enable of the divided clock FF was the output of an FF instead of 2 layers of 4LUTs. From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t7g2000vbj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Mon, 11 Oct 2010 09:42:43 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: <8697a35b-aa64-4393-9ed0-f9552ec2ceab@t7g2000vbj.googlegroups.com> References: NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286815363 8826 127.0.0.1 (11 Oct 2010 16:42:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Oct 2010 16:42:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t7g2000vbj.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4206 As has been mentioned, your code compares count to zero after it has been decremented, meaning both combinatorial circuits must settle in series before you get a valid answer, and that takes more time than would otherwise be necessary. There are a couple of ways around this. The first is to check and then only decrement if safe to do so: if counter = 0 then -- parallel comparison of each bit counter := half_100us_period; -- use a constant (hint: 2500 - 1)! clk_100us <= not clk_100us; else counter := counter - 1; end if; This method compares the output of the count register to zero, before it is decremented, thus avoiding the serial delays of decrement and compare within one clock cycle. The second is related to this, but uses a trait of integer arithmetic to avoid the parallel comparison of the count to zero: if count - 1 < 0 then -- checked the carry bit count := half_100us_period; clk_100us <= not clk_100us; else count := count - 1; -- share decrementer with the comparison end if; The above ONLY WORKS WITH INTEGER SUBTYPE COUNTERS! No matter what the integer subtype range of the operands, the - operator (or any other integer operator) returns a full integer range result. That is not an error. It is only an error if you try to store the result in a subtype, and it is outside of that subtype's range. So, even though count cannot be less than zero, count - 1 can be less than zero, and can be used to check the carry bit. What's more, the synthesis tool will share the two decrementers (the one for the comparison, and the one for the counting action), resulting in only one decrementer being produced. In real life, if the counter is plenty fast (and/or the clock is plenty slow), use the method that is most easily understood by the reader, that also still meets timing. That reader could be a reviewer, a verification engineer, a test engineer, or another developer that needs to update the design, and could even be you in another 6 weeks after you have forgotten why you did it the way you did. Andy From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q28g2000prb.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Mon, 11 Oct 2010 18:56:54 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <17a5e439-f36c-47c8-852b-6d43a145a318@q28g2000prb.googlegroups.com> References: <8697a35b-aa64-4393-9ed0-f9552ec2ceab@t7g2000vbj.googlegroups.com> NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286848614 9637 127.0.0.1 (12 Oct 2010 01:56:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Oct 2010 01:56:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q28g2000prb.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4207 On Oct 11, 9:42=A0am, Andy wrote: > As has been mentioned, your code compares count to zero after it has > been decremented, meaning both combinatorial circuits must settle in > series before you get a valid answer, and that takes more time than > would otherwise be necessary. Right, this is obvious now that it has been pointed out to me. :) To ask a question related to my OP, what is the preferred method (or methods) of driving FFs at a rate derived from a master clock? For example, suppose I want to clock some FFs at 1kHz from a 50MHz clock. Is it to use the 1-clock-out-of-N enable as was discussed above? Are there other "correct" ways as well? I guess the question is, do FFs being updated at rates of MasterClock/N normally have their clock inputs driven by MasterClock with suitable enables, or is it common to actually derive other clocks from MasterClock? From newsfish@newsfish Fri Dec 24 22:55:19 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f25g2000yqc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Mon, 11 Oct 2010 21:07:58 -0700 (PDT) Organization: http://groups.google.com Lines: 55 Message-ID: <529db332-ae4d-4745-be52-ab6739f57dbc@f25g2000yqc.googlegroups.com> References: <8697a35b-aa64-4393-9ed0-f9552ec2ceab@t7g2000vbj.googlegroups.com> <17a5e439-f36c-47c8-852b-6d43a145a318@q28g2000prb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1286856478 10915 127.0.0.1 (12 Oct 2010 04:07:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Oct 2010 04:07:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f25g2000yqc.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4208 On Oct 11, 9:56=A0pm, KK6GM wrote: > > To ask a question related to my OP, what is the preferred method (or > methods) of driving FFs at a rate derived from a master clock? =A0 In FPGAs or CPLDs, generate a clock enable. In ASICs, an actual gated clock might be considered appropriate. The reason gated clocks are generally not acceptable in FPGAs or CPLDs is because then the design becomes sensitive to *minimum* propogation delays through logic due to the inevitable need to reliably transfer signals from one clock domain to the other, but there are no resources to control this delay. This will create hold time issues where the signals from one clock domain can switch prior to and be accepted by the gated clock one clock cycle 'early' or can cause incorrect logic because hold times were violated. While a timing analysis will reveal the problem, the only recourse is to change a random number seed and try to re-route and get something different and hope. Every iteration of the design will require this same sort of hand holding...most people have better things to do with their time. > For > example, suppose I want to clock some FFs at 1kHz from a 50MHz clock. > Is it to use the 1-clock-out-of-N enable as was discussed above? =A0 Yes > Are > there other "correct" ways as well? =A0 If the division is fixed and known at design time, then there are better forms of counters. As an example, an LFSR counter would minimize the amount of logic needed to create the counter. Another technique is to break the counter up into smaller pieces to improve the clock cycle performance. Consider a 24 bit counter. Rather than having to decode all 24 bits to decide that the count has rolled over, another technique would be to break the counter up into two (or three) sections of 8-12 bits. When the 'more significant' bits sections counts down it sets a flop. Then the final rollover occurs when all higher order sections have their bit set, and the 'least significant' bit section also counts down to 0. > I guess the question is, do FFs > being updated at rates of MasterClock/N normally have their clock > inputs driven by MasterClock with suitable enables, In CPLDs and FPGAs...yes > or is it common to > actually derive other clocks from MasterClock? In ASICs...yes (clock enables also work here also) Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.146.MISMATCH!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 12 Oct 2010 05:41:44 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Tue, 12 Oct 2010 11:50:33 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <8697a35b-aa64-4393-9ed0-f9552ec2ceab@t7g2000vbj.googlegroups.com> <17a5e439-f36c-47c8-852b-6d43a145a318@q28g2000prb.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 63 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-yg8gbNwK43SVkSEjVnYU+v4I120kmQP9n2SS1uKl03467C6PIPJGA6+9CrjF21RG61km1/MjDQwxXg+!EbUEHECDea7m//szAFLKu/IuGG3WzzH9RHBtDoBKhXJZKdMbyFhoUBIt3p0GIOhNdBQvF/XOixTg!7rdO X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4505 Xref: feeder.eternal-september.org comp.lang.vhdl:4209 On Mon, 11 Oct 2010 18:56:54 -0700 (PDT), KK6GM wrote: >On Oct 11, 9:42 am, Andy wrote: >> As has been mentioned, your code compares count to zero after it has >> been decremented, meaning both combinatorial circuits must settle in >> series before you get a valid answer, and that takes more time than >> would otherwise be necessary. > >Right, this is obvious now that it has been pointed out to me. :) > >To ask a question related to my OP, what is the preferred method (or >methods) of driving FFs at a rate derived from a master clock? For >example, suppose I want to clock some FFs at 1kHz from a 50MHz clock. >Is it to use the 1-clock-out-of-N enable as was discussed above? Are >there other "correct" ways as well? I guess the question is, do FFs >being updated at rates of MasterClock/N normally have their clock >inputs driven by MasterClock with suitable enables, or is it common to >actually derive other clocks from MasterClock? In FPGAs it is normal to use the 1-of-N clock enable. If your design meets timings without any struggle that way (as I would expect at 50MHz), forget about going any further and concentrate your energy elsewhere. It's simplest; it's clean, and life is short. Otherwise... If you can identify signal paths that are entirely within the slow domain (i.e. both source and dest run off the enable) you can add multi-cycle timing constraints to them, so that P&R doesn't waste effort improving their speed. Then it can concentrate on improving what needs to be fast. (If you don't follow me here, try increasing your target clock rate 10MHz at a time. You will probably see P&R time explode at some point...) If you have a real reason for wanting to reduce the clock speed there are ways to do it. The main reason would be to reduce power consumption ( e.g. for battery operated equipment) or device temperature in more complex designs. But recognise that FPGAs don't offer as much scope for power saving through redesign as ASICS. There are low power device families, though. The canonical way to change clock speed is to use the FPGA's clock generation blocks (DCM in Xilinx, PLL in Altera or newer Xilinx). These offer frequency synthesis options including programmable division ratios, variable phase shift, automatically align the divided (or multiplied!) clock edges with the source clock, and so on. But more importantly, the timing analysis tools know about them. So timing constraints are correctly propagated through the DCM with appropriate margins for jitter and error, and output clocks will route using clock resources. Contrast this with the mess you get simply dividing a clock yourself. Typically you wouldn't want to change the source clock frequency by more than an order of magnitude this way (cascading DCMs is a BIG no-no; each adds its own jitter until the last one can't achieve lock) so you might divide your clock down to 1 or 10MHz and use 1-of-n enables from there. Beyond that point, the static power consumption will dominate, so there is no further saving. - Brian From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!q3g2000pra.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Re: Why is this code persnickety? Date: Tue, 12 Oct 2010 20:50:51 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: References: <8697a35b-aa64-4393-9ed0-f9552ec2ceab@t7g2000vbj.googlegroups.com> <17a5e439-f36c-47c8-852b-6d43a145a318@q28g2000prb.googlegroups.com> NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1286941852 22325 127.0.0.1 (13 Oct 2010 03:50:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Oct 2010 03:50:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q3g2000pra.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4211 OK, things are much clearer now. Thanks for all the good info. Mike From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Generating JEDEC for GAL programming? From: Merciadri Luca Organization: ULg Date: Wed, 13 Oct 2010 11:55:20 +0200 Message-ID: <877hhmzabb.fsf@merciadriluca-eee.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:m7Y3OMY1YlkjyS3ohp4oJsUgGyY= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 26 NNTP-Posting-Host: 139.165.240.119 X-Trace: news.sunsite.dk DXC=F`7DZlE?o6n`;IS0i7S8TaYSB=nbEKnkk[R[7PZBi8onZEVG4aK_]RP;@H2onFf7K8NJeTca=K iEYEARECAAYFAky1ggcACgkQM0LLzLt8MhynlgCeOADjmIVnNdHB1N8EAy7pmQWJ lrUAn1txx0EtfFXNuFjPZAhGAGFiBAKE =xsvC -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? From: Merciadri Luca Organization: ULg Date: Wed, 13 Oct 2010 12:00:11 +0200 Message-ID: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:Yf7ncT928rzUjgLjiS3Tcq2q9UU= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 24 NNTP-Posting-Host: 139.165.240.119 X-Trace: news.sunsite.dk DXC=SF0H1olhd8lbJlfT[;@_ShYSB=nbEKnkk[R[7PZBi8onZEVG4aK_]RP;@H2onFf7K8NJeTca=K iEYEARECAAYFAky1gysACgkQM0LLzLt8Mhw6CwCfZET0USUWaW3NV2oCDoFMLwat /OsAn1Yu0QL668QAuAHHoQkveFIkW3dr =a9BT -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? Date: Wed, 13 Oct 2010 23:11:07 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <1362a426-7385-40b4-bcd9-c6d8abd8c6c6@k22g2000yqh.googlegroups.com> References: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287036667 18754 127.0.0.1 (14 Oct 2010 06:11:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 06:11:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.10) Gecko/20100915 Ubuntu/10.04 (lucid) Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4214 On 13 Okt., 12:00, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Are there any differences between 'Synplicity VHDL compiler, v1.0, > b. 074R' and GHDL compiler? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > When making your choices in life, do not forget to live. (Samuel > =A0Johnson) > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAky1gysACgkQM0LLzLt8Mhw6CwCfZET0USUWaW3NV2oCDoFMLwat > /OsAn1Yu0QL668QAuAHHoQkveFIkW3dr > =3Da9BT > -----END PGP SIGNATURE----- Hi, Synplicity(now owned by Synopsys) tools (namely Synplify) are for synthesis. They have a comercial license. GHDL is an open source simulation tool. Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j18g2000yqd.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Generating JEDEC for GAL programming? Date: Wed, 13 Oct 2010 23:13:53 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: References: <877hhmzabb.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287036833 15999 127.0.0.1 (14 Oct 2010 06:13:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 06:13:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000yqd.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.10) Gecko/20100915 Ubuntu/10.04 (lucid) Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4215 On 13 Okt., 11:55, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > For a project, I know that I need to generate, among others, JEDEC > code to program on a GAL. I use GHDL as a front-end compiler for VHDL, > but I can't find any way on how to generate JEDEC code. Is there any > simple solution, or simply something that I am misunderstanding? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > Live as if you were to die tomorrow; learn as if you were to live > =A0forever. (Mahatma Gandhi) > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAky1ggcACgkQM0LLzLt8MhynlgCeOADjmIVnNdHB1N8EAy7pmQWJ > lrUAn1txx0EtfFXNuFjPZAhGAGFiBAKE > =3DxsvC > -----END PGP SIGNATURE----- Hi, GHDL is just for simulation. You need a tool for synthesis and implementation that targets GALS. Only vendor that still offers both is Lattice, to my knowledge. The support for GALs should be available in their free software and genrerates the JEDEC files too. Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? References: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> <1362a426-7385-40b4-bcd9-c6d8abd8c6c6@k22g2000yqh.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Thu, 14 Oct 2010 09:13:40 +0200 Message-ID: <87fww9mel7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:QqLF4gSOA+DeVDowI4k3YDFGi2g= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 57 NNTP-Posting-Host: 62.197.101.67 X-Trace: news.sunsite.dk DXC=dXEJI01jRUJc5QH[6O^X]LYSB=nbEKnkK[O0<:LjfBnLZEVG4AK_]RP;@H2oNCV6C80:GO?F;Q=HHGJm writes: > On 13 Okt., 12:00, Merciadri Luca > wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> Are there any differences between 'Synplicity VHDL compiler, v1.0, >> b. 074R' and GHDL compiler? >> >> Thanks. >> - -- >> Merciadri Luca >> Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ >> - -- >> >> When making your choices in life, do not forget to live. (Samuel >>  Johnson) >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.9 (GNU/Linux) >> Comment: Processed by Mailcrypt 3.5.8 >> >> iEYEARECAAYFAky1gysACgkQM0LLzLt8Mhw6CwCfZET0USUWaW3NV2oCDoFMLwat >> /OsAn1Yu0QL668QAuAHHoQkveFIkW3dr >> =a9BT >> -----END PGP SIGNATURE----- > > Hi, > Synplicity(now owned by Synopsys) tools (namely Synplify) are for > synthesis. They have a comercial license. > GHDL is an open source simulation tool. Yes, but do they do the same things? Is one more limited than another? > > Have a nice synthesis Thanks! - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- - -- You cannot escape the responsibility of tomorrow by evading it today. (Abraham Lincoln) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAky2raQACgkQM0LLzLt8MhxFIwCgkAwB6sjJHiXH6kN49j0uQPFb uJMAn1nsFLoNEybh5Ji/9A3tAwOXDMwa =oAwG -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:20 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.newsland.it!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!ecngs!feeder2.ecngs.de!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Generating JEDEC for GAL programming? References: <877hhmzabb.fsf@merciadriluca-eee.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Thu, 14 Oct 2010 09:14:16 +0200 Message-ID: <87bp6xmek7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:++M7xerFc5rmqmOXsOprjx7XSYw= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 56 NNTP-Posting-Host: 62.197.101.67 X-Trace: news.sunsite.dk DXC=dXEJI01jRUZlG4QK_]RP;@H2o^CV6C80:GO?V;Q=HHGJm writes: > On 13 Okt., 11:55, Merciadri Luca > wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> For a project, I know that I need to generate, among others, JEDEC >> code to program on a GAL. I use GHDL as a front-end compiler for VHDL, >> but I can't find any way on how to generate JEDEC code. Is there any >> simple solution, or simply something that I am misunderstanding? >> >> Thanks. >> - -- >> Merciadri Luca >> Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ >> - -- >> >> Live as if you were to die tomorrow; learn as if you were to live >>  forever. (Mahatma Gandhi) >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.9 (GNU/Linux) >> Comment: Processed by Mailcrypt 3.5.8 >> >> iEYEARECAAYFAky1ggcACgkQM0LLzLt8MhynlgCeOADjmIVnNdHB1N8EAy7pmQWJ >> lrUAn1txx0EtfFXNuFjPZAhGAGFiBAKE >> =xsvC >> -----END PGP SIGNATURE----- > > Hi, > GHDL is just for simulation. > You need a tool for synthesis and implementation that targets GALS. > Only vendor that still offers both is Lattice, to my knowledge. > The support for GALs should be available in their free software and > genrerates the JEDEC files too. Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- What doesn't kill you will make you stronger. (Friedrich Nietzsche) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAky2rcgACgkQM0LLzLt8Mhyc+ACeM09qmbrmF44IZCf7gJK8Wub0 M0sAnjDVyCQxsgvSP6vH6SEWWGAREHkj =HzTr -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 14 Oct 2010 09:16:21 +0200 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.7) Gecko/20100111 Thunderbird/3.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: change with sums and shifts Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.246.68.219 X-Trace: 1287040574 reader3.news.tin.it 21359 95.246.68.219:10664 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4218 hello guys! I 've a question how can i change this istructions in my structural with simple sums and shifts operations? pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); thank you in advance From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!just2write2.myftp.org!aioe.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!d18g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts Date: Thu, 14 Oct 2010 00:42:54 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <754103c1-bf3e-4998-b707-804b9ca256b8@d18g2000yqc.googlegroups.com> References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287042174 32597 127.0.0.1 (14 Oct 2010 07:42:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 07:42:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d18g2000yqc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4219 On Oct 14, 8:16=A0am, tommy wrote: > hello guys! > > I 've a question how can i change this istructions in my structural with > simple sums and shifts operations? > > pOut <=3D CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + = 1); > > pOut <=3D CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); > > thank you in advance for 2* pOut <=3D pIn & '0'; for 2* + 1; pOut <=3D pIn & '1'; I see you're using std_logic_unsigned/arith. Stop doing this NOW, and replace it all with numeric_std. It is a real standard. std_logic_unsigned is a fake standard that some weirdos made up 20 years ago. From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts Date: Thu, 14 Oct 2010 11:33:10 +0100 Organization: Parallel Points Lines: 25 Message-ID: References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net CM+4tBPhLsfqf4fozXmuoACdzUubQAlQnrmdBM36plL6ddxzU= Cancel-Lock: sha1:b6qqIO8xf8etVXEvfooO9RDg9OA= sha1:qO+91oFOkI3IStM7o9cm9o03lIY= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4220 tommy writes: > hello guys! > > I 've a question how can i change this istructions in my structural > with simple sums and shifts operations? > > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); > > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); > > thank you in advance > First, use the numeric_std libraries instead of conv_*: http://www.parallelpoints.com/node/3 Second, why do you want to change to sums and shifts? Does the code not do what you want? Cheers, Martin -- From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n7g2000vbo.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? Date: Thu, 14 Oct 2010 04:29:32 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <5eb8a71d-d711-416b-9bba-847631bf6a37@n7g2000vbo.googlegroups.com> References: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> <1362a426-7385-40b4-bcd9-c6d8abd8c6c6@k22g2000yqh.googlegroups.com> <87fww9mel7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287055772 16839 127.0.0.1 (14 Oct 2010 11:29:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 11:29:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n7g2000vbo.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.6.30 Version/10.62,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4221 On Oct 14, 8:13=A0am, Merciadri Luca wrote: > > Yes, but do they do the same things? Is one more limited than another? > They will certainly be different. Finding out what the specific differences, limitations and bugs are may be near impossible though! In theory the VHDL LRM (Language Reference Manual) provides sufficient information for all compilers to behave identically (assuming they are LRM compliant) regardless of the underlying implementation details. Tool vendors will usually claim compliance to a particular version of the standard with certain exceptions. AFAIK no tool vendors fully support VHDL-2008 yet. In practice, you will find that certain tools require work-arounds to navigate deficiencies and bugs. The way the Xilinx tools handle libraries and record types appears to be a poorly executed afterthought, though the new parser improves matters slightly. All tools have their own niggles and foibles to discover - not always a fun experience. Chris From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!g18g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? Date: Thu, 14 Oct 2010 05:03:44 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <0c5f88ac-cf63-48ce-b0fc-0a4ad42c856d@g18g2000vbn.googlegroups.com> References: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> <1362a426-7385-40b4-bcd9-c6d8abd8c6c6@k22g2000yqh.googlegroups.com> <87fww9mel7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.62.143.97 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287057824 1546 127.0.0.1 (14 Oct 2010 12:03:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 12:03:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g18g2000vbn.googlegroups.com; posting-host=192.62.143.97; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4222 > > Hi, > > Synplicity(now owned by Synopsys) tools (namely Synplify) are for > > synthesis. They have a comercial license. > > GHDL is an open source simulation tool. > > Yes, but do they do the same things? Is one more limited than another? > > > Have a nice synthesis > Perhaps take 30 minutes and read up about what the different tools do. One hint: Synplify and GHDL perform completely different tasks. The only common element is that the input is VHDL. KJ From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.newsland.it!nntp.infostrada.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 14 Oct 2010 14:50:46 +0200 From: Sonia newsgroup User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> <754103c1-bf3e-4998-b707-804b9ca256b8@d18g2000yqc.googlegroups.com> In-Reply-To: <754103c1-bf3e-4998-b707-804b9ca256b8@d18g2000yqc.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 59 Message-ID: <4cb6fca0$0$10757$4fafbaef@reader2.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 87.13.129.254 X-Trace: 1287060640 reader2.news.tin.it 10757 87.13.129.254:11995 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4223 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BombUnit is generic ( bitWidth : integer range 1 to 128 := 16 ); port ( input : in std_logic_vector(bitWidth-1 downto 0); output : out std_logic; nOut : out std_logic_vector(bitWidth-1 downto 0); pIn : in std_logic_vector( bitWidth/2 downto 0); pOut : out std_logic_vector( bitWidth/2 downto 0) ); end BombUnit; architecture Behavioral of BombUnit is begin main : process (input, pIn) variable to_comp : std_logic_vector(bitWidth/2 downto 0); begin to_comp := SHL(pIn, "10"); to_comp := to_comp + 1; if (input >= to_comp) then output <= '1'; nOut <= input - to_comp; pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); else output <= '0'; nOut <= input; pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); end if; end process main; end Behavioral; ----------------------- sorry i don't understood, this is my code, how can I must modify it with your help? thank you in advance From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u13g2000vbo.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts Date: Thu, 14 Oct 2010 08:12:58 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287069178 31593 127.0.0.1 (14 Oct 2010 15:12:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 15:12:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u13g2000vbo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4224 On Oct 14, 5:33=A0am, Martin Thompson wrote: > tommy writes: > > hello guys! > > > I 've a question how can i change this istructions in my structural > > with simple sums and shifts operations? > > > pOut <=3D CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 = + 1); > > > pOut <=3D CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1)= ; > > > thank you in advance > > First, use the numeric_std libraries instead of conv_*: > > http://www.parallelpoints.com/node/3 > > Second, why do you want to change to sums and shifts? =A0Does the code > not do what you want? > > Cheers, > Martin > > -- It would be cleaner if you used numeric_std, but I have seen synopsys refuse to synthesize mult, div or mod of numeric_std.unsigned by integral powers of two (many years ago, so they may have fixed it). Unless this is a homework assignment, and you have been directed to code it with a shift and a sum, then any synthesis tool worth its salt will in fact implement your code as a shift and sum (actually shift and stuff). You don't have to do anything to get it. But here it is anyway: if input >=3D to_comp then output <=3D '1'; nOut <=3D input - to_comp; pOut <=3D pIn(bitwidth - 2 downto 0) & '1'; else output <=3D '0'; nOut <=3D input; pOut <=3D pIn(bitwidth - 2 downto 0) & '0'; end if; Unless directed to do otherwise (sometimes by a poor tool that won't work unless you spell it out for it), I would use the form that is easiest to understand the BEHAVIOR you want, not the implementation you want. Does the algorithm need to do a shift and stuff, or does it need to do a scale and add? Andy From newsfish@newsfish Fri Dec 24 22:55:21 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.newsland.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 14 Oct 2010 17:22:16 +0200 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.7) Gecko/20100111 Thunderbird/3.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 60 Message-ID: <4cb72020$0$23149$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.246.68.219 X-Trace: 1287069728 reader1.news.tin.it 23149 95.246.68.219:11038 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4225 Il 14/10/2010 17:12, Andy ha scritto: > On Oct 14, 5:33 am, Martin Thompson wrote: >> tommy writes: >>> hello guys! >> >>> I 've a question how can i change this istructions in my structural >>> with simple sums and shifts operations? >> >>> pOut<= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); >> >>> pOut<= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); >> >>> thank you in advance >> >> First, use the numeric_std libraries instead of conv_*: >> >> http://www.parallelpoints.com/node/3 >> >> Second, why do you want to change to sums and shifts? Does the code >> not do what you want? >> >> Cheers, >> Martin >> >> -- > > > It would be cleaner if you used numeric_std, but I have seen synopsys > refuse to synthesize mult, div or mod of numeric_std.unsigned by > integral powers of two (many years ago, so they may have fixed it). > > Unless this is a homework assignment, and you have been directed to > code it with a shift and a sum, then any synthesis tool worth its salt > will in fact implement your code as a shift and sum (actually shift > and stuff). You don't have to do anything to get it. > > But here it is anyway: > > if input>= to_comp then > output<= '1'; > nOut<= input - to_comp; > pOut<= pIn(bitwidth - 2 downto 0)& '1'; > else > output<= '0'; > nOut<= input; > pOut<= pIn(bitwidth - 2 downto 0)& '0'; > end if; > > Unless directed to do otherwise (sometimes by a poor tool that won't > work unless you spell it out for it), I would use the form that is > easiest to understand the BEHAVIOR you want, not the implementation > you want. Does the algorithm need to do a shift and stuff, or does it > need to do a scale and add? > > Andy it's a strucutral architecture of sqrt, I've done also a behavioral for sqrt, and my test-bench check if the result is the same as for strucutral and for behav.. anyway i try your solution now! thanks From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.panservice.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 14 Oct 2010 17:33:20 +0200 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.7) Gecko/20100111 Thunderbird/3.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 68 Message-ID: <4cb722b8$0$23140$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.246.68.219 X-Trace: 1287070392 reader1.news.tin.it 23140 95.246.68.219:11103 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4226 Il 14/10/2010 17:12, Andy ha scritto: > On Oct 14, 5:33 am, Martin Thompson wrote: >> tommy writes: >>> hello guys! >> >>> I 've a question how can i change this istructions in my structural >>> with simple sums and shifts operations? >> >>> pOut<= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); >> >>> pOut<= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); >> >>> thank you in advance >> >> First, use the numeric_std libraries instead of conv_*: >> >> http://www.parallelpoints.com/node/3 >> >> Second, why do you want to change to sums and shifts? Does the code >> not do what you want? >> >> Cheers, >> Martin >> >> -- > > > It would be cleaner if you used numeric_std, but I have seen synopsys > refuse to synthesize mult, div or mod of numeric_std.unsigned by > integral powers of two (many years ago, so they may have fixed it). > > Unless this is a homework assignment, and you have been directed to > code it with a shift and a sum, then any synthesis tool worth its salt > will in fact implement your code as a shift and sum (actually shift > and stuff). You don't have to do anything to get it. > > But here it is anyway: > > if input>= to_comp then > output<= '1'; > nOut<= input - to_comp; > pOut <= pIn(bitwidth - 2 downto 0) & '0'; > else > output<= '0'; > nOut<= input; > pOut<= pIn(bitwidth - 2 downto 0)& '0'; > end if; > > Unless directed to do otherwise (sometimes by a poor tool that won't > work unless you spell it out for it), I would use the form that is > easiest to understand the BEHAVIOR you want, not the implementation > you want. Does the algorithm need to do a shift and stuff, or does it > need to do a scale and add? > > Andy I think you wrong when you says (bitwidth - 2 downto 0) is correct --> (bitwdth/2 downto 0). Anyway i tested and in my simulation i can't see any result after this modification. This is my test-bench http://pastebin.com/EDe8aWtU i have a loop for calculate first 100 sqrt root of numbers, does i have to change this input <= CONV_STD_LOGIC_VECTOR(i, 16); ? thanks in advnace From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!o34g2000vbl.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts Date: Thu, 14 Oct 2010 09:48:31 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> <4cb722b8$0$23140$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287074911 15424 127.0.0.1 (14 Oct 2010 16:48:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Oct 2010 16:48:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o34g2000vbl.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4227 My bad, it should be pin(bitwidth / 2 - 1 downto 0). If the concatenation of the portion of pin and the 0 or 1 are to fit in pout, then you must reduce the size of pin by one, and on the left end, thus bitwidth / 2 - 1 is the MSB of the portion of Pin that is transferred to pout. Andy From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news.astraweb.com!border3.a.newsrouter.astraweb.com!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 14 Oct 2010 19:02:38 +0200 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.7) Gecko/20100111 Thunderbird/3.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> <4cb722b8$0$23140$4fafbaef@reader1.news.tin.it> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 22 Message-ID: <4cb737a6$0$23149$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.246.68.219 X-Trace: 1287075750 reader1.news.tin.it 23149 95.246.68.219:10965 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4228 Il 14/10/2010 18:48, Andy ha scritto: > My bad, it should be pin(bitwidth / 2 - 1 downto 0). If the > concatenation of the portion of pin and the 0 or 1 are to fit in pout, > then you must reduce the size of pin by one, and on the left end, thus > bitwidth / 2 - 1 is the MSB of the portion of Pin that is transferred > to pout. > > Andy Ok, now works! And is correct i think, and no need to change the istruction in test bench where i have input <= conv_std_logic_vector(i,16). I'm not sure if I've understood the problem why need to do bitwidth/2 -1. Just before of this error I have pIn(8:0) & '1' in the if statement and pIn(8:0) & 0 in else condition. Now with your correction pIn take (7:0) i.e. 8 bit. you said that i need to reduce the size by one, but why I need reduce? I can't use pOut as 9 bit? In port defintion I have pout defined like: pOut : out std_logic_vector( bitWidth/2 downto 0) Mine is only curiosity to understand well the problem. Thanks again From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler? References: <8739saza38.fsf@merciadriluca-eee.MERCIADRILUCA> <1362a426-7385-40b4-bcd9-c6d8abd8c6c6@k22g2000yqh.googlegroups.com> <87fww9mel7.fsf@merciadriluca-station.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Thu, 14 Oct 2010 22:40:19 +0200 Message-ID: <87wrpkzex8.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:omkRc9MaNRHLlcJFxhyly2zPR3M= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 21 NNTP-Posting-Host: 62.197.101.67 X-Trace: news.sunsite.dk DXC=Rc39BPflD3XOH21j@:G^6UYSB=nbEKnk[0>Me?MlWgBQZEVG4QK_]RP;@H2o^CV6C80:GO?V;Q=HHGJm iEYEARECAAYFAky3arMACgkQM0LLzLt8MhwJygCgnL6gBpJcyWEWntM3HinGKxH+ 5skAn3CTFAwSSCMiL2tWyALAFb5gJ7hK =p41Z -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!h7g2000yqn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: change with sums and shifts Date: Fri, 15 Oct 2010 08:07:24 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <87f2bdba-b20a-478f-b960-cf9c7c5117f7@h7g2000yqn.googlegroups.com> References: <4cb6ae3e$0$21359$4fafbaef@reader3.news.tin.it> <4cb722b8$0$23140$4fafbaef@reader1.news.tin.it> <4cb737a6$0$23149$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287155244 14791 127.0.0.1 (15 Oct 2010 15:07:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Oct 2010 15:07:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h7g2000yqn.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4230 On Oct 14, 12:02=A0pm, tommy wrote: > Il 14/10/2010 18:48, Andy ha scritto: > > > My bad, it should be pin(bitwidth / 2 - 1 downto 0). If the > > concatenation of the portion of pin and the 0 or 1 are to fit in pout, > > then you must reduce the size of pin by one, and on the left end, thus > > bitwidth / 2 - 1 is the MSB of the portion of Pin that is transferred > > to pout. > > > Andy > > Ok, now works! And is correct i think, and no need to change the > istruction in test bench where i have input <=3D conv_std_logic_vector(i,= 16). > I'm not sure if I've understood the problem why need to do bitwidth/2 > -1. Just before of this error I have pIn(8:0) & '1' in the if statement > and pIn(8:0) & 0 in else condition. > Now with your correction pIn take (7:0) i.e. 8 bit. you said that i need > to reduce the size by one, but why I need reduce? I can't use pOut as 9 > bit? In port defintion I have pout defined like: > > pOut : out std_logic_vector( bitWidth/2 downto 0) > > Mine is only curiosity to understand well the problem. > Thanks again Adding a single bit (with a "+") does not increase the size of the result, but concatenating (with a "&") does. If pin and pout are the same size, you cannot fit pin and an extra bit into pout. So you either need to expand pout or reduce pin by one bit, to allow room for the extra LSB. I showed reducing pin by one bit (discarded the MSB). Andy From newsfish@newsfish Fri Dec 24 22:55:22 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a37g2000yqi.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Me and Latches... Date: Sat, 16 Oct 2010 09:57:00 -0700 (PDT) Organization: http://groups.google.com Lines: 67 Message-ID: NNTP-Posting-Host: 74.92.159.213 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287248220 23624 127.0.0.1 (16 Oct 2010 16:57:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 Oct 2010 16:57:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a37g2000yqi.googlegroups.com; posting-host=74.92.159.213; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 6.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4232 Hi there, Having another problem with latches. I've referred to our last conversation about them a few months ago, but couldn't come to any conclusions about what i'm doing wrong in my project. Could someone please help? I get a warning that says: *************************************************************************** Warning (10631): VHDL Process Statement warning at part4.vhd(26): inferring latch(es) for signal or variable "s_out", which holds its previous value in one or more paths through the process *************************************************************************** My code goes: ------------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity part4 is port( SW : in unsigned(2 downto 0); KEY : in unsigned(0 downto 0); HEX0 : out unsigned(6 downto 0) ); end part4; architecture behavioral of part4 is signal s_sw : unsigned(2 downto 0); signal s_key: std_logic; signal s_out: unsigned(3 downto 0); begin s_sw <= SW; s_key <= KEY(0); hx : work.HEX port map (s_out, HEX0); process(s_sw, s_out, s_key) begin s_out <= (others => '0'); -- s_key <= (others => '0'); -- s_sw <= (others => '0'); if(s_sw(0) = '1') then s_out <= "0000"; elsif(s_key = '0') then case s_sw(2 downto 1) is when "00" => s_out <= s_out; when "01" => s_out <= s_out + 1; when "10" => s_out <= s_out + 2; when "11" => s_out <= s_out + 1; end case; end if; end process; end behavioral; ----------------------------------------------------------------------------------------------------------------------- Thanks, Malik From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Best advice for FPGA/VHDL beginner? Date: Sat, 16 Oct 2010 11:28:10 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287253690 23891 127.0.0.1 (16 Oct 2010 18:28:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 Oct 2010 18:28:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4234 As I've mentioned in another post, I'm a longtime software guy with decent hardware experience (I've designed much of the hardware I've programmed), but I've only dipped into the FPGA/VHDL waters in the past few weeks. (And I must say, I'm fascinated by it all!) So far, I've gotten advice on clocking at lower frequencies (generate 1-of-N clock enables) and I've read and understood (?) about unwanted latches. I've gotten my Nexys2 counting, multiplexing the display, debouncing buttons, simple stuff like that. So what I'm interested in is something along the lines of the top N bits of advice for beginners. These can be as simple as a single sentence ("Always do..." or "If this than that"), I can probably take it from there. Or pointers to good articles on the net. I'd really appreciate tapping into the collective knowledge here. Thanks. Mike From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i5g2000yqe.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Sat, 16 Oct 2010 12:54:49 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287258889 2856 127.0.0.1 (16 Oct 2010 19:54:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 Oct 2010 19:54:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i5g2000yqe.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4235 On Oct 16, 12:57=A0pm, laserbeak43 wrote: Kudos for - You remembered to assign a default value to s_out at the begining of the process. - It looks like you also got the sensitivity list correct. But within the case statement you have the following assignments when "00" =3D> s_out <=3D s_out; when "01" =3D> s_out <=3D s_out + 1; when "10" =3D> s_out <=3D s_out + 2; when "11" =3D> s_out <=3D s_out + 1; The combinatorial process is triggered by activity on s_out (and other signals). So when it hits any of the above statements it will cause s_out to update which will then re-trigger the process again. Any time you have a signal assignment where signal 'x' is on both the left and right hand side AND you're in either a combinatorial process or a concurrent statement...you've either created a latch or a combinatorial loop. However you view it, it's likely a design error. Some suggestions: - Don't use non-clocked processes. Too bad that the conversation that was had a few months ago that you referred to either didn't suggest this or that you didn't adhere to this advice. - Simulate your design. In this case, the simulator would likely have failed because an iteration limit was exceeded once any of the case statement assignments was hit. The iteration limit exceeded is the simulator's way of saying that after a large number of iterations, the signal activity has not settled down to a stable value so the simulator cannot advance to the next time step. - During development, use synthesis tools only to * Produce the final output file * Get a heads up on things you haven't yet got around to simulating such as * Entire blocks of code getting optomized away because of unconnected inputs ** Multiple drivers on a net. - Don't use synthesis tools for debug...the error messages aren't always that helpful. Although I must admit in this case, I found it very helpful and easy to understand where exactly to look Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j2g2000yqf.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Sat, 16 Oct 2010 21:09:40 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287288580 8517 127.0.0.1 (17 Oct 2010 04:09:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Oct 2010 04:09:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j2g2000yqf.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 6.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4236 Hello Kevin, Thanks for your reply > The combinatorial process is triggered by activity on s_out (and other > signals). =A0So when it hits any of the above statements it will cause > s_out to update which will then re-trigger the process again. Should I put the case statement in its own process? >=A0Any time you have a signal assignment where signal 'x' is on both the l= eft > and right hand side AND you're in either a combinatorial process or a > concurrent statement...you've either created a latch or a > combinatorial loop. =A0However you view it, it's likely a design error. Hmmm, do you think it'd be better if i made another signal and assigned its value to s_out? > Some suggestions: > - Don't use non-clocked processes. =A0Too bad that the conversation that > was had a few months ago that you referred to either didn't suggest > this or that you didn't adhere to this advice. I think i've heard this one before, The lab that I'm working on(the altera labs that come with the DE2) tell me to use a button as the clock though (KEY). > - Simulate your design. =A0In this case, the simulator would likely have > failed because an iteration limit was exceeded once any of the case > statement assignments was hit. =A0The iteration limit exceeded is the > simulator's way of saying that after a large number of iterations, the > signal activity has not settled down to a stable value so the > simulator cannot advance to the next time step. Would signaltap be effective? > - During development, use synthesis tools only to > * Produce the final output file > * Get a heads up on things you haven't yet got around to simulating > such as * Entire blocks of code getting optomized away because of > unconnected inputs > ** Multiple drivers on a net. > - Don't use synthesis tools for debug...the error messages aren't > always that helpful. =A0Although I must admit in this case, I found it > very helpful and easy to understand where exactly to look although you make much sense, I do dread simulationa nd try to work around it as much as possible. making a testcase seems to be 2 to 3 times longer than actually designing. Which is why i asked if signaltap would be an easier route. Thanks, Malik From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l14g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Sat, 16 Oct 2010 21:26:04 -0700 (PDT) Organization: http://groups.google.com Lines: 84 Message-ID: <1cc3b47e-e458-4908-afb7-acda512f8a75@l14g2000yqb.googlegroups.com> References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287289565 830 127.0.0.1 (17 Oct 2010 04:26:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Oct 2010 04:26:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000yqb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; SearchToolbar 1.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4237 On Oct 17, 12:09=A0am, laserbeak43 wrote: > Hello Kevin, > Thanks for your reply > > > The combinatorial process is triggered by activity on s_out (and other > > signals). =A0So when it hits any of the above statements it will cause > > s_out to update which will then re-trigger the process again. > > Should I put the case statement in its own process? > That wouldn't logically change anything. > >=A0Any time you have a signal assignment where signal 'x' is on both the= left > > and right hand side AND you're in either a combinatorial process or a > > concurrent statement...you've either created a latch or a > > combinatorial loop. =A0However you view it, it's likely a design error. > > Hmmm, do you think it'd be better if i made another signal and > assigned its value to s_out? > No, logically that wouldn't change anything either. The following are both examples of combinatorial loops. The first is the form you originally presented, the second is what you just proposed...they are logically identical and each is a loop/latch. It won't solve the problem Ex 1: x <=3D x + 1; Ex 2: x <=3D y + 1; y <=3D x; > > Some suggestions: > > - Don't use non-clocked processes. =A0Too bad that the conversation tha= t > > was had a few months ago that you referred to either didn't suggest > > this or that you didn't adhere to this advice. > > I think i've heard this one before, The lab that I'm working on(the > altera labs that come with the DE2) tell me to use a button as the > clock though (KEY). > > > - Simulate your design. =A0In this case, the simulator would likely hav= e > > failed because an iteration limit was exceeded once any of the case > > statement assignments was hit. =A0The iteration limit exceeded is the > > simulator's way of saying that after a large number of iterations, the > > signal activity has not settled down to a stable value so the > > simulator cannot advance to the next time step. > > Would signaltap be effective? > Signaltap is not a simulator...so 'no' it would not be effective. Or at best it would not be nearly as effective as a simulator. One can always debug hardware if one has sufficient time...the more efficient way is with a simulator whenever you can, hardware debug when you need to find a clue to isolate where your sim is not covering an area. > > - During development, use synthesis tools only to > > * Produce the final output file > > * Get a heads up on things you haven't yet got around to simulating > > such as * Entire blocks of code getting optomized away because of > > unconnected inputs > > ** Multiple drivers on a net. > > - Don't use synthesis tools for debug...the error messages aren't > > always that helpful. =A0Although I must admit in this case, I found it > > very helpful and easy to understand where exactly to look > > although you make much sense, I do dread simulationa nd try to work > around it as much as possible. Then you'll be at a disadvantage to those who do simulate and are effective at it since they will be far more efficient at getting to working designs then you will be...that's your choice to make, just not one that many would recommend. > making a testcase seems to be 2 to 3 > times longer than actually designing. Your comparison is not relevent. Compare the testcase time to the debug time. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Sun, 17 Oct 2010 12:04:23 +0100 Organization: A noiseless patient Spider Lines: 75 Message-ID: <1iklb6h7m2ra0n4mgb0h2l9haj5d6aem2j@4ax.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="32657"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/anb/nnjdKGz9o5jwYPYZ8TKLQ9mSz5lc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:TqwIYp6B69UsRAJXTXQe/x3jwTw= Xref: feeder.eternal-september.org comp.lang.vhdl:4238 On Sat, 16 Oct 2010 11:28:10 -0700 (PDT), KK6GM wrote: >So far, I've gotten advice on clocking at lower frequencies (generate >1-of-N clock enables) and I've read and understood (?) about unwanted >latches. I've gotten my Nexys2 counting, multiplexing the display, >debouncing buttons, simple stuff like that. So what I'm interested in >is something along the lines of the top N bits of advice for >beginners. These can be as simple as a single sentence ("Always >do..." or "If this than that"), I can probably take it from there. Or >pointers to good articles on the net. I'd really appreciate tapping >into the collective knowledge here. As for any knowledge transfer, it's unwise to seek one-size-fits-all solutions. I am pretty certain that if you could put together a two-page Top FPGA Desiderata sheet that was genuinely useful to a wide audience, someone would have already done it; I'm not aware of anything that fits the bill. Your specific situation (s/w guy with good hardware experience but little exposure to FPGAs and HDLs) is fairly unusual, but we've had a few such popping up here in the past and, like you, they generally seem to get the hang of things faster than most. Many of the guidelines you'll find for HDL design are unduly prescriptive and limiting, partly because there's a sense that traditional digital designers aren't ready to exploit the full power of HDLs that software people often try to use instinctively. Other guidelines are aimed at dyed-in-the-wool software people who wouldn't know a clock edge if you tried to cut them with it. I would not wish to insult your intelligence with either of these flavours of cookbook. Every time I write any HDL code, I'm making use of a large body of experience, wisdom, tricks and pitfall-avoidance techniques that I've accumulated over half a lifetime of real do-it-in-anger work. Much of that is stuff I've learnt from others; some is stuff I've invented for myself because of frustration with the standard solutions. Despite having been a teacher and trainer for a large part of that half-a-lifetime, I still don't know any good way to capture that accumulated know-how in a short document. So I'd instead urge you to go on using your own insight, which is clearly pretty reliable, and keep coming back here or to any other forum you trust. Treat textbooks with the circumspection they mostly deserve, and be even more cautious of web-based information which is often motivated by vanity or commercial interests. A couple of comments on your solution to your problem, from an experienced reviewer, are likely to be more valuable to you than any amount of staring at a cheat-sheet of guidelines. You seem already to have bought in to the really fundamental stuff (be synchronous; be aware of the hardware your code implies; be aware that you're writing code, so all the usual good sense about software applies equally to HDL code). My best shot at guidance that might be useful to you: SIMULATE AND SYNTHESISE early and often. Review the results of both processes and be sure you understand how they relate to your original design intent. Be on the lookout for synthesis results that look bloated or wasteful of hardware - they probably indicate that you wrote a software-like description without thinking of the hardware consequences. Be on the lookout for unexpected or flaky behaviour in simulation, and be sure you understand the reasons before moving on - errors are much easier and cheaper to fix if you fix them early in the development cycle. In other words, keep your brain engaged. That's all. Good luck and happy designing, -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: "Maurice" Newsgroups: comp.lang.vhdl Subject: Re: Generating JEDEC for GAL programming? Date: Sun, 17 Oct 2010 16:46:28 +0300 Organization: Aioe.org NNTP Server Lines: 34 Message-ID: References: <877hhmzabb.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: OCrXjg/NcYOyogSPmsZafQ.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-Notice: Filtered by postfilter v. 0.8.2 X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4239 "Merciadri Luca" wrote in message news:877hhmzabb.fsf@merciadriluca-eee.MERCIADRILUCA... > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > For a project, I know that I need to generate, among others, JEDEC > code to program on a GAL. I use GHDL as a front-end compiler for VHDL, > but I can't find any way on how to generate JEDEC code. Is there any > simple solution, or simply something that I am misunderstanding? > > Thanks. > - -- > Merciadri Luca > See http://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > Live as if you were to die tomorrow; learn as if you were to live > forever. (Mahatma Gandhi) > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAky1ggcACgkQM0LLzLt8MhynlgCeOADjmIVnNdHB1N8EAy7pmQWJ > lrUAn1txx0EtfFXNuFjPZAhGAGFiBAKE > =xsvC > -----END PGP SIGNATURE----- You can try also Atmel WinCPUL downloadable from Atmel Site, but it has its proper language, not VHDL. From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!30g2000yqm.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Sun, 17 Oct 2010 07:49:31 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <1cc3b47e-e458-4908-afb7-acda512f8a75@l14g2000yqb.googlegroups.com> NNTP-Posting-Host: 68.50.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287326971 22451 127.0.0.1 (17 Oct 2010 14:49:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Oct 2010 14:49:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yqm.googlegroups.com; posting-host=68.50.244.35; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 6.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4240 > > Should I put the case statement in its own process? > > That wouldn't logically change anything. > wouldn't the case being in it's own process prevent initialization over and over, at least? > > No, logically that wouldn't change anything either. =A0The following are > both examples of combinatorial loops. =A0The first is the form you > originally presented, the second is what you just proposed...they are > logically identical and each is a loop/latch. =A0It won't solve the > problem > > Ex 1: =A0x <=3D x + 1; > Ex 2: =A0x <=3D y + 1; =A0y <=3D x; > I was thinking of something that involved taking s_out out of the process initializing x to 0, then assigning x to s_out, outside of the process. or at least i am now... > > Signaltap is not a simulator...so 'no' it would not be effective. =A0Or > at best it would not be nearly as effective as a simulator. =A0One can > always debug hardware if one has sufficient time...the more efficient > way is with a simulator whenever you can, hardware debug when you need > to find a clue to isolate where your sim is not covering an area. > :( > > Then you'll be at a disadvantage to those who do simulate and are > effective at it since they will be far more efficient at getting to > working designs then you will be...that's your choice to make, just > not one that many would recommend. > I guess I should get used to it. > > Your comparison is not relevent. =A0Compare the testcase time to the > debug time. LOL true, I'd probably have moved on by now. Thanks, Malik From newsfish@newsfish Fri Dec 24 22:55:23 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Sun, 17 Oct 2010 09:54:51 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: <58787be7-1b84-47f1-9294-051bd9bb3148@v20g2000yqb.googlegroups.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <1iklb6h7m2ra0n4mgb0h2l9haj5d6aem2j@4ax.com> NNTP-Posting-Host: 74.72.162.179 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287334491 20619 127.0.0.1 (17 Oct 2010 16:54:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Oct 2010 16:54:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=74.72.162.179; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (iPhone; U; CPU iPhone OS 4_1 like Mac OS X; en-us) AppleWebKit/532.9 (KHTML, like Gecko) Version/4.0.5 Mobile/8B117 Safari/6531.22.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4241 As someone who made the transition from software to hardware over a year ago, but had little hardware experience, there are some things that bit me that are still fresh. The numbers below are to delineate ideas, they've nothing to do with priority: 1. As Jonathan Bromley said, simulate and synthesize often. As a software developer I'd never written a test bench for a module of code before, only for entire projects. Write a test bench for everything. 2. To go further, early on in your design allow speed of synthesis to inform your design. That is, you could have a 20,000 line project that altering a single line of VHDL affects a 20 minute or 3 hour synthesis time, and may not offer any actual optimization benefit. If it's worth keeping log that you went with the less optimal code-wise option and save it for production releases... 3. Don't be too clever. In software if it's syntactically legal you can do it, in VHDL it may simulate, but if your code isn't a common idiom it may be rejected in synthesis, or may not be optimized. Therefore every time you get an idea you think is clever, try it in a sandbox first before you encorporate it in a project and heap other code on it only to find out you've wasted 3 days because the code simulates but won't synthesize. 4. Elaboration is your friend (I believe this is the name of the stage, someone correct me if I'm wrong...) In many software languages, besides some very simple expressions, most code makes it into the run time. In VHDL any constant expression can be evaluated during elaboration (again, correctme if wrong on the term), including user defined functions. 5. In a process, signal assignment occurs at the next 'wait', which in synthesizable code usually means at the end of the process. This means that there's room for a concurrent process to pick up processing on a synchronous process's results combinatorially IN THE SAME CLOCK CYCLE. The information I read early on led menincorrectly to think that a signal assignment always occurred in hardware at the end of the clock cycle. Similarly, you make put combinatorially logic and processes before your synchronous logic to move some setup burden to before a clock cycle. I.E. If you have a block ram, which is synchronous, you could do some combinatorially processing on data to be written to it in the same entity it's instantiated in, but in the clock cycle of the entity sending it data. 6. Wires are free. For example, if you have an enumerated type and an instance of it, you may want to check it's value and make a decision based on the result (I.e. If statement). This takes a minimum of 1 lut or mux if it's binary, gray, of lfsr encoded, bit if it's one hot encoded checking if it's equal or not equal to a value requires 0 logic! Similarly, perjuring values, shifting endianess, etc., is always free. 7. Think more like a human. In Software development you try to keep steps as simple as possible be wise the more complex your code, the longer the sequences of instructions and the slower it is. In an FPGA checking edge cases is almost free. The way humans tend to think of tasks is they know bow to do the most general case, and handle the edge cases differently, and since our minds work in parallel we can do several approaches simultaneously and just pick the right result. An example might be if you're trying to insert elements into a BRAM based on some characteristic (I.e. values over x go in A, values under go in B, and if x presents itself, put it in a register C) I'm sorry I can't give a better example, I have 3-4 great cases in code I'm looking at now, but it's all proprietary. 8. More of a warning than a suggestion: information is sparse. There isn't a huge open source movement, and as a software developer you won't be used to the idea that googling an error number from a synthesis tool may have 0 results (more than half the time this is the case). I also used to like to joke that software programming made a lot more people athesists, since when you first start you presume a lot ofthe errors you get must be the commoners fault, and very quickly you learn to take responsibility for all errors, and assume there's a rational reason for everything. FPGA development will make you believe in God again, or a least the Devil, since a significant portion of the time (5%+ in my case) I'll find an error in the synthesis or simulation tools. Usually if it synthesis it's fine, I won't get an erroneous result, it'll just bomb or not bomb, and it may not be your fault! This is related to not being clever, hardware developers seem to make bad beta testers or something. I'll think of I can come up with more, bit that covers a bit of the biggest time wasters. Sorry for misspellings, too, the device I'm on lacks a spell checker - yeeesh. From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!i5g2000yqe.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Sun, 17 Oct 2010 11:24:37 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <7f2fb613-d510-48f9-8efb-a406c8320f4c@i5g2000yqe.googlegroups.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <1iklb6h7m2ra0n4mgb0h2l9haj5d6aem2j@4ax.com> <58787be7-1b84-47f1-9294-051bd9bb3148@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287339878 954 127.0.0.1 (17 Oct 2010 18:24:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Oct 2010 18:24:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i5g2000yqe.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4242 Now on better machine. In #6, "Perjuring" should read "permuting", #8 "commoners" should read "compilers." I wanted to add a 9. Remember 5? Stick to synchronous logic as much as possible, and save the combinatorial stuff for optimizations. When I first started I was under the impression the time it took to travel through a wire was trivial compared to logic expenses, but this is not quite the case. Frequently you'll need to register your data. 10. Make sure you've correctly informed the tools of your timing requirements. Don't assume anything. If you fail to correctly constrain a clock in a multiclock design you may be under the impression you're getting hardware errors because your logic was wrong, when in fact it simply wasn't informing you that one of your faster clock domains wasn't making timing (technically it was making timing, just not the timing that relates to the clock you were passing in). 11. Your main advantage over hardware developers is that you've seen the higher level of abstraction and complexity possible in software development than they're used to and will want to achieve the same kind of designs in hardware. This is also your main disadvantage. From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t20g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Mon, 18 Oct 2010 06:06:50 -0700 (PDT) Organization: http://groups.google.com Lines: 46 Message-ID: <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287407210 15592 127.0.0.1 (18 Oct 2010 13:06:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 Oct 2010 13:06:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t20g2000yqa.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) X-Original-Bytes: 2715 Xref: feeder.eternal-september.org comp.lang.vhdl:4243 If you are supposed to use KEY as a clock, then why aren't you doing it? process(s_sw, s_key) begin -- changed sensitivity to clk and reset only s_out <= (others => '0'); -- s_key <= (others => '0'); -- s_sw <= (others => '0'); if(s_sw(0) = '1') then -- now this is async reset s_out <= "0000"; elsif falling_edge(s_key) then -- and this is the clk case s_sw(2 downto 1) is when "00" => s_out <= s_out; when "01" => s_out <= s_out + 1; when "10" => s_out <= s_out + 2; when "11" => s_out <= s_out + 1; end case; end if; end process; Note that this also eliminates your latch and combinatorial feedback loop problems too. s_sw must be synchronized to the s_key clock (either by protocol, e.g. don't change the s_sw inputs while s_key is falling, or by using explicit registers). If it is not, you could get some strange behavior if s_sw changes when s_key falls. And as valuable as simulation is, it is very difficult to use it to find problems from improperly synchronized inputs... Andy From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Mon, 18 Oct 2010 11:03:56 -0700 Lines: 17 Message-ID: <8i3gg1Fu9bU1@mid.individual.net> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net se07nyagPROG8VEODfIx/gvc6vtesR4jw0NROAVHcbFbvbP446 Cancel-Lock: sha1:TRJDfFIiIGjSBVLZ5BiAcocgRpQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.9) Gecko/20100915 Lightning/1.0b2 Thunderbird/3.1.4 In-Reply-To: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4244 On 10/16/2010 11:28 AM, KK6GM wrote: > As I've mentioned in another post, I'm a longtime software guy with > decent hardware experience (I've designed much of the hardware I've > programmed), but I've only dipped into the FPGA/VHDL waters in the > past few weeks. (And I must say, I'm fascinated by it all!) Longtime software guys sometimes like to use functions instead of asynchronous processes and variables for registers. This is how I do it: http://mysite.ncnetwork.net/reszotzl/sync_template.vhd http://mysite.ncnetwork.net/reszotzl/stack.vhd http://mysite.ncnetwork.net/reszotzl/uart.vhd Good luck. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Mon, 18 Oct 2010 13:41:33 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> NNTP-Posting-Host: 188.28.50.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287434494 18219 127.0.0.1 (18 Oct 2010 20:41:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 18 Oct 2010 20:41:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=188.28.50.1; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4245 Don't be afraid to apparently duplicate a lot of code. This refers to say having 2 copies of a case statement with differing when clauses based on some outer state of the machine being coded. It does not consume many extra resources, and can lead to a better data flow. From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l14g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Tue, 19 Oct 2010 08:45:57 -0700 (PDT) Organization: http://groups.google.com Lines: 73 Message-ID: <4dab0674-34f8-4b36-8733-fe15c4e68e10@l14g2000yqb.googlegroups.com> References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> NNTP-Posting-Host: 76.100.125.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287503157 29943 127.0.0.1 (19 Oct 2010 15:45:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Oct 2010 15:45:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000yqb.googlegroups.com; posting-host=76.100.125.106; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4247 On Oct 18, 9:06=A0am, Andy wrote: > If you are supposed to use KEY as a clock, then why aren't you doing > it? > > =A0 =A0 =A0 =A0 process(s_sw, s_key) begin -- changed sensitivity to clk = and > reset only > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D (others =3D> '0'); > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_key <=3D (others =3D> '0'); > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_sw <=3D (others =3D> '0'); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(s_sw(0) =3D '1') then -- now this is a= sync reset > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D "0000"; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif falling_edge(s_key) then -- and thi= s is the clk > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case s_sw(2 downto 1) is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "00"= =3D> s_out <=3D s_out; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "01"= =3D> s_out <=3D s_out + 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "10"= =3D> s_out <=3D s_out + 2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "11"= =3D> s_out <=3D s_out + 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end process; > > Note that this also eliminates your latch and combinatorial feedback > loop problems too. > > s_sw must be synchronized to the s_key clock (either by protocol, e.g. > don't change the s_sw inputs while s_key is falling, or by using > explicit registers). If it is not, you could get some strange behavior > if s_sw changes when s_key falls. > > And as valuable as simulation is, it is very difficult to use it to > find problems from improperly synchronized inputs... > > Andy I am unclear as to what logic you are trying to generate. Is this supposed to be a register? If so, you need to use code that will generate a register. The above is not that. If you are trying to use combinatorial logic to increment a value, the feedback loop you are describing will never stabilize... when "01" =3D> s_out <=3D s_out + 1; when "10" =3D> s_out <=3D s_out + 2; when "11" =3D> s_out <=3D s_out + 1; These three statements describe a value that is generated by the output of an incrementing adder with itself as the input value. Do you see the problem? Without putting a register in the loop the value will increment, then increment again, and again... In fact, the individual bits will propagate at different speeds and you will likely get a random number generator running at top speed! First, decide what logic you are trying to describe. After all, VHDL is a Hardware Description Language. Decide on the logic you want, then DESCRIBE it. Look up templates for registers and add your combinatorial description to that. Or write your combinatorial logic separately in concurrent statements and just put the register in the clocked process. Rick From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Tue, 19 Oct 2010 10:56:46 -0700 (PDT) Organization: http://groups.google.com Lines: 79 Message-ID: References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> <4dab0674-34f8-4b36-8733-fe15c4e68e10@l14g2000yqb.googlegroups.com> NNTP-Posting-Host: 12.35.64.226 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287511007 12406 127.0.0.1 (19 Oct 2010 17:56:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Oct 2010 17:56:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=12.35.64.226; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-Via: 1.1 barracudaweb.tritool.rancho:8080 (http_scan/4.0.2.6.19) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MDDR; .NET4.0C; .NET4.0E; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4249 On Oct 19, 8:45=A0am, rickman wrote: > On Oct 18, 9:06=A0am, Andy wrote: > > > > > > > If you are supposed to use KEY as a clock, then why aren't you doing > > it? > > > =A0 =A0 =A0 =A0 process(s_sw, s_key) begin -- changed sensitivity to cl= k and > > reset only > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D (others =3D> '0'); > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_key <=3D (others =3D> '0'); > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_sw <=3D (others =3D> '0'); > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(s_sw(0) =3D '1') then -- now this is= async reset > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D "0000"; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif falling_edge(s_key) then -- and t= his is the clk > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case s_sw(2 downto 1) i= s > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0= 0" =3D> s_out <=3D s_out; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "0= 1" =3D> s_out <=3D s_out + 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "1= 0" =3D> s_out <=3D s_out + 2; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "1= 1" =3D> s_out <=3D s_out + 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > > =A0 =A0 =A0 =A0 end process; > > > Note that this also eliminates your latch and combinatorial feedback > > loop problems too. > > > s_sw must be synchronized to the s_key clock (either by protocol, e.g. > > don't change the s_sw inputs while s_key is falling, or by using > > explicit registers). If it is not, you could get some strange behavior > > if s_sw changes when s_key falls. > > > And as valuable as simulation is, it is very difficult to use it to > > find problems from improperly synchronized inputs... > > > Andy > > I am unclear as to what logic you are trying to generate. =A0Is this > supposed to be a register? =A0If so, you need to use code that will > generate a register. =A0The above is not that. =A0If you are trying to us= e > combinatorial logic to increment a value, the feedback loop you are > describing will never stabilize... > > when "01" =3D> s_out <=3D s_out + 1; > when "10" =3D> s_out <=3D s_out + 2; > when "11" =3D> s_out <=3D s_out + 1; > > These three statements describe a value that is generated by the > output of an incrementing adder with itself as the input value. =A0Do > you see the problem? =A0Without putting a register in the loop the value > will increment, then increment again, and again... =A0In fact, the > individual bits will propagate at different speeds and you will likely > get a random number generator running at top speed! Doesn't ...elsif falling_edge(s_key) then... generate a register? I'm just a beginner, but if it doesn't I'd like to know why it doesn't. From newsfish@newsfish Fri Dec 24 22:55:24 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l20g2000yqm.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Tue, 19 Oct 2010 17:54:39 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> <4dab0674-34f8-4b36-8733-fe15c4e68e10@l14g2000yqb.googlegroups.com> NNTP-Posting-Host: 76.100.125.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287536079 27739 127.0.0.1 (20 Oct 2010 00:54:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Oct 2010 00:54:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l20g2000yqm.googlegroups.com; posting-host=76.100.125.106; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4250 On Oct 19, 1:56=A0pm, KK6GM wrote: > On Oct 19, 8:45=A0am, rickman wrote: > > > > > On Oct 18, 9:06=A0am, Andy wrote: > > > > If you are supposed to use KEY as a clock, then why aren't you doing > > > it? > > > > =A0 =A0 =A0 =A0 process(s_sw, s_key) begin -- changed sensitivity to = clk and > > > reset only > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D (others =3D> '0'); > > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_key <=3D (others =3D> '0'); > > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_sw <=3D (others =3D> '0'); > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(s_sw(0) =3D '1') then -- now this = is async reset > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D "0000"; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif falling_edge(s_key) then -- and= this is the clk > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case s_sw(2 downto 1)= is > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when = "00" =3D> s_out <=3D s_out; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when = "01" =3D> s_out <=3D s_out + 1; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when = "10" =3D> s_out <=3D s_out + 2; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when = "11" =3D> s_out <=3D s_out + 1; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > > > =A0 =A0 =A0 =A0 end process; > > > > Note that this also eliminates your latch and combinatorial feedback > > > loop problems too. > > > > s_sw must be synchronized to the s_key clock (either by protocol, e.g= . > > > don't change the s_sw inputs while s_key is falling, or by using > > > explicit registers). If it is not, you could get some strange behavio= r > > > if s_sw changes when s_key falls. > > > > And as valuable as simulation is, it is very difficult to use it to > > > find problems from improperly synchronized inputs... > > > > Andy > > > I am unclear as to what logic you are trying to generate. =A0Is this > > supposed to be a register? =A0If so, you need to use code that will > > generate a register. =A0The above is not that. =A0If you are trying to = use > > combinatorial logic to increment a value, the feedback loop you are > > describing will never stabilize... > > > when "01" =3D> s_out <=3D s_out + 1; > > when "10" =3D> s_out <=3D s_out + 2; > > when "11" =3D> s_out <=3D s_out + 1; > > > These three statements describe a value that is generated by the > > output of an incrementing adder with itself as the input value. =A0Do > > you see the problem? =A0Without putting a register in the loop the valu= e > > will increment, then increment again, and again... =A0In fact, the > > individual bits will propagate at different speeds and you will likely > > get a random number generator running at top speed! > > Doesn't > > =A0 ...elsif falling_edge(s_key) then... > > generate a register? =A0I'm just a beginner, but if it doesn't I'd like > to know why it doesn't. It should. Why do you doubt it? Rick From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r4g2000prj.googlegroups.com!not-for-mail From: KK6GM Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Tue, 19 Oct 2010 20:42:43 -0700 (PDT) Organization: http://groups.google.com Lines: 99 Message-ID: <14bccf46-c9d8-4652-b3f7-f674c7b3e2d8@r4g2000prj.googlegroups.com> References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> <4dab0674-34f8-4b36-8733-fe15c4e68e10@l14g2000yqb.googlegroups.com> NNTP-Posting-Host: 76.216.160.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287546163 2676 127.0.0.1 (20 Oct 2010 03:42:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Oct 2010 03:42:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r4g2000prj.googlegroups.com; posting-host=76.216.160.39; posting-account=qZVz2QoAAAAN9WxYp-9jYb7jORc4Zqwt User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB0.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4251 On Oct 19, 5:54=A0pm, rickman wrote: > On Oct 19, 1:56=A0pm, KK6GM wrote: > > > > > > > On Oct 19, 8:45=A0am, rickman wrote: > > > > On Oct 18, 9:06=A0am, Andy wrote: > > > > > If you are supposed to use KEY as a clock, then why aren't you doin= g > > > > it? > > > > > =A0 =A0 =A0 =A0 process(s_sw, s_key) begin -- changed sensitivity t= o clk and > > > > reset only > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D (others =3D> '0'); > > > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_key <=3D (others =3D> '0'); > > > > -- =A0 =A0 =A0 =A0 =A0 =A0 =A0s_sw <=3D (others =3D> '0'); > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(s_sw(0) =3D '1') then -- now thi= s is async reset > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s_out <=3D "0000"; > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif falling_edge(s_key) then -- a= nd this is the clk > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case s_sw(2 downto = 1) is > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 whe= n "00" =3D> s_out <=3D s_out; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 whe= n "01" =3D> s_out <=3D s_out + 1; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 whe= n "10" =3D> s_out <=3D s_out + 2; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 whe= n "11" =3D> s_out <=3D s_out + 1; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > > > > =A0 =A0 =A0 =A0 end process; > > > > > Note that this also eliminates your latch and combinatorial feedbac= k > > > > loop problems too. > > > > > s_sw must be synchronized to the s_key clock (either by protocol, e= .g. > > > > don't change the s_sw inputs while s_key is falling, or by using > > > > explicit registers). If it is not, you could get some strange behav= ior > > > > if s_sw changes when s_key falls. > > > > > And as valuable as simulation is, it is very difficult to use it to > > > > find problems from improperly synchronized inputs... > > > > > Andy > > > > I am unclear as to what logic you are trying to generate. =A0Is this > > > supposed to be a register? =A0If so, you need to use code that will > > > generate a register. =A0The above is not that. =A0If you are trying t= o use > > > combinatorial logic to increment a value, the feedback loop you are > > > describing will never stabilize... > > > > when "01" =3D> s_out <=3D s_out + 1; > > > when "10" =3D> s_out <=3D s_out + 2; > > > when "11" =3D> s_out <=3D s_out + 1; > > > > These three statements describe a value that is generated by the > > > output of an incrementing adder with itself as the input value. =A0Do > > > you see the problem? =A0Without putting a register in the loop the va= lue > > > will increment, then increment again, and again... =A0In fact, the > > > individual bits will propagate at different speeds and you will likel= y > > > get a random number generator running at top speed! > > > Doesn't > > > =A0 ...elsif falling_edge(s_key) then... > > > generate a register? =A0I'm just a beginner, but if it doesn't I'd like > > to know why it doesn't. > > It should. =A0Why do you doubt it? > > Rick- Hide quoted text - > > - Show quoted text - Your previous post made me that that you doubted it. Maybe I misunderstood what you were trying to say. From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!g13g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Me and Latches... Date: Wed, 20 Oct 2010 01:11:46 -0700 (PDT) Organization: http://groups.google.com Lines: 88 Message-ID: References: <69b6a31c-c301-4390-beaa-9245911b4a30@i5g2000yqe.googlegroups.com> <385ba9c6-2f1a-46ca-9db9-2b9891f0d3ca@t20g2000yqa.googlegroups.com> <4dab0674-34f8-4b36-8733-fe15c4e68e10@l14g2000yqb.googlegroups.com> <14bccf46-c9d8-4652-b3f7-f674c7b3e2d8@r4g2000prj.googlegroups.com> NNTP-Posting-Host: 76.100.125.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287562306 21227 127.0.0.1 (20 Oct 2010 08:11:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Oct 2010 08:11:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g13g2000yqj.googlegroups.com; posting-host=76.100.125.106; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4252 On Oct 19, 11:42 pm, KK6GM wrote: > On Oct 19, 5:54 pm, rickman wrote: > > > On Oct 19, 1:56 pm, KK6GM wrote: > > > > On Oct 19, 8:45 am, rickman wrote: > > > > > On Oct 18, 9:06 am, Andy wrote: > > > > > > If you are supposed to use KEY as a clock, then why aren't you doing > > > > > it? > > > > > > process(s_sw, s_key) begin -- changed sensitivity to clk and > > > > > reset only > > > > > > s_out <= (others => '0'); > > > > > -- s_key <= (others => '0'); > > > > > -- s_sw <= (others => '0'); > > > > > > if(s_sw(0) = '1') then -- now this is async reset > > > > > > s_out <= "0000"; > > > > > > elsif falling_edge(s_key) then -- and this is the clk > > > > > > case s_sw(2 downto 1) is > > > > > when "00" => s_out <= s_out; > > > > > when "01" => s_out <= s_out + 1; > > > > > when "10" => s_out <= s_out + 2; > > > > > when "11" => s_out <= s_out + 1; > > > > > end case; > > > > > > end if; > > > > > > end process; > > > > > > Note that this also eliminates your latch and combinatorial feedback > > > > > loop problems too. > > > > > > s_sw must be synchronized to the s_key clock (either by protocol, e.g. > > > > > don't change the s_sw inputs while s_key is falling, or by using > > > > > explicit registers). If it is not, you could get some strange behavior > > > > > if s_sw changes when s_key falls. > > > > > > And as valuable as simulation is, it is very difficult to use it to > > > > > find problems from improperly synchronized inputs... > > > > > > Andy > > > > > I am unclear as to what logic you are trying to generate. Is this > > > > supposed to be a register? If so, you need to use code that will > > > > generate a register. The above is not that. If you are trying to use > > > > combinatorial logic to increment a value, the feedback loop you are > > > > describing will never stabilize... > > > > > when "01" => s_out <= s_out + 1; > > > > when "10" => s_out <= s_out + 2; > > > > when "11" => s_out <= s_out + 1; > > > > > These three statements describe a value that is generated by the > > > > output of an incrementing adder with itself as the input value. Do > > > > you see the problem? Without putting a register in the loop the value > > > > will increment, then increment again, and again... In fact, the > > > > individual bits will propagate at different speeds and you will likely > > > > get a random number generator running at top speed! > > > > Doesn't > > > > ...elsif falling_edge(s_key) then... > > > > generate a register? I'm just a beginner, but if it doesn't I'd like > > > to know why it doesn't. > > > It should. Why do you doubt it? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Your previous post made me that that you doubted it. Maybe I > misunderstood what you were trying to say. My apologies. I was reading the code from your first post, I didn't see that Andy had shown you how to use the VHDL edge functions. From your original code I wasn't sure if you were attempting to design a register or if you were trying to design a combinatorial circuit. Rick From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: type casting / conversion again Date: Wed, 20 Oct 2010 13:02:41 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287604961 24364 127.0.0.1 (20 Oct 2010 20:02:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Oct 2010 20:02:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4253 I struggle with this more than any other subject in VHDL. Ok... from a post by Jonathan Bromley from some time ago: acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8); acc : std_logic_vector(8 downto 0); amplitude : std_logic_vector(7 downto 0); it's such a beautiful line of code to accomplish pwm (DeltaSigma modulator). I would love to keep it as it is without piles of type conversion and casting and what not but alas I don't think that's possible. I've tried all kinds of very unclever combinations of unsigned' this and to_integer that....no glory. Can anyone help? Shannon (struggling with the same issues over and over again) From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!feedme.ziplink.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!w30g2000prj.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Wed, 20 Oct 2010 13:53:33 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <07f0fb25-1cad-4512-82cc-dde29ff5c8b4@w30g2000prj.googlegroups.com> References: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287608014 3780 127.0.0.1 (20 Oct 2010 20:53:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Oct 2010 20:53:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w30g2000prj.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4254 On Oct 20, 1:02=A0pm, Shannon wrote: > I struggle with this more than any other subject in VHDL. > > Ok... from a post by Jonathan Bromley from some time ago: > > acc <=3D ('0' & acc(7 downto 0)) + amplitude + acc(8); > > acc : std_logic_vector(8 downto 0); > amplitude : std_logic_vector(7 downto 0); > > it's such a beautiful line of code to accomplish pwm (DeltaSigma > modulator). =A0I would love to keep it as it is without piles of type > conversion and casting and what not but alas I don't think that's > possible. =A0I've tried all kinds of very unclever combinations of > unsigned' this and to_integer that....no glory. =A0Can anyone help? > > Shannon (struggling with the same issues over and over again) I should mention that I prefer if acc and amplitude were unsigned. This makes the only problem with that line the "+ acc(8)" part. Is there a way to convert std_ulogic to unsigned? Shannon From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c10g2000yqh.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Wed, 20 Oct 2010 23:31:47 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <78448b06-259a-4bfd-a49b-150d648ae3c8@c10g2000yqh.googlegroups.com> References: <07f0fb25-1cad-4512-82cc-dde29ff5c8b4@w30g2000prj.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287642707 2809 127.0.0.1 (21 Oct 2010 06:31:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Oct 2010 06:31:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c10g2000yqh.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.11) Gecko/20101013 Ubuntu/10.04 (lucid) Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4255 On 20 Okt., 22:53, Shannon wrote: > On Oct 20, 1:02=A0pm, Shannon wrote: > > > > > I struggle with this more than any other subject in VHDL. > > > Ok... from a post by Jonathan Bromley from some time ago: > > > acc <=3D ('0' & acc(7 downto 0)) + amplitude + acc(8); > > > acc : std_logic_vector(8 downto 0); > > amplitude : std_logic_vector(7 downto 0); > > > it's such a beautiful line of code to accomplish pwm (DeltaSigma > > modulator). =A0I would love to keep it as it is without piles of type > > conversion and casting and what not but alas I don't think that's > > possible. =A0I've tried all kinds of very unclever combinations of > > unsigned' this and to_integer that....no glory. =A0Can anyone help? > > > Shannon (struggling with the same issues over and over again) > > I should mention that I prefer if acc and amplitude were unsigned. > This makes the only problem with that line the "+ acc(8)" part. =A0Is > there a way to convert std_ulogic to unsigned? > > Shannon Hi Shannon, besides numeric_std there's another library available (since VHDL-2008): numeric_std_unsigned You may try to use this with your tools. In case it won't work, maybe it's predecessor works for you: numeric_unsigned Search the net for the sources and you can work with std_logic(_vector) just like they were unsigned. Goody ol' std_logic_unsigned did a similar thing, and because we liked it so much numeric_std_unsigned is now part of the standard. Have a nice synthesis Eilert From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!x17g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Thu, 21 Oct 2010 00:09:32 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: References: <07f0fb25-1cad-4512-82cc-dde29ff5c8b4@w30g2000prj.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287644972 2137 127.0.0.1 (21 Oct 2010 07:09:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Oct 2010 07:09:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x17g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4256 On Oct 20, 9:53=A0pm, Shannon wrote: > On Oct 20, 1:02=A0pm, Shannon wrote: > > > > > I struggle with this more than any other subject in VHDL. > > > Ok... from a post by Jonathan Bromley from some time ago: > > > acc <=3D ('0' & acc(7 downto 0)) + amplitude + acc(8); > > > acc : std_logic_vector(8 downto 0); > > amplitude : std_logic_vector(7 downto 0); > > > it's such a beautiful line of code to accomplish pwm (DeltaSigma > > modulator). =A0I would love to keep it as it is without piles of type > > conversion and casting and what not but alas I don't think that's > > possible. =A0I've tried all kinds of very unclever combinations of > > unsigned' this and to_integer that....no glory. =A0Can anyone help? > > > Shannon (struggling with the same issues over and over again) > > I should mention that I prefer if acc and amplitude were unsigned. > This makes the only problem with that line the "+ acc(8)" part. =A0Is > there a way to convert std_ulogic to unsigned? > > Shannon you're going to need 1 type conversion, because acc(8) is a not an array, whereas an unsigned type is. To make it an array you will need: unsigned("" & acc(8) ); --this creates a 1 element long array ie. unsigned(0 downto 0); you could always put it into a temporary signal to avoid type conversions on the single line. From newsfish@newsfish Fri Dec 24 22:55:25 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!news.astraweb.com!border2.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: type casting / conversion again Newsgroups: comp.lang.vhdl References: <07f0fb25-1cad-4512-82cc-dde29ff5c8b4@w30g2000prj.googlegroups.com> User-Agent: Pan/0.133 (House of Butterflies) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Oct 2010 10:24:17 GMT Lines: 50 Message-ID: <4cc014d1$0$29970$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: a0fa9234.news.astraweb.com X-Trace: DXC=WA?Bd2b:Z1@We7Bc]TQV_NL?0kYOcDh@JN7:H2`MmAUCFRPSXaZN\EB]G;2>V^?kWC2Of6BS7?ncJfDHJ0KLXWOD[b>2]2`ElMD Xref: feeder.eternal-september.org comp.lang.vhdl:4257 On Thu, 21 Oct 2010 00:09:32 -0700, Tricky wrote: > On Oct 20, 9:53 pm, Shannon wrote: >> On Oct 20, 1:02 pm, Shannon wrote: >> >> >> >> > I struggle with this more than any other subject in VHDL. >> >> > Ok... from a post by Jonathan Bromley from some time ago: >> >> > acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8); >> >> > acc : std_logic_vector(8 downto 0); >> > amplitude : std_logic_vector(7 downto 0); >> >> > it's such a beautiful line of code to accomplish pwm (DeltaSigma >> > modulator).  I would love to keep it as it is without piles of type >> > conversion and casting and what not but alas I don't think that's >> > possible.  I've tried all kinds of very unclever combinations of >> > unsigned' this and to_integer that....no glory.  Can anyone help? >> >> > Shannon (struggling with the same issues over and over again) >> >> I should mention that I prefer if acc and amplitude were unsigned. This >> makes the only problem with that line the "+ acc(8)" part.  Is there a >> way to convert std_ulogic to unsigned? >> >> Shannon > > you're going to need 1 type conversion, because acc(8) is a not an > array, whereas an unsigned type is. > To make it an array you will need: > > unsigned("" & acc(8) ); --this creates a 1 element long array ie. > unsigned(0 downto 0); wouldn't acc(8 downto 8) do just as well? as in: acc : unsigned(8 downto 0); amplitude : unsigned(7 downto 0); acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8 downto 8); This didn't give any syntax errors under the old version of Modelsim I have on this machine. Regards, Allan From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Thu, 21 Oct 2010 21:38:09 +0100 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="10841"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zquplPoYo16vRPT/H7aL2QqN764dpwhI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:pES5S5tgyZrhh8TrC4R5kO553Bw= Xref: feeder.eternal-september.org comp.lang.vhdl:4258 On Wed, 20 Oct 2010 13:02:41 -0700 (PDT), Shannon wrote: >Ok... from a post by Jonathan Bromley from some time ago: > >acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8); > >acc : std_logic_vector(8 downto 0); >amplitude : std_logic_vector(7 downto 0); sheesh, did I really write that? Out of context? I've been campaigning _against_ the use of std_logic_unsigned for years, and now it turns out I've been virally promoting it all that time :-) >it's such a beautiful line of code to accomplish pwm (DeltaSigma >modulator). The end-around-carry is a very neat trick, yes. I claim no originality. As others have said, it will work just fine if acc and amplitude are both "unsigned", except that you need to make the carry-in be a 1-bit vector. acc(8 downto 8) is the easiest, I think. Other possibilities include unsigned'(0=>acc(8)) ("0" & acc(8)) While we're thinking about alternatives, perhaps parameterizing the vectors would be good: [port] amplitude: in unsigned -- unconstrained ... signal acc: unsigned(amplitude'length downto 0); ... acc <= ('0' & acc(acc'length-2 downto 0)) + amplitude + acc(acc'length downto acc'length); -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!news2.euro.net!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!p20g2000prf.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Thu, 21 Oct 2010 15:07:19 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287698839 23814 127.0.0.1 (21 Oct 2010 22:07:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Oct 2010 22:07:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000prf.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4259 > =A0 acc <=3D ('0' & acc(acc'length-2 downto 0)) > =A0 =A0 =A0 =A0+ amplitude + acc(acc'length downto acc'length); > -- > Jonathan Bromley Ahem....and that looks as beautiful as the original to you? o_O (just teasing). Thank you all for the help. To get through the day I made a separate signal called 'carry' that handled the conversion to an array. I'll go back and retry with the acc(8 downto 8) "trick". > I've been campaigning _against_ the use of > std_logic_unsigned for years, and now it turns out > I've been virally promoting it all that time :-) This is the reason I ask dumb questions... what do you mean by "std_logic_unsigned"? does this mean I shouldn't be using unsigned? I use it everywhere! Shannon From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Fri, 22 Oct 2010 00:41:42 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287733302 20896 127.0.0.1 (22 Oct 2010 07:41:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Oct 2010 07:41:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4260 On Oct 21, 11:07=A0pm, Shannon wrote: > > =A0 acc <=3D ('0' & acc(acc'length-2 downto 0)) > > =A0 =A0 =A0 =A0+ amplitude + acc(acc'length downto acc'length); > > -- > > Jonathan Bromley > > Ahem....and that looks as beautiful as the original to you? =A0o_O (just > teasing). =A0Thank you all for the help. =A0To get through the day I made > a separate signal called 'carry' that handled the conversion to an > array. =A0I'll go back and retry with the acc(8 downto 8) "trick". > > > I've been campaigning _against_ the use of > > std_logic_unsigned for years, and now it turns out > > I've been virally promoting it all that time :-) > > This is the reason I ask dumb questions... =A0what do you mean by > "std_logic_unsigned"? =A0does this mean I shouldn't be using unsigned? > I use it everywhere! > > Shannon Std_logic_unsigned is a non-IEEE package that lets you treat std_logic_vectors as unsigned numbers. It was written by Synopsys about 20 year ago. Unfortunatly, because it was released before the IEEE standard numeric_std, there are many text books and examples that use it, and it becomes a vicious circle as new engineers learn from old text books then recommend the same books to the next generation. Many many experienced engineers use it too. Its in such a situation that in the 2008 standard it got rolled into an IEEE standard. So - dont use it and keep this newsgroup happy :) From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 22 Oct 2010 02:55:36 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Fri, 22 Oct 2010 09:04:39 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 16 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-3B8u7MWgOQByQqNkKCcAG58TZ391fdCeGh51PJ6hh1vtXoBqXLAbCi8zDeBnNM8rzwCUtXhdjxNj3vD!RKIiWnCspOjdkReAPL1xuTDFmj/x2Un/HTYPWcND26yh/f3I4vLZ28IShq9UkGibyKN1xA+sTUgO!pQ== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1770 Xref: feeder.eternal-september.org comp.lang.vhdl:4261 On Thu, 21 Oct 2010 15:07:19 -0700 (PDT), Shannon wrote: >> I've been campaigning _against_ the use of >> std_logic_unsigned for years, and now it turns out >> I've been virally promoting it all that time :-) > >This is the reason I ask dumb questions... what do you mean by >"std_logic_unsigned"? does this mean I shouldn't be using unsigned? >I use it everywhere! No, it means the best way to use "unsigned" is to get it from numeric_std instead. (Ditto signed) - Brian From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!l14g2000yqb.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Fri, 22 Oct 2010 01:42:05 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <456e6250-a3d5-4b4c-a688-d5407616745f@l14g2000yqb.googlegroups.com> References: NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287736925 18790 127.0.0.1 (22 Oct 2010 08:42:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Oct 2010 08:42:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000yqb.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 12j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4262 On Oct 21, 11:07=A0pm, Shannon wrote: > > =A0 acc <=3D ('0' & acc(acc'length-2 downto 0)) > > =A0 =A0 =A0 =A0+ amplitude + acc(acc'length downto acc'length); > > Ahem....and that looks as beautiful as the original to you? Tee hee. No, it's horrid-looking, you're right. But it's less likely to need life-support in the future. Aliases might be your friend here... alias acc_MSB_value: unsigned (0 downto 0) is acc(acc'left downto acc'left); alias acc_without_MSB: unsigned(acc'length-2 downto 0) is acc(acc'length-2 downto 0); ... acc <=3D ('0' & acc_without_MSB) + amplitude + acc_MSB_value; Beauty restored :-) -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!a37g2000yqi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Fri, 22 Oct 2010 04:33:02 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: <14ede65d-8f38-4461-8c75-6de1c10ce41f@a37g2000yqi.googlegroups.com> References: <456e6250-a3d5-4b4c-a688-d5407616745f@l14g2000yqb.googlegroups.com> NNTP-Posting-Host: 76.100.125.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287747182 18008 127.0.0.1 (22 Oct 2010 11:33:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Oct 2010 11:33:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a37g2000yqi.googlegroups.com; posting-host=76.100.125.106; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4263 On Oct 22, 4:42=A0am, Jonathan Bromley wrote: > On Oct 21, 11:07=A0pm, Shannon wrote: > > > > =A0 acc <=3D ('0' & acc(acc'length-2 downto 0)) > > > =A0 =A0 =A0 =A0+ amplitude + acc(acc'length downto acc'length); > > > Ahem....and that looks as beautiful as the original to you? > > Tee hee. =A0No, it's horrid-looking, you're right. =A0But it's > less likely to need life-support in the future. > > Aliases might be your friend here... > > =A0 alias acc_MSB_value: unsigned (0 downto 0) > =A0 =A0 =A0 =A0 =A0is acc(acc'left downto acc'left); > =A0 alias acc_without_MSB: unsigned(acc'length-2 downto 0) > =A0 =A0 =A0 =A0 =A0is acc(acc'length-2 downto 0); > ... > =A0 acc <=3D ('0' & acc_without_MSB) + amplitude + acc_MSB_value; > > Beauty restored :-) > -- > Jonathan Bromley I believe the original version is not only ugly (the woes of VHDL type conversions), but it is wrong. Shouldn't part of this be acc(acc'length-1 downto acc'length-1) ? I normally use name'high in this context. But considering 'high vs. 'left, I wouldn't know where the trade-offs are. I guess 'high may not be correct if numbered 0..N which is possible. 'left would not work if the msb is not left, but that wouldn't be compatible with unsigned would it? Rick From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!n26g2000yqh.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: type casting / conversion again Date: Fri, 22 Oct 2010 04:54:42 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <0749764d-8040-4f98-ba46-322cda9e864f@n26g2000yqh.googlegroups.com> References: <456e6250-a3d5-4b4c-a688-d5407616745f@l14g2000yqb.googlegroups.com> <14ede65d-8f38-4461-8c75-6de1c10ce41f@a37g2000yqi.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287748482 28654 127.0.0.1 (22 Oct 2010 11:54:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Oct 2010 11:54:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n26g2000yqh.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 19j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4264 On Oct 22, 12:33=A0pm, rickman wrote: > I believe the original version is not only ugly (the woes of VHDL type > conversions), but it is wrong. =A0Shouldn't part of this be > acc(acc'length-1 downto acc'length-1) ? Yes - good catch. Sorry. > I normally use name'high in this context. =A0 > But considering 'high vs. 'left, I wouldn't > know where the trade-offs are. =A0I guess 'high may > not be correct if numbered 0..N which is possible. >=A0'left would not work if the msb is not left, but > that wouldn't be compatible with unsigned would it? Yes, the MSB is always 'left and I probably should have used that. However, there's still another potential goof because when writing acc(acc'left downto acc'left) you need to choose "to" or "downto" based on the original declaration of acc. However, if you get that wrong the compiler will pick it up. I wish it were possible to declare unconstrained arrays in VHDL with the to/downto direction constrained: type jonathans_unsigned is array(natural range >) of ... (where "range <>" allows both to/downto, "range >" allows only downto, "range <" allows only to) so that it would then be illegal to declare any jonathans_unsigned with a "to" direction. But it is not so :-( The standard defence against being given an array that might have inappropriate direction is to copy or alias it onto an array whose subscript range you've normalized. I'm pretty paranoid about always doing that in real code, but I got sloppy in this morning's post. Thanks Jonathan From newsfish@newsfish Fri Dec 24 22:55:26 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Best advice for FPGA/VHDL beginner? Newsgroups: comp.lang.vhdl Date: Fri, 22 Oct 2010 18:33:43 +0200 References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 15 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1287765224 news.xs4all.nl 81485 puiterl/[::ffff:195.242.97.150]:42927 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4265 jacko wrote: > Don't be afraid to apparently duplicate a lot of code. This refers to > say having 2 copies of a case statement with differing when clauses > based on some outer state of the machine being coded. It does not > consume many extra resources, and can lead to a better data flow. What do yo mean with "apparently duplicate a lot of code"? If it really means copying and pasting a lot of code, I would object. It will result in hard to mantain code. I thoroughly dislike copy-and-paste code. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed.velia.net!weretis.net!feeder4.news.weretis.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: Nipo Newsgroups: comp.lang.vhdl Subject: std types Date: Sat, 23 Oct 2010 15:16:39 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <98f27ccc-80ea-4111-817b-dd2a1d19dedb@t13g2000yqm.googlegroups.com> NNTP-Posting-Host: 187.113.112.57 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1287872199 26973 127.0.0.1 (23 Oct 2010 22:16:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 23 Oct 2010 22:16:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=187.113.112.57; posting-account=C0OkOgoAAAAEhztflpVr2NGX0YXgh8uf User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.10) Gecko/20100915 Ubuntu/10.04 (lucid) Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4266 Hi, i am new in VHDL and i not understand what advantage in use types std_logic/std_ulogic and std_logic_vector/std_ulogic_vector? I always use types bit and bit_vector, but i always see in examples the use of these types. Thanks. From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j2g2000yqf.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: std types Date: Sat, 23 Oct 2010 23:12:44 -0700 (PDT) Organization: http://groups.google.com Lines: 56 Message-ID: <05b044ec-95e9-4dc9-8f69-9c31e7c14042@j2g2000yqf.googlegroups.com> References: <98f27ccc-80ea-4111-817b-dd2a1d19dedb@t13g2000yqm.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1287900764 13041 127.0.0.1 (24 Oct 2010 06:12:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 24 Oct 2010 06:12:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j2g2000yqf.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4267 On Oct 23, 6:16=A0pm, Nipo wrote: > Hi, > i am new in VHDL and i not understand what advantage in use types > std_logic/std_ulogic and std_logic_vector/std_ulogic_vector? I always > use types bit and bit_vector, but i always see in examples the use of > these types. > Thanks. std_logic and std_ulogic bring along the concepts of unknown values, strong and weak driving as well as high impedance. Whereas a 'bit' can only be '0' or '1', a std_logic/std_ulogic has the following definition TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care The 'weak' values 'W', 'L' and 'H' somewhat model the way a resistor on a board behaves. While you can't tie two outputs together and not expect conflicts, you can tie them together through a resistor. The resolution rule if there is more than one driver for a signal is that 'forcing' beats 'weak', so a '1' or '0' would trump a 'L' or an 'H'. Search the source file that contains the ieee std_logic_1164 package for the function called 'resolved' and you'll find the code that does it, which then defines the entire set of 81 rules for when these 9 values crash together. 'Z' is used to model tri-state outputs. 'X' results when you have two drivers for a signal and they are going in different directions. So a '0' driver combined with a '1' driver cause the signal to be 'X'. 'U' models the reality that not all signals power up with a known value. Sometimes it may power up as a '0', other times as a '1'. What 'U' does is say that the value is unknown. While most people generally think of digital systems in terms of '0' and '1' (i.e. type 'bit'), it is generally quite helpful to use std_logic/std_ulogic instead because a design that really does get everything initialized properly will have a designed in mechanism to change any 'U' into a known value. If you use 'bit' instead, you might find yourself in the situation where the simulation appears to be working, but that is because it is using a default value of '0' for a signal, and that '0' might not be something that happens in the normal course of events. In other words, you think everything is fine, but it's not...or at least it's not guaranteed to be working the way you expect. There are a few downsides to std_logic/std_ulogic, but for the most part the benefits outweigh the drawbacks. Kevin From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g25g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Black boxing direct instantiation Date: Mon, 25 Oct 2010 07:25:30 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <0531f95a-e383-4665-aa8e-5575729fe334@g25g2000yqn.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288016730 9663 127.0.0.1 (25 Oct 2010 14:25:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Oct 2010 14:25:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g25g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4268 If I had a component declaration, I could easily black box it like this: attribute black_box : boolean; attribute black_box of my_logic : component is true; But how can I attach the same attribute to a direct instantiation version of my_logic? From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Black boxing direct instantiation Date: Mon, 25 Oct 2010 08:47:15 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <9468495e-9498-4bda-8176-b8913fa08607@26g2000yqv.googlegroups.com> References: <0531f95a-e383-4665-aa8e-5575729fe334@g25g2000yqn.googlegroups.com> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288021635 24517 127.0.0.1 (25 Oct 2010 15:47:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Oct 2010 15:47:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4269 On Oct 25, 9:25=A0am, Tricky wrote: > If I had a component declaration, I could easily black box it like > this: > > attribute black_box : boolean; > attribute black_box of my_logic : component is true; > > But how can I attach the same attribute to a direct instantiation > version of my_logic? Does the following not work? attribute black_box of my_logic : entity is true; Andy From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m7g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: std types Date: Mon, 25 Oct 2010 09:11:11 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: References: <98f27ccc-80ea-4111-817b-dd2a1d19dedb@t13g2000yqm.googlegroups.com> <05b044ec-95e9-4dc9-8f69-9c31e7c14042@j2g2000yqf.googlegroups.com> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288023071 4247 127.0.0.1 (25 Oct 2010 16:11:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Oct 2010 16:11:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000yqm.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4270 VHDL std_logic includes all of these features to ensure applicability and portability across test benches and a wide range of digital logic hardware, including board level, ASIC and FPGA. If your design targets only an FPGA that has a built-in initialization feature (such as most sram based ones have), and you are not specifying tri-state, wired-OR or wired-AND based logic or external interfaces, then you can use bit, bit_vector, and the related package numeric_bit, which defines unsigned and signed bit vectors, and arithmetic operators on them. Note that you can still specify explicit reset behavior, but if you are relying upon it, there is not a good way to verify it is done everywhere it is necessary, since bit does not have an "invalid' value to which to initialize. Using bit/ bit_vector is not very common anymore, but it is done. Note that gate level post-synthesis or post-place&route models will generally have std_logic_vector based IO, regardless of what types you had for your IO in your RTL. That means you would have to create a wrapper for the device level entity, and in that convert back to bit/bit_vector for your testbench, assuming your testbench was written to work with your RTL. Under the same caveats, you can also use integer and its subtypes, but you are practically limited to maximum 32 bit signed and 31 bit unsigned quantities. Within these constraints, integer has several advantages, especially in simulation performance, over bit and std_logic based vectors. Andy From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!news.glorb.com!news2.glorb.com!postnews.google.com!a36g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Black boxing direct instantiation Date: Tue, 26 Oct 2010 00:37:08 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: References: <0531f95a-e383-4665-aa8e-5575729fe334@g25g2000yqn.googlegroups.com> <9468495e-9498-4bda-8176-b8913fa08607@26g2000yqv.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288078628 25974 127.0.0.1 (26 Oct 2010 07:37:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 Oct 2010 07:37:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a36g2000yqc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4272 On Oct 25, 4:47=A0pm, Andy wrote: > On Oct 25, 9:25=A0am, Tricky wrote: > > > If I had a component declaration, I could easily black box it like > > this: > > > attribute black_box : boolean; > > attribute black_box of my_logic : component is true; > > > But how can I attach the same attribute to a direct instantiation > > version of my_logic? > > Does the following not work? > > attribute black_box of my_logic : entity is true; > > Andy No, because technically "my_logic" doesnt exist yet. The component method gives the compiler a port definition to compare the port map of the instantiation against, and black box tells the compiler to not worry about the RTL underneath. Basically I want the compiler to ignore the instantiation. From what I wrote above, Im getting the feeling this isnt possible. From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feed.xsnews.nl!border-1.ams.xsnews.nl!217.73.144.44.MISMATCH!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 26 Oct 2010 07:08:38 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Black boxing direct instantiation Date: Tue, 26 Oct 2010 13:17:47 +0100 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <0531f95a-e383-4665-aa8e-5575729fe334@g25g2000yqn.googlegroups.com> <9468495e-9498-4bda-8176-b8913fa08607@26g2000yqv.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 33 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-1Fz5+9grP0pOg0uxiLiGpSxxBqlnzVdlfGT+6cGqAAwwoclBJEJcgE+fT2DaF1DZrI6JBYrPguxSj35!h5VE8Bz0PzvHI3MrsnlC+UzevawCXd+xL1AOrksg/wUs6YYn92vMYrQ/TpthZIFCUMwyUSDwz5k9!97k= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2417 Xref: feeder.eternal-september.org comp.lang.vhdl:4273 On Tue, 26 Oct 2010 00:37:08 -0700 (PDT), Tricky wrote: >On Oct 25, 4:47 pm, Andy wrote: >> On Oct 25, 9:25 am, Tricky wrote: >> >> > If I had a component declaration, I could easily black box it like >> > this: >> >> > attribute black_box : boolean; >> > attribute black_box of my_logic : component is true; >> >> > But how can I attach the same attribute to a direct instantiation >> > version of my_logic? >> >> Does the following not work? >> >> attribute black_box of my_logic : entity is true; >> >> Andy > >No, because technically "my_logic" doesnt exist yet. The component >method gives the compiler a port definition to compare the port map of >the instantiation against, and black box tells the compiler to not >worry about the RTL underneath. > >Basically I want the compiler to ignore the instantiation. From what I >wrote above, Im getting the feeling this isnt possible. I think this is one place where you need the decoupling between specification and implementation that "component" was designed to provide. - Brian From newsfish@newsfish Fri Dec 24 22:55:27 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!optima2.xanadu-bbs.net!news.glorb.com!postnews.google.com!a37g2000yqi.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Black boxing direct instantiation Date: Tue, 26 Oct 2010 07:37:41 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <0531f95a-e383-4665-aa8e-5575729fe334@g25g2000yqn.googlegroups.com> <9468495e-9498-4bda-8176-b8913fa08607@26g2000yqv.googlegroups.com> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288103862 20669 127.0.0.1 (26 Oct 2010 14:37:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 Oct 2010 14:37:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a37g2000yqi.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4274 Yes, the entity has to exist, but its architecture does not (if you do not specify it in the entity instantiation)... Just like you have to declare the component, you have to define the entity. Whether the tool will find the attribute on the entity, and "bind" the entity to an external primitive, is another matter, and is likely tool dependent. Andy From newsfish@newsfish Fri Dec 24 22:55:28 2010 From: whygee Newsgroups: comp.lang.vhdl Subject: Re: assert of generic, during synthesis Date: Wed, 27 Oct 2010 17:20:03 +0200 Organization: Aioe.org NNTP Server Lines: 36 Message-ID: References: <4e8d265a-af7a-4c9b-885e-7831b364d385@c10g2000yqh.googlegroups.com> NNTP-Posting-Host: 2jfxNi3AN8s9Xsnk0uKAyQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news4us.nl!feeder.news-service.com!94.75.214.39.MISMATCH!aioe.org!not-for-mail Xref: feeder.eternal-september.org comp.lang.vhdl:4277 KJ wrote: > On Oct 3, 7:47 pm, KJ wrote: >> On Oct 3, 4:05 pm, whygee wrote: >>> More precisely, i have a constant table that >>> is addressed by the generic and i want to stop >>> synthesis when the value in the table is 0, >>> or something like that, with a clear message. >> If you have a generic that shouldn't be 0, then it should be defined >> as a 'postive', not 'natural' or 'integer'...either that or define the >> range to be '1 to ??' >> >> KJ > Woops, I retract the above. I misread "when the value in the table is > 0" as "the address specified by the generic is 0" yes, i'm back here and i see that many people have assumed like you. In my case, this is not a matter of testing the generic's value, but testing the value of the table at the address givent by the generic. When there is an illegal value, the table returns 0, and it should normally give an index into a vector that is 1..N. The synth catches that last error, but it's too late, we lost an opportunity to explain what went wrong. A comment in the doc "solved" this. thank you everybody, > KJ yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:28 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Can one declare more than one signal on one line? From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 10:25:15 +0100 Message-ID: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:VrLHdifAoeUYoMcWw5q+84rfqiY= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 27 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=>e;7WNg^51kbJlfT[;@_ShYSB=nbEKnkkOoZn^kHoPehZEVG4aK_]RP;@H2onO>`Ol[NBH>dn2bR\d`N4HieUKKVCA=Sbn X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4279 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Can one write, e.g. in an architecture environment, == signal a, b, c: integer range 0 to 10 == ? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- The greatest good you can do for another is not just share your riches, but reveal to him his own. (Benjamin Disraeli) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOh3sACgkQM0LLzLt8MhwBeQCdG6OQUJ9WEQ0qWiK1Tc7xWcmi nDIAmgKXt0pKcvlopEda63aZwlLD17wq =ztLG -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:28 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.ag!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Quadruple assignment From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 11:45:56 +0100 Message-ID: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:F1BAwLimkS2Z4YUwZH4fXdIjJhI= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 31 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=k>Fk__F:2X31@QH[VaTAe9YSB=nbEKnk;71459NG41K_]RP;@H2o>O>`Ol[NBH>4Qae0d3VLJe71T;O>;oY7Q3 X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4280 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Say you define == signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0; == where MAX_VALUE is a constant. My ghdl compiler will be okay with this statement, but what is its result? I would like to define sig1, sig2, sig3 and sig4 to be, initially, 0. But does that actually achieve what I want? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Men are more moral than they think, and far more immoral than they can imagine. (Sigmund Freud) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOmmMACgkQM0LLzLt8MhwCsgCeL5Wyg61PIBrvIrfWdgo3DWwg Ks8An2MDR1ZI1eg94AnABFWHDWlAIQX4 =kd8P -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:28 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Mon, 1 Nov 2010 05:09:38 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 86.111.223.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288613378 14813 127.0.0.1 (1 Nov 2010 12:09:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 12:09:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=86.111.223.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 06j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4281 On Nov 1, 10:45=A0am, Merciadri Luca wrote: > =3D=3D > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE :=3D 0; > =3D=3D > > where MAX_VALUE is a constant. My ghdl compiler will be okay with this > statement, but what is its result? Each of your four signals has the same subtype (0 to MAX_VALUE). The explicit initialization ":=3D0" is redundant, because any VHDL variable or signal is initialized to the left-most value in its value set; in your case that value is 0 anyway. All four signals will have 0 as their initialization value. Note that the initial value is associated with the subtype part of the declaration. It is not attached to each individual data object; it applies to all four of them. > But does that actually achieve what I want? Only you can answer that :-) -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:28 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? Date: Mon, 1 Nov 2010 05:13:21 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288613601 16682 127.0.0.1 (1 Nov 2010 12:13:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 12:13:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 14j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4282 On Nov 1, 9:25=A0am, Merciadri Luca wrote: > Can one write, e.g. in an architecture environment, > > =3D=3D > signal a, b, c: integer range 0 to 10 > =3D=3D > ? Yes, but wouldn't it be kinder to your readers and reviewers if you write subtype my_range is integer range 0 to 10; signal a : my_range; signal b : my_range; signal c : my_range; ? -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:28 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:30:00 +0100 Message-ID: <877hgxdvdz.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:Ych3XHKvqkCyv6roteiYfSKAwNE= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 44 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=Kj1HJd3TdOGSi^`20K04QCYSB=nbEKnkK71459NG4AK_]RP;@H2oNO>`Ol[NBH>DKMXJ_dg^BhGFJHF`K]idDH X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4283 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jonathan Bromley writes: > On Nov 1, 10:45 am, Merciadri Luca wrote: > >> == >> signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0; >> == >> >> where MAX_VALUE is a constant. My ghdl compiler will be okay with this >> statement, but what is its result? > > Each of your four signals has the same subtype > (0 to MAX_VALUE). The explicit initialization ":=0" > is redundant, because any VHDL variable or signal is > initialized to the left-most value in its value set; > in your case that value is 0 anyway. All four > signals will have 0 as their initialization value. > > Note that the initial value is associated with > the subtype part of the declaration. It is not > attached to each individual data object; it > applies to all four of them. > >> But does that actually achieve what I want? Thanks. I did not know it! :-) - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- In matters of style, swim with the current; in matters of principle, stand like a rock. (Thomas Jefferson) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwNgACgkQM0LLzLt8MhxJwACeKXQNuw9b/r6HNoEuvLaCpStI NRAAn3Qn6Csb4hEWtME0lXKaXPrQik/m =gThP -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:33:26 +0100 Message-ID: <8739rldv89.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:uOE0BQPdu466euSqSzd6UQGjCWE= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 38 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=4P=9m4l=a\cb>:U6jKdTQlYSB=nbEKnkk71459NG4aK_]RP;@H2onO>`Ol[NBH>dKMXJ_dg^BhgFJHF`K]idDh X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4284 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jonathan Bromley writes: > On Nov 1, 9:25 am, Merciadri Luca wrote: > >> Can one write, e.g. in an architecture environment, >> >> == >> signal a, b, c: integer range 0 to 10 >> == >> ? > > Yes, but wouldn't it be kinder to your readers > and reviewers if you write > > subtype my_range is integer range 0 to 10; > signal a : my_range; > signal b : my_range; > signal c : my_range; Yes, exactly. Thanks for the tip. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- When making your choices in life, do not forget to live. (Samuel Johnson) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwaYACgkQM0LLzLt8MhwGDwCfZW9qH/2HdGWjfCihl7jd4zCb cpEAnjlzeuw53rvYk/g6aXFOW3T4kYgd =mM/K -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Two different `architecture' implementations? From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:38:53 +0100 Message-ID: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:E9LitQSyytBS2dmP8bYDr9So8Yo= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 54 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=1>iDM1J[mF_0Sc_VCmP]hZYSB=nbEKnk[71459NG4QK_]RP;@H2o^O>`Ol[NBH>TKMXJ_dg^BhWFJHF`K]idDX X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4285 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I generally write == architecture my_arch of my_stuff is - -- signal, etc., declarations begin process - -- var declarations begin - -- code end process; end my_arch; == but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden designs PTY., LTD., consultant), that he did it this way: == architecture my_arch of my_stuff is - -- signal, etc., declarations begin process is begin end process; end architecture my_arch; == There are two main differences between our approaches. The first is that he uses the `is' keyword after `process'. The second is that he writes `architecture' before the architecture's name, in the closing line of the architecture my_arch. Is there a reason to prefer one of the approaches to the other? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm =Qs9G -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t35g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Mon, 1 Nov 2010 06:49:17 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <907eb12b-b53d-4125-9737-aa376cbfa017@t35g2000yqj.googlegroups.com> References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288619359 1936 127.0.0.1 (1 Nov 2010 13:49:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 13:49:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000yqj.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4286 Both are optional. I prefer adding "is" after a process statement (after the sensitivity clause, if present), simply because it makes it read more like the other vhdl items that have their own declarative regions. I also prefer adding the "architecture" keyword after the end statement, before the name of the architecture, because most "end" statements have a keyword with them identifying what type of structure is being ended (end if, end loop, etc.) But it really boils down to personal preference. I don't mind a little extra typing for syntactic consistency. Andy From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!goblin1!goblin.stu.neva.ru!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? Date: Mon, 1 Nov 2010 07:00:33 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <18b5f159-9132-4b64-921c-deecda782703@t13g2000yqm.googlegroups.com> References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288620033 7946 127.0.0.1 (1 Nov 2010 14:00:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 14:00:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4287 On Nov 1, 7:13=A0am, Jonathan Bromley wrote: > On Nov 1, 9:25=A0am, Merciadri Luca wrote: > > > Can one write, e.g. in an architecture environment, > > > =3D=3D > > signal a, b, c: integer range 0 to 10 > > =3D=3D > > ? > > Yes, but wouldn't it be kinder to your readers > and reviewers if you write > > subtype my_range is integer range 0 to 10; > signal a : my_range; > signal b : my_range; > signal c : my_range; > > ? > -- > Jonathan Bromley Kindness to readers/reviewers is often not quite so simple. If each signal declaration were followed by a comment about what the signal was for (as I often do), I would whole-heartedly agree with separate declarations. If I'm trying to get the point across that all three are the same type, that is communicated most effectively if they are declared in the same statement. Of course, that does not mean that I would declare all of my std_logic (or boolean) signals with one statement either. For example, I very rarely use a dual-process (combinatorial & clocked) representation, but when I do, I prefer to declare the combinatorial and register signals in the same statement (with an end- of-line comment that defines the data held by both, the names will identify which is the reg). Andy From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> <907eb12b-b53d-4125-9737-aa376cbfa017@t35g2000yqj.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 15:57:17 +0100 Message-ID: <87wroxum5u.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:UzEENIk6t86YWwK93Hhe7ZKVJTw= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 36 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=Q`G4QK_]RP;@H2o^O>`Ol[NBH>T^T9NAEJJNBSRR\U@^P4?eP X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4288 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Andy writes: > Both are optional. I prefer adding "is" after a process statement > (after the sensitivity clause, if present), simply because it makes it > read more like the other vhdl items that have their own declarative > regions. > > I also prefer adding the "architecture" keyword after the end > statement, before the name of the architecture, because most "end" > statements have a keyword with them identifying what type of structure > is being ended (end if, end loop, etc.) I agree with you on both points. > But it really boils down to personal preference. I don't mind a little > extra typing for syntactic consistency. You're right. I just thought there was some subtle difference on another point of view than aesthetic considerations, but apparently not. Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Luck is what happens when preparation meets opportunity. (Lucius Annaeus Seneca) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzO1UwACgkQM0LLzLt8MhyazACfX8Qv9HfOhZJ1za2a0vOaMPhS VGwAnAon0L2ixNe9C0Qvn6Kt8ZyKBEdt =hTgf -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l17g2000yqe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Mon, 1 Nov 2010 23:16:30 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288678590 32600 127.0.0.1 (2 Nov 2010 06:16:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 06:16:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l17g2000yqe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4289 On 1 Nov., 14:38, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I generally write > > == > architecture my_arch of my_stuff is > - -- signal, etc., declarations > begin > process > - -- var declarations > begin > - -- code > end process; > end my_arch; > == > > but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden > designs PTY., LTD., consultant), that he did it this way: > > == > architecture my_arch of my_stuff is > - -- signal, etc., declarations > begin > process is > begin > end process; > end architecture my_arch; > == > > There are two main differences between our approaches. The first is > that he uses the `is' keyword after `process'. The second is that he > writes `architecture' before the architecture's name, in the closing > line of the architecture my_arch. > > Is there a reason to prefer one of the approaches to the other? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln) > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld > JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm > =Qs9G > -----END PGP SIGNATURE----- Hi Merciadri. every few years the VHDL standard gets reworked. Beginning with first release in 1987, then came 1993 which should now be accepted by all tools. 2002 was next and most of the changes should be available in the tools. 2008 is the latest change but the tools just started to adopt the new stuff. In your simulator there may be a compile switch to select the allowed standard (e.g. modelsims vcom: -87 -93-2002). While both of your code examples will pass vcom with the -93 or -2002 option, I suspect that the second example will fail with the -87 option enabled. Just give it a try. Have a nice simulation Eilert From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: April Andy Newsgroups: comp.lang.vhdl Subject: Boracay Weather Forecast Date: Tue, 2 Nov 2010 00:39:50 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <8f83eabe-2b49-441c-85b7-acb0a60d5ae5@s4g2000yql.googlegroups.com> NNTP-Posting-Host: 122.144.115.238 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288683590 11439 127.0.0.1 (2 Nov 2010 07:39:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 07:39:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=122.144.115.238; posting-account=Lh1MHAoAAAAJRapwydaEfYdCvKe3AE53 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.1.15) Gecko/20101026 Firefox/3.5.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4290 I'd like to know what's the perfect time to visit the Philippines? I'd like to go to Boracay and wonder where I can get the best and accurate Boracay Weather Forecast in the Philippines? I'd like to visit Boracay island and enjoy all sorts of activities in the day within the island, such as day sports,Paraw, Paragliding, sunbathing, island hopping and so much more. You can go partying until the wee hours of the morning, immerse in the local talents of fire dancers, or better yet enjoy the warm ocean breeze while sipping pi=F1a colada by the seashore. So better visit the Island when The Weather is good. For more information, visit http://www.BoracayWeather.com From newsfish@newsfish Fri Dec 24 22:55:29 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Declaration hides port port_name / Port port_name hidden by declaration in architecture From: Merciadri Luca Organization: ULg Date: Tue, 02 Nov 2010 12:41:13 +0100 Message-ID: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:ea7nE0X3BJh1VVgUh/VNA8auXWg= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 26 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=YMn12QG4aK_]RP;@H2onO>`Ol[NBH>dfSJQkLI]17dY31n6hZd6Oj X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4291 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, When copiling a .vhd that I wrote these days, I get no errors with GHDL, but warnings such as `Declaration hides port port_name' and `Port port_name hidden by declaration in architecture.' Any idea of what it could be caused by? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Remember, no one can make you feel inferior, without your consent. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 =8Qmi -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!p1g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Declaration hides port port_name / Port port_name hidden by declaration in architecture Date: Tue, 2 Nov 2010 06:29:03 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288704543 6363 127.0.0.1 (2 Nov 2010 13:29:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 13:29:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p1g2000yqm.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4292 On Nov 2, 6:41=A0am, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > When copiling a .vhd that I wrote these days, I get no errors with > GHDL, but warnings such as `Declaration hides port port_name' and > `Port port_name hidden by declaration in architecture.' > > Any idea of what it could be caused by? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > Remember, no one can make you feel inferior, without your consent. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p > 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 > =3D8Qmi > -----END PGP SIGNATURE----- You have probably declared a signal in the architecture with the same name as a port on the entity. Thus you have no way to access the port from within the architecture. Andy From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Tue, 2 Nov 2010 10:36:33 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 188.28.190.41 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288719393 11623 127.0.0.1 (2 Nov 2010 17:36:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 17:36:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=188.28.190.41; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4293 On Oct 22, 4:33=A0pm, Paul Uiterlinden wrote: > jacko wrote: > > Don't be afraid to apparently duplicate a lot of code. This refers to > > say having 2 copies of a case statement with differing when clauses > > based on some outer state of the machine being coded. It does not > > consume many extra resources, and can lead to a better data flow. > > What do yo mean with "apparently duplicate a lot of code"? If it really > means copying and pasting a lot of code, I would object. It will result i= n > hard to mantain code. I thoroughly dislike copy-and-paste code. case A when a =3D> case B when b =3D> case B In this example the case B structure is repeated/duplicated. Although it may seem like a good idea to combine the case B into one case and then test case A internally, often the process structure suggest one way as better, case is better than if most of the time because it will warn more than if. Real vs. apparent, copy case delete assignments, put new in context assignments. best hardware performance is often achieved with not with the most beautiful simple code, but with the necessary code to dataflow the signals to pass through a minimal of logic and placing all logic before the flip flop. Look up 'Moore State Machine' which is preferred to a Mealey machine in synchronous design. Cheers Jacko From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: Merciadri Luca Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Tue, 2 Nov 2010 13:21:10 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 85.26.2.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288729270 3653 127.0.0.1 (2 Nov 2010 20:21:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 20:21:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=85.26.2.239; posting-account=V6LrigoAAACudvZ0KlT32AF1BSfjssFY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.19) Gecko/2010072023 Firefox/3.0.6 (Debian-3.0.6-3),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4294 On Nov 2, 7:16=A0am, backhus wrote: > On 1 Nov., 14:38, Merciadri Luca > wrote: > > > > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > > Hi, > > > I generally write > > > =3D=3D > > architecture my_arch of my_stuff is > > - -- signal, etc., declarations > > begin > > process > > - -- var declarations > > begin > > - -- code > > end process; > > end my_arch; > > =3D=3D > > > but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden > > designs PTY., LTD., consultant), that he did it this way: > > > =3D=3D > > architecture my_arch of my_stuff is > > - -- signal, etc., declarations > > begin > > process is > > begin > > end process; > > end architecture my_arch; > > =3D=3D > > > There are two main differences between our approaches. The first is > > that he uses the `is' keyword after `process'. The second is that he > > writes `architecture' before the architecture's name, in the closing > > line of the architecture my_arch. > > > Is there a reason to prefer one of the approaches to the other? > > > Thanks. > > - -- > > Merciadri Luca > > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > > - -- > > > You can fool all of the people some of the time, some of the people all= of the time, but you can't fool all of the people all of the time. (Abraha= m Lincoln) > > -----BEGIN PGP SIGNATURE----- > > Version: GnuPG v1.4.9 (GNU/Linux) > > Comment: Processed by Mailcrypt 3.5.8 > > > iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld > > JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm > > =3DQs9G > > -----END PGP SIGNATURE----- > > Hi Merciadri. > every few years the VHDL standard gets reworked. > Beginning with first release in 1987, then came 1993 which should now > be accepted by all tools. > 2002 was next and most of the changes should be available in the > tools. > 2008 is the latest change but the tools just started to adopt the new > stuff. > > In your simulator there may be a compile switch to select the allowed > standard (e.g. modelsims vcom: -87 -93-2002). > While both of your code examples will pass vcom with the -93 or -2002 > option, > I suspect that the second example will fail with the -87 option > enabled. > > Just give it a try. > Have a nice simulation > =A0 Eilert Thanks for pointing this out. From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Declaration hides port port_name / Port port_name hidden by declaration in architecture References: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Tue, 02 Nov 2010 21:23:53 +0100 Message-ID: <87aalrjwyu.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:IZ83Gfh06B3wbZUAhkTW5J5SPQQ= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 53 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=5G41K_]RP;@H2o>O>`Ol[NBH>4oGK4^hS99d>:c@X[;\3KR6 X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4295 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Andy writes: > On Nov 2, 6:41 am, Merciadri Luca > wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> When copiling a .vhd that I wrote these days, I get no errors with >> GHDL, but warnings such as `Declaration hides port port_name' and >> `Port port_name hidden by declaration in architecture.' >> >> Any idea of what it could be caused by? >> >> Thanks. >> - -- >> Merciadri Luca >> Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ >> - -- >> >> Remember, no one can make you feel inferior, without your consent. >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.9 (GNU/Linux) >> Comment: Processed by Mailcrypt 3.5.8 >> >> iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p >> 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 >> =8Qmi >> -----END PGP SIGNATURE----- > > You have probably declared a signal in the architecture with the same > name as a port on the entity. Thus you have no way to access the port > from within the architecture. Exactly. Thanks! - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- God is a comedian playing to an audience too afraid to laugh. (Voltaire) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzQc1kACgkQM0LLzLt8MhyHPgCeLPBh8u6c+v0GRm0z7A0lWHLW GrcAn2IKdzGp5VGnXmTD8bsBjVFFU0uA =Yx7q -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Tue, 02 Nov 2010 16:05:51 -0700 Lines: 24 Message-ID: <8jbjq4F97uU1@mid.individual.net> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vLZSnFG9z6UrU9gdIgpZ8QofA1JflCh5yYjAOUz1ZIiPq/QTaN Cancel-Lock: sha1:EYMFnzjUEoYntOX7xE9udNGNmHQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4296 On 11/2/2010 10:36 AM, jacko wrote: > > case A > when a => case B > when b => case B > > In this example the case B structure is repeated/duplicated. I agree that duplicating a case expression is sometimes easier to read than a long elsif. > Look up > 'Moore State Machine' which is preferred to a Mealey machine in > synchronous design. If you mean that a design with output registers is usually preferred to one without, I agree. Or if you mean that pipelining for timing closure involves some trial and error, I agree. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 03 Nov 2010 16:07:15 +0000 Organization: TRW Conekt Lines: 26 Message-ID: References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 85cuRHZ/wmulknvZ2gkzrwvl4PRAqMZWQZFsrXjnqgo4xRGi8= Cancel-Lock: sha1:8skjLd8baQh73nt/ANKvCH7JYss= sha1:7DSQkXPoTpC6GUJP5xZae2werq0= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4298 Mike Treseler writes: > On 11/2/2010 10:36 AM, jacko wrote: >> >> case A >> when a => case B >> when b => case B >> >> In this example the case B structure is repeated/duplicated. > > > I agree that duplicating a case expression is sometimes > easier to read than a long elsif. > But for ease of maintenance, I'd tend to move the duplicated content to a subprogram and call it from both cases, rather than copy/paste. Too easy to forget to update both sides when something changes. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:30 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 03 Nov 2010 11:39:37 -0700 Lines: 25 Message-ID: <8jdoisFebpU1@mid.individual.net> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 7mHveXqD4G6Mb389FD/zQQb3UkportvY/AmJj4GfJ6/Avt24uU Cancel-Lock: sha1:BEPf5GGVQ1WUfkmSCsabPIBbxUk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4299 >> On 11/2/2010 10:36 AM, jacko wrote: >>> case A >>> when a => case B >>> when b => case B >>> >>> In this example the case B structure is repeated/duplicated. Mike Treseler wrote: >> I agree that duplicating a case expression is sometimes >> easier to read than a long elsif. On 11/3/2010 9:07 AM, Martin Thompson wrote: > But for ease of maintenance, I'd tend to move the duplicated content > to a subprogram and call it from both cases, rather than copy/paste. > Too easy to forget to update both sides when something changes. Good point. -- Mike Treseler ____________________________ case A_v is when a => my_fn(B); when b => my_fn(B); when c => my_fn(Z); end case; From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!fh19g2000vbb.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 3 Nov 2010 12:10:18 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> NNTP-Posting-Host: 188.28.123.144 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288811418 16853 127.0.0.1 (3 Nov 2010 19:10:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 3 Nov 2010 19:10:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fh19g2000vbb.googlegroups.com; posting-host=188.28.123.144; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4300 On Nov 2, 11:05=A0pm, Mike Treseler wrote: > On 11/2/2010 10:36 AM, jacko wrote: > > > > > case A > > =A0 =A0when a =3D> =A0case B > > =A0 =A0when b =3D> =A0case B > > > In this example the case B structure is repeated/duplicated. > > I agree that duplicating a case expression is sometimes > easier to read than a long elsif. > > > Look up > > 'Moore State Machine' which is preferred to a Mealey machine in > > synchronous design. Another example was duplicating a register for to separate uses of the content. While increasing fan in, it can reduce fan out, which is preferred for a low fan in signal set anyhow when it has a high fan out. This fan balancing can be useful. Some tools can do this balancing automatically, but sometimes the differing content of register possibility can be used to good effect. Some tools automatically throw logic to the other side of the flip flop to balance logic complexity between flops. > If you mean that a design with output registers > is usually preferred to one without, I agree. Yes, design with registered output. Registered input is also a good idea... It does let full clock speed of device be used, but with external memory say, it needs an extra clock state in the state machine. > Or if you mean that pipelining for timing closure > involves some trial and error, I agree. Yes this relates to the above, I had a case where some logic on the inputs before the first register, and the delay cycle was not acceptable, so the auto logic movement was used to good effect. In the X3 I may explicitly do this adjustment by using a variable combinational of register output instead of an if then selecting register input. It's that annoying feeling of SRAM access delay PLUS some logic delay, before the clock, and expressing this to the tool. This is preferable to a 20% speed penalty as the critical path is elsewhere. The splitting fan of the inputs, can cause a bit of a headache as you decide on the fast input register meaning, as there is likely to only be one per input.... Cheers Jacko http://nibz.googlecode.com From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: boolean operations on "integer" in VHDL'93 Date: Thu, 04 Nov 2010 12:28:31 +0100 Organization: Aioe.org NNTP Server Lines: 14 Message-ID: NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4301 Hello, I really miss the "or", "and", "xor", "not", "shr", "shl" etc. operators in the "integer" type. To my knowledge, they are available only for the types like std_(u)logic(_vector) but they are... slow. I would like to do some quick behavioural stuff and I'm ready to code some extensions to my favorite simulator (GHDL) but I wonder if anyone knows an existing solution. Any hint ? Did I miss something ? yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Nov 2010 15:28:33 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Thu, 04 Nov 2010 20:37:54 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-JAzLiGW1d5hQjW/eKWwvOxKNOSTfNIZCOXCD9Dvr2U0z5Sz/74bpYoPpzPH4XksSTYKJ5vkHq69HTYw!EZRdJIUMhkfV+bH2FpMtWHuhk/B5ETEKLUjNkWl56AoZleiRZLt7BuauITmo5MLe6lxoIXg4icMX!O+A= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1688 Xref: feeder.eternal-september.org comp.lang.vhdl:4302 On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >Hello, > >I really miss the "or", "and", "xor", "not", "shr", "shl" etc. >operators in the "integer" type. To my knowledge, they are available >only for the types like std_(u)logic(_vector) but they are... slow. >I would like to do some quick behavioural stuff and >I'm ready to code some extensions to my favorite simulator >(GHDL) but I wonder if anyone knows an existing solution. > >Any hint ? Did I miss something ? bit_vector should be less heavyweight than std_logic_vector. - Brian From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: Matt Longbrake Newsgroups: comp.lang.vhdl Subject: Generate statement with varying signal width Date: Thu, 4 Nov 2010 14:19:31 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 134.131.125.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288905572 17274 127.0.0.1 (4 Nov 2010 21:19:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Nov 2010 21:19:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=134.131.125.49; posting-account=MSTlZgoAAAD_zHgCSsJ-fGgs0cHA71At User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11 GTB7.1 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4303 Is there any way to use a signal from a previous generate loop iteration in a later iteration? As an example, say you were building a variable length adder chain. The output of each adder is one bit wider than the previous adder. The inelegant solution would be to create an array of std_logic_vector where the width of each vector is as wide as the widest needed. These vectors are just selected based on the loop index. The problem with this is that you get all kinds of unused signal warnings when you synthesize. As an alternative approach, you could use the declarative region of the generate loop to create a signal of the appropriate width for the current iteration. Then, if you could somehow access that signal from the next iteration you could have variable width signals and avoid a bunch of warnings. Is something like this possible? From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Thu, 04 Nov 2010 23:13:47 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <4cd3301c$0$10046$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 04 Nov 2010 23:13:48 MET NNTP-Posting-Host: 82.246.229.10 X-Trace: 1288908828 news-3.free.fr 10046 82.246.229.10:52064 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4304 Le 04/11/2010 12:28, whygee a écrit : > Hello, > > I really miss the "or", "and", "xor", "not", "shr", "shl" etc. > operators in the "integer" type. To my knowledge, they are available > only for the types like std_(u)logic(_vector) but they are... slow. > I would like to do some quick behavioural stuff and > I'm ready to code some extensions to my favorite simulator > (GHDL) but I wonder if anyone knows an existing solution. > > Any hint ? Did I miss something ? That's strong typing for you... Nicolas From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g26g2000vba.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: combinatorial process not simulating correctly Date: Thu, 4 Nov 2010 16:33:34 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288913615 24820 127.0.0.1 (4 Nov 2010 23:33:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Nov 2010 23:33:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g26g2000vba.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13083 comp.lang.vhdl:4305 Hi, I coded a combinatorial process. However when simulated in Modelsim, the output does not change when my input which is in the process sensitivity list changes.the output remains constant and takes into account only the initial value of my input. when i add a clk to my sensitivity list, i get the expected output. However my process should be combinatorial! there is nothing wrong with my SIMPLE combinatorial process. any help please?? I used ISE synthesiser tool to synthesise my programs . CHEERS From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed-00.mathworks.com!newsfeed2.dallas1.level3.net!news.level3.com!bos-service1.raytheon.com!bos-service2b.ext.ray.com.POSTED!53ab2750!not-for-mail Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly From: Ian Shef References: Message-ID: User-Agent: Xnews/06.08.25 Lines: 28 Date: Fri, 05 Nov 2010 00:35:23 GMT NNTP-Posting-Host: 147.24.143.70 X-Complaints-To: news@ext.ray.com X-Trace: bos-service2b.ext.ray.com 1288917323 147.24.143.70 (Fri, 05 Nov 2010 00:35:23 UTC) NNTP-Posting-Date: Fri, 05 Nov 2010 00:35:23 UTC Organization: Raytheon Company Xref: feeder.eternal-september.org comp.arch.fpga:13084 comp.lang.vhdl:4306 Angus wrote in news:cc605b18-e83d-4ffd-82a9- 6b13ac150ee8@g26g2000vba.googlegroups.com: > Hi, > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes.the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . > > CHEERS > My crystal ball is broken today, and my extra-sensory perception doesn't seem to reach to your location. :-) Please provide your code. All of it. Pasted, not re-typed. I read your posting in comp.arch.fpga, but I am going to guess (since you didn't provide much information) that because you also posted to comp.lang.vhdl then your code is probably VHDL. Maybe it is not as SIMPLE and as combinatorial as you think. Thanks! From newsfish@newsfish Fri Dec 24 22:55:31 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:38:59 +0000 (UTC) Organization: A noiseless patient Spider Lines: 25 Message-ID: References: Injection-Date: Fri, 5 Nov 2010 00:38:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="27891"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NCndu2ILyCZ7WY1KhuYzJ" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:XjZr8PfAmxJ86VyHX1aUbIrpUms= Xref: feeder.eternal-september.org comp.arch.fpga:13085 comp.lang.vhdl:4307 In comp.arch.fpga Angus wrote: > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes. That seems to mean that it isn't combinatorial. > the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. It shouldn't have a clock, so how can you add one? OK, if you add to the sensitivity list and the output changes when that new signal changes, then it seems that the input is not in the sensitivity list. Could it be spelled wrong, so that it looks like it is in the list? > However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . -- glen From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!multikabel.net!newsfeed20.multikabel.net!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!n32g2000prc.googlegroups.com!not-for-mail From: Amal Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Thu, 4 Nov 2010 17:44:02 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 119.194.48.102 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288917843 5787 127.0.0.1 (5 Nov 2010 00:44:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 00:44:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000prc.googlegroups.com; posting-host=119.194.48.102; posting-account=aaW8HAkAAABqrMdJYSf-acWh2T9ofAYm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.11 (KHTML, like Gecko) Chrome/9.0.570.0 Safari/534.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4308 On Nov 4, 5:19=A0pm, Matt Longbrake wrote: > Is there any way to use a signal from a previous generate loop > iteration in a later iteration? =A0As an example, say you were building > a variable length adder chain. =A0The output of each adder is one bit > wider than the previous adder. =A0The inelegant solution would be to > create an array of std_logic_vector where the width of each vector is > as wide as the widest needed. =A0These vectors are just selected based > on the loop index. =A0The problem with this is that you get all kinds of > unused signal warnings when you synthesize. > > As an alternative approach, you could use the declarative region of > the generate loop to create a signal of the appropriate width for the > current iteration. =A0Then, if you could somehow access that signal from > the next iteration you could have variable width signals and avoid a > bunch of warnings. =A0Is something like this possible? There are a number of things you can do. You can declare signals outside the generate block and make an assignment based on generate index: signal a : std_logic_vector(7 downto 0); signal b : std_logic; g_test: for i in 0 to 7 generate if ( i =3D 0 ) then b <=3D a(i); end if end generate : g_test The other option you are looking for is possible by declaring signals within the generate for: g_test: for i in 0 to 7 generate signal x : std_logic_vector(i+2 downto 0); x(i+2 downto 0) <=3D whatever; end generate : g_test In this case, you will have 8 x's defined as: x(2:0), x(3:0), ... x(9:0). But only accessible within the generate block. Cheers, -- Amal From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 05:30:12 +0100 Organization: Aioe.org NNTP Server Lines: 21 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4309 Hi ! Brian Drummond wrote: > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >> Any hint ? Did I miss something ? > bit_vector should be less heavyweight than std_logic_vector. sure but i want to use integers :-/ > - Brian Nicolas Matringe wrote : > That's strong typing for you... it's not a problem of typing, i can create new functions, however I see nowhere an explanation of these missing operations. why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) and not on integer, as in any other language ? > Nicolas yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f33g2000yqh.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:21:22 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288941682 21033 127.0.0.1 (5 Nov 2010 07:21:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:21:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000yqh.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13090 comp.lang.vhdl:4310 all right here you go (I read there was A problem with MODELSIM in simulating combinatorial processes): SIGNAL DATA1 : Data_t:=(7,3,2); SIGNAL DATA2 : Data_t :=(9,5,1); PROCESS (SEL) BEGIN -- CASE SEL IS WHEN "00" =>temp<=DATA1; WHEN "01" =>temp<=DATA2; WHEN OTHERS =>NULL; END CASE; Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1), 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); END PROCESS; when i change SEL in my testbench, Data does not change. I had to embed my CASE within a clk edge detection to see the changes on modelsim CHEERS From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:24:42 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <82821ba5-b77f-4059-9ea4-62c311d1d9c8@t13g2000yqm.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288941882 19983 127.0.0.1 (5 Nov 2010 07:24:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:24:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13091 comp.lang.vhdl:4311 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS i forgot to add SIGNAL temp : Data_t ; From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f33g2000yqh.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 00:24:46 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <95c5cdc7-2603-4c91-a54b-e145df0afd56@f33g2000yqh.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288941886 19994 127.0.0.1 (5 Nov 2010 07:24:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:24:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000yqh.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4312 On 5 Nov., 05:30, whygee wrote: > Hi ! > > Brian Drummond wrote: > > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: > >> Any hint ? Did I miss something ? > > bit_vector should be less heavyweight than std_logic_vector. > > sure but i want to use integers :-/ > > =A0> - Brian > > Nicolas Matringe wrote : > =A0> That's strong typing for you... > it's not a problem of typing, i can create new functions, > however I see nowhere an explanation of these missing operations. > why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) > and not on integer, as in any other language ? > > =A0> Nicolas > yg > --http://ygdes.com/http://yasep.org Hi, maybe it's because integers were not intended to be used for your logic data. They are made for array indexing and loop counting stuff, where the need for logic functions is neglectible. If you want to do convenient algorithmic stuff with VHDL use numeric_std types signed and unsigned. While the std_logic types need more computing time in your simulator, the advantage is that they are not limited to 32 bit max. width. You may not need this in your current project, but maybe somewhen. Have a nice simulation Eilert From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:27:59 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288942079 21701 127.0.0.1 (5 Nov 2010 07:27:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:27:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13092 comp.lang.vhdl:4313 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS obviously,my case statement has 4 conditions, that';s why SEL is of 2 bits. i simplified the code in order not to distract you from the real problem. From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!b25g2000vbz.googlegroups.com!not-for-mail From: "maurizio.tranchero" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:39:53 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <1cf54872-86f1-4bea-9ef3-d853e3bc3a8d@b25g2000vbz.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 217.140.96.21 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288942793 27652 127.0.0.1 (5 Nov 2010 07:39:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:39:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b25g2000vbz.googlegroups.com; posting-host=217.140.96.21; posting-account=uO6v-goAAABkLf6DVKtE8Z5Ly72qnjLn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.1.1) Gecko/20090715 Firefox/3.5.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13093 comp.lang.vhdl:4314 On Nov 5, 8:27=A0am, Angus wrote: > On Nov 5, 7:21=A0am, Angus wrote: > > > > > all right here you go (I read there was A problem with MODELSIM in > > simulating combinatorial processes): > > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > > PROCESS (SEL) > > BEGIN > > -- > > =A0 =A0 =A0 =A0 =A0CASE SEL IS > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > > =A0 =A0 =A0 =A0 END CASE; > > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC= _VECTOR(temp(1), > > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > > END PROCESS; > > when i change SEL in my testbench, Data does not change. I had to > > embed my CASE within a clk edge detection to see the changes on > > modelsim Your process isn't fully combinatorial: a process in order to be combinatorial has to contain in its sensitivity list ALL the inputs that can affect the output. In your case you only have the multiplexer selector in the sensitivity list, while the DATA1 and DATA2 are not included. Try to add them and it will work. Ciao! maurizio From newsfish@newsfish Fri Dec 24 22:55:32 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!optima2.xanadu-bbs.net!news.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 5 Nov 2010 01:30:49 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <639b89a6-5417-4264-bd1b-1c93c9d48525@r14g2000yqa.googlegroups.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288945849 21862 127.0.0.1 (5 Nov 2010 08:30:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:30:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4315 =A0The inelegant solution would be to > create an array of std_logic_vector where the width of each vector is > as wide as the widest needed. =A0 Very inelegent, because unsigned/signed types are what you should be using if you're doing arithmatic, not std_logic_vector. But otherwise, you cannot access signals out of scope (as you were suggesting with the 2nd paragraph). Personally, Id probably just convert them to integers and back to unsigned/signed at the end (if I really need to - why not just keep it an integer?) and then let the synthesiser chose the correct bit length. From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 01:32:14 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288946047 23604 127.0.0.1 (5 Nov 2010 08:34:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:34:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4316 On Nov 4, 11:28=A0am, whygee wrote: > Hello, > > I really miss the "or", "and", "xor", "not", "shr", "shl" etc. > operators in the "integer" type. To my knowledge, they are available > only for the types like std_(u)logic(_vector) but they are... slow. > I would like to do some quick behavioural stuff and > I'm ready to code some extensions to my favorite simulator > (GHDL) but I wonder if anyone knows an existing solution. > > Any hint ? Did I miss something ? > > yg > --http://ygdes.com/http://yasep.org Use signed/unsigned instead? you can do arithmatic and boolean with them. From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 01:34:32 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288946072 28624 127.0.0.1 (5 Nov 2010 08:34:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:34:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13095 comp.lang.vhdl:4317 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS As maurizio has pointed out, if you add DATA1 and DATA2 to the sensitivity list it will work. But one word of warning - this code will create latches, which is probably not what you want to do. From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 03:56:29 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 09:05:53 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 53 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-EeHo01ijOqkJ/AULeWqM3UXU/atnjLG+KGaBjNp6b/MAe9MzdcnHPwGbwfkyeYoGuTahHkXwJfQojpq!2hzsk9wUsl4wwPePbswxKAG7iwQRwS8Mm7+6TiOujdJ5m558ydfP1nBjYKpXp5Zt9YEX0TCtzLJD!1wIf X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3160 Xref: feeder.eternal-september.org comp.lang.vhdl:4318 On Fri, 05 Nov 2010 05:30:12 +0100, whygee wrote: >Hi ! > >Brian Drummond wrote: >> On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >>> Any hint ? Did I miss something ? >> bit_vector should be less heavyweight than std_logic_vector. >sure but i want to use integers :-/ > > > - Brian > >Nicolas Matringe wrote : > > That's strong typing for you... >it's not a problem of typing, i can create new functions, >however I see nowhere an explanation of these missing operations. >why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) >and not on integer, as in any other language ? Not "any" other language. Mainly C and its followers, which tend to trade a superficial convenience for a thousand subtle ways to screw yourself. These operations are not "missing" in VHDL's integer types; they were never part of Integer at any time in the history of mathematics, and there is no rational reason for them to be now. They basically crept into C's "int" via some late 1960's assembly language, and we have been paying the price in software "quality" ever since. If you need to "AND" two quantities, you can be pretty close to certain that they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, maybe. Control signals, possibly. Oh and while I'm still coffee-deprived, adding two positive integers will NEVER EVER result in a negative integer. Integers don't, and can't, overflow. >From which we can see that C doesn't actually have ANY integer data types at all - merely a bit-vector type, misleadingly labelled "int", on which they allow instructions that occasionally resemble addition, etc. (Pedantically, modulo-n addition). Oh, and "unsigned char", as if there was ever such a thing as a signed character. (If you think this is a little OTT, just count the number of "integer overflow" bugs reported in a project like Firefox. And weep.) - Brian From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.142.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 04:02:11 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 05 Nov 2010 09:11:35 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <88i7d65se7oasvf313gt6u631jo9ppamjq@4ax.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-pxwVdSL9EhPmkTp0ZcmDG6y4ktfoSKFOQhx5c3JCZc3E466HwKORWCDsngkwaK38Y8zblfqQztZb/l3!hM7eS35JvOGBr6cy+AGAW4AiUbC25MI3XaCRCsnPjxYSIevXWHqnm/awXjdSx+55Om/FYu895NKy!jVEW X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1975 Xref: feeder.eternal-september.org comp.lang.vhdl:4319 On Thu, 4 Nov 2010 14:19:31 -0700 (PDT), Matt Longbrake wrote: >Is there any way to use a signal from a previous generate loop >iteration in a later iteration? As an example, say you were building >a variable length adder chain. The output of each adder is one bit >wider than the previous adder. You may be able to do this by nesting two generate statements, using the outer one's loop variable as the inner one's control parameter. I would be wary of encountering synthesis bugs, and check the results unusually carefully. Alternatively, realise that synthesis warnings are merely warnings, not errors, and can safely be ignored if you understand and expect them. Synthesis tools will do an excellent job of trimming fixed-width adders down to the size required. - Brian From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 10:20:58 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 49 Message-ID: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b271b4f9.news.skynet.be X-Trace: 1288948858 news.skynet.be 14248 91.177.173.208:40769 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4320 Brian Drummond wrote: > Not "any" other language. > > Mainly C and its followers, which tend to trade a superficial convenience for a > thousand subtle ways to screw yourself. > > These operations are not "missing" in VHDL's integer types; they were never part > of Integer at any time in the history of mathematics, and there is no rational > reason for them to be now. > > They basically crept into C's "int" via some late 1960's assembly language, and > we have been paying the price in software "quality" ever since. > > If you need to "AND" two quantities, you can be pretty close to certain that > they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, > maybe. Control signals, possibly. > > Oh and while I'm still coffee-deprived, adding two positive integers will NEVER > EVER result in a negative integer. Integers don't, and can't, overflow. > > From which we can see that C doesn't actually have ANY integer data types at all > - merely a bit-vector type, misleadingly labelled "int", on which they allow > instructions that occasionally resemble addition, etc. (Pedantically, modulo-n > addition). > > Oh, and "unsigned char", as if there was ever such a thing as a signed > character. All true, but I think it is also possible to do it right and that the result is very useful, especially for hardware designers. I think a language like Python does it right. Integers are true integers, but through the boolean operators you have access to the underlying 2's complement representation if desired. What I do in MyHDL with the intbv type, is to add an indexing and slicing interface to such integers. The result is indeed a "dual mode" type. But for arithmetic, it doesn't have any of the confusion of signed/unsigned. I believe this is exactly what hardware designers need in practice. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Fri, 5 Nov 2010 03:04:56 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288951496 5876 127.0.0.1 (5 Nov 2010 10:04:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 10:04:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4321 On Nov 1, 8:09=A0am, Jonathan Bromley wrote: > On Nov 1, 10:45=A0am, Merciadri Luca wrote: > > > =3D=3D > > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE :=3D 0; > > =3D=3D > > > where MAX_VALUE is a constant. My ghdl compiler will be okay with this > > statement, but what is its result? > > Each of your four signals has the same subtype > (0 to MAX_VALUE). =A0The explicit initialization ":=3D0" > is redundant, because any VHDL variable or signal is > initialized to the left-most value in its value set; > in your case that value is 0 anyway. =A0All four > signals will have 0 as their initialization value. > > Note that the initial value is associated with > the subtype part of the declaration. =A0It is not > attached to each individual data object; it > applies to all four of them. > > > But does that actually achieve what I want? > > Only you can answer that :-) > -- > Jonathan Bromley That may be true for simulation, but for synthesis the initialization is often used for the initial value set during configuration. If the explicit assignment is omitted, will the synthesis tool match the simulation? Rick From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.tornevall.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!q18g2000vbm.googlegroups.com!not-for-mail From: "maurizio.tranchero" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 03:17:55 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 217.140.96.21 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288952275 12408 127.0.0.1 (5 Nov 2010 10:17:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 10:17:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbm.googlegroups.com; posting-host=217.140.96.21; posting-account=uO6v-goAAABkLf6DVKtE8Z5Ly72qnjLn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.1.1) Gecko/20090715 Firefox/3.5.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13096 comp.lang.vhdl:4322 > As maurizio has pointed out, if you add DATA1 and DATA2 to the > sensitivity list it will work. > But one word of warning - this code will create latches, which is > probably not what you want to do. Yes, Tricky, I forgot the latches...sorry for that Angus, each time in an HDL statement you leave a default behavior that simply keeps the previous value of a signal (when others => null, actually does this) you will introduce a latch element. A small advice, when you are developing HW, never forget that you are not writing software, but describing HW. Try to ask yourself "how this behavior can result in gates?" you will reduce a lot the number of unwanted behavior. Good luck! maurizio From newsfish@newsfish Fri Dec 24 22:55:33 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 05 Nov 2010 10:22:37 +0000 Organization: TRW Conekt Lines: 64 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 1SzUQU3P5cG7f0UawlHtMQjKImwnsZq2fu5TFRiRDfQM+4A3w= Cancel-Lock: sha1:Ik1vIWqQFpPoHhwmU5xmf35QuYc= sha1:KHYgeeFKg77XpFZYjmkIizMaKmI= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.arch.fpga:13097 comp.lang.vhdl:4323 Angus writes: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=(7,3,2); > SIGNAL DATA2 : Data_t :=(9,5,1); > > PROCESS (SEL) Do you not want DATA1 and DATA2 in here? Are you trying to latch your result *only* when SEL changes (and not when the data changes)? > BEGIN > -- > CASE SEL IS > WHEN "00" =>temp<=DATA1; > WHEN "01" =>temp<=DATA2; > WHEN OTHERS =>NULL; Here you've scheduled a transaction on temp to happen at the end of the process. > END CASE; > > > Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); Here you are using temp, but it hasn't updated yet as the process hasn't suspended. To get this to update the way you seem to want you need to use a variable for temp. That updates immediately. BTW, you're using conv_std_logic_vector, which means you must have used ieee.std_logic_arith - don't do that, use ieee.numeric_std. Some other threads on this: https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/389677dd60f7b91c/af0ec67dda4ee7ba?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith&pli=1#af0ec67dda4ee7ba https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffd35914d/83cc0f19350fc392?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith#83cc0f19350fc392 http://www.alteraforum.com/forum/showthread.php?t=20925 And some notes I made after writing about it on newsgroups once too often: http://www.parallelpoints.com/node/3 > END PROCESS; > when i change SEL in my testbench, Data does not change. Are you sure you're not just seeing it change on the *next* change of sel? > I had to > embed my CASE within a clk edge detection to see the changes on > modelsim Well, that's probably a good plan anyway, as I doubt the description above is remotely synthesisable... That should also show a pipelined behaviour though (where data changes one extra tick after sel changes). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 04:24:31 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288956271 14652 127.0.0.1 (5 Nov 2010 11:24:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 11:24:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4324 On Nov 5, 5:20=A0am, Jan Decaluwe wrote: > Brian Drummond wrote: > > Not "any" other language. > > > Mainly C and its followers, which tend to trade a superficial convenien= ce for a > > thousand subtle ways to screw yourself. > > > These operations are not "missing" in VHDL's integer types; they were n= ever part > > of Integer at any time in the history of mathematics, and there is no r= ational > > reason for them to be now. > > > They basically crept into C's "int" via some late 1960's assembly langu= age, and > > we have been paying the price in software "quality" ever since. > > > If you need to "AND" two quantities, you can be pretty close to certain= that > > they are, fundamentally, not integers. Instructions, perhaps. Sets of b= its, > > maybe. Control signals, possibly. > > > Oh and while I'm still =A0coffee-deprived, adding two positive integers= will NEVER > > EVER result in a negative integer. Integers don't, and can't, overflow. > > > From which we can see that C doesn't actually have ANY integer data typ= es at all > > - merely a bit-vector type, misleadingly labelled "int", on which they = allow > > instructions that occasionally resemble addition, etc. (Pedantically, m= odulo-n > > addition). > > > Oh, and "unsigned char", as if there was ever such a thing as a signed > > character. > > All true, but I think it is also possible to do it right and that > the result is very useful, especially for hardware designers. > > I think a language like Python does it right. Integers are true integers, > but through the boolean operators you have access to the underlying > 2's complement representation if desired. But that is the problem. Who says an integer is implemented as a 2's complement binary signal array? > What I do in MyHDL with the intbv type, is to add an indexing and slicing > interface to such integers. The result is indeed a "dual mode" type. But > for arithmetic, it doesn't have any of the confusion of signed/unsigned. > I believe this is exactly what hardware designers need in practice. So MyHDL assumes a specific implementation of integers in the hardware? If the OP wants to treat integers as an array of a binary data type, then he needs to write the functions to do that. He will either need to convert the integers to an array of binary values and perform the logic operation on those, or he can use looping constructs to isolate the individual bits of the integer and operate on those. The problem is not that it can't be done, the OP simply doesn't know how to write a function to do this. He is thinking at a very simple level expecting there to be logic operators on integers for him to use. He needs to consider how logic operators could be implemented on integers. Rick From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 15:09:27 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 47 Message-ID: <4cd41017$0$14253$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: f514c5e8.news.skynet.be X-Trace: 1288966167 news.skynet.be 14253 91.177.173.208:52422 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4325 rickman wrote: > On Nov 5, 5:20 am, Jan Decaluwe wrote: >> >> I think a language like Python does it right. Integers are true integers, >> but through the boolean operators you have access to the underlying >> 2's complement representation if desired. > > But that is the problem. Who says an integer is implemented as a 2's > complement binary signal array? The Python Language LRM of course. It's not an axioma. Other definitions and languages are perfectly feasible, although less practical probably. >> What I do in MyHDL with the intbv type, is to add an indexing and slicing >> interface to such integers. The result is indeed a "dual mode" type. But >> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >> I believe this is exactly what hardware designers need in practice. > > So MyHDL assumes a specific implementation of integers in the > hardware? The intbv type is an integer-like type with a defined bit-vector representation. Much like Verilog's signed and unsigned regs, with the big difference that integer arithmetic works as it should. At the same time, it's more "abstract" than VHDL's integer - no arbitrary 32 bit limit. Intbv's can be used as integers without ever referring to their bit vector representation. They can also be used as bit vectors without ever referring to their integer interpretation, for example to represent integers in different ways in hardware. However, it is equally possible to mix the 2 interpretations as needed. Let's be honest, that happens all the time in practical hardware design. I have a lot of sympathy for purity, but I find your call to it a litte surprizing. I thought you were in the process of moving from VHDL to Verilog for practical reasons :-) ? Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!42g2000prt.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 07:55:29 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> NNTP-Posting-Host: 173.13.214.113 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288968929 9462 127.0.0.1 (5 Nov 2010 14:55:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 14:55:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 42g2000prt.googlegroups.com; posting-host=173.13.214.113; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4326 On Nov 5, 10:09=A0am, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 5:20 am, Jan Decaluwe wrote: > > >> I think a language like Python does it right. Integers are true intege= rs, > >> but through the boolean operators you have access to the underlying > >> 2's complement representation if desired. > > > But that is the problem. =A0Who says an integer is implemented as a 2's > > complement binary signal array? > > The Python Language LRM of course. It's not an axioma. Other definitions > and languages are perfectly feasible, although less practical probably. That's great, but not useful for hardware design is it? > >> What I do in MyHDL with the intbv type, is to add an indexing and slic= ing > >> interface to such integers. The result is indeed a "dual mode" type. B= ut > >> for arithmetic, it doesn't have any of the confusion of signed/unsigne= d. > >> I believe this is exactly what hardware designers need in practice. > > > So MyHDL assumes a specific implementation of integers in the > > hardware? > > The intbv type is an integer-like type with a defined bit-vector > representation. Much like Verilog's signed and unsigned regs, with > the big difference that integer arithmetic works as it should. > At the same time, it's more "abstract" than VHDL's integer - no > arbitrary 32 bit limit. > > Intbv's can be used as integers without ever referring to their > bit vector representation. They can also be used as bit vectors > without ever referring to their integer interpretation, for example > to represent integers in different ways in hardware. However, it > is equally possible to mix the 2 interpretations as needed. Let's > be honest, that happens all the time in practical hardware design. > > I have a lot of sympathy for purity, but I find your call to it > a litte surprizing. I thought you were in the process of moving > from VHDL to Verilog for practical reasons :-) ? I won't say the intent was "for practical reasons". It is more that I want to find out for myself what is good and bad about Verilog and possibly be more compatible with customers. I don't have a need for "purity" and I don't think I said that. HDLs are designed to be implementation independent unless you want to specify an implementation. Integers in VHDL are not intended to specify implementation, while signed and unsigned are. Is being implementation independent the same as being "pure"? Besides, I explained how integers can be treated as bit vectors with two choices. You just need to define your own functions for it. Rick From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.ett.com.ua!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!f8g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 08:13:02 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288969982 18880 127.0.0.1 (5 Nov 2010 15:13:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 15:13:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f8g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4327 On Nov 5, 2:09=A0pm, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 5:20 am, Jan Decaluwe wrote: > > >> I think a language like Python does it right. Integers are true intege= rs, > >> but through the boolean operators you have access to the underlying > >> 2's complement representation if desired. > > > But that is the problem. =A0Who says an integer is implemented as a 2's > > complement binary signal array? > > The Python Language LRM of course. It's not an axioma. Other definitions > and languages are perfectly feasible, although less practical probably. > > >> What I do in MyHDL with the intbv type, is to add an indexing and slic= ing > >> interface to such integers. The result is indeed a "dual mode" type. B= ut > >> for arithmetic, it doesn't have any of the confusion of signed/unsigne= d. > >> I believe this is exactly what hardware designers need in practice. > > > So MyHDL assumes a specific implementation of integers in the > > hardware? > > The intbv type is an integer-like type with a defined bit-vector > representation. Much like Verilog's signed and unsigned regs, with > the big difference that integer arithmetic works as it should. > At the same time, it's more "abstract" than VHDL's integer - no > arbitrary 32 bit limit. > > Intbv's can be used as integers without ever referring to their > bit vector representation. They can also be used as bit vectors > without ever referring to their integer interpretation, for example > to represent integers in different ways in hardware. However, it > is equally possible to mix the 2 interpretations as needed. Let's > be honest, that happens all the time in practical hardware design. > > I have a lot of sympathy for purity, but I find your call to it > a litte surprizing. I thought you were in the process of moving > from VHDL to Verilog for practical reasons :-) ? > > Jan > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0 Python as a HDL:http://www.myhdl.org > =A0 =A0 VHDL development, the modern way:http://www.sigasi.com > =A0 =A0 Analog design automation:http://www.mephisto-da.com > =A0 =A0 World-class digital design:http://www.easics.com Can you explain to me why you should use intbv over signed/unsigned? From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 15:34:39 +0100 Organization: Aioe.org NNTP Server Lines: 121 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4328 Hi everybody ! It's nice to see some activity here :-) To Tricky and Eilert : Yes of course I know numeric_std (signed and unsigned) enough to see what it is good for and to know it does not address my need. Currently I'm not looking at synthesisable code but behavioural description. I want to avoid SystemC and similar oddities, why would I need them when I have GHDL ? :-) And when the behaviour is right, i translate to std_ulogic. rickman wrote: > On Nov 5, 5:20 am, Jan Decaluwe wrote: >> Brian Drummond wrote: >>> Not "any" other language. >>> Mainly C and its followers, which tend to trade a superficial convenience for a >>> thousand subtle ways to screw yourself. CRAY screwed with floating point, but despite the high costs, it sold well. Hint : it was FAST. Yet I know the reluctantly accepted IEEE758, the same way they accepted 2-s complement after the CDC line which was 1s complement. I don't want to screw with arithmetics or standards. I just see that I spend too much time coding and simulating individual bits when the simulator's CPU can do a much simpler and faster work. I'll sort all the initialisation and other usual issues of my models later (during the transition to std_ulogic) but i don't think there will be much to care about because i use to code defensivly and forward-looking. >>> These operations are not "missing" in VHDL's integer types; they were never part >>> of Integer at any time in the history of mathematics, and there is no rational >>> reason for them to be now. I'm not doing mathematics, i'm doing digital electronics and I look at what does the job fastest :-) Don't worry : std_ulogic is not going to be thrown away, or else, how will i synthesise my code ? >>> They basically crept into C's "int" via some late 1960's assembly language, and >>> we have been paying the price in software "quality" ever since. >>> If you need to "AND" two quantities, you can be pretty close to certain that >>> they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, >>> maybe. Control signals, possibly. yes, so what ? data is data. >>> Oh and while I'm still coffee-deprived, adding two positive integers will NEVER >>> EVER result in a negative integer. Integers don't, and can't, overflow. >>> From which we can see that C doesn't actually have ANY integer data types at all >>> - merely a bit-vector type, misleadingly labelled "int", on which they allow >>> instructions that occasionally resemble addition, etc. (Pedantically, modulo-n >>> addition). i agree. On the other side, how many times did you see in VHDL "x / 2**y " that makes a stupid bit shift using a divide (slow) and an exponential ? (super slow) ? >>> Oh, and "unsigned char", as if there was ever such a thing as a signed >>> character. haha :-) >> All true, but I think it is also possible to do it right and that >> the result is very useful, especially for hardware designers. more precisely : designers who know HW and SW well. I often hear the argument : "don't do X because it is potentially dangerous". Fine, I know the dangers and I take appropriate precautions. C integers are a bitch but I know them for a while now so I can code defensively and efficiently. >> I think a language like Python does it right. Integers are true integers, >> but through the boolean operators you have access to the underlying >> 2's complement representation if desired. > > But that is the problem. Who says an integer is implemented as a 2's > complement binary signal array? it's a convenient compromise, it is adopted by ... all the new computer architectures since the 1980's that i know. Now if you prefer 1's complement, it's not my problem :-) >> What I do in MyHDL with the intbv type, is to add an indexing and slicing >> interface to such integers. The result is indeed a "dual mode" type. But >> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >> I believe this is exactly what hardware designers need in practice. > > So MyHDL assumes a specific implementation of integers in the > hardware? > > If the OP wants to treat integers as an array of a binary data type, > then he needs to write the functions to do that. > He will either need > to convert the integers to an array of binary values and perform the > logic operation on those, or he can use looping constructs to isolate > the individual bits of the integer and operate on those. There are 3 ways : - as you wrote : plain slow (use of std_ulogic is faster) - modify the compiler : that's a long-term goal - VHPIDIRECT : what i'll do first :-) it only works with GHDL (maybe Aldec) but it's easy and fast to write and it's a first step to defining the behaviour of the boolean extension before the compiler is modified. > The problem is not that it can't be done, the OP simply doesn't know > how to write a function to do this. Rick, I thought you knew me better :-/ > He is thinking at a very simple > level expecting there to be logic operators on integers for him to > use. He needs to consider how logic operators could be implemented on > integers. give me 48h (well 2h are enough) and i'll show you a few tricks :-) Did I say that I have added a graphic framebuffer interface to GHDL, or I wrote code that reads the computer's environment variables ? OK it's only for GHDL but it works great and once you understand the guts, it's easy :-) Talk to you all soon, > Rick yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.wiretrip.org!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 17:40:50 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> In-Reply-To: <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 12 Message-ID: <4cd43391$0$14248$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 3e96c8a7.news.skynet.be X-Trace: 1288975249 news.skynet.be 14248 91.177.173.208:60651 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4329 Tricky wrote: > Can you explain to me why you should use intbv over signed/unsigned? Because it makes integer arithmetic work like God intended it :-) -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:34 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!tudelft.nl!txtfeed1.tudelft.nl!newsfeed.kpn.net!pfeed08.wxs.nl!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 18:44:54 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> In-Reply-To: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 73 Message-ID: <4cd44295$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: ca4d4994.news.skynet.be X-Trace: 1288979093 news.skynet.be 14247 91.177.173.208:33441 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4330 rickman wrote: > On Nov 5, 10:09 am, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>> I think a language like Python does it right. Integers are true integers, >>>> but through the boolean operators you have access to the underlying >>>> 2's complement representation if desired. >>> But that is the problem. Who says an integer is implemented as a 2's >>> complement binary signal array? >> The Python Language LRM of course. It's not an axioma. Other definitions >> and languages are perfectly feasible, although less practical probably. > > That's great, but not useful for hardware design is it? I don't see what you are referring to here. It can't be Python/MyHDL's actual choice, because that is the same as VHDL/Verilog for signed, and probably any VHDL synthesis tool for integer. >>>> What I do in MyHDL with the intbv type, is to add an indexing and slicing >>>> interface to such integers. The result is indeed a "dual mode" type. But >>>> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >>>> I believe this is exactly what hardware designers need in practice. >>> So MyHDL assumes a specific implementation of integers in the >>> hardware? >> The intbv type is an integer-like type with a defined bit-vector >> representation. Much like Verilog's signed and unsigned regs, with >> the big difference that integer arithmetic works as it should. >> At the same time, it's more "abstract" than VHDL's integer - no >> arbitrary 32 bit limit. >> >> Intbv's can be used as integers without ever referring to their >> bit vector representation. They can also be used as bit vectors >> without ever referring to their integer interpretation, for example >> to represent integers in different ways in hardware. However, it >> is equally possible to mix the 2 interpretations as needed. Let's >> be honest, that happens all the time in practical hardware design. >> >> I have a lot of sympathy for purity, but I find your call to it >> a litte surprizing. I thought you were in the process of moving >> from VHDL to Verilog for practical reasons :-) ? > > I won't say the intent was "for practical reasons". It is more that I > want to find out for myself what is good and bad about Verilog and > possibly be more compatible with customers. I don't have a need for > "purity" and I don't think I said that. Agreed, you complained about the consequences of VHDL's strong typing system. But that's what I intended to refer to also. > HDLs are designed to be > implementation independent unless you want to specify an > implementation. Integers in VHDL are not intended to specify > implementation, while signed and unsigned are. Is being > implementation independent the same as being "pure"? That's what I mean, yes: strong typing and abstract types without an implied representation, such as VHDL's boolean, enum and integer. I'm personally all for it, > Besides, I explained how integers can be treated as bit vectors with > two choices. You just need to define your own functions for it. Note that would have to make choice how to represent integers in those function. I wonder what that choice would be :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t7g2000vbj.googlegroups.com!not-for-mail From: Matt Longbrake Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 5 Nov 2010 11:11:51 -0700 (PDT) Organization: http://groups.google.com Lines: 68 Message-ID: <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 134.131.125.50 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288980712 19956 127.0.0.1 (5 Nov 2010 18:11:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 18:11:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t7g2000vbj.googlegroups.com; posting-host=134.131.125.50; posting-account=MSTlZgoAAAD_zHgCSsJ-fGgs0cHA71At User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11 GTB7.1 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4331 > There are a number of things you can do. =A0You can declare signals > outside the generate block and make an assignment based on generate > index: > > =A0 signal a : std_logic_vector(7 downto 0); > =A0 signal b : std_logic; > > =A0 g_test: for i in 0 to 7 generate > =A0 =A0 if ( i =3D 0 ) then > =A0 =A0 =A0 b <=3D a(i); > =A0 =A0 end if > =A0 end generate : g_test > > The other option you are looking for is possible by declaring signals > within the generate for: > > =A0 g_test: for i in 0 to 7 generate > =A0 =A0 signal x : std_logic_vector(i+2 downto 0); > > =A0 =A0 x(i+2 downto 0) <=3D whatever; > > =A0 end generate : g_test > > In this case, you will have 8 x's defined as: x(2:0), x(3:0), ... > x(9:0). =A0But only accessible within the generate block. > > Cheers, > -- Amal Here's an example of what I meant with option 1 (probably not syntactically correct): type input_array is array(0 to 3) of signed(3 downto 0); signal inputs : input_array; type sum_array is array(0 to 4) of signed(7 downto 0); signal sums : sum_array; signal input : signed(3 downto 0); signal output : signed(7 downto 0); sums(0)(3 downto 0) <=3D inputs(0); output <=3D sums(4); abc: for i in 0 to 3 generate adder: adder2 generic map( width =3D> i+4) port map( A =3D> resize(inputs(i+1), i+4), B =3D> sums(i), S =3D> sums(i+1)(i+4 downto 0)); end generate; I wrote that off the cuff, but the point is that the width of the adder is easily adjusted by the generate statement, but I can't see any way to adjust the size of the signals feeding them. The above solution works, but you get unused signal warnings. > Alternatively, realise that synthesis warnings are merely warnings, not e= rrors, > and can safely be ignored if you understand and expect them. Synthesis to= ols > will do an excellent job of trimming fixed-width adders down to the size > required. I try to reduce the warnings as much as possible so that they actually have some meaning when they happen, maybe I'm being to optimistic. I just know that if I see a list of 1000 warnings, most of which can be ignored, it's hard to find the one that's actually something that needs fixing. From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 19:23:04 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> In-Reply-To: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 74 Message-ID: <4cd44b87$0$14255$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 11bc70aa.news.skynet.be X-Trace: 1288981383 news.skynet.be 14255 91.177.173.208:59175 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4332 rickman wrote: > On Nov 5, 10:09 am, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>> I think a language like Python does it right. Integers are true integers, >>>> but through the boolean operators you have access to the underlying >>>> 2's complement representation if desired. >>> But that is the problem. Who says an integer is implemented as a 2's >>> complement binary signal array? >> The Python Language LRM of course. It's not an axioma. Other definitions >> and languages are perfectly feasible, although less practical probably. > > That's great, but not useful for hardware design is it? I don't see what you are referring to here. It can't be Python/MyHDL's actual choice, because that is the same as VHDL/Verilog for signed, and probably any VHDL synthesis tool for integer. >>>> What I do in MyHDL with the intbv type, is to add an indexing and slicing >>>> interface to such integers. The result is indeed a "dual mode" type. But >>>> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >>>> I believe this is exactly what hardware designers need in practice. >>> So MyHDL assumes a specific implementation of integers in the >>> hardware? >> The intbv type is an integer-like type with a defined bit-vector >> representation. Much like Verilog's signed and unsigned regs, with >> the big difference that integer arithmetic works as it should. >> At the same time, it's more "abstract" than VHDL's integer - no >> arbitrary 32 bit limit. >> >> Intbv's can be used as integers without ever referring to their >> bit vector representation. They can also be used as bit vectors >> without ever referring to their integer interpretation, for example >> to represent integers in different ways in hardware. However, it >> is equally possible to mix the 2 interpretations as needed. Let's >> be honest, that happens all the time in practical hardware design. >> >> I have a lot of sympathy for purity, but I find your call to it >> a litte surprizing. I thought you were in the process of moving >> from VHDL to Verilog for practical reasons :-) ? > > I won't say the intent was "for practical reasons". It is more that I > want to find out for myself what is good and bad about Verilog and > possibly be more compatible with customers. I don't have a need for > "purity" and I don't think I said that. Agreed, you complained about the consequences of VHDL's strong typing system. But that's what I intended to refer to also. > HDLs are designed to be > implementation independent unless you want to specify an > implementation. Integers in VHDL are not intended to specify > implementation, while signed and unsigned are. Is being > implementation independent the same as being "pure"? That's what I mean, yes: strong typing and abstract types without an implied representation, such as VHDL's boolean, enum and integer. I'm personally all for it in general, but not for the case of integer. Sometimes practicality beats purity. > Besides, I explained how integers can be treated as bit vectors with > two choices. You just need to define your own functions for it. Note that you would have to make a choice how to represent integers in those functions. I wonder what that choice would be :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g25g2000yqn.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 14:35:24 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <0331399d-df23-49de-9ead-cf0628d0aabe@g25g2000yqn.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> <1cf54872-86f1-4bea-9ef3-d853e3bc3a8d@b25g2000vbz.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288992924 1554 127.0.0.1 (5 Nov 2010 21:35:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 21:35:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g25g2000yqn.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13104 comp.lang.vhdl:4333 > > Your process isn't fully combinatorial: a process in order to be > combinatorial > has to contain in its sensitivity list ALL the inputs that can affect > the output. > In your case you only have the multiplexer selector in the sensitivity > list, > while the DATA1 and DATA2 are not included. Try to add them and it > will > work. > > Ciao! > maurizio- Hide quoted text - > > - Show quoted text - Maurizio, Data1 and Data2 are constant. I think they don't have to be in the sensitivity list. I have fixed the problem as explained in my post below From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 14:39:38 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <05599483-6a4d-4414-96cb-61f78025ce58@c20g2000yqj.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288993178 3628 127.0.0.1 (5 Nov 2010 21:39:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 21:39:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4334 Many thanks Martin. I had to use Variables and not Signals as you suggested and this fixed my error. should we then generalise that in combinatorial processes, variables should be used instead of signals in the intermediate assignments? From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!diablo2.news.osn.de!news.osn.de!diablo2.news.osn.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 17:42:21 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 05 Nov 2010 22:51:45 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> <05599483-6a4d-4414-96cb-61f78025ce58@c20g2000yqj.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-RJWZj0HkoUd0PpHpOV3TImejNq7fK3BeAOMgryvq4TpBAPr48s//lmdtTSZQcq1EXywfBQXQqU1ZUCc!pt6vbCiuf7s81M4rUzsWwrWHHSgSF55VkAMudBEUQH7YniqGk7jJVleyfyvxzioX4bMM6fN4UXNI!zShN X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1866 Xref: feeder.eternal-september.org comp.lang.vhdl:4335 On Fri, 5 Nov 2010 14:39:38 -0700 (PDT), Angus wrote: >Many thanks Martin. I had to use Variables and not Signals as you >suggested and this fixed my error. should we then generalise that in >combinatorial processes, variables should be used instead of signals >in the intermediate assignments? Not necessarily. You could also have solved the problem by adding "temp" to the sensitivity list, since it appears on the RHS of a statement within the process. - Brian From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Element update within records Date: Fri, 05 Nov 2010 23:58:49 +0100 Organization: T-Online Lines: 30 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1288997930 00 n14699 Db0sChY1LpQVSilV 101105 22:58:50 X-Complaints-To: usenet-abuse@t-online.de X-ID: ZYUAMsZFreE6sjmUSQWqgiteFr0iDutnTwTXq2Dhw1GNkA8gbBFngU User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4336 Hi, I have a problem which I would like to optimize for simulation speed. I have a signal "a", which is a record with many different elements and element types. Now I would like to substitue single elements within this record asynchronously. Currently I do the following: process(a, b, c) is begin out <= a; out.record_element_x <= b; out.record_element_y <= c; end process; "out" is of the same type as "a", so I first copy all record elements and then overwrite the ones I would like to substitute. Like that I don't have to copy each record element individually. The problem is that "b" and "c" might be asynchronously calculated as well, which means the process can be triggered several times per rising clock edge, slowing down the simulation (copying "a" to "out" seems quite time consuming). Is there a better solution for this problem, which prevents me from copying "a" to "out" a couple of times per clock? Of course, the solution should be synthesizable. Thanks, Matthias From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feed.xsnews.nl!border-1.ams.xsnews.nl!193.201.147.77.MISMATCH!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 06 Nov 2010 03:44:12 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 08:53:37 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-GyZQfOhbSDWUIOit9Tv64ysUW+gTC3TNuqHskvBxUfSuZm0YFcjPS3rmAmYK2qArMM0LkcZExNRZuvG!TBdUfl/urd186TSsgDGiLIetRlz2wB0Z0+QmouDyHhRJTVXdNZaNrE99hsp4N8qhV1QxnlFclksT!65Da X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2153 Xref: feeder.eternal-september.org comp.lang.vhdl:4337 On Fri, 05 Nov 2010 23:58:49 +0100, Matthias Alles wrote: >Hi, > >I have a problem which I would like to optimize for simulation speed. I >have a signal "a", which is a record with many different elements and >element types. >out <= a; > >out.record_element_x <= b; >out.record_element_y <= c; >"out" is of the same type as "a", so I first copy all record elements >and then overwrite the ones I would like to substitute. Like that I >don't have to copy each record element individually. The problem is that >"b" and "c" might be asynchronously calculated as well, which means the >process can be triggered several times per rising clock edge, slowing >down the simulation (copying "a" to "out" seems quite time consuming). Write a simple function returning that record type, accepting arguments a,b,c. A sketch: function combine(a: in : b,c : in std_logic) return is variable temp : := a; begin temp.x := b; return temp; end combine; - Brian From newsfish@newsfish Fri Dec 24 22:55:35 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 09:09:13 +0000 Organization: A noiseless patient Spider Lines: 29 Message-ID: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="17207"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DSBoL0Onggf0pvn0P/3lvMoQgxbgNenc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:+qNGvaxWLPZhroTQ9c2kPb5kP6I= Xref: feeder.eternal-september.org comp.lang.vhdl:4338 On Sat, 06 Nov 2010 08:53:37 +0000, Brian Drummond wrote: >function combine(a: in : b,c : in std_logic) return is >variable temp : := a; >begin > temp.x := b; > return temp; >end combine; Right, but I don't think that solves the OP's problem, which was to try to avoid the performance hit of repeated copying of a large record when his process is repeatedly triggered in successive deltas. Indeed, your function potentially causes THREE copy operations: - one to put the actual argument value into the formal "a" - one to copy "a" to "temp" - one to copy "temp" to the return target although any half-decent compiler will collapse those on to only one or two, I imagine. The real solution is to avoid retriggering of the process, which is best done by NOT writing a combinational process with multiple signals in its sensitivity list. Matthias, is there any way you could fold the record processing into your clocked process, so you know it's executed only once per cycle? -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Sat, 06 Nov 2010 09:53:03 +0000 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="25240"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/a4tt5SVq/urMWOfh7RKVoOoK830/oFAg=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:5O0CnepxaPZaFJL15hObb0EvpUI= Xref: feeder.eternal-september.org comp.lang.vhdl:4339 On Fri, 5 Nov 2010 11:11:51 -0700 (PDT), Matt Longbrake wrote: >I try to reduce the warnings as much as possible so that they actually >have some meaning when they happen Sounds good. I am not sure whether you got a clear response about whether you can reference one generate block's signals from within another; the answer is "no" (except by using VHDL-2008 cross-scope references or whatever they're called). The pragmatic solution is definitely to use interconnect vectors of sufficient width. To remove the warnings, consider driving unused bits of those vectors with a common value that preserves the arithmetic meaning (typically zero-pad or sign-extend the MSBs). Synthesis will strip out the common or constant logic. You may get some note-level messages about that too, but that happens all the time and there's not a lot we can do about it. -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!37g2000prx.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 6 Nov 2010 09:52:01 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289062322 27057 127.0.0.1 (6 Nov 2010 16:52:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Nov 2010 16:52:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000prx.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4340 On Nov 5, 6:58=A0pm, Matthias Alles wrote: > > Is there a better solution for this problem, which prevents me from > copying "a" to "out" a couple of times per clock? Of course, the > solution should be synthesizable. > Yes, either use multiple concurrent assignment statements... out.record_element_a <=3D a.a; -- Copy out.record_element_b <=3D a.b; -- Copy out.record_element_x <=3D b; out.record_element_y <=3D c; Or, a single assignment out <=3D ( record_element_a =3D> a.a, -- Copy record_element_b =3D> a.b, -- Copy record_element_x =3D> b; record_element_y =3D> c ); The second method has the advantage that if you add/remove record elements, the assignment to 'out' will fail when you compile it, forcing you to explicitly fix it at that time (that's a good thing). The first method of independent assignments would compile correctly without complaint (which can be nice), but might not represent what you intend to do. The second method is usually better. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Sat, 06 Nov 2010 15:14:44 -0700 Lines: 13 Message-ID: <8jm2a4F28bU1@mid.individual.net> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 4KaCS0+41hs8+IJ/nZczMQtyrs5K/NHt2I/SCu1YZDrKLQjPJb Cancel-Lock: sha1:AGOhvLanRw5Q1vpMwyfg38X+vmo= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4341 On 11/5/2010 3:04 AM, rickman wrote: > That may be true for simulation, but for synthesis the initialization > is often used for the initial value set during configuration. If the > explicit assignment is omitted, will the synthesis tool match the > simulation? I would consider it unsafe to count on value of an internal register between power up configuration and system reset, for any target device. So I guess I see no reason to simulate it. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 06 Nov 2010 18:41:09 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 23:50:35 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 64 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-HRha4TXM531VXJUeX20McCas2V/JpSVY6DoUR+23AYlh9hjyg722fWw5zFsBu/s3DYOEeFvFOD3BBPE!V6biTY9Qci5h0QxXJr3hTIxaIRUuRGZfdp6Sh4klYf2pldXFcp8wEmm3WRYgFr4Z0BIQHjXhXCnK!nv2l X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3972 Xref: feeder.eternal-september.org comp.lang.vhdl:4342 On Sat, 06 Nov 2010 09:09:13 +0000, Jonathan Bromley wrote: >On Sat, 06 Nov 2010 08:53:37 +0000, Brian Drummond wrote: > >>function combine(a: in : b,c : in std_logic) return is >>variable temp : := a; >>begin >> temp.x := b; >> return temp; >>end combine; > >Right, but I don't think that solves the OP's problem, which >was to try to avoid the performance hit of repeated copying >of a large record when his process is repeatedly triggered >in successive deltas. Indeed, your function potentially >causes THREE copy operations: >- one to put the actual argument value into the formal "a" >- one to copy "a" to "temp" >- one to copy "temp" to the return target >although any half-decent compiler will collapse those >on to only one or two, I imagine. Could be. I thought the slowness he found was when copying a to out, i.e. when a potentially tricky resolution took place. This solution should at least reduce the number of assignments to "out" to one. Which - I would guess - would give most of the benefit of whatever the optimum approach is. Confession time; I haven't spent an afternoon benchmarking different approaches with a few million iterations each, so I could be wrong here. --- Is it just me that pays (almost) no attention to simulation efficiency? It seems to me that my thinking time dwarfs sim runtime anyway. And corrupting the design for more "efficient" simulation seems to be a move in the wrong direction - away from efficient use of my time - to me. Am I so far out on a limb? I try to get the heavy lifting done by fairly well focussed test cases rather than by distorting the most natural (to me) - and therefore most likely to be bug-free - design approach in the cause of pandering to simulators. Even when I run a long simulation (e.g. error mapping a 32-bit floating point square root) testing every one of 16 million mantissa values only took an hour or two, with no concession to fast simulation coding. (About 200 of them had error just over 0.5LSB so it wasn't 100% P754 compliant). Of course by that stage I'm not interactively debugging, but if I were, after lunch, I could focus on the specific values that were giving trouble. The only time simulation speed REALLY bugs me is when vendors insist on supplying only a gate-level representation of their core (and sometimes even their testbench - I'm not kidding here!!! *cough* Xilinx PCI express ) - that is too large to run on their basic pay-for simulator! Then I restrict the simulation to a few basic reads and writes, and drop in a higher level interface (approximating the PCIe core's local bus) for the real system-level simulations. - Brian From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Sat, 6 Nov 2010 19:24:29 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.157.42.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289096670 871 127.0.0.1 (7 Nov 2010 02:24:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 7 Nov 2010 02:24:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=68.157.42.151; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13112 comp.lang.vhdl:4343 On Nov 5, 3:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS ---------------------------------------------------------------------------= -------- items to the right of <=3D are typically in the sensitivity list DATA1, DATA2, temp, SEL You may have to play around with the vector notation in the sensitivity list. You forgot temp From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u25g2000pra.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sun, 7 Nov 2010 01:25:03 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <6fcb0328-61a0-4e6b-b484-35ebd0e8b9bf@u25g2000pra.googlegroups.com> References: NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289118304 25824 127.0.0.1 (7 Nov 2010 08:25:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 7 Nov 2010 08:25:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u25g2000pra.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4344 I had a similar situation on a project where I noticed an assignment to a signal record significantly increased sim runtime. My solution was to keep the record as a variable inside a process. It appeared to be the assignment to the signal that caused the simulation slow down. If I was debugging I would assign the variable to a signal to see what was going on. If the record has to be a signal then you can reduce the number of members or size of the members of the record can also help. So you could try splitting the record if some elements get 'touched' more that others. Darrin On Nov 6, 9:58=A0am, Matthias Alles wrote: > Hi, > > I have a problem which I would like to optimize for simulation speed. I > have a signal "a", which is a record with many different elements and > element types. Now I would like to substitue single elements within this > record asynchronously. Currently I do the following: > > process(a, b, c) is > begin > > out <=3D a; > > out.record_element_x <=3D b; > out.record_element_y <=3D c; > > end process; > > "out" is of the same type as "a", so I first copy all record elements > and then overwrite the ones I would like to substitute. Like that I > don't have to copy each record element individually. The problem is that > "b" and "c" might be asynchronously calculated as well, which means the > process can be triggered several times per rising clock edge, slowing > down the simulation (copying "a" to "out" seems quite time consuming). > > Is there a better solution for this problem, which prevents me from > copying "a" to "out" a couple of times per clock? Of course, the > solution should be synthesizable. > > Thanks, > Matthias From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!f16g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Mon, 8 Nov 2010 08:53:43 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289235223 419 127.0.0.1 (8 Nov 2010 16:53:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 16:53:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f16g2000prj.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4345 On Nov 6, 5:14=A0pm, Mike Treseler wrote: > On 11/5/2010 3:04 AM, rickman wrote: > > > That may be true for simulation, but for synthesis the initialization > > is often used for the initial value set during configuration. =A0If the > > explicit assignment is omitted, will the synthesis tool match the > > simulation? > > I would consider it unsafe to count on value of an internal register > between power up configuration and system reset, for any target device. > So I guess I see no reason to simulate it. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler I'm not sure what your point is. Are you saying that you don't make use of the built in global reset function? That value matches the configuration reset value. Of course if you use logic to generate your own system reset you can set it to whatever you want independent of the configuration value. But that is out of context to what Jonathan was saying which is what I was replying to. Rick From newsfish@newsfish Fri Dec 24 22:55:36 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u11g2000prn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 09:57:05 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289239025 2885 127.0.0.1 (8 Nov 2010 17:57:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 17:57:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u11g2000prn.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4346 The VHDL standard has already adopted an assumed two's complement numeric representation for vectors (numeric_std, numeric_std_unsigned, ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement representation for integes as well?! The primary problem with vhdl vector based arithmetic (numeric_*) is that it rolls over (not to signed, but what's the difference, an unsigned rollover is still inaccurate). Take two unsigned, add them together, and you can get a result that is less than either of the operands. The closest vhdl vector arithmetic comes to true integer arithmetic accuracy is the fixed point package types, with zero fractional bits declared. Fixed point operators automatically pad the result size to account for accuracy in all cases, except one: a ufixed minus a ufixed is still a ufixed (but actually bigger by one bit! go figure) rather than an sfixed. With the almost universal need to resize sfixed/ufixed results to fit in an assigned signal/variable, the conversion from sfixed to ufixed could easily be handled in the resize function anyway. Or better yet, allow assignment operators to be overloaded so that they can do the resizing automatically. Hey, I can dream, can't I? Andy From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g28g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 10:53:02 -0800 (PST) Organization: http://groups.google.com Lines: 54 Message-ID: <4ff4f712-4b04-4414-a712-b277acb6cc31@g28g2000pra.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 98.232.140.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289242382 32083 127.0.0.1 (8 Nov 2010 18:53:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 18:53:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g28g2000pra.googlegroups.com; posting-host=98.232.140.93; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4347 > The VHDL standard has already adopted an assumed two's complement > numeric representation for vectors (numeric_std, numeric_std_unsigned, > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > representation for integes as well?! It certainly would be worth while to entertain enhancements to integers in the next revision of VHDL - I have heard others issues in addition to this one. See my separate post about study group formation. The first baby step toward the next standard - but it is important to attend and voice an opinion on the issues mentioned. > The closest vhdl vector arithmetic comes to true integer arithmetic > accuracy is the fixed point package types, with zero fractional bits > declared. Fixed point operators automatically pad the result size to > account for accuracy in all cases, except one: a ufixed minus a ufixed > is still a ufixed (but actually bigger by one bit! go figure) rather > than an sfixed. With the almost universal need to resize sfixed/ufixed > results to fit in an assigned signal/variable, the conversion from > sfixed to ufixed could easily be handled in the resize function > anyway. I think both have issues. For example: signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto 0) ; signal Y_ufixed11 : ufixed(10 downto 0) ; Y_ufixed11 <= A_ufixed8 + B_ufixed8 + C_ufixed8 + D_ufixed8 ; results in a different size than: signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto 0) ; signal Y_ufixed10 : ufixed(9 downto 0) ; Y_ufixed10 <= (A_ufixed8 + B_ufixed8) + (C_ufixed8 + D_ufixed8) ; > Or better yet, allow assignment operators to be overloaded so that > they can do the resizing automatically. It would be an interesting proposal. If it gets approved, are you interested in writing it? Can you formulate something that chooses between modulo math (like unsigned/signed) or full precision arith (like ufixed/sfixed)? If you blow the doors open and allow anything, I would think that is bad. If you add more saftey such as enforcement of ranges for ufixed/sfixed (so that more than size is enforced) then it would be exciting. Best, Jim From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m20g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: VHDL Study Group Meeting Notice Date: Mon, 8 Nov 2010 10:57:08 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: <8d1b4c0e-204e-43de-8adc-d3ad5cf058e8@m20g2000prc.googlegroups.com> NNTP-Posting-Host: 98.232.140.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289242629 1601 127.0.0.1 (8 Nov 2010 18:57:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 18:57:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000prc.googlegroups.com; posting-host=98.232.140.93; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4348 Hi, In preparation for the next revision of VHDL, the DASC (parent of the 1076 - VHDL) has given us permission to form a study group with the purpose of writing the PAR (project authorization request). Meeting is scheduled for Wednesday Dec 1 at 8 am Pacific. Dial in details will be announced later. Please enroll in the VASG email reflector at (see bottom of page under participation) http://www.eda.org/vasg/ This meeting is open to all who have a vested interest in VHDL. Please participate. While I expect most of the PAR to be easy for all, we do have one item that will come up. One item that will come up is whether to organize the VHDL working group as an individual (as it has been) or corporate based working group. Anyone with a vested interest in VHDL can participate (attend meetings, be on the working group email reflector, and attain voting rights) in an individual based working group. In a corporate based working group, to be an observer (attend meetings or be on the reflector) will cost a company between $1250 and $5500 (depending on corporate revenue). To be a voting member, one must be an advanced corporate member at a cost of $3500 to $10000. Unfortunately none of this money goes to the working group, instead it goes to fund IEEE Standards Association (which is a separate organization from IEEE). Any funding needed by the working group will be a separate assessment. Please attend and weigh in on this issue as this will effect the working group. Best Regards, Jim Lewis P.S. If you think you are already on the VHDL-200X reflector, and did not get this already, your email is bouncing (Mike T). -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 16:13:02 -0800 (PST) Organization: http://groups.google.com Lines: 80 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289261582 13944 127.0.0.1 (9 Nov 2010 00:13:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Nov 2010 00:13:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4349 On Nov 5, 1:23=A0pm, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 10:09 am, Jan Decaluwe wrote: > >> rickman wrote: > >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: > >>>> I think a language like Python does it right. Integers are true inte= gers, > >>>> but through the boolean operators you have access to the underlying > >>>> 2's complement representation if desired. > >>> But that is the problem. =A0Who says an integer is implemented as a 2= 's > >>> complement binary signal array? > >> The Python Language LRM of course. It's not an axioma. Other definitio= ns > >> and languages are perfectly feasible, although less practical probably= . > > > That's great, but not useful for hardware design is it? > > I don't see what you are referring to here. It can't be Python/MyHDL's > actual choice, because that is the same as VHDL/Verilog for signed, and > probably any VHDL synthesis tool for integer. I think I have no idea what you are saying with this. What Python does with integers has no bearing on what VHDL does. So what is your point about mentioning Python? > >> I have a lot of sympathy for purity, but I find your call to it > >> a litte surprizing. I thought you were in the process of moving > >> from VHDL to Verilog for practical reasons :-) ? > > > I won't say the intent was "for practical reasons". =A0It is more that = I > > want to find out for myself what is good and bad about Verilog and > > possibly be more compatible with customers. =A0I don't have a need for > > "purity" and I don't think I said that. > > Agreed, you complained about the consequences of VHDL's strong > typing system. But that's what I intended to refer to also. Again, I have no idea why you are bringing this up. How does it pertain to the discussion? > > HDLs are designed to be > > implementation independent unless you want to specify an > > implementation. =A0Integers in VHDL are not intended to specify > > implementation, while signed and unsigned are. =A0Is being > > implementation independent the same as being "pure"? > > That's what I mean, yes: strong typing and abstract types without > an implied representation, such as VHDL's boolean, enum and > integer. I'm personally all for it in general, but not for the > case of integer. Sometimes practicality beats purity. Ok, you have stated your preference, but you have not given any basis for it. In general a given type does not have an representation implied so that it can be implemented in the manner that suits the application the best. Although 2's complement is pretty universal, it is not the only way to use integers. Do you think it is worth eliminating the use of integers for any other representation by specifying one representation in the standard? I guess I know the answer to that one. But you can see where this is a problem for some usage that others may want, no? Besides, the OP can do what he wants and perform bit wise operations on integers. He just has to write a few functions to do that. > > Besides, I explained how integers can be treated as bit vectors with > > two choices. =A0You just need to define your own functions for it. > > Note that you would have to make a choice how to represent integers > in those functions. I wonder what that choice would be :-) That is up to the author to suit their application. I can see where they would choose to use 2's complement or unsigned possibly. It depends on how they intend to use it in the application. Rick From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!194.134.4.91.MISMATCH!news2.euro.net!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 09 Nov 2010 10:06:48 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 85 Message-ID: <4cd90f28$0$14261$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: ee99856e.news.skynet.be X-Trace: 1289293608 news.skynet.be 14261 91.177.109.178:44493 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4350 rickman wrote: > On Nov 5, 1:23 pm, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 10:09 am, Jan Decaluwe wrote: >>>> rickman wrote: >>>>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>>>> I think a language like Python does it right. Integers are true integers, >>>>>> but through the boolean operators you have access to the underlying >>>>>> 2's complement representation if desired. >>>>> But that is the problem. Who says an integer is implemented as a 2's >>>>> complement binary signal array? >>>> The Python Language LRM of course. It's not an axioma. Other definitions >>>> and languages are perfectly feasible, although less practical probably. >>> That's great, but not useful for hardware design is it? >> I don't see what you are referring to here. It can't be Python/MyHDL's >> actual choice, because that is the same as VHDL/Verilog for signed, and >> probably any VHDL synthesis tool for integer. > > I think I have no idea what you are saying with this. What Python > does with integers has no bearing on what VHDL does. So what is your > point about mentioning Python? I try to convince people to take a good look at Python/MyHDL integers and possibly consider to do it similarly in a future VHDL standard. >>>> I have a lot of sympathy for purity, but I find your call to it >>>> a litte surprizing. I thought you were in the process of moving >>>> from VHDL to Verilog for practical reasons :-) ? >>> I won't say the intent was "for practical reasons". It is more that I >>> want to find out for myself what is good and bad about Verilog and >>> possibly be more compatible with customers. I don't have a need for >>> "purity" and I don't think I said that. >> Agreed, you complained about the consequences of VHDL's strong >> typing system. But that's what I intended to refer to also. > > Again, I have no idea why you are bringing this up. How does it > pertain to the discussion? The ideas I'm proposing would solve many of the VHDL usability issues that we are all struggling with, including the OP and you as I understood it, when you announced that you'd rather switch (to Verilog) than fight (with VHDL). >>> HDLs are designed to be >>> implementation independent unless you want to specify an >>> implementation. Integers in VHDL are not intended to specify >>> implementation, while signed and unsigned are. Is being >>> implementation independent the same as being "pure"? >> That's what I mean, yes: strong typing and abstract types without >> an implied representation, such as VHDL's boolean, enum and >> integer. I'm personally all for it in general, but not for the >> case of integer. Sometimes practicality beats purity. > > Ok, you have stated your preference, but you have not given any basis > for it. In general a given type does not have an representation > implied so that it can be implemented in the manner that suits the > application the best. Although 2's complement is pretty universal, it > is not the only way to use integers. Do you think it is worth > eliminating the use of integers for any other representation by > specifying one representation in the standard? I guess I know the > answer to that one. But you can see where this is a problem for some > usage that others may want, no? No, I don't think there is a problem. Imagine an integer type with an "accessible" 2's complement representation. A synthesis tool only has to honour that when the representation is actually "accessed" in the code, something which is easy for a tool to detect. Otherwise, it could implement it with any optimized representation it chooses. The latter case is equivalent to the current situation, with an "inaccessible" representation. In other words, this would be a backwards compatible enhancement. If you need full control over representation, you'd have to do it like today: use bit vectors with dedicated logic, and interprete the bit vector values as numbers yourself. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!news.weisnix.org!newsfeed.ision.net!newsfeed2.easynews.net!ision!newsfeed3.dallas1.level3.net!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!w38g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Tue, 9 Nov 2010 05:53:02 -0800 (PST) Organization: http://groups.google.com Lines: 85 Message-ID: <7d5fc000-c5de-4d28-8958-997e371ef953@w38g2000pri.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> <4cd90f28$0$14261$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289310783 8851 127.0.0.1 (9 Nov 2010 13:53:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Nov 2010 13:53:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w38g2000pri.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4351 On Nov 9, 4:06=A0am, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 1:23 pm, Jan Decaluwe wrote: > >> I don't see what you are referring to here. It can't be Python/MyHDL's > >> actual choice, because that is the same as VHDL/Verilog for signed, an= d > >> probably any VHDL synthesis tool for integer. > > > I think I have no idea what you are saying with this. =A0What Python > > does with integers has no bearing on what VHDL does. =A0So what is your > > point about mentioning Python? > > I try to convince people to take a good look at Python/MyHDL integers > and possibly consider to do it similarly in a future VHDL standard. > > >> Agreed, you complained about the consequences of VHDL's strong > >> typing system. But that's what I intended to refer to also. > > > Again, I have no idea why you are bringing this up. =A0How does it > > pertain to the discussion? > > The ideas I'm proposing would solve many of the VHDL usability > issues that we are all struggling with, including the OP and > you as I understood it, when you announced that you'd rather > switch (to Verilog) than fight (with VHDL). I don't see where it would solve the problems I have seen unless it allows the use of integers to replace all data types... I tried using Boolean for some control signals as this simplifies expressions in conditionals. But in simulation Boolean signals are displayed as a value like an integer which is a PITA. A std_logic signal is displayed as a line with two levels and is very easy to see rather than having to read a value which can be off the display. > >> That's what I mean, yes: strong typing and abstract types without > >> an implied representation, such as VHDL's boolean, enum and > >> integer. I'm personally all for it in general, but not for the > >> case of integer. Sometimes practicality beats purity. > > > Ok, you have stated your preference, but you have not given any basis ccc> > for it. =A0In general a given type does not have an representation > > implied so that it can be implemented in the manner that suits the > > application the best. =A0Although 2's complement is pretty universal, i= t > > is not the only way to use integers. =A0Do you think it is worth > > eliminating the use of integers for any other representation by > > specifying one representation in the standard? =A0I guess I know the > > answer to that one. =A0But you can see where this is a problem for some > > usage that others may want, no? > > No, I don't think there is a problem. > > Imagine an integer type with an "accessible" 2's complement representatio= n. > A synthesis tool only has to honour that when the representation is > actually "accessed" in the code, something which is easy for a tool to > detect. Otherwise, it could implement it with any optimized representatio= n it > chooses. The latter case is equivalent to the current situation, with an > "inaccessible" representation. In other words, this would be a backwards > compatible enhancement. > > If you need full control over representation, you'd have to do it like > today: use bit vectors with dedicated logic, and interprete the bit > vector values as numbers yourself. I don't need control over the representation of integers. But my tool vendor may need that. The synthesis tool is designed for the target. If it works better to represent integers as signed magnitude then the synthesis tool can do that without my involvement or knowledge. How would you allow a synthesis tool to optimize for a given target implementation if the representation is fixed? By requiring the tool to work one way when the bit representation is accessed and a different way when it is not sounds like a complexity that could cause problems for users. Maybe that is not really important. I know it is an issue in the software world, but in FPGAs and ASICs I can't think of an example where the number representation is anything other than 2's complement. But I don't see it helping with any problems unless you can replace all data types with integers. Rick From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Tue, 09 Nov 2010 10:13:38 -0800 Lines: 17 Message-ID: <8jthagFdreU1@mid.individual.net> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net ya2DfFT/CpwnP/YGPxqaKA2XG5bezqBdSM2/rtdvr35C7Ux9Is Cancel-Lock: sha1:LpytZb9Uc3nTqoPSTTLNf9PNbFA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4352 On 11/8/2010 8:53 AM, rickman wrote: > I'm not sure what your point is. Are you saying that you don't make > use of the built in global reset function? I use Altera parts, and the internal "reset" logic is fixed. Pins go to Z and flops go to 0. > Of course if you use logic to generate > your own system reset you can set it to whatever you want independent > of the configuration value. This is what I have have always done. Otherwise, the only way to force a "reset" is to reload the configuration. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:08:57 +0100 Organization: T-Online Lines: 27 Message-ID: References: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289336938 00 n18220 D0GECmhvJ4fFRyx 101109 21:08:58 X-Complaints-To: usenet-abuse@t-online.de X-ID: GhujB-ZbYezPVbZIl2cOOkRLM+7VRLuvy8VMaamEmE9lHsj1BIAxk5 User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4353 I tried both approaches, and both result in a significant simulation speed-up. > out.record_element_a <= a.a; -- Copy > out.record_element_b <= a.b; -- Copy > out.record_element_x <= b; > out.record_element_y <= c; > > Or, a single assignment > out <= > ( > record_element_a => a.a, -- Copy > record_element_b => a.b, -- Copy > record_element_x => b; > record_element_y => c > ); The first approach is slower than the second one. With some other improvements I gained 15% speed-up with multiple concurrent assignments and 30% speed-up with a single assignment. So I'm using a single assignment now. The code is still readable, but the problem remains that the copied signals are written in every delta-cycle in which the signals b or c change. Thus, I also tried to make sure that b and c are calculated at the same delta. Thanks, Matthias From newsfish@newsfish Fri Dec 24 22:55:37 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:13:40 +0100 Organization: T-Online Lines: 14 Message-ID: References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289337220 00 n18220 08GECmhvv4m7png 101109 21:13:40 X-Complaints-To: usenet-abuse@t-online.de X-ID: VsVUt8Za8eGEPTjM2tLx0b6tm-YejmgGWphamqqDidTMvloI3X1Ak4 User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4354 > The real solution is to avoid retriggering of the process, > which is best done by NOT writing a combinational process > with multiple signals in its sensitivity list. > > Matthias, is there any way you could fold the record > processing into your clocked process, so you know it's > executed only once per cycle? Unfortunately not, but I reduced the number of deltas in which the process (or now concurrent assignment, see other post) is triggered. Matthias From newsfish@newsfish Fri Dec 24 22:55:38 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:27:42 +0100 Organization: T-Online Lines: 42 Message-ID: References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289338067 03 n11093 bGXECfQ64zJoEA4 101109 21:27:47 X-Complaints-To: usenet-abuse@t-online.de X-ID: XpaCy+ZTreljwCoNdkqYVAafRsd9CCB5fx3uhzq4z4KZpvYQhDLV8I User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4355 > Is it just me that pays (almost) no attention to simulation efficiency? > It seems to me that my thinking time dwarfs sim runtime anyway. > And corrupting the design for more "efficient" simulation seems to be a move in > the wrong direction - away from efficient use of my time - to me. Am I so far > out on a limb? Usually I don't care that much either. But think of regression tests that you might want to perform after fixing a bug. Those can be quite time consuming, since you usually perform them for every single change you make on a design. In this particular case, spending one hour in profiling the VHDL code can easily save me many many hours of simulation time later on. Matthias > I try to get the heavy lifting done by fairly well focussed test cases rather > than by distorting the most natural (to me) - and therefore most likely to be > bug-free - design approach in the cause of pandering to simulators. > > Even when I run a long simulation (e.g. error mapping a 32-bit floating point > square root) testing every one of 16 million mantissa values only took an hour > or two, with no concession to fast simulation coding. (About 200 of them had > error just over 0.5LSB so it wasn't 100% P754 compliant). > > Of course by that stage I'm not interactively debugging, but if I were, after > lunch, I could focus on the specific values that were giving trouble. > > The only time simulation speed REALLY bugs me is when vendors insist on > supplying only a gate-level representation of their core (and sometimes even > their testbench - I'm not kidding here!!! *cough* Xilinx PCI express ) - that > is too large to run on their basic pay-for simulator! > > Then I restrict the simulation to a few basic reads and writes, and drop in a > higher level interface (approximating the PCIe core's local bus) for the real > system-level simulations. > > - Brian > From newsfish@newsfish Fri Dec 24 22:55:38 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o29g2000vbi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Wed, 10 Nov 2010 04:49:52 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> <8jthagFdreU1@mid.individual.net> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289393392 13917 127.0.0.1 (10 Nov 2010 12:49:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 12:49:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o29g2000vbi.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4358 On Nov 9, 1:13=A0pm, Mike Treseler wrote: > On 11/8/2010 8:53 AM, rickman wrote: > > > I'm not sure what your point is. =A0Are you saying that you don't make > > use of the built in global reset function? > > I use Altera parts, and the internal "reset" logic is fixed. > Pins go to Z and flops go to 0. I thought they had dropped that long ago. I have used some pretty old Altera parts and what they do to provide a preset condition is to reset the FF and treat the signal as a low true. Otherwise there are things you couldn't do properly. > > Of course if you use logic to generate > > your own system reset you can set it to whatever you want independent > > of the configuration value. > > This is what I have have always done. > Otherwise, the only way to force a "reset" > is to reload the configuration. I am pretty sure Altera parts have the exact same functionality of a system reset that the Xilinx and Lattice parts do, but it has been years since I have used their tools. One of us needs to check the docs... I'll do that when I get some time. Rick From newsfish@newsfish Fri Dec 24 22:55:38 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Damian Drewulski Newsgroups: comp.lang.vhdl Subject: matrix generation Date: Wed, 10 Nov 2010 06:57:45 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: <173668ec-83ec-4c17-8e96-fb856140c058@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 94.75.66.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289401066 15139 127.0.0.1 (10 Nov 2010 14:57:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 14:57:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=94.75.66.49; posting-account=a2FzzAoAAAAo1ltX21u5iIbdaYjK0AHF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; pl; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4359 Hi there, i have some problem. I need to get sorting net. 40 comparators in 81 line. First i declared matrix: type wire is array (0 to 81) of std_logic_vector (7 downto 0); type connections is array (0 to 81) of wire; Then i'm trying to generate a net of comparators. component comparator port( clk : in std_logic; rst : in std_logic; A_in : in std_logic_vector (7 downto 0); B_in : in std_logic_vector (7 downto 0); A_out : out std_logic_vector (7 downto 0); B_out : out std_logic_vector (7 downto 0) ); end component; sorting_net : for i in 0 to 40 generate ins: for j in (0 to 81) generate comparatorx : comparator port map(clk, rst, connections(i*2) of wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j +1), connections(i*2 + 1) of wire (j+1)); end generate; end generate; And after that i get few errors. I use quartus. Anyone could help me? best wishes, Damian From newsfish@newsfish Fri Dec 24 22:55:38 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!s5g2000yqm.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: XST - configuration - VHDL Date: Wed, 10 Nov 2010 08:53:16 -0800 (PST) Organization: http://groups.google.com Lines: 47 Message-ID: NNTP-Posting-Host: 194.25.252.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289407996 18106 127.0.0.1 (10 Nov 2010 16:53:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 16:53:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s5g2000yqm.googlegroups.com; posting-host=194.25.252.189; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-Via: 1.1 S04921 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13142 comp.lang.vhdl:4360 Dear all, In my current project I have an entity for which I which arhitecture to use on a VHDL file where I instantiate the entity, like following configuration code: -- Embedded configuration -- Select control architecture to use for all : Ctrl2D use entity work.Ctrl2D(rtl_small); Within the VHDL file where Ctrl2D is defined, I have different configurations, namely rtl_tiny and rtl_small. Within each of those, are processes which have variables whose length depend on some constants (KA, KB), like: process_out : process (in_a, in_b) variable var : std_logic_vector (KA-KB-1 downto 0) := (others => '0'); begin I should select which architecture to use in the configuration (rtl_tiny or rtl_small) depending on a given a given set of values KA and KB. For a set of values KA and KB that works fine with rtl_small and having rtl_small selected in the configuration, XST, when parsing, gives me warnign and error messages: Entity compiled. WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null range: -33 downto 0 ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of concat operation is different than size of the target. Entity (Architecture ) compiled. But those lines (157 and 214) are within the architecture rtl_tiny, not rtl_small. I was confident that by selecting the right architecture in the configuration I was completely bypassing everything related to non- desired architectures, but it seems like I was wrong. How can I direct XST to ignore the code of the non-interesting architectures, and parse and synthesize only the one that I selected in the configuration? Thanks a lot in advance, JaaC From newsfish@newsfish Fri Dec 24 22:55:38 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!j2g2000yqf.googlegroups.com!not-for-mail From: "Dr. Giovanni Squillero" Newsgroups: alt.cad,comp.lang.vhdl,comp.cad.synthesis,comp.arch Subject: GECCO 2011: Call for Papers on Artificial Life, Robotics, Evolvable Hardware Track Date: Wed, 10 Nov 2010 09:42:35 -0800 (PST) Organization: http://groups.google.com Lines: 43 Message-ID: NNTP-Posting-Host: 130.192.5.144 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289410955 12902 127.0.0.1 (10 Nov 2010 17:42:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 17:42:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j2g2000yqf.googlegroups.com; posting-host=130.192.5.144; posting-account=wDgnTQkAAAAxWbsVNyuWtiZ5iM59iBkz User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.28 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org alt.cad:1781 comp.lang.vhdl:4361 comp.cad.synthesis:35 comp.arch:13053 Call for Papers Artificial Life, Robotics, Evolvable Hardware Track @ GECCO 2011 Genetic and Evolutionary Computation Conference July 12-16, Dublin, Ireland http://www.sigevo.org/gecco-2011/ This track promotes evolutionary computation and bio-inspired heuristics as instruments able to face engineering problems and scientific questions in different areas that include (but are not limited to): artificial life, robotics, and evolvable hardware. Artificial life studies artificial systems (software, hardware, or chemical) with properties similar to those of living systems. There are two main complementary goals: to better understand living systems and to use this understanding to build artificial systems with properties of living systems, such as adaptability, evolvability, active perception, communication, organization. Evolutionary computation techniques can be particularly useful for a large branch of robotics. The evolution of controllers, morphologies, sensors, and communication protocols is being used to build systems to provide robust, adaptive and scalable solutions to different problems in robotics. Finally, the term =93evolvable hardware=94 has been used in the past to denote both the design of electronic devices able to evolve themselves, and the generic exploitation of evolutionary techniques for creating hardware. While the first task sounds ambitious, the second is routinely applied by industries. The track will show both real and potential applications. Important Dates: * Submission deadline: January 26, 2011 * Notification of paper acceptance: March 23, 2011 * Camera-ready submission: April 8, 2011 * GECCO-2010 Conference: July 12-16, 2011 Submission guidelines: http://www.sigevo.org/gecco-2011/papers.html Track chairs: Carlos Gershenson http://turing.iimas.unam.mx/~cgg/ Giovanni Squillero http://www.cad.polito.it/~squillero/ From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!k30g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Wed, 10 Nov 2010 09:50:05 -0800 (PST) Organization: http://groups.google.com Lines: 84 Message-ID: <93aa53bb-5df3-4ae4-92d9-00d0c09e7a71@k30g2000vbn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <4ff4f712-4b04-4414-a712-b277acb6cc31@g28g2000pra.googlegroups.com> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289411405 17208 127.0.0.1 (10 Nov 2010 17:50:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 17:50:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k30g2000vbn.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4362 On Nov 8, 12:53=A0pm, JimLewis wrote: > > The closest vhdl vector arithmetic comes to true integer arithmetic > > accuracy is the fixed point package types, with zero fractional bits > > declared. Fixed point operators automatically pad the result size to > > account for accuracy in all cases, except one: a ufixed minus a ufixed > > is still a ufixed (but actually bigger by one bit! go figure) rather > > than an sfixed. With the almost universal need to resize sfixed/ufixed > > results to fit in an assigned signal/variable, the conversion from > > sfixed to ufixed could easily be handled in the resize function > > anyway. > > I think both have issues. =A0For example: > signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto > 0) ; > signal Y_ufixed11 : ufixed(10 downto 0) ; > Y_ufixed11 <=3D A_ufixed8 + B_ufixed8 + C_ufixed8 + D_ufixed8 ; > > results in a different size than: > signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto > 0) ; > signal Y_ufixed10 : ufixed(9 downto 0) ; > Y_ufixed10 <=3D (A_ufixed8 + B_ufixed8) + (C_ufixed8 + D_ufixed8) ; If you used y_ufixed10 <=3D resize(expr, y_ufixed10); it wouldn't make any difference, no matter which form of the expression you used. I find it very seldom that you do not have to use a resize function prior to an assignment with the fixed point packages, which is why overloading the assignment operator to include the resize functionality makes a lot of sense. Again, this would work very similarly to the way integer expressions and assignments work, but without the limitations of size in integer. > > > Or better yet, allow assignment operators to be overloaded so that > > they can do the resizing automatically. > > It would be an interesting proposal. If it gets approved, are you > interested in writing it? =A0 I don't have any compiler writing experience, so defining the syntax to use for overloading an assignment operator, and limiting its use to cases that are reasonable to implement would be beyond me. But I am certainly willing to help where I can (defining what we want to be able to do). > Can you formulate something that > chooses between modulo math (like unsigned/signed) or full precision > arith > (like ufixed/sfixed)? =A0If you blow the doors open and allow anything, > I > would think that is bad. =A0If you add more saftey such as =A0enforcement > of > ranges for ufixed/sfixed (so that more than size is enforced) then it > would > be exciting. Allowing blanket overloading of assignment operators would necessarily "blow the doors off". Perhaps restricting overloaded assignment operators to be defined in the same declarative region as the type to which they assign would help, especially in the case of the standard packages (users could not re-overload the assignment operators outside the package). An overloaded assignment operator for vectors, unlike a standard operator, would have to be able to know what the target range is, which is not currently possible for a function in vhdl. So it would have to be handled more like a procedure with an in and out argument, unless we developed some whole new syntax. It would not be the assignment operator which would define modulo (roll-over) math vs full-precision. That is controlled by the type, and those operators that are defined for the type. The assignment operator could define behavior like truncate, saturate, round, etc. when assigning a larger vector into a smaller one. On the other hand, we would not need overloaded assignment operators (and all of their potential pitfalls blowing doors off) if we had an arbitrarily sized type of integer, including fixed point capability and bit-wise logical operations defined. Then there would be no overloaded assignment operators and all their potential pitfalls to deal with. Andy From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!fh19g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:16:18 -0800 (PST) Organization: http://groups.google.com Lines: 66 Message-ID: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289412978 22458 127.0.0.1 (10 Nov 2010 18:16:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:16:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fh19g2000vbb.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13144 comp.lang.vhdl:4363 On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona wrote: > Dear all, > > In my current project I have an entity for which I which arhitecture > to use on a VHDL file where I instantiate the entity, like following > configuration code: > > -- Embedded configuration > -- Select control architecture to use > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > Within the VHDL file where Ctrl2D is defined, I have different > configurations, namely rtl_tiny and rtl_small. Within each of those, > are processes which have variables whose length depend on some > constants (KA, KB), like: > > process_out : process (in_a, in_b) > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (other= s =3D> > '0'); > =A0 begin > > I should select which architecture to use in the configuration > (rtl_tiny or rtl_small) depending on a given a given set of values KA > and KB. For a set of values KA and KB that works fine with rtl_small > and having rtl_small selected in the configuration, XST, when parsing, > gives me warnign and error messages: > > Entity compiled. > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > range: -33 downto 0 > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > concat operation is different than size of the target. > Entity (Architecture ) compiled. > > But those lines (157 and 214) are within the architecture rtl_tiny, > not rtl_small. > > I was confident that by selecting the right architecture in the > configuration I was completely bypassing everything related to non- > desired architectures, but it seems like I was wrong. > > How can I direct XST to ignore the code of the non-interesting > architectures, and parse and synthesize only the one that I selected > in the configuration? > > Thanks a lot in advance, > > JaaC Unlike simulation tools, synthesis tools combine the analysis and elaboration phases into one. This is probably leading to your problem. Leaving something out in a configuration is not quite like conditionally compiling it. Everything gets analyzed (if it is in a file that is being analyzed), whether it is chosen at elaboration or not. Some simulators have options for compiling (analyzing) only certain types of units (packages, package bodies, entities, architectures, etc.) and ignoring others in the same file. I have not seen that in a synthesis tool. Other than fixing the problem with the mismatched size (if even possible), I would suggest moving the two architectures into separate files, and only including the appropriate file in the project. Andy From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!tramontana.escomposlinux.org!cagarruta.escomposlinux.org!escomposlinux.org!news.antakira.com!weretis.net!feeder4.news.weretis.net!news.musoftware.de!wum.musoftware.de!news.weisnix.org!newsfeed.ision.net!newsfeed2.easynews.net!ision!newsfeed3.dallas1.level3.net!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:50:34 -0800 (PST) Organization: http://groups.google.com Lines: 91 Message-ID: References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> NNTP-Posting-Host: 62.143.30.164 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415035 7638 127.0.0.1 (10 Nov 2010 18:50:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:50:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=62.143.30.164; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13145 comp.lang.vhdl:4364 On 10 Nov., 19:16, Andy wrote: > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > wrote: > > Dear all, > > > In my current project I have an entity for which I which arhitecture > > to use on a VHDL file where I instantiate the entity, like following > > configuration code: > > > -- Embedded configuration > > -- Select control architecture to use > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > Within the VHDL file where Ctrl2D is defined, I have different > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > are processes which have variables whose length depend on some > > constants (KA, KB), like: > > > process_out : process (in_a, in_b) > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (oth= ers =3D> > > '0'); > > =A0 begin > > > I should select which architecture to use in the configuration > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > and KB. For a set of values KA and KB that works fine with rtl_small > > and having rtl_small selected in the configuration, XST, when parsing, > > gives me warnign and error messages: > > > Entity compiled. > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > range: -33 downto 0 > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > concat operation is different than size of the target. > > Entity (Architecture ) compiled. > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > not rtl_small. > > > I was confident that by selecting the right architecture in the > > configuration I was completely bypassing everything related to non- > > desired architectures, but it seems like I was wrong. > > > How can I direct XST to ignore the code of the non-interesting > > architectures, and parse and synthesize only the one that I selected > > in the configuration? > > > Thanks a lot in advance, > > > JaaC > > Unlike simulation tools, synthesis tools combine the analysis and > elaboration phases into one. This is probably leading to your problem. > Leaving something out in a configuration is not quite like > conditionally compiling it. Everything gets analyzed (if it is in a > file that is being analyzed), whether it is chosen at elaboration or > not. Some simulators have options for compiling (analyzing) only > certain types of units (packages, package bodies, entities, > architectures, etc.) and ignoring others in the same file. I have not > seen that in a synthesis tool. > > Other than fixing the problem with the mismatched size (if even > possible), I would suggest moving the two architectures into separate > files, and only including the appropriate file in the project. > > Andy Hi Andy, Thanks for your reply, I found the solution however: adding pragmas: architecture struct of Stack2D is signal dat_2ext : buf2dwrd; signal rd_2ext : std_logic; signal dat_2slv : buf2dwrd; signal wr_2slv : std_logic; -- pragma synthesis on for all : Ctrl2D use entity work.Ctrl2D(rtl_small); -- pragma synthesis off begin The commented pragmas did the job. Regards. From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:54:55 -0800 (PST) Organization: http://groups.google.com Lines: 109 Message-ID: <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> NNTP-Posting-Host: 62.143.30.164 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415295 9942 127.0.0.1 (10 Nov 2010 18:54:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:54:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=62.143.30.164; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13146 comp.lang.vhdl:4365 On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona wrote: > On 10 Nov., 19:16, Andy wrote: > > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > wrote: > > > Dear all, > > > > In my current project I have an entity for which I which arhitecture > > > to use on a VHDL file where I instantiate the entity, like following > > > configuration code: > > > > -- Embedded configuration > > > -- Select control architecture to use > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > > are processes which have variables whose length depend on some > > > constants (KA, KB), like: > > > > process_out : process (in_a, in_b) > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (o= thers =3D> > > > '0'); > > > =A0 begin > > > > I should select which architecture to use in the configuration > > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > > and KB. For a set of values KA and KB that works fine with rtl_small > > > and having rtl_small selected in the configuration, XST, when parsing= , > > > gives me warnign and error messages: > > > > Entity compiled. > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > range: -33 downto 0 > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > concat operation is different than size of the target. > > > Entity (Architecture ) compiled. > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > not rtl_small. > > > > I was confident that by selecting the right architecture in the > > > configuration I was completely bypassing everything related to non- > > > desired architectures, but it seems like I was wrong. > > > > How can I direct XST to ignore the code of the non-interesting > > > architectures, and parse and synthesize only the one that I selected > > > in the configuration? > > > > Thanks a lot in advance, > > > > JaaC > > > Unlike simulation tools, synthesis tools combine the analysis and > > elaboration phases into one. This is probably leading to your problem. > > Leaving something out in a configuration is not quite like > > conditionally compiling it. Everything gets analyzed (if it is in a > > file that is being analyzed), whether it is chosen at elaboration or > > not. Some simulators have options for compiling (analyzing) only > > certain types of units (packages, package bodies, entities, > > architectures, etc.) and ignoring others in the same file. I have not > > seen that in a synthesis tool. > > > Other than fixing the problem with the mismatched size (if even > > possible), I would suggest moving the two architectures into separate > > files, and only including the appropriate file in the project. > > > Andy > > Hi Andy, > > Thanks for your reply, I found the solution however: adding pragmas: > > architecture struct of Stack2D is > > =A0 signal dat_2ext : buf2dwrd; > =A0 signal rd_2ext =A0: std_logic; > =A0 signal dat_2slv : buf2dwrd; > =A0 signal wr_2slv =A0: std_logic; > > =A0 -- pragma synthesis on > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > =A0 -- pragma synthesis off > > begin > > The commented pragmas did the job. > > Regards. Dear all, By the way, is there a way to make a conditional selection of architecture to use, something in the lines of: for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) else use entity work.Ctrl2D(architecture_b); ??? Or is there an alternative approach? Thanks lot in advance. JaaC From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gandalf.srv.welterde.de!news.unit0.net!news.glorb.com!news2.glorb.com!postnews.google.com!k3g2000vbp.googlegroups.com!not-for-mail From: Kevin Thibedeau Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Wed, 10 Nov 2010 11:00:14 -0800 (PST) Organization: http://groups.google.com Lines: 35 Message-ID: <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: 173.85.161.91 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415614 12838 127.0.0.1 (10 Nov 2010 19:00:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 19:00:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000vbp.googlegroups.com; posting-host=173.85.161.91; posting-account=WHzLMgoAAABnFPi2ZJ1UFqg0jT69I-kr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4366 On Nov 4, 11:30=A0pm, whygee wrote: > Hi ! > > Brian Drummond wrote: > > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: > >> Any hint ? Did I miss something ? > > bit_vector should be less heavyweight than std_logic_vector. > > sure but i want to use integers :-/ > > =A0> - Brian > > Nicolas Matringe wrote : > =A0> That's strong typing for you... > it's not a problem of typing, i can create new functions, > however I see nowhere an explanation of these missing operations. > why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) > and not on integer, as in any other language ? > > =A0> Nicolas > yg > --http://ygdes.com/http://yasep.org The reason is because this is an artifact carried over from Ada-83. In Ada and VHDL, integers are always considered to be signed even if the range is restricted to positive numbers. There is no universal way to handle boolean operations on signed numbers so it was decided to leave out implicit boolean operators in Ada. This was remedied in Ada-95 with the addition of modular types. They are restricted to unsigned integers and *do* have implicit boolean operators. As their name suggests, modular types also wraparound on overflow and underflow without throwing an exception. It would be interesting to consider adding them to a future revision to VHDL for those who want an efficient alternative to the array types. From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 13:34:08 -0800 Lines: 54 Message-ID: <8k0hecF277U1@mid.individual.net> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net dWZzVs+RNsOF7iSaEeYZ5w3wOQzhqcFYMrke6M8ybXT2Sa0dC0 Cancel-Lock: sha1:jr0Ug82ZSw0UVhDKv9LtL+pYAiE= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> Xref: feeder.eternal-september.org comp.arch.fpga:13147 comp.lang.vhdl:4367 On 11/10/2010 10:54 AM, Jaime Andrés Aranguren Cardona wrote: >> architecture struct of Stack2D is >> >> signal dat_2ext : buf2dwrd; >> signal rd_2ext : std_logic; >> signal dat_2slv : buf2dwrd; >> signal wr_2slv : std_logic; >> >> -- pragma synthesis on >> for all : Ctrl2D use entity work.Ctrl2D(rtl_small); >> -- pragma synthesis off >> >> begin >> >> The commented pragmas did the job. Maybe. Were both architectures in the synthesis file list? If so which one was first? I use a similar trick to insert debug code into synthesis sources: -- synthesis translate off spy: process (strobe_s) is begin -- process watch if falling_edge(strobe_s) then report("data = ", work.my_pkg.std2hexstr(my_ctr)); end if; end process spy; -- synthesis translate on > By the way, is there a way to make a conditional selection of > architecture to use, something in the lines of: > > for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a) else > use entity work.Ctrl2D(architecture_b); ??? Not that I know of for synthesis, where I must declare one top entity and file list. There is no notion of vhdl libraries or configurations. > Or is there an alternative approach? I could generate one direct instance or another based on a packaged constant value, but I find this confusing. If the architecture differences are much less the spare fpga resources, I might combine both modes and select using a mode register or a jumper. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: matrix generation Date: Thu, 11 Nov 2010 00:45:01 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <12e7ed74-0e4d-4ac0-b9be-6e85d5d2ef77@r14g2000yqa.googlegroups.com> References: <173668ec-83ec-4c17-8e96-fb856140c058@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289465101 20439 127.0.0.1 (11 Nov 2010 08:45:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 08:45:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4368 On Nov 10, 2:57=A0pm, Damian Drewulski wrote: > Hi there, > i have some problem. I need to get sorting net. 40 comparators in 81 > line. > > First i declared matrix: > > =A0 =A0 =A0 =A0 type wire is array (0 to 81) of std_logic_vector (7 downt= o 0); > =A0 =A0 =A0 =A0 type connections is array (0 to 81) of wire; > > Then i'm trying to generate a net of comparators. > > component comparator > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 clk : in std_logic; > =A0 =A0 =A0 =A0 rst : in std_logic; > > =A0 =A0A_in : in std_logic_vector (7 downto 0); > =A0 =A0 =A0 =A0 B_in : in std_logic_vector (7 downto 0); > > =A0 =A0 =A0 =A0 A_out : out std_logic_vector (7 downto 0); > =A0 =A0 =A0 =A0 B_out : out std_logic_vector (7 downto 0) > ); > end component; > > sorting_net : for i in 0 to 40 generate > =A0 =A0 =A0 =A0 ins: for j in (0 to 81) generate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 comparatorx : comparator port map(clk, rs= t, connections(i*2) of > wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j > +1), connections(i*2 + 1) of wire (j+1)); > =A0 =A0 =A0 =A0 end generate; > end generate; > > And after that i get few errors. I use quartus. > Anyone could help me? > > best wishes, > Damian You have to connect the IO of the instantiation to signals or IO, you cannot connect them to types. You need to declare a signal of type "connections" and connect everything to that. From newsfish@newsfish Fri Dec 24 22:55:39 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 11 Nov 2010 15:52:54 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> In-Reply-To: <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 56 Message-ID: <4cdc0343$0$14262$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 4c593229.news.skynet.be X-Trace: 1289487171 news.skynet.be 14262 91.177.233.223:58145 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4369 Kevin Thibedeau wrote: > On Nov 4, 11:30 pm, whygee wrote: >> Hi ! >> >> Brian Drummond wrote: >>> On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >>>> Any hint ? Did I miss something ? >>> bit_vector should be less heavyweight than std_logic_vector. >> sure but i want to use integers :-/ >> >> > - Brian >> >> Nicolas Matringe wrote : >> > That's strong typing for you... >> it's not a problem of typing, i can create new functions, >> however I see nowhere an explanation of these missing operations. >> why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) >> and not on integer, as in any other language ? >> >> > Nicolas >> yg >> --http://ygdes.com/http://yasep.org > > The reason is because this is an artifact carried over from Ada-83. In > Ada and VHDL, integers are always considered to be signed even if the > range is restricted to positive numbers. There is no universal way to > handle boolean operations on signed numbers so it was decided to leave > out implicit boolean operators in Ada. > > This was remedied in Ada-95 with the addition of modular types. They > are restricted to unsigned integers and *do* have implicit boolean > operators. As their name suggests, modular types also wraparound on > overflow and underflow without throwing an exception. It would be > interesting to consider adding them to a future revision to VHDL for > those who want an efficient alternative to the array types. Fascinating stuff - thanks for this info. Restricting the bit view to the "unsigned" domain makes a lot of sense (talking from my own language design experience). During a quick survey I found that part of the rationale behind modular types was "easier interaction with hardware". Interesting, isn't it? It seems that a lot of the groundwork that would turn VHDL into the "easy" HDL is readily available. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!x4g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Thu, 11 Nov 2010 09:03:19 -0800 (PST) Organization: http://groups.google.com Lines: 142 Message-ID: <2b0654d8-ade1-4d10-a4f5-b864964ea1ad@x4g2000pre.googlegroups.com> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289495000 22647 127.0.0.1 (11 Nov 2010 17:03:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 17:03:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x4g2000pre.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13153 comp.lang.vhdl:4370 On Nov 10, 12:54=A0pm, Jaime Andr=E9s Aranguren Cardona wrote: > On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona > > > > > > wrote: > > On 10 Nov., 19:16, Andy wrote: > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > wrote: > > > > Dear all, > > > > > In my current project I have an entity for which I which arhitectur= e > > > > to use on a VHDL file where I instantiate the entity, like followin= g > > > > configuration code: > > > > > -- Embedded configuration > > > > -- Select control architecture to use > > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > > configurations, namely rtl_tiny and rtl_small. Within each of those= , > > > > are processes which have variables whose length depend on some > > > > constants (KA, KB), like: > > > > > process_out : process (in_a, in_b) > > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D = (others =3D> > > > > '0'); > > > > =A0 begin > > > > > I should select which architecture to use in the configuration > > > > (rtl_tiny or rtl_small) depending on a given a given set of values = KA > > > > and KB. For a set of values KA and KB that works fine with rtl_smal= l > > > > and having rtl_small selected in the configuration, XST, when parsi= ng, > > > > gives me warnign and error messages: > > > > > Entity compiled. > > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > > range: -33 downto 0 > > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > > concat operation is different than size of the target. > > > > Entity (Architecture ) compiled. > > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > > not rtl_small. > > > > > I was confident that by selecting the right architecture in the > > > > configuration I was completely bypassing everything related to non- > > > > desired architectures, but it seems like I was wrong. > > > > > How can I direct XST to ignore the code of the non-interesting > > > > architectures, and parse and synthesize only the one that I selecte= d > > > > in the configuration? > > > > > Thanks a lot in advance, > > > > > JaaC > > > > Unlike simulation tools, synthesis tools combine the analysis and > > > elaboration phases into one. This is probably leading to your problem= . > > > Leaving something out in a configuration is not quite like > > > conditionally compiling it. Everything gets analyzed (if it is in a > > > file that is being analyzed), whether it is chosen at elaboration or > > > not. Some simulators have options for compiling (analyzing) only > > > certain types of units (packages, package bodies, entities, > > > architectures, etc.) and ignoring others in the same file. I have not > > > seen that in a synthesis tool. > > > > Other than fixing the problem with the mismatched size (if even > > > possible), I would suggest moving the two architectures into separate > > > files, and only including the appropriate file in the project. > > > > Andy > > > Hi Andy, > > > Thanks for your reply, I found the solution however: adding pragmas: > > > architecture struct of Stack2D is > > > =A0 signal dat_2ext : buf2dwrd; > > =A0 signal rd_2ext =A0: std_logic; > > =A0 signal dat_2slv : buf2dwrd; > > =A0 signal wr_2slv =A0: std_logic; > > > =A0 -- pragma synthesis on > > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > =A0 -- pragma synthesis off > > > begin > > > The commented pragmas did the job. > > > Regards. > > Dear all, > > By the way, is there a way to make a conditional selection of > architecture to use, something in the lines of: > > for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) =A0els= e > use entity work.Ctrl2D(architecture_b); =A0 ??? > > Or is there an alternative approach? > > Thanks lot in advance. > > JaaC- Hide quoted text - > > - Show quoted text - The only way to do that is with an if-generate on the instantiation, not the configuration. In fact, since the '93 standard, you can directly instantiate an entity and its architecture: if a =3D 0 generate u1: entity work.entity_name(architecture_name)... end generate; if a /=3D 0 generate u1: entity work.entity_name(alternative_architecture_name) ... end generate; You don't even need to mess with a configuration! Andy From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!r21g2000pri.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 09:14:23 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289495663 7723 127.0.0.1 (11 Nov 2010 17:14:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 17:14:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r21g2000pri.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4371 I have only been programming full-time in VHDL for a little over a year so I tend to be skeptical at my ability to come up with suggestions that would enhance the language. So before I go through any process to make any official request I'd like to get some feedback here on a few ideas that I've felt would improve the VHDL experience. 1. 'SCOPE' or 'CONTEXT' - a keyword to define a scope. An example usage follows: CountDown : CONTEXT VARIABLE Counter : UNSIGNED( 15 DOWNTO 0 ) := x"FFFF"; BEGIN Counter := Counter - 1; END CONTEXT CountDown; Counter := Counter - 1; -- Error: Counter is not defined here. This is a trivial example, but the idea is as follows. Many variables are used only a few times and in a small section. By having the variable declaration close to where it's used it makes the code more readable as the programmer does not need to search through the file for the definition. Originally the idea was to simply allow the BEGIN keyword to be used in IF statements, but the syntax would be very odd with respect to how it would look if you used ELSE statements. This is broader. I would suggest CONTEXT be allowed both within a process body and outside of it for the benefit of concurrent statements. This models one of the uses of the curly brackets in C++. 2. Often times signals are used only within a single process because the semantics are ideal if you don't want changes to take effect until the next clock cycle. For example, all of my state machines, even if they're only defined within a process, are signals. Similar to the above reasoning of keeping variable declarations close to where they're used, I'd like to see the SIGNAL keyword be legal to use wherever you can use VARIABLE. I realize simulators require more CPU resources to simulate signals than variables and so some people try to discourage their use, but for those of us who use them often I feel this would help readability. 3. This is less well thought out than the two above and comes more in the shape of a problem than a solution. VHDL's ability for static elaboration is amazing in comparison to many other languages (i.e. C+ +). However, consider the following type. Imagine that I wanted to implement a LFSR that cycles every N increments. Can this be coded in VHDL 2008? I.E., can I have something like the following: TYPE lfsr5 IS lfsr( period => 5 ); ... VARIABLE state : lfsr5 := lfsr5'POS(0); ... CASE state IS WHEN lfsr5'POS(0) => ... WHEN lfsr5'POS(1) => ... ... WHEN lfsr5'POS(4) => ... END CASE; state := state + 1; I don't see how to do anything quite like that at the moment. The values of POS(0) through POS(1) for an LFSR depend on the period so they would need to be generated during elaboration. I wouldn't mind a custom attribute other than POS to be used, I just don't see how to do this as a generic variable. If I'm mistaken please let me know. From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!postnews.google.com!y2g2000prf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 10:17:15 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289499435 10134 127.0.0.1 (11 Nov 2010 18:17:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 18:17:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y2g2000prf.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4372 It seems like what you want for #1 is to be able to use the block statement as a sequential statement. It would be just as valuable, and syntactically simpler, to allow declarative regions within control statements (if, case, loop, etc.; anything with an "end" should be able to have a declarative region). An existing solution to #2 is to wrap your process with a block statement that declares the signals that are "local" to the process. This can also be used to declare signals (and types) that are used to communicate only between two processes (e.g. a clocked and combo process pair) by putting both processes in the same block. Opinions vary, but the semantics of signal assignment/update rarely lead to a "more readable" description within a process. I prefer the semantics of variables because it "reads" like it executes. There is no hidden "oh, this doesn't actually change until the process suspends" garbage. I have no comment on #3. Andy From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a9g2000pro.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 11:53:59 -0800 (PST) Organization: http://groups.google.com Lines: 69 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289505239 14887 127.0.0.1 (11 Nov 2010 19:53:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 19:53:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a9g2000pro.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4373 On Nov 11, 1:17=A0pm, Andy wrote: > It seems like what you want for #1 is to be able to use the block > statement as a sequential statement. It would be just as valuable, and > syntactically simpler, to allow declarative regions within control > statements (if, case, loop, etc.; anything with an "end" should be > able to have a declarative region). > > An existing solution to #2 is to wrap your process with a block > statement that declares the signals that are "local" to the process. > This can also be used to declare signals (and types) that are used to > communicate only between two processes (e.g. a clocked and combo > process pair) by putting both processes in the same block. > > Opinions vary, but the semantics of signal assignment/update rarely > lead to a "more readable" description within a process. I prefer the > semantics of variables because it "reads" like it executes. There is > no hidden "oh, this doesn't actually change until the process > suspends" garbage. > > I have no comment on #3. > > Andy Thanks - very informative. Yes, I suppose I am simply looking for a sequential version of block. As I said, my original suggestion was going to be to allow the use of BEGIN within control statements, but the following usage bothered me: IF Condition THEN VARIABLE LocalValue : LocalType :=3D LocalInitialization; BEGIN DoSomething; ELSE DoSomethingElse; END IF; Is LocalValue defined in both branches of the if statement? We'd want it to be so, yes, but I could see how it might possibly lead to occasional (and/or newbie) confusion. The other issue was that if the BEGIN syntax is used as above it would lead to the BEGIN keyword being optional in some locations and mandatory in others (unless the definitions of many other keywords). Although I will admit that there are many times I've wanted to not write BEGIN (i.e. functions/procedures/processes where I have no variables...), there does tend to be inertia to such wide-scale changes, even if they don't break previous code. As for the comment on #2, this certainly does most of what I want, and a bit more. That said, when I use a signal purely inside a process it's not as clean, but it'll certainly help make my code at least a little more readable, especially in the clocked/combo pair example you cited. Often times I find myself write code "backwards" though when I use variables instead of signals. I.E., if I have the following schedule of tasks to accomplish, each taking 1 clock cycle, and depending on each other: A < B < C, that is C depends on the result of B depends on the result of A, if their results are output as variables I tend to write the code: C B A This is (to me) more opaque to read. But different developers will do things differently, and as long as people are using signals the way I use them, it would be nice to be able to declare them closer to where they're used. From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!o11g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Thu, 11 Nov 2010 13:33:56 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 173.13.214.113 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289511236 2208 127.0.0.1 (11 Nov 2010 21:33:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 21:33:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000prf.googlegroups.com; posting-host=173.13.214.113; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4374 On Nov 8, 12:57 pm, Andy wrote: > The VHDL standard has already adopted an assumed two's complement > numeric representation for vectors (numeric_std, numeric_std_unsigned, > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > representation for integes as well?! Your statement is not exactly correct. "vectors" are not 2's complement. numeric_std is 2's complement. SLV is still not arithmetic at all. That is the difference. If you wanted to add a 2's complement integer type as a new type then that would be backwards compatible by not changing the standard integer type. The new type could be defined in something like integer_numeric_std or maybe added to numeric_std. > The primary problem with vhdl vector based arithmetic (numeric_*) is > that it rolls over (not to signed, but what's the difference, an > unsigned rollover is still inaccurate). Take two unsigned, add them > together, and you can get a result that is less than either of the > operands. What you call "inaccurate" is a result of limited range of the representation. What would you have the implementation do when the "overflow" occurs? I can see three choices: roll over treating the limited range as modulo arithmetic (minimum logic), saturate at the max and min of the range (more logic and still "inaccurate") or just not perform the operation (also more logic and who knows what "inaccurate" really means in this case). Both can/should throw an error if the operation is actually doing arithmetic. But it is often that a counter is intended to roll over. For those I have to use an explicit modulo operator. > The closest vhdl vector arithmetic comes to true integer arithmetic > accuracy is the fixed point package types, with zero fractional bits > declared. Fixed point operators automatically pad the result size to > account for accuracy in all cases, except one: a ufixed minus a ufixed > is still a ufixed (but actually bigger by one bit! go figure) rather > than an sfixed. With the almost universal need to resize sfixed/ufixed > results to fit in an assigned signal/variable, the conversion from > sfixed to ufixed could easily be handled in the resize function > anyway. > > Or better yet, allow assignment operators to be overloaded so that > they can do the resizing automatically. > > Hey, I can dream, can't I? I believe overloading operators has been suggested for the next go around on the VHDL spec. I have no idea if this would create any problems. Rick From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z22g2000pri.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Programmable Logic at StackExchange Date: Thu, 11 Nov 2010 15:43:05 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289518986 26444 127.0.0.1 (11 Nov 2010 23:43:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 23:43:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z22g2000pri.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4375 Someone recently added a Programmable Logic Stack on Stack Exchange, and it needs more followers to get official status. As most VHDL developers can attest, getting information can be difficult, and these stack sites (the original is StackOverflow.com) are immensely useful. The site can be found here: http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design Someone tried to start a VHDL stack but it was too specific and was pruned. From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r31g2000prg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 15:50:22 -0800 (PST) Organization: http://groups.google.com Lines: 67 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289519423 8779 127.0.0.1 (11 Nov 2010 23:50:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 23:50:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r31g2000prg.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4376 On Nov 11, 1:53=A0pm, Jonathan Ross wrote: > > Thanks - very informative. Yes, I suppose I am simply looking for a > sequential version of block. As I said, my original suggestion was > going to be to allow the use of BEGIN within control statements, but > the following usage bothered me: > > IF Condition THEN > =A0 =A0VARIABLE LocalValue : LocalType :=3D LocalInitialization; > BEGIN > =A0 =A0DoSomething; > ELSE > =A0 =A0DoSomethingElse; > END IF; > > Is LocalValue defined in both branches of the if statement? We'd want > it to be so, yes, but I could see how it might possibly lead to > occasional (and/or newbie) confusion. > Every other place BEGIN is used in VHDL, its context continues until the corresponding END. I could easily agree with a change that made BEGIN keywords optional if there were no declarative region needed, for all cases, including process, architecture, etc. "IS" is already optional after PROCESS (...). > Often times I find myself write code "backwards" though when I use > variables instead of signals. I.E., if I have the following schedule > of tasks to accomplish, each taking 1 clock cycle, and depending on > each other: A < B < C, that is C depends on the result of B depends on > the result of A, if their results are output as variables I tend to > write the code: > > C > B > A > > This is (to me) more opaque to read. That's part of the unintuitiveness of signals: a <=3D b; b <=3D c; has exactly the same results as: b <=3D c; a <=3D b; This is not intuitive. The difference in behavior between sequential signal assignments and concurrent signal assignments is muddied because the order of statements does not matter in either case, which leads to lots of confusion with newbies. A sequential signal assignment is not quite sequential, but not quite concurrent either. With variables, the assignment executes entirely in the order it is written, and as expected, the different orders have different results. Having to "reverse the order" is no different whether you are writing code for compilation and execution on a processor, or on an FPGA/ASIC. Andy From newsfish@newsfish Fri Dec 24 22:55:40 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!r21g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 18:03:21 -0800 (PST) Organization: http://groups.google.com Lines: 81 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289527401 5757 127.0.0.1 (12 Nov 2010 02:03:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 02:03:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r21g2000pri.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4377 On Nov 11, 6:50=A0pm, Andy wrote: > On Nov 11, 1:53=A0pm, Jonathan Ross > wrote: > > > > > > > Thanks - very informative. Yes, I suppose I am simply looking for a > > sequential version of block. As I said, my original suggestion was > > going to be to allow the use of BEGIN within control statements, but > > the following usage bothered me: > > > IF Condition THEN > > =A0 =A0VARIABLE LocalValue : LocalType :=3D LocalInitialization; > > BEGIN > > =A0 =A0DoSomething; > > ELSE > > =A0 =A0DoSomethingElse; > > END IF; > > > Is LocalValue defined in both branches of the if statement? We'd want > > it to be so, yes, but I could see how it might possibly lead to > > occasional (and/or newbie) confusion. > > Every other place BEGIN is used in VHDL, its context continues until > the corresponding END. > > I could easily agree with a change that made BEGIN keywords optional > if there were no declarative region needed, for all cases, including > process, architecture, etc. =A0"IS" is already optional after PROCESS > (...). > > > Often times I find myself write code "backwards" though when I use > > variables instead of signals. I.E., if I have the following schedule > > of tasks to accomplish, each taking 1 clock cycle, and depending on > > each other: A < B < C, that is C depends on the result of B depends on > > the result of A, if their results are output as variables I tend to > > write the code: > > > C > > B > > A > > > This is (to me) more opaque to read. > > That's part of the unintuitiveness of signals: > > a <=3D b; > b <=3D c; > > has exactly the same results as: > > b <=3D c; > a <=3D b; > > This is not intuitive. > > The difference in behavior between sequential signal assignments and > concurrent signal assignments is muddied because the order of > statements does not matter in either case, which leads to lots of > confusion with newbies. A sequential signal assignment is not quite > sequential, but not quite concurrent either. > > With variables, the assignment executes entirely in the order it is > written, and as expected, the different orders have different results. > > Having to "reverse the order" is no different whether you are writing > code for compilation and execution on a processor, or on an FPGA/ASIC. When you say "unintuitive" you mean you have learned how software works and had to relearn how hardware works. HDL is the way it is because it is describing hardware. Trying to treat HDL like software may result in a working design, but has great potential to cause problems. Yes, if you already know how procedural languages work, you will have to forget that or at least not think HDL is similar. I know that is what I had to do. Rick From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 09:13:38 +0000 Organization: TRW Conekt Lines: 40 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 9vXdUszZ2hLRuWwQfrdkTwImBEZgmfME9HuuaXioO841MLmfc= Cancel-Lock: sha1:6VaojYq7eM+UX3n+7tfOzk5W7OM= sha1:sqEuWBAl1iaUCT7/vwcDMAtus+U= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4378 Jan Decaluwe writes: > Kevin Thibedeau wrote: >> Ada and VHDL, integers are always considered to be signed even if the >> range is restricted to positive numbers. There is no universal way to >> handle boolean operations on signed numbers so it was decided to leave >> out implicit boolean operators in Ada. >> >> This was remedied in Ada-95 with the addition of modular types. They >> are restricted to unsigned integers and *do* have implicit boolean >> operators. As their name suggests, modular types also wraparound on >> overflow and underflow without throwing an exception. It would be >> interesting to consider adding them to a future revision to VHDL for >> those who want an efficient alternative to the array types. > > Fascinating stuff - thanks for this info. > > Restricting the bit view to the "unsigned" domain makes a lot > of sense (talking from my own language design experience). > > During a quick survey I found that part of the rationale > behind modular types was "easier interaction with hardware". > Interesting, isn't it? > > It seems that a lot of the groundwork that would turn VHDL > into the "easy" HDL is readily available. > Maybe we should just quit VHDL and start synthesising Ada directly (with only half-a-smiley ;) Maybe call it SystemAda :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Fri, 12 Nov 2010 09:19:34 +0000 Organization: TRW Conekt Lines: 21 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net gb0ZfD4FNU4p3l6XjkHGkghMnOkPMGfRfGXubudzRvkM9avAU= Cancel-Lock: sha1:NIQIIiPKpun3zIig8Qlr9DH16KE= sha1:RdS2SnkXO6i9CFFPmmd91HlQaBk= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4379 Andy writes: > It seems like what you want for #1 is to be able to use the block > statement as a sequential statement. It would be just as valuable, and > syntactically simpler, to allow declarative regions within control > statements (if, case, loop, etc.; anything with an "end" should be > able to have a declarative region). Which is the C99 and C++ way (dunno if that's in its favour or not :) Personally, I'd like it. I think the "if blah then variable.... begin... else... end;" proposal made downthread could work well. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 12 Nov 2010 05:43:20 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 11:52:54 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 64 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-1qeYFktKYLl893TrvOJL47HUlFZ7hL8ztIhOnJsyNnr+kqhCbihqpqnwVT1JWecg9CeKhNdH6bYJiKW!hA/I+xfRG30yS3xk+eMCV3sR68iBuFjwvQ3rJwBycFiydVpLTDkhdsu0rruyzaApWPJDNlqgdfNd!iuUL X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3983 Xref: feeder.eternal-september.org comp.lang.vhdl:4380 On Fri, 12 Nov 2010 09:13:38 +0000, Martin Thompson wrote: >Jan Decaluwe writes: > >> Kevin Thibedeau wrote: ... >>> This was remedied in Ada-95 with the addition of modular types. They >>> are restricted to unsigned integers and *do* have implicit boolean >>> operators. As their name suggests, modular types also wraparound on >>> overflow and underflow without throwing an exception. It would be >>> interesting to consider adding them to a future revision to VHDL for >>> those who want an efficient alternative to the array types. >> >> Fascinating stuff - thanks for this info. >> >> Restricting the bit view to the "unsigned" domain makes a lot >> of sense (talking from my own language design experience). >> >> During a quick survey I found that part of the rationale >> behind modular types was "easier interaction with hardware". >> Interesting, isn't it? >> >> It seems that a lot of the groundwork that would turn VHDL >> into the "easy" HDL is readily available. >> > >Maybe we should just quit VHDL and start synthesising Ada directly >(with only half-a-smiley ;) > >Maybe call it SystemAda :) I believe that would make a lot more sense as a starting point than C or C++. I am playing with Ada, and finding it very nice indeed. Ada-95 and now 2005 add a rational type of object oriented programing, maintaining good type safety even in a complex class hierarchy. If VHDL is to acquire classes, I hope they will be along the same lines. As well as adding the modular types, Ada has fixed point types (you specify range and precision) which could make DSP a breeze. I suspect the original VHDL committee chose about the right subset of Ada as a starting point in the 1980s, but now a larger subset could be useful - fixed point types for example. Since then there has been parallel (usually divergent) evolution, but VHDL-2008 got conditional- (and case?) -expressions before Ada (they are due in Ada-2012). But if we're going down the SystemAda route, we need a synthesisable subset - no heap allocation, limits on recursion, etc. It'll look a lot like the SPARK subset - with which, using annotations in the form of Ada comments - your design can be proved formally correct. There would seem to be a lot of commonality between restructuring logic for formal proof, and restructuring it for synthesis - and certainly there are a lot of similar limitations. If the prover fails to terminate, that probably implies infinite hardware, etc... So, I'm going with SystemSPARK, and using Ada for my testbenches! - Brian From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 06:38:15 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289572695 29860 127.0.0.1 (12 Nov 2010 14:38:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 14:38:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4381 On Nov 11, 3:33 pm, rickman wrote: > On Nov 8, 12:57 pm, Andy wrote: > > > The VHDL standard has already adopted an assumed two's complement > > numeric representation for vectors (numeric_std, numeric_std_unsigned, > > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > > representation for integes as well?! > > Your statement is not exactly correct. "vectors" are not 2's > complement. numeric_std is 2's complement. SLV is still not > arithmetic at all. That is the difference. I beg to differ. The new numeric_std_unsigned package assigns an arithmetic interpretation to std_logic_vector, just like std_logic_arith did. Also, by using the conversion unsigned(my_slv) you are already implying that the unconverted slv has the same bit representation as unsigned, which is arithmetic. The tool is not allowed to convert/move bits around in that conversion, so the new interpretation is in effect placed on the old slv as well. > > > The primary problem with vhdl vector based arithmetic (numeric_*) is > > that it rolls over (not to signed, but what's the difference, an > > unsigned rollover is still inaccurate). Take two unsigned, add them > > together, and you can get a result that is less than either of the > > operands. > > What you call "inaccurate" is a result of limited range of the > representation. What would you have the implementation do when the > "overflow" occurs? I can see three choices: roll over treating the > limited range as modulo arithmetic (minimum logic), saturate at the > max and min of the range (more logic and still "inaccurate") or just > not perform the operation (also more logic and who knows what > "inaccurate" really means in this case). Both can/should throw an > error if the operation is actually doing arithmetic. But it is often > that a counter is intended to roll over. For those I have to use an > explicit modulo operator. > If I tell the simulator or synthesis tool to add one to a value, the new value better be larger than the old value, by exactly one, or it should die trying (with an informative error message in the case of a simulator). It should not silently assume that something else will be good enough. Same goes for subtraction. If I need it do do something besides adding or subtracting, then I will tell it what I want it to do (either by resize() or mod, etc.) Integer and sfixed/ufixed do this correctly, with the exception of subtracting ufixed values. > > > Or better yet, allow assignment operators to be overloaded so that > > they can do the resizing automatically. > > > Hey, I can dream, can't I? > > I believe overloading operators has been suggested for the next go > around on the VHDL spec. I have no idea if this would create any > problems. > > Rick I think limiting overloaded assignment operators to re-sizing the same type (between the expression and the target) would be pretty safe, but it also would not handle the signed/unsigned issue. But because integer and natural are the same base type, it can also handle signed/ unsigned conversions (with bounds checking). Those are different base types in VHDL. So maybe we limit the actions of overloaded assignment operators to converting "closely related" types and resizing to this relatively safe. If it works out, maybe we can extend overloaded assignments to other areas, but I'd rather take baby steps and not break anything, than take too big a step and cause bigger, unforseen problems. Andy From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 12 Nov 2010 16:09:06 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> In-Reply-To: <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 77 Message-ID: <4cdd5892$0$14252$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 84a31462.news.skynet.be X-Trace: 1289574546 news.skynet.be 14252 91.177.142.122:32880 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4382 Brian Drummond wrote: > On Fri, 12 Nov 2010 09:13:38 +0000, Martin Thompson > wrote: > >> Jan Decaluwe writes: >> >>> Kevin Thibedeau wrote: > ... > >>>> This was remedied in Ada-95 with the addition of modular types. They >>>> are restricted to unsigned integers and *do* have implicit boolean >>>> operators. As their name suggests, modular types also wraparound on >>>> overflow and underflow without throwing an exception. It would be >>>> interesting to consider adding them to a future revision to VHDL for >>>> those who want an efficient alternative to the array types. >>> Fascinating stuff - thanks for this info. >>> >>> Restricting the bit view to the "unsigned" domain makes a lot >>> of sense (talking from my own language design experience). >>> >>> During a quick survey I found that part of the rationale >>> behind modular types was "easier interaction with hardware". >>> Interesting, isn't it? >>> >>> It seems that a lot of the groundwork that would turn VHDL >>> into the "easy" HDL is readily available. >>> >> Maybe we should just quit VHDL and start synthesising Ada directly >> (with only half-a-smiley ;) >> >> Maybe call it SystemAda :) > > I believe that would make a lot more sense as a starting point than C or C++. > > I am playing with Ada, and finding it very nice indeed. > > Ada-95 and now 2005 add a rational type of object oriented programing, > maintaining good type safety even in a complex class hierarchy. If VHDL is to > acquire classes, I hope they will be along the same lines. > > As well as adding the modular types, Ada has fixed point types (you specify > range and precision) which could make DSP a breeze. > > I suspect the original VHDL committee chose about the right subset of Ada as a > starting point in the 1980s, but now a larger subset could be useful - fixed > point types for example. > > Since then there has been parallel (usually divergent) evolution, but VHDL-2008 > got conditional- (and case?) -expressions before Ada (they are due in Ada-2012). > > But if we're going down the SystemAda route, we need a synthesisable subset To get started, we would need to define/implement an RTL semantics subset. The language has built-in concurrency support, so no problem there. An RTL-style signal would probably be easy. The remaining problem is a model for sensitivity, and then a simulation engine could be written ... > heap allocation, limits on recursion, etc. It'll look a lot like the SPARK > subset - with which, using annotations in the form of Ada comments - your design > can be proved formally correct. > > There would seem to be a lot of commonality between restructuring logic for > formal proof, and restructuring it for synthesis - and certainly there are a lot > of similar limitations. If the prover fails to terminate, that probably implies > infinite hardware, etc... > > So, I'm going with SystemSPARK, and using Ada for my testbenches! > > - Brian -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!o11g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 07:58:38 -0800 (PST) Organization: http://groups.google.com Lines: 109 Message-ID: <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289577518 26646 127.0.0.1 (12 Nov 2010 15:58:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 15:58:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000prf.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4383 On Nov 12, 9:38=A0am, Andy wrote: > On Nov 11, 3:33 pm, rickman wrote: > > > On Nov 8, 12:57 pm, Andy wrote: > > > > The VHDL standard has already adopted an assumed two's complement > > > numeric representation for vectors (numeric_std, numeric_std_unsigned= , > > > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > > > representation for integes as well?! > > > Your statement is not exactly correct. =A0"vectors" are not 2's > > complement. =A0numeric_std is 2's complement. =A0SLV is still not > > arithmetic at all. =A0That is the difference. > > I beg to differ. The new numeric_std_unsigned package assigns an > arithmetic interpretation to std_logic_vector, just like > std_logic_arith did. > > Also, by using the conversion unsigned(my_slv) you are already > implying that the unconverted slv has the same bit representation as > unsigned, which is arithmetic. The tool is not allowed to convert/move > bits around in that conversion, so the new interpretation is in effect > placed on the old slv as well. Yes, if the designer wants to consider SLV as a 2's complement vector, there is nothing in the language to prevent that. But there is nothing in the language to promote it either. Anyone is free to create their own libraries or to use standard ones to add capabilities to the language. That is what is going on in both numeric_std_unsigned and in numeric_std. The utility of these data types is being extended as the designer wishes. It is not a default part of the language. > > > The primary problem with vhdl vector based arithmetic (numeric_*) is > > > that it rolls over (not to signed, but what's the difference, an > > > unsigned rollover is still inaccurate). Take two unsigned, add them > > > together, and you can get a result that is less than either of the > > > operands. > > > What you call "inaccurate" is a result of limited range of the > > representation. =A0What would you have the implementation do when the > > "overflow" occurs? =A0I can see three choices: roll over treating the > > limited range as modulo arithmetic (minimum logic), saturate at the > > max and min of the range (more logic and still "inaccurate") or just > > not perform the operation (also more logic and who knows what > > "inaccurate" really means in this case). =A0Both can/should throw an > > error if the operation is actually doing arithmetic. =A0But it is often > > that a counter is intended to roll over. =A0For those I have to use an > > explicit modulo operator. > > If I tell the simulator or synthesis tool to add one to a value, the > new value better be larger than the old value, by exactly one, or it > should die trying (with an informative error message in the case of a > simulator). It should not silently assume that something else will be > good enough. Same goes for subtraction. If I need it do do something > besides adding or subtracting, then I will tell it what I want it to > do (either by resize() or mod, etc.) > > Integer and sfixed/ufixed do this correctly, with the exception of > subtracting ufixed values. How do you expect a synthesis tool to handle this requirement? If you write VHDL code to increment a counter, what do you expect the hardware to do when the counter reaches the max value? Are you saying you expect the synthesis tool to throw an error if the designer does not indicate explicitly what will happen with an IF statement or a MOD operator? What does the synthesis tool do with integers in the case of a counter that can overflow? signal a : integer range 0 to 15; -- clocked process wrapper... a <=3D a + 1; What hardware should this produce? Or how should I write this for a 4 bit counter? How exactly should the synthesis tool "die trying"? > > > Or better yet, allow assignment operators to be overloaded so that > > > they can do the resizing automatically. > > > > Hey, I can dream, can't I? > > > I believe overloading operators has been suggested for the next go > > around on the VHDL spec. =A0I have no idea if this would create any > > problems. > > > Rick > > I think limiting overloaded assignment operators to re-sizing the same > type (between the expression and the target) would be pretty safe, but > it also would not handle the signed/unsigned issue. But because > integer and natural are the same base type, it can also handle signed/ > unsigned conversions (with bounds checking). Those are different base > types in VHDL. > > So maybe we limit the actions of overloaded assignment operators to > converting "closely related" types and resizing to this relatively > safe. If it works out, maybe we can extend overloaded assignments to > other areas, but I'd rather take baby steps and not break anything, > than take too big a step and cause bigger, unforseen problems. I have no idea what is safe and what is not. But us talking about it won't solve anything. Rick From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!n32g2000prc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 11:46:16 -0800 (PST) Organization: http://groups.google.com Lines: 70 Message-ID: <55049319-4709-4af5-8987-17194ca0de88@n32g2000prc.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289591177 4349 127.0.0.1 (12 Nov 2010 19:46:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 19:46:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000prc.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4384 On Nov 12, 9:58=A0am, rickman wrote: > Yes, if the designer wants to consider SLV as a 2's complement vector, > there is nothing in the language to prevent that. =A0But there is > nothing in the language to promote it either. =A0Anyone is free to > create their own libraries or to use standard ones to add capabilities > to the language. =A0That is what is going on in both > numeric_std_unsigned and in numeric_std. =A0The utility of these data > types is being extended as the designer wishes. =A0It is not a default > part of the language. > The standard ("default part of the") language now includes the packages. And by allowing the unsigned(my_slv) conversion, which does not include any reforming of the elements within my_slv, and my_slv =3D 10 (via numeric_std_unsigned), the language is ensuring that the numeric interpretation is extended to slv. Whether you choose to access that interpretation or not, the representation must be consistent with the numeric interpretation. > How do you expect a synthesis tool to handle this requirement? =A0If you > write VHDL code to increment a counter, what do you expect the > hardware to do when the counter reaches the max value? =A0Are you saying > you expect the synthesis tool to throw an error if the designer does > not indicate explicitly what will happen with an IF statement or a MOD > operator? > > What does the synthesis tool do with integers in the case of a counter > that can overflow? > > signal a : integer range 0 to 15; > -- clocked process wrapper... > =A0 a <=3D a + 1; > > What hardware should this produce? =A0Or how should I write this for a 4 > bit counter? =A0How exactly should the synthesis tool "die trying"? Your description did not legally tell the synthesis tool what to do when a is 15, since storing the result of 15 + 1 in a would be illegal (and in fact impossible in a four bit storage register). Therefore, the synthesis tool is free to do anything it wants in that case. So, one way to look at what really happens in synthesis is this: signal a : integer range 0 to 15; -- clocked process wrapper... if a + 1 > 15 then -- implied by the range of a a <=3D "don't care"; -- because assigning 16 to a is illegal anyway else a <=3D a + 1; end if; Lucky for us, it turns out that the most efficient implementation of the above is to simply truncate the result of 15 + 1, which is a roll over, or modulo counter. I would prefer that it at least give me a warning that it was doing this, but in reality, it could do anything it wants, because I did not tell it what to do. To keep simulation and synthesis on the same page, a better way to write it in the first place would be: signal a : integer range 0 to 15; -- clocked process wrapper... a <=3D (a + 1) mod 16; This way, you are explicitly, legally telling the synthesis tool (and the simulator) what you want to do when a is 15. Andy From newsfish@newsfish Fri Dec 24 22:55:41 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!y2g2000prf.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Fri, 12 Nov 2010 11:54:58 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <80085633-1739-4b6a-8230-1127083cbbb8@y2g2000prf.googlegroups.com> References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 66.80.67.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289591698 9410 127.0.0.1 (12 Nov 2010 19:54:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 19:54:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y2g2000prf.googlegroups.com; posting-host=66.80.67.189; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4385 Jonathan, Now once you have written about what you want, if you would like to make an official feature request to the VHDL working group, you can submit an enhancement request at: http://www.eda.org/vasg/ Look on the left hand side of the page for enhancement & bug request Best, Jim From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news.musoftware.de!wum.musoftware.de!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 12 Nov 2010 17:10:43 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 23:11:13 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-fmKNFvR8DJUFEeEqqDTTqqPUkxKHtq4SoX1EZmXkySBjo2dl2nhr/GWkFqhcWJDwLA09OM6xFyhfbLW!wuLYvdHYHNlD2SDUBi4i5iPq3520PqWYKE1SfvY2/B810Xr0qWa78gkcXKop12Jmrl6z0jQrt8cM!a16z X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2549 Xref: feeder.eternal-september.org comp.lang.vhdl:4386 On Fri, 12 Nov 2010 06:38:15 -0800 (PST), Andy wrote: >On Nov 11, 3:33 pm, rickman wrote: >> On Nov 8, 12:57 pm, Andy wrote: >So maybe we limit the actions of overloaded assignment operators to >converting "closely related" types and resizing to this relatively >safe. If it works out, maybe we can extend overloaded assignments to >other areas, but I'd rather take baby steps and not break anything, >than take too big a step and cause bigger, unforseen problems. Before you go too far with overloaded assignment operators, you have to face another issue : assignment is not an operator! And changing that in VHDL would probably be difficult (for a mild understatement). For better or worse, it's a 50-year old design decision in, clearly not just VHDL, but back through Ada, and right back to Algol-60. I don't see it happening. - Brian From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!i32g2000pri.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 17:39:54 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <9f0c07cc-1717-489c-9f94-bd4558a74ce1@i32g2000pri.googlegroups.com> References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289612394 2322 127.0.0.1 (13 Nov 2010 01:39:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 01:39:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i32g2000pri.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4387 On Nov 12, 6:11=A0pm, Brian Drummond wrote: > > Before you go too far with overloaded assignment operators, > you have to face another issue : > > assignment is not an operator! > > And changing that in VHDL would probably be difficult (for a mild > understatement). For better or worse, it's a 50-year old design decision = in, > clearly not just VHDL, but back through Ada, and right back to Algol-60. > > I don't see it happening. > Rather than overloading the assignment operator, my suggestion to the (*1) VHDL pubas (two years ago) is to add a method to allow a function to get access to the attributes associated with whatever the result of the function will be assigned to. Adds to the language without breaking anything existing and accomplishes the same goal. Kevin Jennings (*1) bug #240 https://bugzilla.mentor.com/show_bug.cgi?id=3D240 From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n10g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 18:35:06 -0800 (PST) Organization: http://groups.google.com Lines: 84 Message-ID: <0bc6ee0b-cca8-4c42-8883-dc924de813f9@n10g2000prj.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> <55049319-4709-4af5-8987-17194ca0de88@n32g2000prc.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289615706 2554 127.0.0.1 (13 Nov 2010 02:35:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 02:35:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000prj.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4388 On Nov 12, 2:46 pm, Andy wrote: > On Nov 12, 9:58 am, rickman wrote: > > > Yes, if the designer wants to consider SLV as a 2's complement vector, > > there is nothing in the language to prevent that. But there is > > nothing in the language to promote it either. Anyone is free to > > create their own libraries or to use standard ones to add capabilities > > to the language. That is what is going on in both > > numeric_std_unsigned and in numeric_std. The utility of these data > > types is being extended as the designer wishes. It is not a default > > part of the language. > > The standard ("default part of the") language now includes the > packages. And by allowing the unsigned(my_slv) conversion, which does > not include any reforming of the elements within my_slv, and my_slv = > 10 (via numeric_std_unsigned), the language is ensuring that the > numeric interpretation is extended to slv. Whether you choose to > access that interpretation or not, the representation must be > consistent with the numeric interpretation. > > > > > How do you expect a synthesis tool to handle this requirement? If you > > write VHDL code to increment a counter, what do you expect the > > hardware to do when the counter reaches the max value? Are you saying > > you expect the synthesis tool to throw an error if the designer does > > not indicate explicitly what will happen with an IF statement or a MOD > > operator? > > > What does the synthesis tool do with integers in the case of a counter > > that can overflow? > > > signal a : integer range 0 to 15; > > -- clocked process wrapper... > > a <= a + 1; > > > What hardware should this produce? Or how should I write this for a 4 > > bit counter? How exactly should the synthesis tool "die trying"? > > Your description did not legally tell the synthesis tool what to do > when a is 15, since storing the result of 15 + 1 in a would be illegal > (and in fact impossible in a four bit storage register). Therefore, > the synthesis tool is free to do anything it wants in that case. > > So, one way to look at what really happens in synthesis is this: > > signal a : integer range 0 to 15; > -- clocked process wrapper... > if a + 1 > 15 then -- implied by the range of a > a <= "don't care"; -- because assigning 16 to a is illegal anyway > else > a <= a + 1; > end if; > > Lucky for us, it turns out that the most efficient implementation of > the above is to simply truncate the result of 15 + 1, which is a roll > over, or modulo counter. > > I would prefer that it at least give me a warning that it was doing > this, but in reality, it could do anything it wants, because I did not > tell it what to do. > > To keep simulation and synthesis on the same page, a better way to > write it in the first place would be: > > signal a : integer range 0 to 15; > -- clocked process wrapper... > a <= (a + 1) mod 16; > > This way, you are explicitly, legally telling the synthesis tool (and > the simulator) what you want to do when a is 15. > > Andy As it turns out, that is exactly what I do because the simulation doesn't work without it. It also solves your synthesis problem. There are any number of things that a synthesis tool assumes if you don't tell it. They think they are doing you a favor. But then these are the same sorts of things that people complain about when using VHDL. That is what VHDL is all about, telling the tools exactly what you want rather than using default. Rick From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!feeder.news-service.com!xlned.com!feeder5.xlned.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 13 Nov 2010 09:02:08 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> In-Reply-To: <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 42 Message-ID: <4cde4600$0$14250$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 490d6e16.news.skynet.be X-Trace: 1289635328 news.skynet.be 14250 91.177.142.122:38598 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4389 Brian Drummond wrote: > On Fri, 12 Nov 2010 06:38:15 -0800 (PST), Andy wrote: > >> On Nov 11, 3:33 pm, rickman wrote: >>> On Nov 8, 12:57 pm, Andy wrote: > >> So maybe we limit the actions of overloaded assignment operators to >> converting "closely related" types and resizing to this relatively >> safe. If it works out, maybe we can extend overloaded assignments to >> other areas, but I'd rather take baby steps and not break anything, >> than take too big a step and cause bigger, unforseen problems. > > Before you go too far with overloaded assignment operators, > you have to face another issue : > > assignment is not an operator! > > And changing that in VHDL would probably be difficult (for a mild > understatement). For better or worse, it's a 50-year old design decision in, > clearly not just VHDL, but back through Ada, and right back to Algol-60. > > I don't see it happening. Moreover, these proposals invariably seem to be inspired by types that force us to deal with the representation to get arithmetic right. For some reason, we seem to think that we are better at that than synthesis tools. The opposite is true of course. For integer arithmetic, a more usable integer type would address the issues in a much better way. I don't know about fixed point, but probably the Ada example can be enlightening. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j33g2000vbb.googlegroups.com!not-for-mail From: "Niv (KP)" Newsgroups: comp.lang.vhdl Subject: Custom views in ModelSim Date: Sat, 13 Nov 2010 03:51:40 -0800 (PST) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 81.110.164.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289649100 1378 127.0.0.1 (13 Nov 2010 11:51:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 11:51:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j33g2000vbb.googlegroups.com; posting-host=81.110.164.109; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4390 I've read somewhere that custom data views can be built using Tcl to view data selected in the wave window in a different format. E.g. display a clock as hrs, mins & secs as a digital clock type display. Can anyone point me to where I can find outhow todo this please? From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Custom views in ModelSim Date: Sat, 13 Nov 2010 17:30:13 +0000 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6153"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IOUMBnOU7V/HSP1cxCyGZR71hvA8EjRA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:a5qUjorhlWKKb/TxORSqV+RvNjk= Xref: feeder.eternal-september.org comp.lang.vhdl:4391 On Sat, 13 Nov 2010 03:51:40 -0800 (PST), "Niv (KP)" wrote: >I've read somewhere that custom data views can be built using Tcl to >view data selected in the wave window in a different format. >E.g. display a clock as hrs, mins & secs as a digital clock type >display. >Can anyone point me to where I can find outhow todo this please? You could start with http://www.doulos.com/knowhow/tcltk/examples/constellation/ However, it's not been updated since I wrote it quite a while ago, so it's entirely possible that the bits have rotted a little, in the way that they do when tool vendors make major revisions of their GUIs. Must try it myself, just to see if it still works :-) -- Jonathan Bromley From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p7g2000prb.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.lang.vhdl Subject: Re: Programmable Logic at StackExchange Date: Sun, 14 Nov 2010 15:03:00 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289775780 31437 127.0.0.1 (14 Nov 2010 23:03:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Nov 2010 23:03:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p7g2000prb.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4392 On Nov 11, 11:43 pm, Jonathan Ross wrote: > Someone recently added a Programmable Logic Stack on Stack Exchange, That was me. I'm glad it's getting a bit more attention, so it can become a live site eventually. A couple of months ago I made a pitch to comp.arch.fpga (which I follow regularly): http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/e4526299628848b7/ I explain there why I think the SE framework, even if imperfect, is the best option for a vendor-agnostic, "owner-less" (sort of) community support site. My post to CAF stopped short of what the SE "Area51" is, so I'll mention it here. The proposal needs at least 60 followers and 5 on- and off-topic questions, each. To count, each of those 10 questions needs to have at least 20 on- or off-topic votes (and 4 times as many on/off-topic as off/on-topic votes). Practically this means that many more than 60 followers are needed. If you choose to support this proposal, then please register, click "follow" on the proposal page, and then vote on the questions. Also, feel free to suggest your own questions. When these conditions are met, the proposal graduates to the "commitment" stage, where people are expected to commit to participate in the discussion of the would-be SE site. With enough committers (with sufficient accumulated SE "karma") the site goes "beta" for a while, and then becomes an "official" SE site if there is enough activity. cheers, saar. http://www.saardrimer.com From newsfish@newsfish Fri Dec 24 22:55:42 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!t35g2000yqj.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Mon, 15 Nov 2010 06:38:21 -0800 (PST) Organization: http://groups.google.com Lines: 160 Message-ID: References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> <2b0654d8-ade1-4d10-a4f5-b864964ea1ad@x4g2000pre.googlegroups.com> NNTP-Posting-Host: 194.25.252.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289831901 31893 127.0.0.1 (15 Nov 2010 14:38:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Nov 2010 14:38:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000yqj.googlegroups.com; posting-host=194.25.252.189; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-Via: 1.1 S04921 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13205 comp.lang.vhdl:4393 On 11 Nov., 18:03, Andy wrote: > On Nov 10, 12:54=A0pm, Jaime Andr=E9s Aranguren Cardona > > > > > > wrote: > > On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona > > > wrote: > > > On 10 Nov., 19:16, Andy wrote: > > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > > wrote: > > > > > Dear all, > > > > > > In my current project I have an entity for which I which arhitect= ure > > > > > to use on a VHDL file where I instantiate the entity, like follow= ing > > > > > configuration code: > > > > > > -- Embedded configuration > > > > > -- Select control architecture to use > > > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > > > configurations, namely rtl_tiny and rtl_small. Within each of tho= se, > > > > > are processes which have variables whose length depend on some > > > > > constants (KA, KB), like: > > > > > > process_out : process (in_a, in_b) > > > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:= =3D (others =3D> > > > > > '0'); > > > > > =A0 begin > > > > > > I should select which architecture to use in the configuration > > > > > (rtl_tiny or rtl_small) depending on a given a given set of value= s KA > > > > > and KB. For a set of values KA and KB that works fine with rtl_sm= all > > > > > and having rtl_small selected in the configuration, XST, when par= sing, > > > > > gives me warnign and error messages: > > > > > > Entity compiled. > > > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > > > range: -33 downto 0 > > > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > > > concat operation is different than size of the target. > > > > > Entity (Architecture ) compiled. > > > > > > But those lines (157 and 214) are within the architecture rtl_tin= y, > > > > > not rtl_small. > > > > > > I was confident that by selecting the right architecture in the > > > > > configuration I was completely bypassing everything related to no= n- > > > > > desired architectures, but it seems like I was wrong. > > > > > > How can I direct XST to ignore the code of the non-interesting > > > > > architectures, and parse and synthesize only the one that I selec= ted > > > > > in the configuration? > > > > > > Thanks a lot in advance, > > > > > > JaaC > > > > > Unlike simulation tools, synthesis tools combine the analysis and > > > > elaboration phases into one. This is probably leading to your probl= em. > > > > Leaving something out in a configuration is not quite like > > > > conditionally compiling it. Everything gets analyzed (if it is in a > > > > file that is being analyzed), whether it is chosen at elaboration o= r > > > > not. Some simulators have options for compiling (analyzing) only > > > > certain types of units (packages, package bodies, entities, > > > > architectures, etc.) and ignoring others in the same file. I have n= ot > > > > seen that in a synthesis tool. > > > > > Other than fixing the problem with the mismatched size (if even > > > > possible), I would suggest moving the two architectures into separa= te > > > > files, and only including the appropriate file in the project. > > > > > Andy > > > > Hi Andy, > > > > Thanks for your reply, I found the solution however: adding pragmas: > > > > architecture struct of Stack2D is > > > > =A0 signal dat_2ext : buf2dwrd; > > > =A0 signal rd_2ext =A0: std_logic; > > > =A0 signal dat_2slv : buf2dwrd; > > > =A0 signal wr_2slv =A0: std_logic; > > > > =A0 -- pragma synthesis on > > > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > =A0 -- pragma synthesis off > > > > begin > > > > The commented pragmas did the job. > > > > Regards. > > > Dear all, > > > By the way, is there a way to make a conditional selection of > > architecture to use, something in the lines of: > > > for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) =A0e= lse > > use entity work.Ctrl2D(architecture_b); =A0 ??? > > > Or is there an alternative approach? > > > Thanks lot in advance. > > > JaaC- Hide quoted text - > > > - Show quoted text - > > The only way to do that is with an if-generate on the instantiation, > not the configuration. > > In fact, since the '93 standard, you can directly instantiate an > entity and its architecture: > > if a =3D 0 generate > u1: entity work.entity_name(architecture_name)... > end generate; > > if a /=3D 0 generate > u1: entity work.entity_name(alternative_architecture_name) ... > end generate; > > You don't even need to mess with a configuration! > > Andy- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - Dear all, Thanks for the feedback. Andy's suggestion seems to be very in the direction I was heading for, thanks a lot. Kindest regards, JaaC From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Colin Paul Gloster Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Tue, 16 Nov 2010 19:40:19 +0000 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> Reply-To: Colin Paul Gloster Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="17925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/5HFR0CTXNQaC/YSJTuF13ugUuUGp0CGnnovCiznWCqQ==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: Cancel-Lock: sha1:CHQijTAIES3gP3tSH0S6oW3t+9o= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4394 Martin Thompson sent on November 12th, 2010: |------------------------------------------------------------------| |"[..] | | | |Maybe we should just quit VHDL and start synthesising Ada directly| |[..]" | |------------------------------------------------------------------| People have claimed to have synthesized Ada to hardware. |--------------------------------------------------------------------| |"Maybe call it SystemAda :)" | |--------------------------------------------------------------------| There was an article by Zainalabedin Navabi and others in "Ada Letters" entitled "System level hardware design and simulation with SystemAda" in 2009. It seems to me that they were trying to get an easy publication instead of doing real work. They and the editor showed unknowingly in the article that they did not know what they were discussing. Yours sincerely, Paul Colin Gloster From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Pin numbers assignment From: Merciadri Luca Organization: ULg Date: Thu, 18 Nov 2010 13:03:49 +0100 Message-ID: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:Y5T6bAKTRT14UDSo0+JcEx2XAro= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 39 NNTP-Posting-Host: 139.165.242.29 X-Trace: news.sunsite.dk DXC=lH]Co=P`_:8jd^7_dR6Ih5YSB=nbEKnk;OoZn^kHoPe8ZEVG41K_]RP;@H2o>Ff7K8NJeTc1TN6Wl7j iEYEARECAAYFAkzlFiUACgkQM0LLzLt8MhzkfgCfZvxK09E4kSF2TmtZJ4OG/Vjc LmEAn1/BfmjFjae2oE7UIqZPLmctfG/e =4xSL -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Buzzer From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 00:18:12 +0100 Message-ID: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:DYVI5S8C5xUzMB35B8ohvuvERUQ= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 37 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=oH8D2k\VJUX5dE91CT5^XYYSB=nbEKnk[=Wf0P_7c\ZVZEVG4QK_]RP;@H2o^O>`Ol[NBH>TX0\Po9^jJaQdkh3GE4Wn]Q X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4397 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I've got a buzzer which is basically an output of my entity. Say this is buzzer BUZ: out std_logic. Then, I want to put BUZ to 1 for just some very small amount of time. I then tried == BUZ <= '1'; BUZ <= '0' after 500 ns; == but it is apparently not appreciated from my compiler's point of view, which complains about tristate problems, etc. Is there a simple solution to it? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- If you want to judge a man's character, give him power. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzltDQACgkQM0LLzLt8Mhxw0wCgpniL+PeT7FMkbEXnSHQmMhiQ jVEAnRS31MQHeCe++BSxwGBPZ1/CRTUB =fMgN -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!c39g2000yqi.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment Date: Thu, 18 Nov 2010 19:18:33 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <8a05ab91-79aa-45dc-ac19-e1529340296b@c39g2000yqi.googlegroups.com> References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290136713 21003 127.0.0.1 (19 Nov 2010 03:18:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 03:18:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c39g2000yqi.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4398 On Nov 18, 7:03=A0am, Merciadri Luca wrote: > attribute pin_numbers of sorter: entity is > "CLK:1 BTN_on:2 LED_size:14"; > However, ispLEVER gives me `Reference to unknown attribute definition > pin_numbers'. What am I doing wrong? > Before you can use an attribute, first you must define what that attribute is in the first place. The attribute 'pin_numbers' is not a pre-defined VHDL language attribute, it is a user defined attribute...so you as the user need to define it. In your case, the following statement is needed prior to your use of the attribute statement that you have above. attribute pin_numbers: STRING; It is also likely that there is some Lattice specific library that has this attribute definition included that you could get access to with a 'use' statement. use work.xxx.all; -- Where xxx is the name of the Lattice lib Lastly, although you may have no intention of ever porting your design to any other device, it is generally not a good idea to embed pin definitions in the source code. If you DO end up moving to a different device (maybe from QFP to BGA as an example, or a bigger part) then those pin definitions in the source code are useless...and in the way now because they are in the source code. Using attributes is also tool dependent (if you move the code from say Lattice to Altera, Xilinx, etc.) and the tools that you use will usually give you an easier way to enter the pin info. Since you will need to archive the synthesis tool files anyway there is no reason that the pin number information can't be kept there also. You will likely have other constraints archived there such as timing constraints so there is no reason why pin number constraints can't be there also. Think of it this way, the VHDL you write is intended to define a logic description. A logic description does not inherently require any specific technology implementation. So any design constraints that are dependent on the underlying technology should generally be stored with whatever tool it is that allows one to implement the logic description in that technology. Use that as your criteria for deciding whether or not to define a constraint in the VHDL source code or elsewhere. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Buzzer Date: Thu, 18 Nov 2010 19:27:24 -0800 (PST) Organization: http://groups.google.com Lines: 62 Message-ID: References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290137245 17539 127.0.0.1 (19 Nov 2010 03:27:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 03:27:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4399 On Nov 18, 6:18=A0pm, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I've got a buzzer which is basically an output of my entity. Say this > is buzzer BUZ: out std_logic. > > Then, I want to put BUZ to 1 for just some very small amount of > time. I then tried > > =3D=3D > BUZ <=3D '1'; > BUZ <=3D '0' after 500 ns; > =3D=3D > > but it is apparently not appreciated from my compiler's point of view, > which complains about tristate problems, etc. > If you're simply trying to simulate this (but I don't think you are), then the solution is to put the statements into a process process(BUZ) begin BUZ <=3D '1' after 1 ns; -- Must want it to be there for *some* time BUZ <=3D '0' after 500 ns; end process; But since you say the complaint is about tristate problems, then I suspect the complaining compiler is a sysnthesis tool which means that you have a few problems: 1. You can't have more than one process or more than one concurrent statement driving any signal (almost without exception). 2. The main exception is I/O pins of the device which generally have tristate control. But you haven't specified any tri-state control. 3. 'after xxx ns' is not synthesizable in today's typical logic devices since those devinces don't have delay lines. This may change in the future, but as of now, there are no delay lines so there is no way to synthesize 'after 500 ns' so it will be ignored. Kevin Jennings > Is there a simple solution to it? > > Thanks. > > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > If you want to judge a man's character, give him power. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzltDQACgkQM0LLzLt8Mhxw0wCgpniL+PeT7FMkbEXnSHQmMhiQ > jVEAnRS31MQHeCe++BSxwGBPZ1/CRTUB > =3DfMgN > -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:43 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!news.glorb.com!news2.glorb.com!postnews.google.com!f9g2000vbf.googlegroups.com!not-for-mail From: dgreig Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment Date: Fri, 19 Nov 2010 01:32:50 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 84.19.254.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290159171 22482 127.0.0.1 (19 Nov 2010 09:32:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 09:32:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f9g2000vbf.googlegroups.com; posting-host=84.19.254.82; posting-account=jWYCGAoAAACtdbpYfrlZ1GVzvYP1FIDc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4401 On Nov 18, 1:03=A0pm, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I'm using an entity `sorter', that I define using > > =3D=3D > entity sorter is > port( > =A0 =A0 =A0 =A0 CLK: in std_logic; > =A0 =A0 =A0 =A0 BTN_on: in std_logic; > =A0 =A0 =A0 =A0 LED_size: out std_logic; > ); > > attribute pin_numbers of sorter: entity is > "CLK:1 BTN_on:2 LED_size:14"; > > end sorter; > =3D=3D > > However, ispLEVER gives me `Reference to unknown attribute definition > pin_numbers'. What am I doing wrong? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > If you fake it, you can't make it. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzlFiUACgkQM0LLzLt8MhzkfgCfZvxK09E4kSF2TmtZJ4OG/Vjc > LmEAn1/BfmjFjae2oE7UIqZPLmctfG/e > =3D4xSL > -----END PGP SIGNATURE----- Try the predefined '93 "chip_pin". The synthesis tool may or may not support it however. I hate to admit knowing this one.. DG From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i17g2000vbq.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Delaying signal assignment Date: Fri, 19 Nov 2010 02:38:36 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290163116 21814 127.0.0.1 (19 Nov 2010 10:38:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 10:38:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i17g2000vbq.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4402 How can I delay a signal in the following manner ? signal clk : std_logic; signal sig : std_logic; process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; Now I want "sig" to be High for 50us, after that it should be assigned the value of clk. The following approach does not work: sig <= '1', clk after 50 us; Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Buzzer Date: Fri, 19 Nov 2010 07:12:55 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <501b7dfe-6682-42bd-aa19-f365e130e325@j25g2000yqa.googlegroups.com> References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290179575 2760 127.0.0.1 (19 Nov 2010 15:12:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:12:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4403 To be more specific on #3, you will need a clock signal, and a circuit that counts out the number of clock cycles needed to keep the signal on. You will need much longer than 500 ns for a human to hear a buzzer. Try something on the order of 100 ms or more. Andy From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Fri, 19 Nov 2010 07:25:49 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290180349 20597 127.0.0.1 (19 Nov 2010 15:25:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:25:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4404 On Nov 19, 4:38=A0am, hssig wrote: > How can I delay a signal in the following manner ? > > signal clk : std_logic; > signal sig : std_logic; > > process > begin > =A0 =A0clk <=3D '1'; wait for 10 ns; > =A0 =A0clk <=3D '0'; wait for 10 ns; > end process; > > Now I want "sig" to be High for 50us, after that it should be assigned > the value of clk. > > The following approach does not work: > sig <=3D '1', clk after 50 us; > > Cheers, hssig signal enable : boolean :=3D false; signal clk : std_logic :=3D '0'; signal sig : std_logic :=3D '1'; enable <=3D true after 50 us; clk <=3D not clk after 10 ns; sig <=3D clk when enable, else '1'; Andy From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Fri, 19 Nov 2010 07:54:05 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <176dcd2e-05ce-4ec9-97ff-44968eabf5b9@d8g2000yqf.googlegroups.com> References: NNTP-Posting-Host: 69.255.126.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290182045 24198 127.0.0.1 (19 Nov 2010 15:54:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:54:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=69.255.126.158; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4405 On Nov 19, 5:38=A0am, hssig wrote: > How can I delay a signal in the following manner ? > > signal clk : std_logic; > signal sig : std_logic; > > process > begin > =A0 =A0clk <=3D '1'; wait for 10 ns; > =A0 =A0clk <=3D '0'; wait for 10 ns; > end process; > > Now I want "sig" to be High for 50us, after that it should be assigned > the value of clk. > > The following approach does not work: > sig <=3D '1', clk after 50 us; > > Cheers, hssig 50us <=3D '1', '0' after 50 us; sig <=3D clk or 50us; Isn't that easy? Don't make things too hard by thinking about them too much... Rick From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nuzba.szn.dk!news.szn.dk!pnx.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> <8a05ab91-79aa-45dc-ac19-e1529340296b@c39g2000yqi.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 20:08:15 +0100 Message-ID: <87hbfdp1wg.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:+nQWbe8PixkZNsd5j/SkznDO3/A= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 69 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=PETUXC[NbcGB^D;0lZCOUDYSB=nbEKnkK3LlDMZ4XbVIZEVG4AK_]RP;@H2oNO>`Ol[NBH>DVH8HSaRLafM]ES=S;40D?B X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4406 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 KJ writes: > On Nov 18, 7:03 am, Merciadri Luca > wrote: > >> attribute pin_numbers of sorter: entity is >> "CLK:1 BTN_on:2 LED_size:14"; > >> However, ispLEVER gives me `Reference to unknown attribute definition >> pin_numbers'. What am I doing wrong? >> > > Before you can use an attribute, first you must define what that > attribute is in the first place. The attribute 'pin_numbers' is not a > pre-defined VHDL language attribute, it is a user defined > attribute...so you as the user need to define it. In your case, the > following statement is needed prior to your use of the attribute > statement that you have above. > > attribute pin_numbers: STRING; > > It is also likely that there is some Lattice specific library that has > this attribute definition included that you could get access to with a > 'use' statement. > > use work.xxx.all; -- Where xxx is the name of the Lattice lib > > Lastly, although you may have no intention of ever porting your design > to any other device, it is generally not a good idea to embed pin > definitions in the source code. If you DO end up moving to a > different device (maybe from QFP to BGA as an example, or a bigger > part) then those pin definitions in the source code are useless...and > in the way now because they are in the source code. Using attributes > is also tool dependent (if you move the code from say Lattice to > Altera, Xilinx, etc.) and the tools that you use will usually give you > an easier way to enter the pin info. Since you will need to archive > the synthesis tool files anyway there is no reason that the pin number > information can't be kept there also. You will likely have other > constraints archived there such as timing constraints so there is no > reason why pin number constraints can't be there also. > > Think of it this way, the VHDL you write is intended to define a logic > description. A logic description does not inherently require any > specific technology implementation. So any design constraints that > are dependent on the underlying technology should generally be stored > with whatever tool it is that allows one to implement the logic > description in that technology. Use that as your criteria for > deciding whether or not to define a constraint in the VHDL source code > or elsewhere. Thanks for your answers. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Give a man a fish and you feed him for a day; teach a man to fish and you feed him for a lifetime. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzmyx8ACgkQM0LLzLt8MhyMlQCfRN5kB/3wXgO+yt93aLVvLNas R5UAn2Er2OSaljdy9iu0GvXP1El2RSKu =igyf -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!nuzba.szn.dk!news.szn.dk!pnx.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Buzzer References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 20:08:24 +0100 Message-ID: <87d3q1p1w7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:tz8thdwv2AhyLOfCc/Z2NgeT74U= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 39 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=PETUXC[NbcW0Sc_VCmP]hZYSB=nbEKnk[3LlDMZ4XbVYZEVG4QK_]RP;@H2o^O>`Ol[NBH>TVH8HSaRLaf]]ES=S;40D?R X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4407 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Merciadri Luca writes: > Hi, > > I've got a buzzer which is basically an output of my entity. Say this > is buzzer BUZ: out std_logic. > > Then, I want to put BUZ to 1 for just some very small amount of > time. I then tried > > == > BUZ <= '1'; > BUZ <= '0' after 500 ns; > == > > but it is apparently not appreciated from my compiler's point of view, > which complains about tristate problems, etc. > > Is there a simple solution to it? > > Thanks. Thanks all. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- If it's worth doing, it's worth over-doing. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzmyygACgkQM0LLzLt8MhyTrACgi7XWHu46WShb6RDnbFnMfxnQ E9QAn28KM4/qcIkIq8sWcDFT/pKHOy2p =eD7k -----END PGP SIGNATURE----- From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q14g2000yqe.googlegroups.com!not-for-mail From: Analog_Guy Newsgroups: comp.lang.vhdl Subject: Multiple Reset Inputs Date: Fri, 19 Nov 2010 23:09:30 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 24.150.100.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290236971 16912 127.0.0.1 (20 Nov 2010 07:09:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Nov 2010 07:09:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q14g2000yqe.googlegroups.com; posting-host=24.150.100.145; posting-account=UWE3jQkAAABcpV79MLIdWDGzI1XYb0Ot User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4408 I generally implement resets with asynchronous assertion and synchronous de-assertion. With a single reset, this is simple. However, what happens if there are multiple reset inputs but I only want one internal reset? I was always under the impression that one should not have any combinational logic in the asynchronous reset path, as it could lead to static hazards (and reset glitches). So, how do you combine two resets into one without using combinational logic somewhere? I was thinking of two scenarios: 1. AND the two resets coming into the FPGA, and connect to the asynchronous reset of a synchronizer. The output of the synchronizer is the single internal reset. 2. Individually synchronize the two resets coming into the FPGA (note that each reset input feeds the asynchronous reset of the synchronizer). AND the output of each of the synchronizers and feed this single signal into the asynchronous reset of a final flip-flop. The output of this flip-flop is the single internal reset. In both cases we achieve asynchronous assertion and synchronous de- assertion ... however, in both cases there is combinational logic in the asynchronous reset path. Any suggestions how these multiple resets should be combined? From newsfish@newsfish Fri Dec 24 22:55:44 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Sat, 20 Nov 2010 11:08:54 -0800 (PST) Organization: http://groups.google.com Lines: 51 Message-ID: <50dff447-aa6d-46ef-955d-551e5ca08ced@j25g2000yqa.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290280134 31303 127.0.0.1 (20 Nov 2010 19:08:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Nov 2010 19:08:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4409 On Nov 20, 2:09=A0am, Analog_Guy wrote: > I was always under the impression that one should not have any > combinational logic in the asynchronous reset path, as it could lead > to static hazards (and reset glitches). =A0 That would be the situation if you're trying to *avoid* resetting something because of a transient condition. An example would be if you're supposed to reset something when you've decoded a particular processor address. Simple combinatorial logic then might inadvertantly generate a reset pulse that is not wanted because of transient conditions on the address bus, propagation delays through logic paths, etc. > So, how do you combine two > resets into one without using combinational logic somewhere? > By or-ing them together. > I was thinking of two scenarios: > 1. AND the two resets coming into the FPGA, and connect to the > asynchronous reset of a synchronizer. =A0The output of the synchronizer > is the single internal reset. I think you mean 'or', not 'and'. But other than that, what you've described would be correct. > 2. Individually synchronize the two resets coming into the FPGA (note > that each reset input feeds the asynchronous reset of the > synchronizer). =A0AND the output of each of the synchronizers and feed > this single signal into the asynchronous reset of a final flip-flop. > The output of this flip-flop is the single internal reset. > Again, except for saying 'and' rather than 'or', what you've descirved would work here also. It would consume more resources, but it would work, no better, no worse than #1. > In both cases we achieve asynchronous assertion and synchronous de- > assertion ... however, in both cases there is combinational logic in > the asynchronous reset path. > But that combinatorial logic that you're talking about is not a problem because in this situation you're not trying to prevent a false logic reset from happening. It's good to question things one has 'always done' every now and then to refresh yourself on fundamentally why you do such things. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Sun, 21 Nov 2010 03:00:27 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: References: NNTP-Posting-Host: 91.84.86.43 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290337227 20870 127.0.0.1 (21 Nov 2010 11:00:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 21 Nov 2010 11:00:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=91.84.86.43; posting-account=yEeedQoAAAAW-TdoIYHIZrGsurykmF2S User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10_5_8; en-us) AppleWebKit/533.19.4 (KHTML, like Gecko) Version/5.0.3 Safari/533.19.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4410 On 19 Nov, 10:38, hssig wrote: > The following approach does not work: > sig <= '1', clk after 50 us; Try:- sig <= transport '1', clk after 50 us; (this instructs the simulator to model sig as a transmission line) From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: makeuptest Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Procedures and Registers Date: Sun, 21 Nov 2010 19:34:19 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290396859 4376 127.0.0.1 (22 Nov 2010 03:34:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 03:34:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=71.176.145.26; posting-account=X05sxgoAAADHzx4d_Xru0yHmZ5OQFj6h User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4411 comp.arch.fpga:13297 I was writing some code and decided to make it a procedure to put in a library. I have written functions many times, but not a procedure. This was a routine for some registers and counters internal to the procedure and so required a clock and reset. I couldn't figure out how to wirte it so that it would be inside a clocked process, so I added the clock and reset to the inputs and put the clocking code within the procedure. That was all well and good. But when I tried to test it, none of the internal variables that should have created registers were being remembered. I ran a simulation and the variables were getting reset initially, but on the next entry to the procedure they were back to being undefined. Do I have a basic misunderstanding about how procedures operate? I haven't found a good reference to explain enough to figure out what I am doing wrong. Greg From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Sun, 21 Nov 2010 21:00:49 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290402049 26978 127.0.0.1 (22 Nov 2010 05:00:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 05:00:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4412 comp.arch.fpga:13299 On Nov 21, 10:34=A0pm, makeuptest wrote: > > That was all well and good. =A0But when I tried to test it, none of the > internal variables that should have created registers were being > remembered. =A0I ran a simulation and the variables were getting reset > initially, but on the next entry to the procedure they were back to > being undefined. > Procedures do not inherently 'remember' the values of internal variables or signals as you would have in a process. Instead you must make the signal available on the interface of the procedure and hook up a real signal to that port. This generally means that you must actually add two signals to the interface of the procedure: one is an 'input' to the procedure which represents the current state of the signal; the other is an 'output' of the procedure which represent the next state of the signal. > Do I have a basic misunderstanding about how procedures operate? Yes...you can't hide signals within a procedure. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!s16g2000yqc.googlegroups.com!not-for-mail From: makeuptest Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Mon, 22 Nov 2010 14:27:34 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290464854 15806 127.0.0.1 (22 Nov 2010 22:27:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 22:27:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s16g2000yqc.googlegroups.com; posting-host=71.176.145.26; posting-account=X05sxgoAAADHzx4d_Xru0yHmZ5OQFj6h User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4413 comp.arch.fpga:13312 On Nov 22, 12:00=A0am, KJ wrote: > On Nov 21, 10:34=A0pm, makeuptest wrote: > > > > > That was all well and good. =A0But when I tried to test it, none of the > > internal variables that should have created registers were being > > remembered. =A0I ran a simulation and the variables were getting reset > > initially, but on the next entry to the procedure they were back to > > being undefined. > > Procedures do not inherently 'remember' the values of internal > variables or signals as you would have in a process. =A0Instead you must > make the signal available on the interface of the procedure and hook > up a real signal to that port. > > This generally means that you must actually add two signals to the > interface of the procedure: =A0one is an 'input' to the procedure which > represents the current state of the signal; the other is an 'output' > of the procedure which represent the next state of the signal. > > > Do I have a basic misunderstanding about how procedures operate? > > Yes...you can't hide signals within a procedure. > > Kevin Jennings Yes, I finally found a reference that says variables won't retain their values between invocations in a procedure. I guess that is different from a process, but now that I think about it, that only makes sense. In order to have a register created, the process would have to pass the value out and back in. Thanks From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Mon, 22 Nov 2010 23:17:35 -0800 Lines: 11 Message-ID: <8l184fF1f2U1@mid.individual.net> References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net JHfqs4AS7aThtMLvpLwU2gDsqIiKYIOAhqJdeP8yY9cfeDtXJd Cancel-Lock: sha1:6Y6Xh/dxb79nJbWrReJq2ejmX2M= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4414 comp.arch.fpga:13319 On 11/22/2010 2:27 PM, makeuptest wrote: > In order to have a register created, the process would > have to pass the value out and back in. > For example, see the procedure "retime" here: http://mysite.ncnetwork.net/reszotzl/rise_count.vhd -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!noc.nerim.net!nerim.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!k38g2000vbc.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Tue, 23 Nov 2010 02:45:55 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290509155 7184 127.0.0.1 (23 Nov 2010 10:45:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 23 Nov 2010 10:45:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k38g2000vbc.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4415 >Don't make things too hard by thinking about them >too much... True point. Thank you for your suggestions. Cheers, hssig From newsfish@newsfish Fri Dec 24 22:55:45 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u3g2000vbj.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Purpose of a string variable in a FSM process Date: Mon, 29 Nov 2010 05:01:51 -0800 (PST) Organization: http://groups.google.com Lines: 55 Message-ID: NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291035711 16398 127.0.0.1 (29 Nov 2010 13:01:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Nov 2010 13:01:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbj.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.41 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4418 Hello, I am working with Xilinx tools and have troubles understanding the purpose of a string variable init_fsm_name in the FSM process posted below (snipped). The code below was generated by Xilinx Core Generator. I guess it must be related to simulation, but simulation tools can already extract the name from the FSM state init_state_r. I would be grateful for shedding a light regarding this question. [code] process (pma_reset_done_i, init_fsm_wait_lock_check, lock_r, pcs_reset_done_i, wait_pcs_done_i, pcs_error_r1,wait_ready_done_i, pcs_error_count_done_i,init_state_r) variable init_fsm_name : string(1 to 25); begin case init_state_r is when C_RESET => init_next_state_r <= C_PMA_RESET; init_fsm_name := ExtendString("C_RESET", 25); when C_PMA_RESET => if (pma_reset_done_i = '1') then init_next_state_r <= C_WAIT_LOCK; else init_next_state_r <= C_PMA_RESET; end if; init_fsm_name := ExtendString("C_PMA_RESET", 25); when C_WAIT_LOCK => if(init_fsm_wait_lock_check = '1') then init_next_state_r <= C_PCS_RESET; else init_next_state_r <= C_WAIT_LOCK; end if; init_fsm_name := ExtendString("C_WAIT_LOCK", 25); -- some cases removed when others => init_next_state_r <= C_RESET; init_fsm_name := ExtendString("C_RESET", 25); end case; end process; [/code] From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Synthesis Only Date: Mon, 29 Nov 2010 12:52:45 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291063965 22306 127.0.0.1 (29 Nov 2010 20:52:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Nov 2010 20:52:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4419 I'm trying to work around a bug in iSim where types with the enum_encoding attribute set such that they're one-hot encoded gives different results than in synthesis - essentially there's an off-by- one error in this case in the simulation for initialization. I've informed Xilinx, though the person handling the webcase seemed quite uninterested and so I have little faith it'll be fixed any time soon. I'm having trouble coming up with an acceptable work around. Take the following example: PROCESS( CLK ) TYPE TestType IS ( A, B, C ); ATTRIBUTE enum_encoding : string; ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; VARIABLE Test : TestType := A; BEGIN ... END PROCESS; XST results in Test having an initial value of A, and in iSim the initial value is B (if I had assigned B, XST would use B, and iSim would use C). The only way I've found to work around this is to use a function as follows: FUNCTION KludgeInit RETURN TestType IS VARIABLE IsSynth : BOOLEAN := TRUE; BEGIN -- pragma synthesis_off IsSynth := FALSE; -- pragma synthesis_on IF IsSynth THEN RETURN B; ELSE RETURN A; END IF; END KludgeInit; Of course, TestType must be declared B, A, C - there's no way to get at the first item in the list due to the error (using the last item causes iSim to crash.) This is horrific. Is there no way for me to disable enum_encoding entirely during simulation? Is there nothing like: -- pragma simulation_off ... -- pragma simulation_on From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!p11g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Mon, 29 Nov 2010 22:15:41 -0800 (PST) Organization: http://groups.google.com Lines: 62 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291097741 23184 127.0.0.1 (30 Nov 2010 06:15:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 06:15:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000vbn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4420 On Nov 29, 3:52=A0pm, Jonathan Ross wrote: > I'm trying to work around a bug in iSim where types with the > enum_encoding attribute set such that they're one-hot encoded gives > different results than in synthesis - essentially there's an off-by- > one error in this case in the simulation for initialization. Just noting here that simulation doesn't give a hoot about the enum_encoding attributes. > I've > informed Xilinx, though the person handling the webcase seemed quite > uninterested and so I have little faith it'll be fixed any time soon. > I'm having trouble coming up with an acceptable work around. Take the > following example: > > PROCESS( CLK ) > =A0 =A0 TYPE TestType IS ( A, B, C ); > =A0 =A0 ATTRIBUTE enum_encoding : string; > =A0 =A0 ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; > =A0 =A0 VARIABLE Test : TestType :=3D A; > BEGIN > =A0 =A0... > END PROCESS; > > XST results in Test having an initial value of A, This is correct... > and in iSim the > initial value is B A few possibilities come to mine: - iSim may be wrong - You've missed a synthesis warning/note that said something to the effect that the encoding of Test is not the same as what you've put into the 'enum_encoding' attribute. - It could be that you're misinterpreting which nodes are which. Presumably 'Test' gets synthesized as actual signals Test(2-0), so when you say "100" for 'A', is Test(2) =3D '1' or is Test(0)? How do you know this to be true? Check the synthesis notes for confirmation. - From your snippet, one can't tell if Test will result in flops or not. If they are not the outputs of flip flops, then 'Test' might get combined with other combinatorial logic in your design but still get assigned the name 'Test' and you're interpreting that node to be the same thing as listed in your source code. Assign an output signal of the top level of the design to 'Test' and see what really pops out. > > This is horrific. Is there no way for me to disable enum_encoding > entirely during simulation? Is there nothing like: > > -- pragma simulation_off > ... > -- pragma simulation_on Any time you try to make simulation different from synthesis you're starting down a bad path. The likely cause is probably listed above. Peruse the synthesis warnings, make 'Test' temporarily be an output of the design if you have to in order to debug and trudge forward. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Purpose of a string variable in a FSM process Date: Tue, 30 Nov 2010 08:41:12 -0800 Lines: 28 Message-ID: <8lknp7Fg7tU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net MpzK8IHdFivEILtoDHhioQyh0LwlkE97X1sJ/86GQUXAKsKSvs Cancel-Lock: sha1:dzQdd+FBwi3mb4rmJRMN9Bc+ugQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4422 On 11/29/2010 5:01 AM, a s wrote: > I am working with Xilinx tools and have troubles understanding the > purpose of a string variable init_fsm_name in the FSM process posted below > The code below was generated by Xilinx Core Generator. > I guess it must be related to simulation, but simulation tools can > already extract the name from the FSM state init_state_r. > I would be grateful for shedding a light regarding this question. If I write my own synthesis code, I can use the same vhdl or verilog code directly for synthesis or as a simulation model. If I use a vendor core, no such vhdl source is provided. Vendor core generators collect parameter strings from me to generate a vendor-specific netlist for synthesis and a vhdl (or verilog) simulation model based on my entered parameters. Note that my synthesis input is a collection of strings, not code. Your code example is probably part of such a simulation model. I don't spend any time analyzing such code because: 1. It is not safe to touch it because I don't have the core source, and 2. If provides little useful information on how equivalent synthesis code might be written. If I were a fpga vendor, I might want my generated models to work well enough to test the core without revealing the design to the user. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!u3g2000vbj.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Tue, 30 Nov 2010 10:41:59 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: <6c324eaa-475e-40fb-a0a4-69f0efffe63a@u3g2000vbj.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 188.28.151.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291142519 1351 127.0.0.1 (30 Nov 2010 18:41:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 18:41:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbj.googlegroups.com; posting-host=188.28.151.15; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4423 remember the two flip flop rule one for async to sync, and one to leave one propergation interval for what? seems almost silly! maybe its a feedback reset reduction fan out technique. From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!c17g2000prm.googlegroups.com!not-for-mail From: Swapnajit Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Do you have a separate Verification team? Date: Tue, 30 Nov 2010 12:11:32 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 12.35.78.5 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291147893 25187 127.0.0.1 (30 Nov 2010 20:11:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 20:11:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c17g2000prm.googlegroups.com; posting-host=12.35.78.5; posting-account=bDLsBQkAAAB3tCuLYhxyPevTa4ZY2yB2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; OfficeLiveConnector.1.3; OfficeLivePatch.0.0; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:2696 comp.lang.vhdl:4424 Request for participation: I started an online poll on this basic question as it is fundamental to verification management. Your participation is requested. Here is the link: polls.linkedin.com/p/111235/fmnat Thanks. From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!29g2000yqq.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Re: Purpose of a string variable in a FSM process Date: Tue, 30 Nov 2010 23:21:18 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: <4bbe0455-c90f-43b9-abea-e845ee410f72@29g2000yqq.googlegroups.com> References: <8lknp7Fg7tU1@mid.individual.net> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291188078 22854 127.0.0.1 (1 Dec 2010 07:21:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 07:21:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000yqq.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.41 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4425 On Nov 30, 5:41=A0pm, Mike Treseler wrote: > On 11/29/2010 5:01 AM, a s wrote: > > > I am working with Xilinx tools and have troubles understanding the > > purpose of a string variable init_fsm_name in the FSM process posted be= low > > The code below was generated by Xilinx Core Generator. > > I guess it must be related to simulation, but simulation tools can > > already extract the name from the FSM state init_state_r. > > I would be grateful for shedding a light regarding this question. > > If I write my own synthesis code, I can use the same vhdl or verilog > code directly for synthesis or as a simulation model. If I use a vendor > core, no such vhdl source is provided. Vendor core generators collect > parameter strings from me to generate a vendor-specific netlist for > synthesis and a vhdl (or verilog) simulation model based on my entered > parameters. > Note that my synthesis input is a collection of strings, not code. > > Your code example is probably part of such a simulation model. > I don't spend any time analyzing such code because: > 1. It is not safe to touch it because I don't have the core source, and > 2. If provides little useful information on how equivalent synthesis > code might be written. > > If I were a fpga vendor, I might want my generated models to > work well enough to test the core without revealing the design > to the user. Mike, thanks for the input. I completely agree that one should not modify the code generated with a "wizard". I am just trying to understand the purpose of that code as I am still learning VHDL. BTW, the code sample is taken from the code which is responsible for initialization of RocketIO in Virtex4, but I have seen similar constructs in other Xilinx "wizard" generated code. From newsfish@newsfish Fri Dec 24 22:55:46 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!a17g2000yql.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: CONFUSED WITH NUMBERS Date: Wed, 1 Dec 2010 08:27:20 -0800 (PST) Organization: http://groups.google.com Lines: 13 Message-ID: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> NNTP-Posting-Host: 93.173.6.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291220841 14327 127.0.0.1 (1 Dec 2010 16:27:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 16:27:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a17g2000yql.googlegroups.com; posting-host=93.173.6.39; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4426 Hi all Numbers confuse me in VHDL . For example when a in port receives data from an Analog To Digital converter that represents fractions numbers smaller then one like +0.54 or - 0.33 . In that case how do I define that in port I gues i will use the NUMERIC_STD package . Please clarift the subject for me and all newbees to VHDL . Thanks EC From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 01 Dec 2010 11:42:24 -0600 Date: Wed, 01 Dec 2010 09:42:25 -0800 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> In-Reply-To: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> Lines: 75 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-JNAH7WKnoazRKULmCtVKkIHXVURq1sypc6jKo4JZE+Nybhj5tlk0zsPhJ4q63j7jT7KBMsgM7Jf0lzE!k3hbShl+HVdSsfUcM1kvgXRl5Qnzu+gLlWaNDG1D+Q/iQVMQ5yFiUU1+Gn06iNfPTs8TNZ2W08nx!Bg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4932 Xref: feeder.eternal-september.org comp.lang.vhdl:4427 On 12/1/2010 8:27 AM, TheRightInfo wrote: > Hi all > Numbers confuse me in VHDL . > For example when a in port receives data from an Analog To Digital > converter that represents fractions numbers smaller then > one like +0.54 or - 0.33 . > > In that case how do I define that in port I gues i will use the > NUMERIC_STD package . > > Please clarift the subject for me and all newbees to VHDL . > > Thanks > EC A port connected to an analog to digital converter receives bits. 1's and 0's. Sometimes parallel, sometimes serially, sometimes a combination of the two. And, as it's connected to external hardware, you'll have the best luck doing that connection using std_logic and std_logic_vector. Now you've got bits, and it's your job to come up with an interpretation of them. Typically, you'd represent that as either a SIGNED or an UNSIGNED, based on whether the ADC is bipolar or unipolar. It's possible that the ADC is bipolar (SIGNED) but outputs it's information not in two's compliment but in what's known as offset binary (0 = -fullscale, '1' followed by all '0's = 0, all '1' = +fullscale), in which case you'd want to invert the MSB in order to have a normal, two's compliment SIGNED number. You could also use the native integer type for this instead of a NUMERIC_STD, in which case you'd want to use a bounded one, i.e. x : integer range 0 to 4095. This will simulate ever so marginally faster, simplify some tasks, and complicate some others. So now you've got an entity. That entity's job is to look on one side like an interface full of std_logic* types to talk to the physical ADC, and on the other to be one of the NUMERIC_STD types along with whatever control signals the rest of your design needs. The left side talks to the physical layer, the right side provides semi-abstracted data. Designing the contents of that entity required you to become fairly familiar with the data sheet of the specific ADC in question, but you now get to leave the knowledge of the specific interface details inside that box, flush your brain cache, bring that entity in as a component of your larger design, and concentrate on what you wish to do with the data rather than how you got it. Whether you've chosen to work with NUMERIC_STD types or integers, you're now holding data that you've declared to represent integer numbers. These numbers map linearly onto the voltage applied at the input of the ADC. For instance, a 12-bit unipolar ADC with a 4.096V input range. In this case, you've got one of the following: x : unsigned(11 downto 0); x : integer range 0 to 4095; In either case, 1 LSB (least significant bit) corresponds to 1 mV on the input. Keeping track of this is your responsibility, the tools have no help to offer you. So it's your job to know that 10 (16#00A#) means 10 mV. This is where comments are your friend. If the numbers only matter to you relative to full scale, the fundamental relationship is, in this case, value = x / 4096. Notice that, as x can never exceed 4095, you now have a fractional value between 0 and 0.99976. This, once again, has to be kept track of by you. It's theoretically possible to use the VHDL2008 fixed point package for this instead; practically the tool support for doing so is pretty abysmal and you'll most likely just get yourself in trouble. Thus concludes the answer to your question. Now, in exchange for this lesson, please turn on the damn spell check for whatever method it is you're using to throw questions out to the Internet. It's like reading a train crash in a blender. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS Date: Wed, 1 Dec 2010 09:53:41 -0800 (PST) Organization: http://groups.google.com Lines: 81 Message-ID: <4cdd5f67-1f3d-4430-bee6-6f374fd6a271@30g2000yql.googlegroups.com> References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> NNTP-Posting-Host: 93.172.170.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291226021 31925 127.0.0.1 (1 Dec 2010 17:53:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 17:53:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=93.172.170.107; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4428 On Dec 1, 7:42=A0pm, Rob Gaddi wrote: > On 12/1/2010 8:27 AM, TheRightInfo wrote: > > > Hi all > > Numbers confuse me in VHDL . > > For example when a in port receives data from an Analog To Digital > > converter that represents fractions numbers smaller then > > one like +0.54 or - 0.33 . > > > In that case how do I define that in port I gues i will use the > > NUMERIC_STD package . > > > Please clarift the subject for me and all newbees to VHDL . > > > Thanks > > EC > > A port connected to an analog to digital converter receives bits. =A01's > and 0's. =A0Sometimes parallel, sometimes serially, sometimes a > combination of the two. =A0And, as it's connected to external hardware, > you'll have the best luck doing that connection using std_logic and > std_logic_vector. > > Now you've got bits, and it's your job to come up with an interpretation > of them. =A0Typically, you'd represent that as either a SIGNED or an > UNSIGNED, based on whether the ADC is bipolar or unipolar. =A0It's > possible that the ADC is bipolar (SIGNED) but outputs it's information > not in two's compliment but in what's known as offset binary (0 =3D > -fullscale, '1' followed by all '0's =3D 0, all '1' =3D +fullscale), in > which case you'd want to invert the MSB in order to have a normal, two's > compliment SIGNED number. =A0You could also use the native integer type > for this instead of a NUMERIC_STD, in which case you'd want to use a > bounded one, i.e. x : integer range 0 to 4095. =A0This will simulate ever > so marginally faster, simplify some tasks, and complicate some others. > > So now you've got an entity. =A0That entity's job is to look on one side > like an interface full of std_logic* types to talk to the physical ADC, > and on the other to be one of the NUMERIC_STD types along with whatever > control signals the rest of your design needs. =A0The left side talks to > the physical layer, the right side provides semi-abstracted data. > > Designing the contents of that entity required you to become fairly > familiar with the data sheet of the specific ADC in question, but you > now get to leave the knowledge of the specific interface details inside > that box, flush your brain cache, bring that entity in as a component of > your larger design, and concentrate on what you wish to do with the data > rather than how you got it. > > Whether you've chosen to work with NUMERIC_STD types or integers, you're > now holding data that you've declared to represent integer numbers. > These numbers map linearly onto the voltage applied at the input of the > ADC. =A0For instance, a 12-bit unipolar ADC with a 4.096V input range. = =A0In > this case, you've got one of the following: > =A0 =A0 =A0 =A0 x : unsigned(11 downto 0); > =A0 =A0 =A0 =A0 x : integer range 0 to 4095; > > In either case, 1 LSB (least significant bit) corresponds to 1 mV on the > input. =A0Keeping track of this is your responsibility, the tools have no > help to offer you. =A0So it's your job to know that 10 (16#00A#) means 10 > mV. =A0This is where comments are your friend. > > If the numbers only matter to you relative to full scale, the > fundamental relationship is, in this case, value =3D x / 4096. =A0Notice > that, as x can never exceed 4095, you now have a fractional value > between 0 and 0.99976. =A0This, once again, has to be kept track of by > you. =A0It's theoretically possible to use the VHDL2008 fixed point > package for this instead; practically the tool support for doing so is > pretty abysmal and you'll most likely just get yourself in trouble. > > Thus concludes the answer to your question. =A0Now, in exchange for this > lesson, please turn on the damn spell check for whatever method it is > you're using to throw questions out to the Internet. =A0It's like reading > a train crash in a blender. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Many Many Thanks EC From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Thu, 2 Dec 2010 10:59:58 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <5595c317-30c2-46d5-9836-f905fe1c6315@r29g2000yqj.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> <6c324eaa-475e-40fb-a0a4-69f0efffe63a@u3g2000vbj.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291316398 20918 127.0.0.1 (2 Dec 2010 18:59:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Dec 2010 18:59:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4429 On Nov 30, 12:41=A0pm, jacko wrote: > remember the two flip flop rule one for async to sync, and one to > leave one propergation interval for what? seems almost silly! maybe > its a feedback reset reduction fan out technique. The 2nd flop is to reject a potential metastable pulse from the 1st synchronizing flop. It is not necessary if the destination is another flop on the same or related clock, and you have sufficiently extra timing margin to get there (a few extra nanoseconds will buy an eon in MTBF in most FPGAs). Andy From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j29g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS Date: Thu, 2 Dec 2010 11:06:34 -0800 (PST) Organization: http://groups.google.com Lines: 110 Message-ID: <1f34187c-f118-4a9e-8582-464b755aeecb@j29g2000yqm.googlegroups.com> References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> <4cdd5f67-1f3d-4430-bee6-6f374fd6a271@30g2000yql.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291316794 25201 127.0.0.1 (2 Dec 2010 19:06:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Dec 2010 19:06:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j29g2000yqm.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4430 On Dec 1, 11:53=A0am, TheRightInfo wrote: > On Dec 1, 7:42=A0pm, Rob Gaddi wrote: > > > > > > > On 12/1/2010 8:27 AM, TheRightInfo wrote: > > > > Hi all > > > Numbers confuse me in VHDL . > > > For example when a in port receives data from an Analog To Digital > > > converter that represents fractions numbers smaller then > > > one like +0.54 or - 0.33 . > > > > In that case how do I define that in port I gues i will use the > > > NUMERIC_STD package . > > > > Please clarift the subject for me and all newbees to VHDL . > > > > Thanks > > > EC > > > A port connected to an analog to digital converter receives bits. =A01'= s > > and 0's. =A0Sometimes parallel, sometimes serially, sometimes a > > combination of the two. =A0And, as it's connected to external hardware, > > you'll have the best luck doing that connection using std_logic and > > std_logic_vector. > > > Now you've got bits, and it's your job to come up with an interpretatio= n > > of them. =A0Typically, you'd represent that as either a SIGNED or an > > UNSIGNED, based on whether the ADC is bipolar or unipolar. =A0It's > > possible that the ADC is bipolar (SIGNED) but outputs it's information > > not in two's compliment but in what's known as offset binary (0 =3D > > -fullscale, '1' followed by all '0's =3D 0, all '1' =3D +fullscale), in > > which case you'd want to invert the MSB in order to have a normal, two'= s > > compliment SIGNED number. =A0You could also use the native integer type > > for this instead of a NUMERIC_STD, in which case you'd want to use a > > bounded one, i.e. x : integer range 0 to 4095. =A0This will simulate ev= er > > so marginally faster, simplify some tasks, and complicate some others. > > > So now you've got an entity. =A0That entity's job is to look on one sid= e > > like an interface full of std_logic* types to talk to the physical ADC, > > and on the other to be one of the NUMERIC_STD types along with whatever > > control signals the rest of your design needs. =A0The left side talks t= o > > the physical layer, the right side provides semi-abstracted data. > > > Designing the contents of that entity required you to become fairly > > familiar with the data sheet of the specific ADC in question, but you > > now get to leave the knowledge of the specific interface details inside > > that box, flush your brain cache, bring that entity in as a component o= f > > your larger design, and concentrate on what you wish to do with the dat= a > > rather than how you got it. > > > Whether you've chosen to work with NUMERIC_STD types or integers, you'r= e > > now holding data that you've declared to represent integer numbers. > > These numbers map linearly onto the voltage applied at the input of the > > ADC. =A0For instance, a 12-bit unipolar ADC with a 4.096V input range. = =A0In > > this case, you've got one of the following: > > =A0 =A0 =A0 =A0 x : unsigned(11 downto 0); > > =A0 =A0 =A0 =A0 x : integer range 0 to 4095; > > > In either case, 1 LSB (least significant bit) corresponds to 1 mV on th= e > > input. =A0Keeping track of this is your responsibility, the tools have = no > > help to offer you. =A0So it's your job to know that 10 (16#00A#) means = 10 > > mV. =A0This is where comments are your friend. > > > If the numbers only matter to you relative to full scale, the > > fundamental relationship is, in this case, value =3D x / 4096. =A0Notic= e > > that, as x can never exceed 4095, you now have a fractional value > > between 0 and 0.99976. =A0This, once again, has to be kept track of by > > you. =A0It's theoretically possible to use the VHDL2008 fixed point > > package for this instead; practically the tool support for doing so is > > pretty abysmal and you'll most likely just get yourself in trouble. > > > Thus concludes the answer to your question. =A0Now, in exchange for thi= s > > lesson, please turn on the damn spell check for whatever method it is > > you're using to throw questions out to the Internet. =A0It's like readi= ng > > a train crash in a blender. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order > > Many Many Thanks > EC- Hide quoted text - > > - Show quoted text - You should take a look at the new fixed point VHDL packages, for doing fixed point (integer and fractional) arithmetic in synthesizable vhdl. Andy From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!22g2000prx.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: FPGA project structure definition Date: Fri, 3 Dec 2010 04:32:42 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291379563 17937 127.0.0.1 (3 Dec 2010 12:32:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Dec 2010 12:32:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 22g2000prx.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13522 comp.lang.verilog:2703 comp.lang.vhdl:4431 I've written up an (informal) draft proposal for an FPGA project structure that could be easily extended as the project grows and is version control friendly. I'd be grateful for any type of feedback... http://www.saardrimer.com/fpgaproj/ cheers, saar. From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!v19g2000yqa.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Sat, 4 Dec 2010 10:05:00 -0800 (PST) Organization: http://groups.google.com Lines: 79 Message-ID: <8f170397-081e-4631-a211-c422d46f7dea@v19g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291485900 4768 127.0.0.1 (4 Dec 2010 18:05:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 18:05:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqa.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13547 comp.lang.verilog:2705 comp.lang.vhdl:4432 On Dec 3, 7:32=A0am, saar drimer wrote: > I've written up an (informal) draft proposal for an FPGA project > structure that could be easily extended as the project grows and is > version control friendly. I'd be grateful for any type of feedback... > > =A0http://www.saardrimer.com/fpgaproj/ > > cheers, > saar. First some minuta. The figures aren't labeled, so it's hard to target comments for one. The first figure, "The 'flow'", doesn't have a "Build Scripts" as a source file type. I realize you had planned to make a distinction between scripts and source, but our build scripts are checked into our repository under the Philosophy that any checkout should be buildable as is, and we consider them part of our source. Also, testbenches should make mention of Unit Testing in hardware - it's automated and should be part of a mature build cycle. Scoping/ Tapping on the other hand is part of the development process so doesn't necessarily need to be mentioned here. I was in the study phase of implementing an SCons Builder/Scanner for XST/VHDL for my build cycles. Requiring that VHDL files share the entity name would make scanning dramatically easier; as I control our own internal standards I'll make this a requirement, along with configurations and components as well. You might consider requiring that source files fall under a directory with the same name as the library they're in. For example, if the entity Foo was part of library work, and Bar was part of library play, the directory structure look like so: ../Project/sources/hdl/work/Foo.vhd ../Project/sources/hdl/play/Bar.vhd We don't do any Verilog development so I'm not sure how the concept of a library is handled there. Another issue we have is that a lot of our sub-components should be accessible by some engineers, but not all engineers. By writing SCons SConstruct and SConscript files and using BuildBot, the idea was that an engineer could check in their sub-project and the server would initialize a build over the whole project while keeping components isolated to their respective developers. That is - our organizational issue is as follows: each component should have two levels of access - one public for declaration, one private for specification; if a team was designing an Ethernet controller we'd want the entity, component, configurations, behavioral simulations, and packages that define the types needed to interface with it to be available to everyone, while we'd want the implementation structure hidden. This would require a public/private fork of the directory structure under mercurial to accomplish, i.e. ../Project/public/source/hdl/work/Foo.vhd ../Project/private/source/hdl/work/Bar.vhd Then there would be a mercurial repository at Project, and public and private would be sub-repositories. Further, since mercurial allows pre and post hooks for all commands, the plan was to preempt any push to a stable repository on the server with an initiation of Unit Tests across the entire project (sub and sup modules...) that must be passed before it can successfully be pushed. The issue is that some modules will be used in multiple projects. We have yet to figure out the optimal method of doing this. I.E. Project1/submodules/Project3/... Project2/submodules/Project3/... Project3/... Pushes to Project3 should automatically initiate unit testing for Project1 and Project2. I have no clue how to do this effectively and efficiently. Overall though, I like the proposal. If I can make it fit my need for public/private portions of submodules I'll definitely use it. Thanks. ~Jonathan Ross From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sat, 4 Dec 2010 10:57:51 -0800 (PST) Organization: http://groups.google.com Lines: 82 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291489071 2575 127.0.0.1 (4 Dec 2010 18:57:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 18:57:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4433 On Nov 30, 1:15=A0am, KJ wrote: > On Nov 29, 3:52=A0pm, Jonathan Ross > wrote: > > > I'm trying to work around a bug in iSim where types with the > > enum_encoding attribute set such that they're one-hot encoded gives > > different results than in synthesis - essentially there's an off-by- > > one error in this case in the simulation for initialization. > > Just noting here that simulation doesn't give a hoot about the > enum_encoding attributes. > > > > > > > > > > > I've > > informed Xilinx, though the person handling the webcase seemed quite > > uninterested and so I have little faith it'll be fixed any time soon. > > I'm having trouble coming up with an acceptable work around. Take the > > following example: > > > PROCESS( CLK ) > > =A0 =A0 TYPE TestType IS ( A, B, C ); > > =A0 =A0 ATTRIBUTE enum_encoding : string; > > =A0 =A0 ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; > > =A0 =A0 VARIABLE Test : TestType :=3D A; > > BEGIN > > =A0 =A0... > > END PROCESS; > > > XST results in Test having an initial value of A, > > This is correct... > > > and in iSim the > > initial value is B > > A few possibilities come to mine: > - iSim may be wrong > - You've missed a synthesis warning/note that said something to the > effect that the encoding of Test is not the same as what you've put > into the 'enum_encoding' attribute. > - It could be that you're misinterpreting which nodes are which. > Presumably 'Test' gets synthesized as actual signals Test(2-0), so > when you say "100" for 'A', is Test(2) =3D '1' or is Test(0)? =A0How do > you know this to be true? =A0Check the synthesis notes for confirmation. > - From your snippet, one can't tell if Test will result in flops or > not. =A0If they are not the outputs of flip flops, then 'Test' might get > combined with other combinatorial logic in your design but still get > assigned the name 'Test' and you're interpreting that node to be the > same thing as listed in your source code. =A0Assign an output signal of > the top level of the design to 'Test' and see what really pops out. > > > > > This is horrific. Is there no way for me to disable enum_encoding > > entirely during simulation? Is there nothing like: > > > -- pragma simulation_off > > ... > > -- pragma simulation_on > > Any time you try to make simulation different from synthesis you're > starting down a bad path. =A0The likely cause is probably listed above. > Peruse the synthesis warnings, make 'Test' temporarily be an output of > the design if you have to in order to debug and trudge forward. > > Kevin Jennings There was no warning. It's a highly repeatable issue. It probably went undiscovered because it doesn't occur if you set a value during reset - only if you initialize a value. The workaround we finally came up with was to use a function to produce a one-hot encoding for the string argument of enum_encoding. When it doesn't detect simulation it produces a binary encoding instead. From newsfish@newsfish Fri Dec 24 22:55:47 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Concurrent Logic Timing Date: Sat, 4 Dec 2010 14:32:53 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291501973 22282 127.0.0.1 (4 Dec 2010 22:32:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 22:32:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4434 comp.arch.fpga:13551 I suppose this is something that you need to expect, but I just have never come across this before. I have some concurrent logic equations using integers where one input common to two assignments changes and because one gets updated before the other, one is set to a value that is outside the range of the integer and flags an error in simulation. C <= B - A * stuff; D <= A + C; -- A changes and puts D outside of its range until C is updated In the real world, this is not really an issue since all sorts of intermediate states are expected when doing arithmetic. But VHDL doesn't seem to accommodate this well. The only way I can think of to fix this, without changing the logic, is to do these calculations inside a combinatorial process using variables. Then I can control the sequence of updates explicitly. The only other thing I can think is to assign A to A' and use A' in place of A in the assignment for D. That may still allow an error, but if A'' is used, then there will be two delta delays in D assignment path. However, if C grows because A has shrunk, then that could cause the same sort of out of bounds error on D. Is there another way make this work that isn't so cumbersome? Rick From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 23:29:44 +0000 (UTC) Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> Injection-Date: Sat, 4 Dec 2010 23:29:44 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="30122"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/fdpEjHS4AFSfCeehgqV7i" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:ndTzA/eMX3waBinu0mmL9tQOoXI= Xref: feeder.eternal-september.org comp.lang.vhdl:4435 comp.arch.fpga:13552 In comp.arch.fpga rickman wrote: > I suppose this is something that you need to expect, but I just have > never come across this before. I have some concurrent logic equations > using integers where one input common to two assignments changes and > because one gets updated before the other, one is set to a value that > is outside the range of the integer and flags an error in > simulation. > C <= B - A * stuff; > D <= A + C; -- A changes and puts D outside of its range until C is > updated > In the real world, this is not really an issue since all sorts of > intermediate states are expected when doing arithmetic. But VHDL > doesn't seem to accommodate this well. I don't think verilog has this problem, but it might just be because I would do it with reg [32] and not integer. I think you can do something similar to reg [32] in VHDL, and likely avoid the problem. (snip) -- glen From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: VHDL Automated Testing Date: Sat, 4 Dec 2010 16:09:17 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291507757 20309 127.0.0.1 (5 Dec 2010 00:09:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 00:09:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4436 I'm trying to implement an automated testing hardness for a VHDL project. We compile and link with vhpcomp and fuse respectively. 1. The program generated will only run under xtclsh - is there any way to get it to run in bash? 2. The following code generates the following output: PROCESS BEGIN REPORT "Hello World!" SEVERITY NOTE; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY NOTE; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY WARNING; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY ERROR; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY FAILURE; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY NOTE; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY WARNING; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY ERROR; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY FAILURE; WAIT; END PROCESS; ISim> run Simulator is doing circuit initialization process. at 0 ps: Note: Hello World! (/vhdlunit/). at 0 ps: Note: 1 = 2 (/vhdlunit/). at 0 ps, Instance /vhdlunit/ : Warning: 1 = 2 at 0 ps: Error: 1 = 2 ** Failure:1 = 2 User(VHDL) Code Called Simulation Stop In process VHDLUNIT.vhd:10 INFO: Simulator is stopped. ISim> The program doesn't exit even on failure, so there's no error code for my harness to use. Also, besides reporting or asserting with severity failure, I can't figure out how to get it to stop. How to I control my return code? 3. GHDL seems better designed for this use, but we've seen discrepancies between iSim and XST so we're worried they'd be even worse with a tool not made by Xilinx. To be fair though, most of the issues have been iSim issues more than they've been XST issues, so if GHDL works well it might work better than XST. Thanks. From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!i18g2000yqn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 17:05:54 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291511154 20733 127.0.0.1 (5 Dec 2010 01:05:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 01:05:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000yqn.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4437 comp.arch.fpga:13553 On Dec 4, 5:32=A0pm, rickman wrote: > I suppose this is something that you need to expect, but I just have > never come across this before. =A0I have some concurrent logic equations > using integers where one input common to two assignments changes and > because one gets updated before the other, one is set to a value that > is outside the range of the integer and flags an error in > simulation. > > C <=3D B - A * stuff; > D <=3D A + C; =A0-- A changes and puts D outside of its range until C is > updated > > In the real world, this is not really an issue since all sorts of > intermediate states are expected when doing arithmetic. =A0But VHDL > doesn't seem to accommodate this well. =A0The only way I can think of to > fix this, without changing the logic, is to do these calculations > inside a combinatorial process using variables. =A0Then I can control > the sequence of updates explicitly. > > The only other thing I can think is to assign A to A' and use A' in > place of A in the assignment for D. =A0That may still allow an error, > but if A'' is used, then there will be two delta delays in D > assignment path. =A0However, if C grows because A has shrunk, then that > could cause the same sort of out of bounds error on D. > > Is there another way make this work that isn't so cumbersome? > > Rick Try using either the SIGNED or UNSIGNED type instead of integer. From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sat, 4 Dec 2010 18:58:52 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291517932 19204 127.0.0.1 (5 Dec 2010 02:58:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 02:58:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4438 On Dec 4, 1:57=A0pm, Jonathan Ross wrote: > > There was no warning. It's a highly repeatable issue. It probably went > undiscovered because it doesn't occur if you set a value during reset > - only if you initialize a value. > The only place you should ever consider using an initial value is in the shift register that synchronizes an external reset signal to a clock. You shouldn't use initial values anywhere else. You likely have no control over when the clock starts up relative to the design coming alive which means you have no way of guaranteeing setup/hold times are met on that very first clock cycle. That's why you should always design in an explicit reset...and why you found that it 'works' for you when you do that. > The workaround we finally came up with was to use a function to > produce a one-hot encoding for the string argument of enum_encoding. > When it doesn't detect simulation it produces a binary encoding > instead. When you have the solution and found that it works (i.e. using an explicit reset) then why would you even consider a workaround? As I mentioned before, any time you try to make simulation different from synthesis you're starting down a bad path. That bad path will end up biting you in the rear eventually if you continue to follow it. KJ From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!216.196.98.144.MISMATCH!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!j18g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 19:55:34 -0800 (PST) Organization: http://groups.google.com Lines: 54 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291521335 13396 127.0.0.1 (5 Dec 2010 03:55:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 03:55:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4439 comp.arch.fpga:13554 On Dec 4, 8:05=A0pm, Jonathan Ross wrote: > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > I suppose this is something that you need to expect, but I just have > > never come across this before. =A0I have some concurrent logic equation= s > > using integers where one input common to two assignments changes and > > because one gets updated before the other, one is set to a value that > > is outside the range of the integer and flags an error in > > simulation. > > > C <=3D B - A * stuff; > > D <=3D A + C; =A0-- A changes and puts D outside of its range until C i= s > > updated > > > In the real world, this is not really an issue since all sorts of > > intermediate states are expected when doing arithmetic. =A0But VHDL > > doesn't seem to accommodate this well. =A0The only way I can think of t= o > > fix this, without changing the logic, is to do these calculations > > inside a combinatorial process using variables. =A0Then I can control > > the sequence of updates explicitly. > > > The only other thing I can think is to assign A to A' and use A' in > > place of A in the assignment for D. =A0That may still allow an error, > > but if A'' is used, then there will be two delta delays in D > > assignment path. =A0However, if C grows because A has shrunk, then that > > could cause the same sort of out of bounds error on D. > > > Is there another way make this work that isn't so cumbersome? > > > Rick > > Try using either the SIGNED or UNSIGNED type instead of integer. I see what the two of you are saying. By using integer it will be tested for range bounds. std_logic_vector types don't get that level of analysis. The range testing is useful when it is done properly. By properly, I mean so that it is checking the logic, not your skill at eliminating glitches in combinatorial logic... For the short term I put it in a combinatorial process. The other thing that would have been pretty easy would be to combine the two into one assignment. The first assignment was just an intermediate to facilitate debugging. I guess I'm just surprised that I've never been bitten by this before. Rick From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!ircam.fr!freenix!exabot.com!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp9-1.free.fr!not-for-mail Date: Sun, 05 Dec 2010 14:55:45 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> In-Reply-To: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 45 Message-ID: <4cfb99de$0$7523$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 05 Dec 2010 14:55:42 MET NNTP-Posting-Host: 82.246.229.10 X-Trace: 1291557342 news-3.free.fr 7523 82.246.229.10:52831 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4440 Le 05/12/2010 01:09, Jonathan Ross a écrit : > [...] > 2. The following code generates the following output: > > PROCESS > BEGIN > REPORT "Hello World!" SEVERITY NOTE; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY NOTE; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY WARNING; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY ERROR; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY FAILURE; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY NOTE; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY WARNING; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY ERROR; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY FAILURE; > WAIT; > END PROCESS; > > ISim> run > Simulator is doing circuit initialization process. > at 0 ps: Note: Hello World! (/vhdlunit/). > at 0 ps: Note: 1 = 2 (/vhdlunit/). > at 0 ps, Instance /vhdlunit/ : Warning: 1 = 2 > at 0 ps: Error: 1 = 2 > > ** Failure:1 = 2 > User(VHDL) Code Called Simulation Stop > In process VHDLUNIT.vhd:10 > > INFO: Simulator is stopped. > ISim> > > The program doesn't exit even on failure, so there's no error code for > my harness to use. Also, besides reporting or asserting with severity > failure, I can't figure out how to get it to stop. How to I control my > return code? Hi It looks like the simulator DID exit after the failure. Try to put something that the simulator would execute if it didn't exit and see what happens, instead of exiting (or not) on the last instruction. Nicolas From newsfish@newsfish Fri Dec 24 22:55:48 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 10:07:57 -0800 (PST) Organization: http://groups.google.com Lines: 61 Message-ID: <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291572477 23595 127.0.0.1 (5 Dec 2010 18:07:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:07:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4441 On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > [...] > > > > > > > > > > > 2. The following code generates the following output: > > > =A0 =A0 =A0PROCESS > > =A0 =A0 =A0BEGIN > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > =A0 =A0 =A0 =A0 =A0WAIT; > > =A0 =A0 =A0END PROCESS; > > > ISim> =A0run > > Simulator is doing circuit initialization process. > > at 0 ps: Note: Hello World! (/vhdlunit/). > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > at 0 ps: Error: 1 =3D 2 > > > ** Failure:1 =3D 2 > > User(VHDL) Code Called Simulation Stop > > In process VHDLUNIT.vhd:10 > > > INFO: Simulator is stopped. > > ISim> > > > The program doesn't exit even on failure, so there's no error code for > > my harness to use. Also, besides reporting or asserting with severity > > failure, I can't figure out how to get it to stop. How to I control my > > return code? > > Hi > It looks like the simulator DID exit after the failure. > Try to put something that the simulator would execute if it didn't exit > and see what happens, instead of exiting (or not) on the last instruction= . > > Nicolas Actually, the simulator is still on. The iSim> prompt means it didn't exit to the Xilinx TCL shell, which has a %> or so prompt. That said, it does STOP at the failure. I need it to exit so I can get an exit code to tell me whether it failed or not by the launching application/ script. From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!c39g2000yqi.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 10:24:43 -0800 (PST) Organization: http://groups.google.com Lines: 47 Message-ID: <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291573483 682 127.0.0.1 (5 Dec 2010 18:24:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:24:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c39g2000yqi.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4442 On Dec 4, 9:58=A0pm, KJ wrote: > On Dec 4, 1:57=A0pm, Jonathan Ross > wrote: > > > > > There was no warning. It's a highly repeatable issue. It probably went > > undiscovered because it doesn't occur if you set a value during reset > > - only if you initialize a value. > > The only place you should ever consider using an initial value is in > the shift register that synchronizes an external reset signal to a > clock. =A0You shouldn't use initial values anywhere else. =A0You likely > have no control over when the clock starts up relative to the design > coming alive which means you have no way of guaranteeing setup/hold > times are met on that very first clock cycle. =A0That's why you should > always design in an explicit reset...and why you found that it 'works' > for you when you do that. > > > The workaround we finally came up with was to use a function to > > produce a one-hot encoding for the string argument of enum_encoding. > > When it doesn't detect simulation it produces a binary encoding > > instead. > > When you have the solution and found that it works (i.e. using an > explicit reset) then why would you even consider a workaround? > > As I mentioned before, any time you try to make simulation different > from synthesis you're starting down a bad path. =A0That bad path will > end up biting you in the rear eventually if you continue to follow it. > > KJ We tend to use a lot of initial values and have never had trouble with them in hardware - only in simulation (due to the off-by-one error). I see what you're saying, though either the Xilinx tools or board must be compensating for it or I'd expect we'd have been bitten by it by now (we've been doing this for a long time and never seen an issue). We use initial values instead of reset whenever there's no harm running the process during RESET with the hope of shortening logic paths. That said, you're right. I'm now deeply worried we've been getting lucky. Does anyone know about this in detail? We use Virtex-6 chips and we've been doing our initial development on the ML605 board from Xilinx. Are we going to have a catastrophic failure when we move to our production board? From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!h22g2000vbr.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Sun, 5 Dec 2010 10:36:28 -0800 (PST) Organization: http://groups.google.com Lines: 69 Message-ID: References: NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291574189 7703 127.0.0.1 (5 Dec 2010 18:36:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:36:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h22g2000vbr.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13561 comp.lang.verilog:2706 comp.lang.vhdl:4443 Great, thanks for sharing. I have set up an FPGA project organization which ended up quite similar to yours. The build dir is introducing (to me) a new level which seems to be a good idea, we used sim, synt, par dirs in paralell to the src, doc etc. We don't have the products dir, instead products (of specific revisions) are manually archived on a separate archive server. Also our constraint files have been lying in the synt ans par dirs, but I like the Idea of just removing the entire build dir to do a clean. However I also kind of like to do "cd synt; make" (or "make -C synt") to get the synthesis done. So I need to keep at least the makefile when doing a clean. Often the project has several "products" built from the same sources, e.g. a "board_test" bit file for production tests, and possibly some bit file to develop or debug a specific part or function of the board. Further down the road you may end up with having to support different FPGAs (i.e different speed grades/ sizes). Another aspect is when using the project as a submodule, you may want to be able to publish several variants (16/32, master/slave, etc.) All this made us come up with the concept of a "component" of a module (for the lack of a better word (component is probably the most overloaded word in HW design)). In our system a module may have several components, e.g. "board_test", "ddr_debug", "small_fpga" etc. During build: Usually there are many warnings in the log files of quite different severity. An approach I have taken is to view the log file as the primary goal in the makefile (for both sim, synt and par). Or actually a filtered log file obtained by running a (bash) script using "grep -v" to remove "known and accepted" warnings. Nothing should be left after the filter has worked on the file. The filter also does some simple statistics such as reporting the number of warnings filtered out etc. The filter is setup with a specific "component" control file that lists all acceptable warnings. This control file is also an excellent place to document why specific warnings are acceptable. So e.g. the (synt result) .edi file is obtained as a side effect of wanting a filtered synthesis log file. The filter can have make fail if wished (we currently don't do that). So the directories we have at the module level is src/ synt/ sim/ par/ doc/ submodule_1/ and design/ "make -C src" will compile (for simulation) all src code including any generated "macros" from the fpga vendor "make -C sim" will run a set of batchmode simulations generating filtered log files which can be inspected. "make -C synt my_comp" will synt the component my_comp (or actaully aim to generate my_comp's filtered log file) "make -C par my_comp" will {build; map; par; trace} my_comp by [again] aim for a filtered log file. "make all" in the module top will do all four steps above. Finally in design/ we keep all build scripts and makefiles and a file to setup the environment, i.e. paths to all tools used. In that way we also check in which tools and their versions that were used for a given project at a given time. One thing I have noted is that implementing "make help" in each directory has made the system much more user friendly. -- Pontus From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e20g2000vbx.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 10:41:47 -0800 (PST) Organization: http://groups.google.com Lines: 72 Message-ID: <4568ed0c-4e6d-4868-a468-a806616e2a79@e20g2000vbx.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291574507 6628 127.0.0.1 (5 Dec 2010 18:41:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:41:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbx.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4444 On Dec 5, 7:07=A0pm, Jonathan Ross wrote: > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > [...] > > > > 2. The following code generates the following output: > > > > =A0 =A0 =A0PROCESS > > > =A0 =A0 =A0BEGIN > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > =A0 =A0 =A0END PROCESS; > > > > ISim> =A0run > > > Simulator is doing circuit initialization process. > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > at 0 ps: Error: 1 =3D 2 > > > > ** Failure:1 =3D 2 > > > User(VHDL) Code Called Simulation Stop > > > In process VHDLUNIT.vhd:10 > > > > INFO: Simulator is stopped. > > > ISim> > > > > The program doesn't exit even on failure, so there's no error code fo= r > > > my harness to use. Also, besides reporting or asserting with severity > > > failure, I can't figure out how to get it to stop. How to I control m= y > > > return code? > > > Hi > > It looks like the simulator DID exit after the failure. > > Try to put something that the simulator would execute if it didn't exit > > and see what happens, instead of exiting (or not) on the last instructi= on. > > > Nicolas > > Actually, the simulator is still on. The iSim> prompt means it didn't > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > it does STOP at the failure. I need it to exit so I can get an exit > code to tell me whether it failed or not by the launching application/ > script. Instead of just doing "run" I do "run; exit" which does what you want, at least for modelsim/riviera. The simulation will stop at "failure" (configurable, you can stop at warning if you wish). Simulation will also stop when there are no more scheduled events, so by stopping your clock you will stop the sim. HTH -- Pontus From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 11:01:45 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291575705 18041 127.0.0.1 (5 Dec 2010 19:01:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:01:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4445 On Dec 5, 1:07=A0pm, Jonathan Ross wrote: > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > [...] > > > > 2. The following code generates the following output: > > > > =A0 =A0 =A0PROCESS > > > =A0 =A0 =A0BEGIN > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > =A0 =A0 =A0END PROCESS; > > > > ISim> =A0run > > > Simulator is doing circuit initialization process. > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > at 0 ps: Error: 1 =3D 2 > > > > ** Failure:1 =3D 2 > > > User(VHDL) Code Called Simulation Stop > > > In process VHDLUNIT.vhd:10 > > > > INFO: Simulator is stopped. > > > ISim> > > > > The program doesn't exit even on failure, so there's no error code fo= r > > > my harness to use. Also, besides reporting or asserting with severity > > > failure, I can't figure out how to get it to stop. How to I control m= y > > > return code? > > > Hi > > It looks like the simulator DID exit after the failure. > > Try to put something that the simulator would execute if it didn't exit > > and see what happens, instead of exiting (or not) on the last instructi= on. > > > Nicolas > > Actually, the simulator is still on. The iSim> prompt means it didn't > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > it does STOP at the failure. I need it to exit so I can get an exit > code to tell me whether it failed or not by the launching application/ > script. As Pontus says, you can use a command in ISim to exit the program after it ends the simulation run. But that doesn't tell your program why it exited. Is there a simulation result available at the ISim command line that could be used as an exit condition for the program? Rick From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z20g2000pra.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 11:12:22 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291576342 24184 127.0.0.1 (5 Dec 2010 19:12:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:12:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z20g2000pra.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4446 On Dec 5, 1:24=A0pm, Jonathan Ross wrote: > On Dec 4, 9:58=A0pm, KJ wrote: > > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > wrote: > > > > There was no warning. It's a highly repeatable issue. It probably wen= t > > > undiscovered because it doesn't occur if you set a value during reset > > > - only if you initialize a value. > > > The only place you should ever consider using an initial value is in > > the shift register that synchronizes an external reset signal to a > > clock. =A0You shouldn't use initial values anywhere else. =A0You likely > > have no control over when the clock starts up relative to the design > > coming alive which means you have no way of guaranteeing setup/hold > > times are met on that very first clock cycle. =A0That's why you should > > always design in an explicit reset...and why you found that it 'works' > > for you when you do that. > > > > The workaround we finally came up with was to use a function to > > > produce a one-hot encoding for the string argument of enum_encoding. > > > When it doesn't detect simulation it produces a binary encoding > > > instead. > > > When you have the solution and found that it works (i.e. using an > > explicit reset) then why would you even consider a workaround? > > > As I mentioned before, any time you try to make simulation different > > from synthesis you're starting down a bad path. =A0That bad path will > > end up biting you in the rear eventually if you continue to follow it. > > > KJ > > We tend to use a lot of initial values and have never had trouble with > them in hardware - only in simulation (due to the off-by-one error). I > see what you're saying, though either the Xilinx tools or board must > be compensating for it or I'd expect we'd have been bitten by it by > now (we've been doing this for a long time and never seen an issue). > We use initial values instead of reset whenever there's no harm > running the process during RESET with the hope of shortening logic > paths. > > That said, you're right. I'm now deeply worried we've been getting > lucky. Does anyone know about this in detail? We use Virtex-6 chips > and we've been doing our initial development on the ML605 board from > Xilinx. Are we going to have a catastrophic failure when we move to > our production board? I'm not clear on what your reset concept is. It used to be that the tools did not use initializations in synthesis. I believe now that many of them do. The values used in the initialization is imposed on registers coming out of configuration and if the GSR is connected externally, this will give the same result. Check with your synthesis vendor to find out if initialization is supported. However... The issue with using GSR is not asserting it, but removing it. The GSR path is slow and if your clock is running and any clock enables are asserted different registers are released at different clock cycles than others. This can result in state machines ending up in invalid states, counters at wrong initial counts, etc. In essence, your synchronous logic is out of sync! There are many ways to deal with this. Often various parts of the design will do nothing until some condition enables them. These parts don't need to be changed unless there is a way they can be enabled when GSR is released. If any parts of the design need to be held in reset and released on the same clock cycle, then you need a sync reset on those portions. You can do this on a section by section basis so that you don't have one sync reset driving the entire design. Or you can use one common sync reset to the entire design which will most likely be replicated anyway. But this should be coded as a sync reset, not an async reset. Rick From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j9g2000vbl.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 11:57:44 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291579064 22309 127.0.0.1 (5 Dec 2010 19:57:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:57:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000vbl.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4447 On Dec 5, 2:01=A0pm, rickman wrote: > On Dec 5, 1:07=A0pm, Jonathan Ross > wrote: > > > > > > > > > > > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > > [...] > > > > > 2. The following code generates the following output: > > > > > =A0 =A0 =A0PROCESS > > > > =A0 =A0 =A0BEGIN > > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE= ; > > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > > =A0 =A0 =A0END PROCESS; > > > > > ISim> =A0run > > > > Simulator is doing circuit initialization process. > > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > > at 0 ps: Error: 1 =3D 2 > > > > > ** Failure:1 =3D 2 > > > > User(VHDL) Code Called Simulation Stop > > > > In process VHDLUNIT.vhd:10 > > > > > INFO: Simulator is stopped. > > > > ISim> > > > > > The program doesn't exit even on failure, so there's no error code = for > > > > my harness to use. Also, besides reporting or asserting with severi= ty > > > > failure, I can't figure out how to get it to stop. How to I control= my > > > > return code? > > > > Hi > > > It looks like the simulator DID exit after the failure. > > > Try to put something that the simulator would execute if it didn't ex= it > > > and see what happens, instead of exiting (or not) on the last instruc= tion. > > > > Nicolas > > > Actually, the simulator is still on. The iSim> prompt means it didn't > > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > > it does STOP at the failure. I need it to exit so I can get an exit > > code to tell me whether it failed or not by the launching application/ > > script. > > As Pontus says, you can use a command in ISim to exit the program > after it ends the simulation run. =A0But that doesn't tell your program > why it exited. =A0Is there a simulation result available at the ISim > command line that could be used as an exit condition for the > program? > > Rick I'm not quite following - perhaps because I'm not sure what's meant by "simulation result." Is there some object that iSim is aware of or can be made aware of, or is this terminology colloquial? I'm open to making any changes needed - in fact I won't be using ASSERT for this (I'm going to follow the xUnit pattern and make my results openly available at vhdlunit.org). From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!z17g2000prz.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 12:22:19 -0800 (PST) Organization: http://groups.google.com Lines: 99 Message-ID: <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291580539 4049 127.0.0.1 (5 Dec 2010 20:22:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 20:22:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000prz.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4448 On Dec 5, 2:12=A0pm, rickman wrote: > On Dec 5, 1:24=A0pm, Jonathan Ross > wrote: > > > > > > > > > > > On Dec 4, 9:58=A0pm, KJ wrote: > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > > wrote: > > > > > There was no warning. It's a highly repeatable issue. It probably w= ent > > > > undiscovered because it doesn't occur if you set a value during res= et > > > > - only if you initialize a value. > > > > The only place you should ever consider using an initial value is in > > > the shift register that synchronizes an external reset signal to a > > > clock. =A0You shouldn't use initial values anywhere else. =A0You like= ly > > > have no control over when the clock starts up relative to the design > > > coming alive which means you have no way of guaranteeing setup/hold > > > times are met on that very first clock cycle. =A0That's why you shoul= d > > > always design in an explicit reset...and why you found that it 'works= ' > > > for you when you do that. > > > > > The workaround we finally came up with was to use a function to > > > > produce a one-hot encoding for the string argument of enum_encoding= . > > > > When it doesn't detect simulation it produces a binary encoding > > > > instead. > > > > When you have the solution and found that it works (i.e. using an > > > explicit reset) then why would you even consider a workaround? > > > > As I mentioned before, any time you try to make simulation different > > > from synthesis you're starting down a bad path. =A0That bad path will > > > end up biting you in the rear eventually if you continue to follow it= . > > > > KJ > > > We tend to use a lot of initial values and have never had trouble with > > them in hardware - only in simulation (due to the off-by-one error). I > > see what you're saying, though either the Xilinx tools or board must > > be compensating for it or I'd expect we'd have been bitten by it by > > now (we've been doing this for a long time and never seen an issue). > > We use initial values instead of reset whenever there's no harm > > running the process during RESET with the hope of shortening logic > > paths. > > > That said, you're right. I'm now deeply worried we've been getting > > lucky. Does anyone know about this in detail? We use Virtex-6 chips > > and we've been doing our initial development on the ML605 board from > > Xilinx. Are we going to have a catastrophic failure when we move to > > our production board? > > I'm not clear on what your reset concept is. =A0It used to be that the > tools did not use initializations in synthesis. =A0I believe now that > many of them do. =A0The values used in the initialization is imposed on > registers coming out of configuration and if the GSR is connected > externally, this will give the same result. =A0Check with your synthesis > vendor to find out if initialization is supported. =A0However... > > The issue with using GSR is not asserting it, but removing it. =A0The > GSR path is slow and if your clock is running and any clock enables > are asserted different registers are released at different clock > cycles than others. =A0This can result in state machines ending up in > invalid states, counters at wrong initial counts, etc. =A0In essence, > your synchronous logic is out of sync! > > There are many ways to deal with this. =A0Often various parts of the > design will do nothing until some condition enables them. =A0These parts > don't need to be changed unless there is a way they can be enabled > when GSR is released. =A0If any parts of the design need to be held in > reset and released on the same clock cycle, then you need a sync reset > on those portions. =A0You can do this on a section by section basis so > that you don't have one sync reset driving the entire design. =A0Or you > can use one common sync reset to the entire design which will most > likely be replicated anyway. =A0But this should be coded as a sync > reset, not an async reset. > > Rick I found the following post: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-and-Virtex-6-confi= guration-and-GSR/m-p/98892/highlight/true#M7728 All of our state machines have either no reset logic (purely initialized) or synchronous reset logic, so it sounds like we're safe. From newsfish@newsfish Fri Dec 24 22:55:49 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 14:46:44 -0800 (PST) Organization: http://groups.google.com Lines: 101 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291589204 22887 127.0.0.1 (5 Dec 2010 22:46:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 22:46:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4449 On Dec 5, 2:57=A0pm, Jonathan Ross wrote: > On Dec 5, 2:01=A0pm, rickman wrote: > > > > > On Dec 5, 1:07=A0pm, Jonathan Ross > > wrote: > > > > On Dec 5, 8:55=A0am, Nicolas Matringe wrot= e: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > > > [...] > > > > > > 2. The following code generates the following output: > > > > > > =A0 =A0 =A0PROCESS > > > > > =A0 =A0 =A0BEGIN > > > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNI= NG; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR= ; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILU= RE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNI= NG; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR= ; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILU= RE; > > > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > > > =A0 =A0 =A0END PROCESS; > > > > > > ISim> =A0run > > > > > Simulator is doing circuit initialization process. > > > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > > > at 0 ps: Error: 1 =3D 2 > > > > > > ** Failure:1 =3D 2 > > > > > User(VHDL) Code Called Simulation Stop > > > > > In process VHDLUNIT.vhd:10 > > > > > > INFO: Simulator is stopped. > > > > > ISim> > > > > > > The program doesn't exit even on failure, so there's no error cod= e for > > > > > my harness to use. Also, besides reporting or asserting with seve= rity > > > > > failure, I can't figure out how to get it to stop. How to I contr= ol my > > > > > return code? > > > > > Hi > > > > It looks like the simulator DID exit after the failure. > > > > Try to put something that the simulator would execute if it didn't = exit > > > > and see what happens, instead of exiting (or not) on the last instr= uction. > > > > > Nicolas > > > > Actually, the simulator is still on. The iSim> prompt means it didn't > > > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > > > it does STOP at the failure. I need it to exit so I can get an exit > > > code to tell me whether it failed or not by the launching application= / > > > script. > > > As Pontus says, you can use a command in ISim to exit the program > > after it ends the simulation run. =A0But that doesn't tell your program > > why it exited. =A0Is there a simulation result available at the ISim > > command line that could be used as an exit condition for the > > program? > > > Rick > > I'm not quite following - perhaps because I'm not sure what's meant by > "simulation result." Is there some object that iSim is aware of or can > be made aware of, or is this terminology colloquial? I'm open to > making any changes needed - in fact I won't be using ASSERT for this > (I'm going to follow the xUnit pattern and make my results openly > available at vhdlunit.org). That's why I'm asking the question, I don't know either. If there is a way to use command line functions to determine the result of the simulation... and there is a way to make ISim return an exit code on exiting, then you can make this work the way I think you want to do it. But I don't know if ISim will do either of those things. Would it be easier to have ISim save the log to a file and then read the log to get a result? Rick From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!u25g2000pra.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 14:49:56 -0800 (PST) Organization: http://groups.google.com Lines: 117 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291589396 24517 127.0.0.1 (5 Dec 2010 22:49:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 22:49:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u25g2000pra.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4450 On Dec 5, 3:22=A0pm, Jonathan Ross wrote: > On Dec 5, 2:12=A0pm, rickman wrote: > > > > > On Dec 5, 1:24=A0pm, Jonathan Ross > > wrote: > > > > On Dec 4, 9:58=A0pm, KJ wrote: > > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > > > wrote: > > > > > > There was no warning. It's a highly repeatable issue. It probably= went > > > > > undiscovered because it doesn't occur if you set a value during r= eset > > > > > - only if you initialize a value. > > > > > The only place you should ever consider using an initial value is i= n > > > > the shift register that synchronizes an external reset signal to a > > > > clock. =A0You shouldn't use initial values anywhere else. =A0You li= kely > > > > have no control over when the clock starts up relative to the desig= n > > > > coming alive which means you have no way of guaranteeing setup/hold > > > > times are met on that very first clock cycle. =A0That's why you sho= uld > > > > always design in an explicit reset...and why you found that it 'wor= ks' > > > > for you when you do that. > > > > > > The workaround we finally came up with was to use a function to > > > > > produce a one-hot encoding for the string argument of enum_encodi= ng. > > > > > When it doesn't detect simulation it produces a binary encoding > > > > > instead. > > > > > When you have the solution and found that it works (i.e. using an > > > > explicit reset) then why would you even consider a workaround? > > > > > As I mentioned before, any time you try to make simulation differen= t > > > > from synthesis you're starting down a bad path. =A0That bad path wi= ll > > > > end up biting you in the rear eventually if you continue to follow = it. > > > > > KJ > > > > We tend to use a lot of initial values and have never had trouble wit= h > > > them in hardware - only in simulation (due to the off-by-one error). = I > > > see what you're saying, though either the Xilinx tools or board must > > > be compensating for it or I'd expect we'd have been bitten by it by > > > now (we've been doing this for a long time and never seen an issue). > > > We use initial values instead of reset whenever there's no harm > > > running the process during RESET with the hope of shortening logic > > > paths. > > > > That said, you're right. I'm now deeply worried we've been getting > > > lucky. Does anyone know about this in detail? We use Virtex-6 chips > > > and we've been doing our initial development on the ML605 board from > > > Xilinx. Are we going to have a catastrophic failure when we move to > > > our production board? > > > I'm not clear on what your reset concept is. =A0It used to be that the > > tools did not use initializations in synthesis. =A0I believe now that > > many of them do. =A0The values used in the initialization is imposed on > > registers coming out of configuration and if the GSR is connected > > externally, this will give the same result. =A0Check with your synthesi= s > > vendor to find out if initialization is supported. =A0However... > > > The issue with using GSR is not asserting it, but removing it. =A0The > > GSR path is slow and if your clock is running and any clock enables > > are asserted different registers are released at different clock > > cycles than others. =A0This can result in state machines ending up in > > invalid states, counters at wrong initial counts, etc. =A0In essence, > > your synchronous logic is out of sync! > > > There are many ways to deal with this. =A0Often various parts of the > > design will do nothing until some condition enables them. =A0These part= s > > don't need to be changed unless there is a way they can be enabled > > when GSR is released. =A0If any parts of the design need to be held in > > reset and released on the same clock cycle, then you need a sync reset > > on those portions. =A0You can do this on a section by section basis so > > that you don't have one sync reset driving the entire design. =A0Or you > > can use one common sync reset to the entire design which will most > > likely be replicated anyway. =A0But this should be coded as a sync > > reset, not an async reset. > > > Rick > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FPGA= s/Virtex-5-and-Virtex-6... > > All of our state machines have either no reset logic (purely > initialized) or synchronous reset logic, so it sounds like we're safe. Do you know if the initialized machines are init the way you want? I don't depend on init values to set my GSR state... BTW, if you think using init values somehow gets you around the GSR problem, you don't understand what I am saying. If the init values are used for synthesis, then they are used to set the GSR behavior of the registers. You then have to deal with how the register comes out of reset. Are you using an external reset of any kind? Is that the sync reset? If so, how do you activate the GSR reset for the rest of the chip? Rick From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 15:44:20 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291592660 19454 127.0.0.1 (5 Dec 2010 23:44:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 23:44:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4451 On Dec 5, 3:22 pm, Jonathan Ross wrote: > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-and-Virtex-6... > > All of our state machines have either no reset logic (purely > initialized) or synchronous reset logic, so it sounds like we're safe. > I'm not seeing how you think you're safe if you have synchronous logic that depends only on initial values. The issue is not whether or not the initial values get loaded, but how the transition from configuration to user mode with a running clock happens and whether it occurs at a time which violates a setup or hold time requirement. Any flop that is part of a feedback path (such as state machines or counters) are candidates for problems; any flop that is not part of a feedback (such as a synchronizer or delay) will not be a problem. Having said that, the odds of seeing such a failure might also be rather slim since configuration generally happens only once per power cycle. So, yes you are getting lucky, but you're also not in a high probability of failure situation. Still, good design practice generally dictactes that you should not rely on initial values for two reasons: - Potential timing issues at end of configuration as just discussed - No way to have the design recover from any unusual situation without cycling power Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 06 Dec 2010 02:18:29 +0100 Lines: 39 Message-ID: <8m2rv5F1gdU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 52vyDVbxASav88J7u2o+UgPZohTialh9EF8MKN0yj+4xJKQLkA Cancel-Lock: sha1:X3fyOocXuN92DlBvXoXSN3nHNzM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:13564 comp.lang.verilog:2708 comp.lang.vhdl:4452 On 12/3/2010 1:32 PM, saar drimer wrote: > I've written up an (informal) draft proposal for an FPGA project > structure that could be easily extended as the project grows and is > version control friendly. I'd be grateful for any type of feedback... > > http://www.saardrimer.com/fpgaproj/ > > cheers, > saar. First of all I'd like to point out that your proposal looks consistent and in some aspects very elegant. I like the idea of having a common structured approach everyone understands and follows rigorously and methodically, in order to promote reuse and modular design. On the contrary I believe the effort becomes huge when you need to deal with FPGA vendors, since every one is pushing their own product and through their own Integrated Development Environment they tie down the designers to their own structure. As already posted, I also like the idea of cleaning a build in one go, but I think that a constraint file is pretty much different from an hdl file and collecting them under /source will make a lot of confusion, especially when you are interested in developing rtl while some other people are interested in adding constraints for the implementation. Dividing the dir tree in processes has the big advantage that even though you are the only one designer, you make your project flowing, in several reiterations, with the processes. Once you are happy with the simulation and the rtl you would move into synthesis and so on (with a good chance you need to come back to your rtl). In the end I believe that having a structure, regardless the type, is the most important thing, since nothing can be more confusing than having no organization. I sometimes stare for minutes at the list of directory names my group is creating and believe that no matter what structure you want to propose their capability to screw it up is greatly above any imagination (I still remember my very first vhdl project soon moved from directory /test to directory /final and then /reallyfinal and then /reallyfinal2...). From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!j18g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 18:27:38 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: <0094b499-679c-4468-a751-4c201d91fbc4@j18g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291602458 16432 127.0.0.1 (6 Dec 2010 02:27:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 02:27:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4453 On Dec 5, 6:44=A0pm, KJ wrote: > On Dec 5, 3:22 pm, Jonathan Ross > wrote: > > > > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FP= GAs/Virtex-5-and-Virtex-6... > > > All of our state machines have either no reset logic (purely > > initialized) or synchronous reset logic, so it sounds like we're safe. > > I'm not seeing how you think you're safe if you have synchronous logic > that depends only on initial values. =A0The issue is not whether or not > the initial values get loaded, but how the transition from > configuration to user mode with a running clock happens and whether it > occurs at a time which violates a setup or hold time requirement. > > Any flop that is part of a feedback path (such as state machines or > counters) are candidates for problems; any flop that is not part of a > feedback (such as a synchronizer or delay) will not be a problem. > > Having said that, the odds of seeing such a failure might also be > rather slim since =A0configuration generally happens only once per power > cycle. =A0So, yes you are getting lucky, but you're also not in a high > probability of failure situation. =A0Still, good design practice > generally dictactes that you should not rely on initial values for two > reasons: > - Potential timing issues at end of configuration as just discussed > - No way to have the design recover from any unusual situation without > cycling power Depending on initial states does not require a power cycle. Most, if not all FPGAs can be reloaded by asserting a pin, often called PRGM or something similar. Otherwise I agree with you. Rick From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 21:18:14 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <31f5420d-2455-488f-9e99-e2c9f021be2f@f20g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> <0094b499-679c-4468-a751-4c201d91fbc4@j18g2000prn.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291612694 17360 127.0.0.1 (6 Dec 2010 05:18:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 05:18:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4454 On Dec 5, 9:27=A0pm, rickman wrote: > Depending on initial states does not require a power cycle. =A0Most, if > not all FPGAs can be reloaded by asserting a pin, often called PRGM or > something similar. =A0Otherwise I agree with you. > > Rick You're right, I thought of that too soon after clicking on 'Send'. KJ From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v19g2000yqa.googlegroups.com!not-for-mail From: Kolja Sulimma Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 02:09:10 -0800 (PST) Organization: http://groups.google.com Lines: 63 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 87.155.69.23 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291630150 28217 127.0.0.1 (6 Dec 2010 10:09:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 10:09:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqa.googlegroups.com; posting-host=87.155.69.23; posting-account=GgLtCgoAAAD1eGcaDvWVJ6l90w-YMYMc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4455 comp.arch.fpga:13567 On 5 Dez., 04:55, rickman wrote: > On Dec 4, 8:05=A0pm, Jonathan Ross > wrote: > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > I suppose this is something that you need to expect, but I just have > > > never come across this before. =A0I have some concurrent logic equati= ons > > > using integers where one input common to two assignments changes and > > > because one gets updated before the other, one is set to a value that > > > is outside the range of the integer and flags an error in > > > simulation. > > > > C <=3D B - A * stuff; > > > D <=3D A + C; =A0-- A changes and puts D outside of its range until C= is > > > updated > > > > In the real world, this is not really an issue since all sorts of > > > intermediate states are expected when doing arithmetic. =A0But VHDL > > > doesn't seem to accommodate this well. =A0The only way I can think of= to > > > fix this, without changing the logic, is to do these calculations > > > inside a combinatorial process using variables. =A0Then I can control > > > the sequence of updates explicitly. > > > > The only other thing I can think is to assign A to A' and use A' in > > > place of A in the assignment for D. =A0That may still allow an error, > > > but if A'' is used, then there will be two delta delays in D > > > assignment path. =A0However, if C grows because A has shrunk, then th= at > > > could cause the same sort of out of bounds error on D. > > > > Is there another way make this work that isn't so cumbersome? > > > > Rick > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > I see what the two of you are saying. =A0By using integer it will be > tested for range bounds. =A0std_logic_vector types don't get that level > of analysis. =A0The range testing is useful when it is done properly. > By properly, I mean so that it is checking the logic, not your skill > at eliminating glitches in combinatorial logic... Use signed or unsigned from the numeric_std package and perform the range check yourself at times when you know the intermediate states have settled: if rising_edge(clk) then assert c >=3D lower_bound and c <=3D upper_bound report "C out of range"; end if; I believe that virtually all HDL-Designers should use a lot more assertions than they do. (Myself included.) Kolja From newsfish@newsfish Fri Dec 24 22:55:50 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m20g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 05:57:33 -0800 (PST) Organization: http://groups.google.com Lines: 75 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291643853 30138 127.0.0.1 (6 Dec 2010 13:57:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 13:57:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000prc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4456 comp.arch.fpga:13575 On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > On 5 Dez., 04:55, rickman wrote: > > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > wrote: > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > I suppose this is something that you need to expect, but I just hav= e > > > > never come across this before. =A0I have some concurrent logic equa= tions > > > > using integers where one input common to two assignments changes an= d > > > > because one gets updated before the other, one is set to a value th= at > > > > is outside the range of the integer and flags an error in > > > > simulation. > > > > > C <=3D B - A * stuff; > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range until= C is > > > > updated > > > > > In the real world, this is not really an issue since all sorts of > > > > intermediate states are expected when doing arithmetic. =A0But VHDL > > > > doesn't seem to accommodate this well. =A0The only way I can think = of to > > > > fix this, without changing the logic, is to do these calculations > > > > inside a combinatorial process using variables. =A0Then I can contr= ol > > > > the sequence of updates explicitly. > > > > > The only other thing I can think is to assign A to A' and use A' in > > > > place of A in the assignment for D. =A0That may still allow an erro= r, > > > > but if A'' is used, then there will be two delta delays in D > > > > assignment path. =A0However, if C grows because A has shrunk, then = that > > > > could cause the same sort of out of bounds error on D. > > > > > Is there another way make this work that isn't so cumbersome? > > > > > Rick > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > I see what the two of you are saying. =A0By using integer it will be > > tested for range bounds. =A0std_logic_vector types don't get that level > > of analysis. =A0The range testing is useful when it is done properly. > > By properly, I mean so that it is checking the logic, not your skill > > at eliminating glitches in combinatorial logic... > > Use signed or unsigned from the numeric_std package and perform the > range check yourself > at times when you know the intermediate states have settled: > > if rising_edge(clk) then > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > range"; > end if; > > I believe that virtually all HDL-Designers should use a lot more > assertions than they do. > (Myself included.) > > Kolja That's an interesting approach. I'm not accustomed to using assertions in my synthesizable code, but there is certainly no reason not to. Rick From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!matrix.darkstorm.co.uk!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!z9g2000yqz.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 06:30:03 -0800 (PST) Organization: http://groups.google.com Lines: 98 Message-ID: <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.18.17.161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291645803 16647 127.0.0.1 (6 Dec 2010 14:30:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 14:30:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqz.googlegroups.com; posting-host=68.18.17.161; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4457 comp.arch.fpga:13579 On Dec 6, 8:57=A0am, rickman wrote: > On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > > > > > > > On 5 Dez., 04:55, rickman wrote: > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > > wrote: > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > > I suppose this is something that you need to expect, but I just h= ave > > > > > never come across this before. =A0I have some concurrent logic eq= uations > > > > > using integers where one input common to two assignments changes = and > > > > > because one gets updated before the other, one is set to a value = that > > > > > is outside the range of the integer and flags an error in > > > > > simulation. > > > > > > C <=3D B - A * stuff; > > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range unt= il C is > > > > > updated > > > > > > In the real world, this is not really an issue since all sorts of > > > > > intermediate states are expected when doing arithmetic. =A0But VH= DL > > > > > doesn't seem to accommodate this well. =A0The only way I can thin= k of to > > > > > fix this, without changing the logic, is to do these calculations > > > > > inside a combinatorial process using variables. =A0Then I can con= trol > > > > > the sequence of updates explicitly. > > > > > > The only other thing I can think is to assign A to A' and use A' = in > > > > > place of A in the assignment for D. =A0That may still allow an er= ror, > > > > > but if A'' is used, then there will be two delta delays in D > > > > > assignment path. =A0However, if C grows because A has shrunk, the= n that > > > > > could cause the same sort of out of bounds error on D. > > > > > > Is there another way make this work that isn't so cumbersome? > > > > > > Rick > > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > > I see what the two of you are saying. =A0By using integer it will be > > > tested for range bounds. =A0std_logic_vector types don't get that lev= el > > > of analysis. =A0The range testing is useful when it is done properly. > > > By properly, I mean so that it is checking the logic, not your skill > > > at eliminating glitches in combinatorial logic... > > > Use signed or unsigned from the numeric_std package and perform the > > range check yourself > > at times when you know the intermediate states have settled: > > > if rising_edge(clk) then > > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > > range"; > > end if; > > > I believe that virtually all HDL-Designers should use a lot more > > assertions than they do. > > (Myself included.) > > > Kolja > > That's an interesting approach. =A0I'm not accustomed to using > assertions in my synthesizable code, but there is certainly no reason > not to. > > Rick- Hide quoted text - > > - Show Iquoted text - I have not tried it, but what is below may do what you want also. signal G_sv : signed(10 downto 0); signal Signed_int : integer range -128 to 127; -- specified valid range here ................. if rising_edge(clk) then Signed_int <=3D TO_INTEGER(G_sv); end if; From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 06:38:20 -0800 (PST) Organization: http://groups.google.com Lines: 107 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 68.18.17.161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291646329 21791 127.0.0.1 (6 Dec 2010 14:38:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 14:38:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=68.18.17.161; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4458 comp.arch.fpga:13580 On Dec 6, 9:30=A0am, Newman wrote: > On Dec 6, 8:57=A0am, rickman wrote: > > > > > > > On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > > > > On 5 Dez., 04:55, rickman wrote: > > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > > > wrote: > > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > > > I suppose this is something that you need to expect, but I just= have > > > > > > never come across this before. =A0I have some concurrent logic = equations > > > > > > using integers where one input common to two assignments change= s and > > > > > > because one gets updated before the other, one is set to a valu= e that > > > > > > is outside the range of the integer and flags an error in > > > > > > simulation. > > > > > > > C <=3D B - A * stuff; > > > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range u= ntil C is > > > > > > updated > > > > > > > In the real world, this is not really an issue since all sorts = of > > > > > > intermediate states are expected when doing arithmetic. =A0But = VHDL > > > > > > doesn't seem to accommodate this well. =A0The only way I can th= ink of to > > > > > > fix this, without changing the logic, is to do these calculatio= ns > > > > > > inside a combinatorial process using variables. =A0Then I can c= ontrol > > > > > > the sequence of updates explicitly. > > > > > > > The only other thing I can think is to assign A to A' and use A= ' in > > > > > > place of A in the assignment for D. =A0That may still allow an = error, > > > > > > but if A'' is used, then there will be two delta delays in D > > > > > > assignment path. =A0However, if C grows because A has shrunk, t= hen that > > > > > > could cause the same sort of out of bounds error on D. > > > > > > > Is there another way make this work that isn't so cumbersome? > > > > > > > Rick > > > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > > > I see what the two of you are saying. =A0By using integer it will b= e > > > > tested for range bounds. =A0std_logic_vector types don't get that l= evel > > > > of analysis. =A0The range testing is useful when it is done properl= y. > > > > By properly, I mean so that it is checking the logic, not your skil= l > > > > at eliminating glitches in combinatorial logic... > > > > Use signed or unsigned from the numeric_std package and perform the > > > range check yourself > > > at times when you know the intermediate states have settled: > > > > if rising_edge(clk) then > > > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > > > range"; > > > end if; > > > > I believe that virtually all HDL-Designers should use a lot more > > > assertions than they do. > > > (Myself included.) > > > > Kolja > > > That's an interesting approach. =A0I'm not accustomed to using > > assertions in my synthesizable code, but there is certainly no reason > > not to. > > > Rick- Hide quoted text - > > > - Show Iquoted text - > > I have not tried it, but what is below may do what you want also. > > signal G_sv =A0 =A0 =A0 =A0 =A0 =A0 : signed(10 downto 0); > signal Signed_int =A0 : integer range -128 to 127; =A0 -- specified valid > range here > ................. > > if rising_edge(clk) then > =A0 Signed_int <=3D =A0 TO_INTEGER(G_sv); > end if;- Hide quoted text - > > - Show quoted text - I might have wrongly assumed that the combinatorial result was going to be eventually registered. Oops! From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j29g2000yqm.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Mon, 6 Dec 2010 09:14:20 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291655661 10789 127.0.0.1 (6 Dec 2010 17:14:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 17:14:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j29g2000yqm.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4459 On Dec 5, 2:46=A0pm, rickman wrote: > > Would it be easier to have ISim save the log to a file and then read > the log to get a result? > > Rick Do what Rick says. Create a log file. At the very least, have the word PASS or FAIL appear in the log file. Eventually you will want to have something in your log file to tell you why and when the failure was detected. Hint: Assertions are your friend. RK From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!k14g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 10:00:23 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291658424 5046 127.0.0.1 (6 Dec 2010 18:00:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:00:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k14g2000pre.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4460 comp.arch.fpga:13589 I think I would use a function for the intermediate calculation, and then call the function in both concurrent assignment statements per the original implementation. Integers give you the benefits of bounds checking in simulation (even below the 2^n granularity if desired), and a big improvement in simulation performance, especially if integers are widely used in the design (instead of vectors). Andy From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!feeder4.news.weretis.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!a28g2000prb.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 10:25:38 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291659938 19774 127.0.0.1 (6 Dec 2010 18:25:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:25:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a28g2000prb.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13590 comp.lang.verilog:2709 comp.lang.vhdl:4461 Thank you Jonathan, Pontus and Alessandro for your comments and suggestions -- I will consider them for the next revision of the document. On Dec 6, 1:18=A0am, Alessandro Basili wrote: > In the end I believe that having a structure, regardless the type, is > the most important thing, since nothing can be more confusing than > having no organization. That's the main point, yes. The primary motivation for writing this specification was to provide a starting point for engineers, together with the reasoning behind the choices that I have made. Obviously, there's no way for a single structure definition to fit everyone's needs. I do think, though, that within the rigid rules of this proposal, there's enough flexibility for customization without loss of most benefits. Further comments and suggestions are welcome! cheers, saar. From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 10:50:39 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 216.127.159.67 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291661439 5928 127.0.0.1 (6 Dec 2010 18:50:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:50:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=216.127.159.67; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4462 comp.arch.fpga:13591 On Dec 6, 1:00=A0pm, Andy wrote: > I think I would use a function for the intermediate calculation, and > then call the function in both concurrent assignment statements per > the original implementation. > > Integers give you the benefits of bounds checking in simulation (even > below the 2^n granularity if desired), and a big improvement in > simulation performance, especially if integers are widely used in the > design (instead of vectors). > > Andy I know everyone says that integers run faster, but is this a significant effect? Has it been measured or at least verified on current simulators? Rick From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!y19g2000prb.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 12:46:54 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291668414 4135 127.0.0.1 (6 Dec 2010 20:46:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 20:46:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y19g2000prb.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13594 comp.lang.verilog:2710 comp.lang.vhdl:4463 On 6 d=E9c, 13:25, saar drimer wrote: > Thank you Jonathan, Pontus and Alessandro for your comments and > suggestions -- I will consider them for the next revision of the > document. > > On Dec 6, 1:18=A0am, Alessandro Basili > wrote: > > > In the end I believe that having a structure, regardless the type, is > > the most important thing, since nothing can be more confusing than > > having no organization. > > That's the main point, yes. The primary motivation for writing this > specification was to provide a starting point for engineers, together > with the reasoning behind the choices that I have made. Obviously, > there's no way for a single structure definition to fit everyone's > needs. I do think, though, that within the rigid rules of this > proposal, there's enough flexibility for customization without loss of > most benefits. > > Further comments and suggestions are welcome! > > cheers, > saar. I was just wondering, with your project structure, where would vendor- specific cores would fit in? Let's say I use core generator to generate a FIR filter. Coregen generates a .xco file along with .ngc, .mif .vhd (for simulation), etc. Where would you put it in your structure and what files would you add to your version control. Technically, you only need the .xco file, and maybe the .coef file the regenerate your core. However, if you have a lot of cores, it might take a lot of time to regenerate the missing core files. From newsfish@newsfish Fri Dec 24 22:55:51 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n2g2000pre.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 13:46:34 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <0d80e6ec-227c-4db9-958a-7fe9cadf7139@n2g2000pre.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291671994 10425 127.0.0.1 (6 Dec 2010 21:46:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 21:46:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n2g2000pre.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13598 comp.lang.verilog:2711 comp.lang.vhdl:4464 > I was just wondering, with your project structure, where would vendor- > specific cores would fit in? Let's say I use core generator to > generate a FIR filter. Coregen generates a .xco file along > with .ngc, .mif .vhd (for simulation), etc. Where would you put it in > your structure and what files would you add to your version control. > Technically, you only need the .xco file, and maybe the .coef file the > regenerate your core. However, if you have a lot of cores, it might > take a lot of time to regenerate the missing core files. Some of this is already covered in the document; see the "build environment" section. This is the Makefile bit (I've noted that I'm inconsistent with "/source" and "/sources", and will fix it in the next revision): CGP = fifo # Generate black boxes # (Unfortunately, CoreGen will generate the core where the .cgp and # .xco files are, NOT from where it is invoked. There is no output # path directive either. Hack is to copy the source files first) %.v %.cgp: cp ../sources/blackbox/$(CGP).cgp $(SYN)/$(CGP).cgp cp ../sources/blackbox/$(CGP).xco $(SYN)/$(CGP).xco cd $(SYN) && coregen -p $(CGP).cgp -b $(CGP).xco bbox: $(SYN)/$(CGP).v $(SYN)/$(CGP).cgp I'm suggesting that the required source files (in this case, .xco and .cgp) be put in version control at "/sources/blackbox" (for a single core). An FIR filter and FIFO source files could sit in "/ sources/blackbox/fir_filter", and "/sources/blackbox/fifo", respectively. "blackbox" isn't special -- they could similarly be placed in "/sources/fir_filter", and "/sources/fifo", and the Makefile changed accordingly. Another valid option is to consider these cores as submodules with a build of their own, though I decided not to do that because these modules typically aren't significant enough to justify it. Generated files (.vhd/.v, .ngc, etc.) are placed in "/build/synthesis/ /", for example. The Makefile should know when to regenerate the required files if they are missing. Indeed, generating the .ngc files take a long time, so "/build/synthesis//" shouldn't be deleted too often... this can also be set up by the Makefile (i.e., selective clean of the various generated directories, as I have it in the example Makefile in the document for "syn" and "imp"). cheers, saar. From newsfish@newsfish Fri Dec 24 22:55:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!k11g2000vbf.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 14:31:10 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: <611bf397-eb75-429c-9738-c1397e23b0d9@k11g2000vbf.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> <0d80e6ec-227c-4db9-958a-7fe9cadf7139@n2g2000pre.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291674670 32051 127.0.0.1 (6 Dec 2010 22:31:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 22:31:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k11g2000vbf.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13601 comp.lang.verilog:2712 comp.lang.vhdl:4465 Considering that you may want to use a module as a submodule, parent modules will need to be able to find your submodule's generated macros (black-boxes) for their build (sim/synt/par). If you start copying files within a submodule you will not succeed cleaning it (from a parent modules view), or you need to clean the copies as well. Which one should the parent use? The original, or the copy? I found that, as long as I know where the submodule's generated items are stored, I could, for simulation, use a configuration to override paths using generics [vhdl]. For par (ngdbuild) use -sd to point out the macro. Synthesis treats it as a blackbox but I guess timing to/from the blackbox could/should be possible? In the cleaning process I excluded removing any macros (since they are quite time consuming to regenerate), however the build process still requires the macro-control-file (e.g. .xco) to be older than the macro-result-file (e.g. .mif, .ngc etc.). -- Pontus From newsfish@newsfish Fri Dec 24 22:55:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r40g2000prh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 14:43:18 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <15b96527-d885-46dc-88a5-2d67409def46@r40g2000prh.googlegroups.com> References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291675398 10527 127.0.0.1 (6 Dec 2010 22:43:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 22:43:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r40g2000prh.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4466 comp.arch.fpga:13603 On Dec 6, 12:50=A0pm, rickman wrote: > On Dec 6, 1:00=A0pm, Andy wrote: > > > I think I would use a function for the intermediate calculation, and > > then call the function in both concurrent assignment statements per > > the original implementation. > > > Integers give you the benefits of bounds checking in simulation (even > > below the 2^n granularity if desired), and a big improvement in > > simulation performance, especially if integers are widely used in the > > design (instead of vectors). > > > Andy > > I know everyone says that integers run faster, but is this a > significant effect? =A0Has it been measured or at least verified on > current simulators? > > Rick A few years back, I had a design for a small FPGA with several modules on a common bus. I started out with unsigned(4 downto 0) for the address, and each module decoded its own address (each was given a generic for address and size). Then I changed only that address to a natural with equivalent range. Just that one change sped up my RTL simulation from over 2.5 hours down to less than 1 hour. I considered it very significant... Andy From newsfish@newsfish Fri Dec 24 22:55:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Tue, 07 Dec 2010 14:09:41 +0100 Lines: 35 Message-ID: <8m6q0lFdgiU1@mid.individual.net> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /L/QUrL5u1dD0DSIH9nfmgm1gBwOw1NLA3heJNmVfGscxHH7vw Cancel-Lock: sha1:sXUWcDbTLylaOVlo8WJDpZ5JaXs= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4467 On 12/6/2010 6:14 PM, d_s_klein wrote: > On Dec 5, 2:46 pm, rickman wrote: >> >> Would it be easier to have ISim save the log to a file and then read >> the log to get a result? >> >> Rick > > Do what Rick says. > > Create a log file. At the very least, have the word PASS or FAIL > appear in the log file. > > Eventually you will want to have something in your log file to tell > you why and when the failure was detected. > > Hint: Assertions are your friend. > > RK Maybe I haven't quite well understood the topic, but you maybe interested in this thread: http://www.velocityreviews.com/forums/t57165-how-to-stop-simulation-in-vhdl.html One of the first replies from Mike Treseler point to a broken link which you may check here: http://mysite.ncnetwork.net/reszotzl/ It gives a very good approach to testbench and once there are no scheduled transitions any longer (through done_s signal) the simulation should stop automatically. Hope that helps, Al From newsfish@newsfish Fri Dec 24 22:55:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y19g2000prb.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Using integers for counters in synthesis Date: Tue, 7 Dec 2010 17:25:40 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291771541 31238 127.0.0.1 (8 Dec 2010 01:25:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 01:25:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y19g2000prb.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4468 Hi everyone, I have a simple question. Assuming we have this process : MY_PROCESS : process(CLK) variable cnt : natural range 0 to 255; begin if rising_edge(CLK) then output_signal <= '0'; if (srst = '1') then cnt := 0; else if (cnt = 100) then output_signal <= '1'; end if; cnt := cnt + 1; end if; end if; end process; In simulation, I will get an error at the rising edge of CLK when cnt is 255. However, what happens in synthesis? Will the synthesizer add logic to prevent cnt from wrapping aroung ? Or will it simply implement the "usual" wraparound behavior? Is it synthesizer specific? Best regards. Benjamin From newsfish@newsfish Fri Dec 24 22:55:52 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 00:57:48 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291798668 16217 127.0.0.1 (8 Dec 2010 08:57:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 08:57:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4469 On Dec 8, 1:25=A0am, Benjamin Couillard wrote: > Hi everyone, > > I have a simple question. Assuming we have this process : > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 output_signal <=3D '0'; > =A0 =A0 if (srst =3D '1') then > =A0 =A0 =A0 cnt :=3D 0; > =A0 =A0else > =A0 =A0 if (cnt =3D 100) then > =A0 =A0 =A0 =A0output_signal <=3D '1'; > =A0 =A0end if; > =A0 =A0cnt :=3D cnt + 1; > =A0 =A0end if; > =A0 end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? > > Best regards. > > Benjamin >From my experience, counters like this will just wrap in synthesis. The error you get is more to do with the VHDL type system rather than how it works on hardware. It is one danger of the VHDL types, but it might just be safer to stick with an Unsigned type in your code. Personally, If I want wrapping behaviour I use and unsigned, but if I always reset at a specific number, Ill use an integer. From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 08 Dec 2010 14:28:39 +0000 Organization: TRW Conekt Lines: 65 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net VV2EIBqXTLJ6RR97mtpJlwTEhYT9/U1MOOo0aQkqNhunxpaJ4= Cancel-Lock: sha1:D3laQNeyXQdwIc3q1q7rrQU37bQ= sha1:n9tPikeuFolDr8n4UFuS/yS98x8= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4470 Benjamin Couillard writes: > Hi everyone, > > I have a simple question. Assuming we have this process : > > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > if rising_edge(CLK) then > output_signal <= '0'; > if (srst = '1') then > cnt := 0; > else > if (cnt = 100) then > output_signal <= '1'; > end if; > cnt := cnt + 1; > end if; > end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. Quite right too, you're trying to push 256 into that variable and you've said "it can't happen" when you defined the range. > However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? In theory it's completely undefined - you've told the synthesiser that that variable can't be bigger than 255, so if you try and make it so, the synthesiser is probably within its rights to generate logic that shorts the power supplies and makes magic smoke issue forth from your FPGA :) In reality, no synthesiser I know of would implement this as anything other than an 8 bit counter which wraps around. HOWEVER... in order to keep your simulation matching your synthesis (which IMHO you must do), you should either: 1) Use an unsigned vector, for which wraparound behaviour is the defined behaviour on overflow. 2) Put some explicit code in to handle the overflow - the synthesiser will spot that it is unneeded in your case, and implement the same as it would've before. As an aside - if you find yourself using a different maximum for cnt (say 200 for example), and you don't do option 2) you'll likely find the synthesiser generating an 8 bit wraparound counter which will still count up to 255, making your sim and synth completely different... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Wed, 08 Dec 2010 16:47:38 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 79 Message-ID: <4cffa89a$0$14258$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 6677cd28.news.skynet.be X-Trace: 1291823258 news.skynet.be 14258 91.177.212.228:58239 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4471 Martin Thompson wrote: > Benjamin Couillard writes: > >> Hi everyone, >> >> I have a simple question. Assuming we have this process : >> >> >> MY_PROCESS : process(CLK) >> variable cnt : natural range 0 to 255; >> begin >> if rising_edge(CLK) then >> output_signal <= '0'; >> if (srst = '1') then >> cnt := 0; >> else >> if (cnt = 100) then >> output_signal <= '1'; >> end if; >> cnt := cnt + 1; >> end if; >> end if; >> end process; >> >> In simulation, I will get an error at the rising edge of CLK when cnt >> is 255. > > Quite right too, you're trying to push 256 into that variable and > you've said "it can't happen" when you defined the range. > >> However, what happens in synthesis? Will the synthesizer add >> logic to prevent cnt from wrapping aroung ? Or will it simply >> implement the "usual" wraparound behavior? Is it synthesizer >> specific? > > In theory it's completely undefined - you've told the synthesiser that > that variable can't be bigger than 255, so if you try and make it so, > the synthesiser is probably within its rights to generate logic that > shorts the power supplies and makes magic smoke issue forth from your > FPGA :) > > In reality, no synthesiser I know of would implement this as anything > other than an 8 bit counter which wraps around. > > HOWEVER... in order to keep your simulation matching your synthesis > (which IMHO you must do), you should either: > > 1) Use an unsigned vector, for which wraparound behaviour is the > defined behaviour on overflow. > > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. I agree that you have to fix your code like that, but not for any synthesis-related reason - simply because it is wrong. The run-time bound error proves that your there is a mismatch between the model and the design intent. You would have to fix the code regardless of whether the code is synthesisable or not. > As an aside - if you find yourself using a different maximum for cnt > (say 200 for example), and you don't do option 2) you'll likely find the > synthesiser generating an 8 bit wraparound counter which will still > count up to 255, making your sim and synth completely different... Again, I find this a very dangerous way of putting it. Now newbies may think that they should avoid integers because of sim/synth mismatches, which simply do not exist. It is meaningless to talk about mismatches beyond a simulation error. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: spacewire project on opencores.org Date: Wed, 08 Dec 2010 20:10:51 +0100 Lines: 68 Message-ID: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net xBQcxxZK/74unjF3eZBr+gduyTnNoYCvxRghw8aC+o7jXisvJJ Cancel-Lock: sha1:R3tRYDHX5pfWJjDYbRXzrVXn8t4= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 Xref: feeder.eternal-september.org comp.arch.fpga:13635 comp.lang.vhdl:4472 comp.lang.verilog:2714 Hi everyone, after some struggles I have eventually found the time to revive an old project on opencores which hasn't been updated since a while: a spacewire link and router. I have just been assigned as co-maintainer since the original one seems not available since a while. I intend to bring back the status of the project to "planning", since I would like to discuss again the structure of the project, starting from the specification documentation and the overall design structure. I'd like to stress that I am not a spacewire expert, but I have been working on a "modified" version of it that is in use in the AMS-02 experiment (http://ams.cern.ch) which is ready to be launched next year on the International Space Station. At the moment I would like to share my motivation, hoping to find some feedback and some interest. The purpose of the spacewire standard is (citation from the ECSSâ€Eâ€STâ€50â€12C): - to facilitate the construction of highâ€performance onâ€board dataâ€handling systems; - to help reduce system integration costs; - to promote compatibility between dataâ€handling equipment and subsystems; - to encourage reuse of dataâ€handling equipment across several different missions. In this respect a handful of firms have grown to provide SoC know-how and system integration capabilities to "serve" space exploration and space science. ESA for example is promoting R&D in order to improve european space industry sector. Even though I do understand the commercial impact of this approach, I still believe that we can do much more through an open platform, improving the quality of the solutions and allowing for a greater spectrum of products. In my limited experience I have been working on two space experiments (pamela.roma2.infn.it and ams.cern.ch) and witnessed other four at least (ALTEA, GLAST-FERMI, LAZIO-SiRAD, AGILE). A great deal of development was focused on the onboard data-handling systems, with ad-hoc interfaces and non-standard solutions. We had the possibility to adopt spacewire, but the "closed" solutions provided by the industry is rather counter productive in an open environment like the one of the academic collaborations we have (costs are rather high and liability is often unclear). This is where open IP cores may come in action and empower low-budget experiments to build reliable and reusable systems cutting the development costs and enabling them to focus on science. The industry itself may benefit from this approach, since a good licensing policy (like the LGPL) may foster interests and wide spread the usage (hence enhancing the reliability) of these IP cores. A more reliable and widely used standard gives a tremendous boost to our space related dreams and even though it's just a piece of wire, I believe it still build bridges worldwide. Any feedback is appreciated. Al p.s.: this post will be on opencores.org forum as well. -- Alessandro Basili CERN, PH/UGC Electronic Engineer From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 12:42:42 -0800 (PST) Organization: http://groups.google.com Lines: 56 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291840962 2696 127.0.0.1 (8 Dec 2010 20:42:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 20:42:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4473 On Dec 7, 6:25=A0pm, Benjamin Couillard wrote: > Hi everyone, > > I have a simple question. Assuming we have this process : > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 output_signal <=3D '0'; > =A0 =A0 if (srst =3D '1') then > =A0 =A0 =A0 cnt :=3D 0; > =A0 =A0else > =A0 =A0 if (cnt =3D 100) then > =A0 =A0 =A0 =A0output_signal <=3D '1'; > =A0 =A0end if; > =A0 =A0cnt :=3D cnt + 1; > =A0 =A0end if; > =A0 end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? > > Best regards. > > Benjamin Put a modulo 256 on the counter: count : process (clk) is variable cnt : natural range 0 to 255; begin if (srst =3D '1') then cnt :=3D 0; outreg <=3D '0'; elsif rising_edge(clk) then if (cnt =3D 100) then outreg <=3D '1'; else outreg <=3D '0'; end if; cnt :=3D (cnt + 1) mod 256; end if; end process count; The synthesis tool will recognize that the modulo is just there to prevent overflow in simulation and it gets optimized away in the hardware. -a From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o9g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 15:40:05 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <964571ef-a8be-4e49-b6f3-f4a031732a75@o9g2000pre.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291851605 389 127.0.0.1 (8 Dec 2010 23:40:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 23:40:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000pre.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4474 On Dec 8, 8:28=A0am, Martin Thompson wrote: > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. That depends on what code you put in there to "handle the overflow"... If your resulting code will not allow an overflow of the assignment, then you are removing the ambiguity caused by the illegal condition of an overflow. Absent the ambiguity, the synthesis tool will then be bound to replicate the resulting behavior, which may or may not be the same as before. A minor point: "the overflow" occurs only upon the assignment, not on the increment. It is perfectly legal to add 1 to cnt when cnt is 255 (the result is 256). What is not legal is to take that result and try to store it back into cnt! For example, (cnt + 1 > 255) is perfectly legal and meaningful with cnt: natural range 0 to 255. With cnt: unsigned (7 downto 0), it is also legal, but meaningless and will always evaluate as false. Using (cnt + 1 > 255) or (cnt - 1 < 0) as a conditional is an excellent way to efficiently detect a roll-over (by accessing the carry/borrow bit), but it only works for integer subtypes, not signed/unsigned. Andy From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s9g2000vby.googlegroups.com!not-for-mail From: Sebastien Bourdeauducq Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Thu, 9 Dec 2010 02:36:07 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> References: <8ma3hpF3caU1@mid.individual.net> NNTP-Posting-Host: 92.225.33.98 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291890968 26534 127.0.0.1 (9 Dec 2010 10:36:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Dec 2010 10:36:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000vby.googlegroups.com; posting-host=92.225.33.98; posting-account=8e6pLwoAAACvu9UuLn7G--_8cF5NYx8j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101027 Fedora/3.6.12-1.fc14 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13644 comp.lang.vhdl:4475 comp.lang.verilog:2716 On 8 d=E9c, 20:10, Alessandro Basili wrote: > after some struggles I have eventually found the time to revive an old > project on opencores which hasn't been updated since a while: I would not bother. Why not simply use GRLIB's code? http://www.gaisler.com/cms/index.php?option=3Dcom_content&task=3Dview&id=3D= 357&Itemid=3D82 While GRLIB also has some of the problems that plague most Opencores designs (namely, slowness and resource utilization through the roof), at least the cores work, are supported and are well documented. S. From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Thu, 09 Dec 2010 15:40:22 +0000 Organization: TRW Conekt Lines: 64 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <4cffa89a$0$14258$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net da3m/8yy0HLxFZHh9hM76wmFmonjlFo7eqTGGoTjZIzhBfBVw= Cancel-Lock: sha1:xMFtDkrll2qmnR2Ml01RgjUkuSc= sha1:DjfmncixDPDWz+Nt43MDxBjzqLU= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4476 Jan Decaluwe writes: > Martin Thompson wrote: >> HOWEVER... in order to keep your simulation matching your synthesis >> (which IMHO you must do), you should either: >> >> 1) Use an unsigned vector, for which wraparound behaviour is the >> defined behaviour on overflow. >> >> 2) Put some explicit code in to handle the overflow - the synthesiser >> will spot that it is unneeded in your case, and implement the same as >> it would've before. > > I agree that you have to fix your code like that, but not for any > synthesis-related reason - simply because it is wrong. The run-time > bound error proves that your there is a mismatch between the model > and the design intent. Yes - I didn't mean to imply it was for a synthesis-related issue. The question asked what would happen - I answered. Then followed up with: >> HOWEVER... in order to keep your simulation matching your synthesis >> (which IMHO you must do), you should either: the implication of "you must do" was intended to be "it's wrong without it" - but I can see it might not be strong enough. Or maybe I should've written "to keep your simulation matching your design intent". > You would have to fix the code regardless > of whether the code is synthesisable or not. > Well, yes, if the simulation is dying like that, something is wrong. I read the question (accurately or not!) to be more "it'll die in sim, but I reckon it'll be alright in the real hardware, do I need to bother with it?" - to which I was trying to say "YES!" > >> As an aside - if you find yourself using a different maximum for cnt >> (say 200 for example), and you don't do option 2) you'll likely find the >> synthesiser generating an 8 bit wraparound counter which will still >> count up to 255, making your sim and synth completely different... > > Again, I find this a very dangerous way of putting it. Now newbies > may think that they should avoid integers because of sim/synth > mismatches, which simply do not exist. Well, that certainly wasn't my intent, sorry! > It is meaningless to talk about mismatches beyond a simulation > error. Yes - assuming your simulation is good enough to show the error. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:53 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Thu, 09 Dec 2010 16:41:57 +0100 Lines: 30 Message-ID: <8mcbm2F5foU1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net uBd6bqOpBbGwdwq/emJs7A3TbFQLosmBNX6fUavDdyfW0LsIW3 Cancel-Lock: sha1:Z6ySQ/u2ouFxOYY03WGqmIYR5xw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> Xref: feeder.eternal-september.org comp.arch.fpga:13648 comp.lang.vhdl:4477 comp.lang.verilog:2717 On 12/9/2010 11:36 AM, Sebastien Bourdeauducq wrote: > On 8 déc, 20:10, Alessandro Basili wrote: >> after some struggles I have eventually found the time to revive an old >> project on opencores which hasn't been updated since a while: > > I would not bother. Why not simply use GRLIB's code? > http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=357&Itemid=82 > While GRLIB also has some of the problems that plague most Opencores > designs (namely, slowness and resource utilization through the roof), > at least the cores work, are supported and are well documented. > > S. I believe you are referring to the gpl package and not to the copyrighted version. I don't quite believe you would have so much support (at least from them) unless you get the proprietary one and secondly the GRLIB promotes the AMBA bus as SoC, which is a rather complex bus compared to the Wishbone. IMHO GRLIB is a great effort to provide a fully integrated system on chip (either FPGA or ASIC) that I do not dare to achieve (or compete against). On the contrary my intent is to have a simple enough IP Core which can be easily integrated and reused in order to promote the protocol. But I do appreciate your comment and I will consider the possibility to publish only the spacewire part out of the whole library, maybe stripping off the amba interface, even though I need to evaluate the licensing issue. Al From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Thu, 09 Dec 2010 15:42:19 +0000 Organization: TRW Conekt Lines: 32 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <964571ef-a8be-4e49-b6f3-f4a031732a75@o9g2000pre.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net hvrGXpKpXMP2HDOQ5u18JQIWHq8unE6ZdRd5dm1REd2o++Djs= Cancel-Lock: sha1:j5SdB/igIWnckirD/T0OS6zcNRY= sha1:a9bly7p2+5/9528fp4W1LpEb3RA= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4478 Andy writes: > On Dec 8, 8:28 am, Martin Thompson wrote: >> 2) Put some explicit code in to handle the overflow - the synthesiser >> will spot that it is unneeded in your case, and implement the same as >> it would've before. > > That depends on what code you put in there to "handle the overflow"... > OK, yes - assuming the code you put in there makes it wrap around to zero (which is what I meant by "in your case") > If your resulting code will not allow an overflow of the assignment, > then you are removing the ambiguity caused by the illegal condition of > an overflow. Absent the ambiguity, the synthesis tool will then be > bound to replicate the resulting behavior, which may or may not be the > same as before. > Yes, if you make it saturate for example, the synthesiser (of course) will add logic to replicate your saturation requirement. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p38g2000vbn.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Fri, 10 Dec 2010 06:57:43 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <8ma3hpF3caU1@mid.individual.net> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291993063 29419 127.0.0.1 (10 Dec 2010 14:57:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 14:57:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p38g2000vbn.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13667 comp.lang.vhdl:4479 comp.lang.verilog:2718 On 8 Dez., 20:10, Alessandro Basili wrote: > after some struggles I have eventually found the time to revive an old > project on opencores which hasn't been updated since a while: > > a spacewire link and router. > [..] > > Any feedback is appreciated. I think spacewire is not the best example for open cores (At least unless you manage to get ESA as co-supporter which is unlikely as ESA has allready spacewire cores). Open cores tend to have a lack in documentation and verification, which is a no-go for developing space electronics. Even if you target on public science projects it is very likely that you need to ensure the "space-readiness" in many aspects for a core before you can use it. For spacewire interface I consider the effort to proof the quality of a core clearly exceeding the effort for writting the core for your own. Are you firm with developing according to ECSS-Q 60 02? I would expect a core development to be complaint to this before using it without further quality checking in case of the core not beeing provided from ESA for a ESA project. In case of detailed questions you may also conntact me by sending an email. You should change the receive-address to thomas @domain_from_email when replying. best regards Thomas From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!postnews.google.com!v23g2000vbi.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 13:13:14 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> NNTP-Posting-Host: 83.188.231.12 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292015594 3792 127.0.0.1 (10 Dec 2010 21:13:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 21:13:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v23g2000vbi.googlegroups.com; posting-host=83.188.231.12; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4480 Consider the following system: inp_clk -- Input clock to FPGA (Xilinx Spartan 3A DSP) -- directly routed to DCM -- PERIOD constraint attached to it -- Frequency: 125 MHz clk_25 -- CLKDV_OUT from DCM -- Frequency: 25 MHz clk_28 -- CLKFX_OUT from DCM -- Frequency: inp_clk*7/31 MHz clk_250k -- Output from a VHDL-module that divides the clk_25 with 100 -- Frequency: 250 kHz CTRL_PROC : process (clk_250k) begin if rising_edge(clk_250k) then if reset =3D '1' then reg1 <=3D '0'; else if byte_received =3D '1' then if data_in =3D =9310101010=94 then reg1 <=3D '1'; else reg1 <=3D '0'; end if; end if; end if; end if; end process; CNT_PROC : process (clk_28) begin if rising_edge(clk_28) then if reset =3D '1' then cnt <=3D (others =3D> =910=92); else if reg1 =3D '1' then cnt <=3D cnt + 1; else cnt <=3D cnt - 1; end if; end if; end if; end process; reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it is crossing clock domains. Do I need to worry about that in the above situation and apply some asynchronous clock domain techniques? I=92m asking since the two clocks actually are related to each other. So, main question: When are two clock domains actually considered asynchronous? Some related questions. How does ISE/XST handle the situation? As I understand the Xilinx software automatically derives a new PERIOD for each of the DCM output clocks and determines the clock relationships between the output clock domains. There will probably be moments where the edges of the two clocks are so close that the timing won=92t be met. Do I need to insert a FALSE PATH constraint in this case? And, last question, should I put the clk_250k on a global clock path? Regards Beppe From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o4g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 14:28:13 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292020093 11120 127.0.0.1 (10 Dec 2010 22:28:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 22:28:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000yqd.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4481 On Dec 10, 4:13=A0pm, Beppe wrote: > Consider the following system: > > inp_clk =A0 -- Input clock to FPGA (Xilinx Spartan 3A DSP) > =A0 =A0 =A0 =A0 =A0 -- directly routed to DCM > =A0 =A0 =A0 =A0 =A0 -- PERIOD constraint attached to it > =A0 =A0 =A0 =A0 =A0 -- Frequency: 125 MHz > > clk_25 =A0 =A0-- CLKDV_OUT from DCM > =A0 =A0 =A0 =A0 =A0 -- Frequency: 25 MHz > > clk_28 =A0 =A0-- CLKFX_OUT from DCM > =A0 =A0 =A0 =A0 =A0 -- Frequency: inp_clk*7/31 MHz > > clk_250k =A0 -- Output from a VHDL-module that divides the clk_25 with > 100 clk_250k will be a problem in an FPGA. In an FPGA environment, you basically almos never want to generate a clock with logic. Even when it comes out of a flip flop you're most likely doomed. > =A0 =A0 =A0 =A0 =A0 -- Frequency: 250 kHz > > CTRL_PROC : process (clk_250k) > begin > =A0if rising_edge(clk_250k) then Yep...doomed > =A0 end if; > =A0end if; > end process; > > CNT_PROC : process (clk_28) > begin > =A0if rising_edge(clk_28) then > =A0 if reset =3D '1' then > =A0 =A0cnt <=3D (others =3D> =910=92); > =A0 else > =A0 =A0if reg1 =3D '1' then > =A0 =A0 cnt <=3D cnt + 1; > =A0 =A0else > =A0 =A0 cnt <=3D cnt - 1; > =A0 =A0end if; > =A0 end if; > =A0end if; > end process; > > reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it > is crossing clock domains. Do I need to worry about that in the above > situation and apply some asynchronous clock domain techniques? Yes and no. - Since you created two clocks, then yes you should treat them as if they are unrelated. - What you should do is generate a clock enable for rather than a clock for the 250k. Then both processes are running in the same clock domain...no clock crossings at all. Instead of this... process(clk_250k) begin if rising_edge(clk_250k) then ... end if; end process; Do this... process(clk) begin if rising_edge(clk) then if (clkenable_250k) then ... end if; end if; end process; Where clkenable_250k is generated by your VHDL code to be exactly one clock cycle in your 0 to 99 counter. > > And, last question, should I put the clk_250k on a global clock path? > No...because you should be getting rid of it as a clock and using it as a clock enable instead. Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Are HDLs Misguided? Date: Fri, 10 Dec 2010 20:25:58 -0800 (PST) Organization: http://groups.google.com Lines: 44 Message-ID: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 76.100.125.243 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292041558 6417 127.0.0.1 (11 Dec 2010 04:25:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 04:25:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=76.100.125.243; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4482 Sometimes I wonder if HDLs are really the right way to go. I mainly use VHDL which we all know is a pig in many ways with its verbosity and arcane type conversion gyrations. But what bothers me most of all is that I have to learn how to tell the tools in their "language" how to construct the efficient logic I can picture in my mind. By "language" I don't mean the HDL language, but actually the specifics of a given inference tool. What I mean is, if I want a down counter that uses the carry out to give me an "end of count" flag, why can't I get that in a simple and clear manner? It seems like every time I want to design a circuit I have to experiment with the exact style to get the logic I want and it often is a real PITA to make that happen. For example, I wanted a down counter that would end at 1 instead of 0 for the convenience of the user. To allow a full 2^N range, I thought it could start at zero and run for the entire range by wrapping around to 2^N-1. I had coded the circuit using a natural range 0 to (2^N)-1. I did the subtraction as a simple assignment foo <= foo -1; I fully expected that even if it were flagged as an error in simulation to load a 0 and let it count "down" to (2^N)-1, it would work in the real world since I stop the down counter when it gets to 1, not zero. Loading a zero in an N bit counter would work just fine wrapping around. But to make the simulation the same as the real hardware I expected to get, I thought adding some simple code to handle the wrap around might be good. So the assignment was done modulo 2^N. But the synthesis size blew up to nearly double the size without the "mod" function added, mostly additional adders! I didn't have time to explore what caused this so I just left out the modulo operation and will live with what I get for the case of loading a zero starting value. I guess what I am trying to say is I would like to be able to specify detailed logic rather than generically coding the function and letting a tool try to figure out how to implement it. This should be possible without the issues of instantiating logic (vendor specific, clumsy, hard to read...). In an ideal design world, shouldn't it be pretty easy to infer logic and to actually know what logic to expect? Rick From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z19g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 20:44:33 -0800 (PST) Organization: http://groups.google.com Lines: 120 Message-ID: <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> NNTP-Posting-Host: 76.100.125.243 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292042673 15819 127.0.0.1 (11 Dec 2010 04:44:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 04:44:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000yqb.googlegroups.com; posting-host=76.100.125.243; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4483 I can't say I totally agree with the doom and gloom predictions of KJ... On Dec 10, 5:28 pm, KJ wrote: > On Dec 10, 4:13 pm, Beppe wrote: > > > Consider the following system: > > > inp_clk -- Input clock to FPGA (Xilinx Spartan 3A DSP) > > -- directly routed to DCM > > -- PERIOD constraint attached to it > > -- Frequency: 125 MHz > > > clk_25 -- CLKDV_OUT from DCM > > -- Frequency: 25 MHz > > > clk_28 -- CLKFX_OUT from DCM > > -- Frequency: inp_clk*7/31 MHz > > > clk_250k -- Output from a VHDL-module that divides the clk_25 with > > 100 > > clk_250k will be a problem in an FPGA. In an FPGA environment, you > basically almos never want to generate a clock with logic. Even when > it comes out of a flip flop you're most likely doomed. I agree that generating a clock from a counter is not a good idea. But it is not a fatal flaw if handled correctly. But you are better off using a clock enable unless there is a reason. > > -- Frequency: 250 kHz > > > CTRL_PROC : process (clk_250k) > > begin > > if rising_edge(clk_250k) then > > Yep...doomed Isn't that a bit dramatic? If the tools properly recognize this signal as a clock and routes it on a clock spline, and you treat it as a separate clock with no clear timing relation to the clock it is generated from, then there shouldn't be any problem. Actually, I have seen the tools not use a clock spline and they seem to handle it correctly, recognizing it as a clock but routing it on the local interconnect. > > end if; > > end if; > > end process; > > > CNT_PROC : process (clk_28) > > begin > > if rising_edge(clk_28) then > > if reset =3D '1' then > > cnt <=3D (others =3D> =910=92); > > else > > if reg1 =3D '1' then > > cnt <=3D cnt + 1; > > else > > cnt <=3D cnt - 1; > > end if; > > end if; > > end if; > > end process; > > > reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it > > is crossing clock domains. Do I need to worry about that in the above > > situation and apply some asynchronous clock domain techniques? > > Yes and no. > - Since you created two clocks, then yes you should treat them as if > they are unrelated. > - What you should do is generate a clock enable for rather than a > clock for the 250k. Then both processes are running in the same clock > domain...no clock crossings at all. > > Instead of this... > process(clk_250k) > begin > if rising_edge(clk_250k) then > ... > end if; > end process; > > Do this... > process(clk) > begin > if rising_edge(clk) then > if (clkenable_250k) then > ... > end if; > end if; > end process; > > Where clkenable_250k is generated by your VHDL code to be exactly one > clock cycle in your 0 to 99 counter. > > > > > And, last question, should I put the clk_250k on a global clock path? > > No...because you should be getting rid of it as a clock and using it > as a clock enable instead. I don't think you can easily put a signal on a global clock line. If the tools recognize it as a clock, because it drives the clock input of a FF, it will consider if it needs to use a global clock line to control skew. If so it will use one. If not it won't. There are times when you don't want to use an enable. A design I did generates a clock enable to control some circuitry. But the input and output of the data signals need to be done on the actual clock edges to optimize the setup and hold times of the external signals. So the data input and output are run through a FF clocked by the clock I am generating and then I deal with the data timing as required. Rick From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: process vs instance Date: Fri, 10 Dec 2010 22:40:16 -0800 Lines: 58 Message-ID: <4D031CD0.2070208@gmail.com> References: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net fdigJyMlKz9awAEpnwqKMQExZ7MiiCwCukM77t9xgCdwshk3Ql Cancel-Lock: sha1:VpnHtKbBCsHcMjFx3107WAqR7bM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <8ma3hpF3caU1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4484 On Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote: > Dear Mr. Treseler, > few years ago I followed quite closely the comp.arch.fpga and comp.lang.vhdl > groups and I was fascinated by your template project especially the > testbench style, that I adopted since then. ... > Talking about your template, how do you see multiple component instantiation > and port mapping, as opposed to your procedural template? My top entity is a collection of direct instances of single process entities with port maps. I use the Quartus rtl viewer to draw a block diagram from my functional code. I use a template to simplify the synthesis of variables. > I believe that component instantiation offers a black-box view pretty much > like a schematic entry and it's easy to me to follow, while I don't have > that picture through your procedural template. Am I missing something? I agree at the top level. I like to see the wired view, but I let quartus draw it for me. I also click on on one of the top blocks on the rtl viewer to verify the structural view of my procedural entity. > Do you think a single process, as opposed to many of them, will simplify the > datapath and allow for better maintainance of the code? I instance single process entities at the top level. I prefer to connect large boxes at the port map level to connecting processes at the architecture level. > What is the gain of having variables as opposed to signals? I can write functional/procedural code for synthesis using standard vhdl source code. > I am very used > to signals since I always though that the way values are assigned to a > signal follow pretty much what happens on hardware, while for a variable > there is an abstraction that I am not accustomed to. I am very used to writing, siming and tracing code descriptions with immediate assignments, and letting synthesis sort out the LUTs and flops using my template. > I hope I haven't bother you too much with my questions. > Best regards, > > Al Not a bother in the least. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:54 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder7.xlned.com!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 11 Dec 2010 14:53:40 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 65 Message-ID: <4d038263$0$14246$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b1451aab.news.skynet.be X-Trace: 1292075619 news.skynet.be 14246 91.177.205.212:59992 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4485 rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. > > What I mean is, if I want a down counter that uses the carry out to > give me an "end of count" flag, why can't I get that in a simple and > clear manner? It seems like every time I want to design a circuit I > have to experiment with the exact style to get the logic I want and it > often is a real PITA to make that happen. > > For example, I wanted a down counter that would end at 1 instead of 0 > for the convenience of the user. To allow a full 2^N range, I thought > it could start at zero and run for the entire range by wrapping around > to 2^N-1. I had coded the circuit using a natural range 0 to > (2^N)-1. I did the subtraction as a simple assignment > > foo <= foo -1; > > I fully expected that even if it were flagged as an error in > simulation to load a 0 and let it count "down" to (2^N)-1, it would > work in the real world since I stop the down counter when it gets to > 1, not zero. Loading a zero in an N bit counter would work just fine > wrapping around. > > But to make the simulation the same as the real hardware I expected to > get, I thought adding some simple code to handle the wrap around might > be good. So the assignment was done modulo 2^N. But the synthesis > size blew up to nearly double the size without the "mod" function > added, mostly additional adders! I didn't have time to explore what > caused this so I just left out the modulo operation and will live with > what I get for the case of loading a zero starting value. Ok. So you didn't have time to explore the issue, but you have all the time in world to write a lengthy post spreading FUD and jumping to all kinds of Big Conclusions? There, as is commonly known, no reason why modulo a power of 2 (hint) would generate additional hardware, and there is overwhelming evidence that decent synthesis tools do this just right. Therefore, if you think you see this, the proper reaction is to be very intruigued and switch to fanatic bug-hunting mode. Do that please (or trick others into doing it for you). Chances are that we will not here about the issue again. All the rest is a waste of everybody's time. > I guess what I am trying to say is I would like to be able to specify > detailed logic rather than generically coding the function and letting > a tool try to figure out how to implement it. This should be possible > without the issues of instantiating logic (vendor specific, clumsy, > hard to read...). In an ideal design world, shouldn't it be pretty > easy to infer logic and to actually know what logic to expect? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.karotte.org!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 11 Dec 2010 10:20:17 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Sat, 11 Dec 2010 16:21:24 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <1k87g6pgurrcujr2hnhjl8pb6q5see2jj5@4ax.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 45 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-GSNjZRqf6evFBIDgh/5Eq6IkdmYnGd+XCcK7HlTo2fVEbY97uVFA8QaN42TuxzwPywtM47fs855h09v!zarDXlLP+4bU9NPt4YlXl0+bdZRogvW18MIfhU9qb1RirFjC7xqgk3gX6+CVgTtult7PMkjEqhab!BxM= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2542 Xref: feeder.eternal-september.org comp.lang.vhdl:4486 On Tue, 7 Dec 2010 17:25:40 -0800 (PST), Benjamin Couillard wrote: >Hi everyone, > >I have a simple question. Assuming we have this process : > > >MY_PROCESS : process(CLK) >variable cnt : natural range 0 to 255; >begin > if rising_edge(CLK) then > output_signal <= '0'; > if (srst = '1') then > cnt := 0; > else > if (cnt = 100) then > output_signal <= '1'; > end if; > cnt := cnt + 1; > end if; > end if; >end process; > >In simulation, I will get an error at the rising edge of CLK when cnt >is 255. As you should. Wrapping round is always an error in integer arithmetic. (Relying on that error is ... IMO, not best practice) If you want wrapround from 255 to 0, you want a modular type - as others point out, numeric_std.unsigned meets your needs. Or you could make the wrapround explicit using the "mod" operator. This is more flexible since the "mod" value can be something other than 256. >However, what happens in synthesis? Anything at all, since you have presumably fixed the error during simulation ;-) Conventionally, synthesis tools will treat the error condition as a "don't care" and implement the smallest (or fastest) logic they can ... which may even be exactly what you wanted. Or not... - Brian From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m37g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 08:29:50 -0800 (PST) Organization: http://groups.google.com Lines: 65 Message-ID: <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292084990 3473 127.0.0.1 (11 Dec 2010 16:29:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 16:29:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m37g2000vbn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4487 On Dec 10, 11:44=A0pm, rickman wrote: > I can't say I totally agree with the doom and gloom predictions of > KJ... > > clk_250k will be a problem in an FPGA. =A0In an FPGA environment, you > > basically almos never want to generate a clock with logic. =A0Even when > > it comes out of a flip flop you're most likely doomed. > > I agree that generating a clock from a counter is not a good idea. > But it is not a fatal flaw if handled correctly. =A0 The only way to 'handle it correctly' will be to treat it as an independent clock domain and design in clock domain crossing logic. Without that, you'll be running into hold time issues with any signal originating from the high speed clock domain that enters the generated clock domain. You can't do anything about those issues except re- route, cross your fingers and hope. Yes you can hand hold a design and get it to work, but before you do so there should be a compelling reason to do so. No such reason was posted. > > > CTRL_PROC : process (clk_250k) > > > begin > > > =A0if rising_edge(clk_250k) then > > > Yep...doomed > > Isn't that a bit dramatic? =A0 No. I would characterize the OP's odds of success as 'low'. At best, he would find that he is never able to get the design working right out of the shoot, abandon the approach and will end up with more knowledge. That would be a good outcome. At worst, the design would be going into production when there starts to become a growing pile of boards that seem to have a 'temperature sensitivity' or 'date code issue'. What is your definition of 'doomed'? >If the tools properly recognize this > signal as a clock and routes it on a clock spline, and you treat it as > a separate clock with no clear timing relation to the clock it is > generated from, But the OP clearly doesn't know this if you read the post. > > There are times when you don't want to use an enable. =A0A design I did > generates a clock enable to control some circuitry. =A0But the input and > output of the data signals need to be done on the actual clock edges > to optimize the setup and hold times of the external signals. =A0So the > data input and output are run through a FF clocked by the clock I am > generating and then I deal with the data timing as required. > But in those situations, you don't have any logic being implemented in the clock domain crossing as was in the OP. In the posted code, the signals reset, byte_received and data_in probably originate in some other domain and are crossing; reg1, as noted by the OP definitely does come from a foreign clock domain and is not treated properly. The clock domain crossing looks like this... Synced_To_Clock_Signal <=3D Synced_To_Other_Clock_Signal when rising_edge(Clock); Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 11 Dec 2010 10:43:39 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sat, 11 Dec 2010 16:44:46 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-deJum5YTwWOHmAr2P5K7+r30UAm12RCnH79DJpoi+rmHrr5FaK/wdCV6IdcV4xCMQ1ivb0fyHMEcXlX!ha9xzeUibLjHhV8GOiKnL2vuuRlH2ULz8lU58nvwUhtd/8r/s0QDL/1dBio6vznWrMe4C5wTMKfd!/18= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3139 Xref: feeder.eternal-september.org comp.lang.vhdl:4488 On Fri, 10 Dec 2010 20:25:58 -0800 (PST), rickman wrote: >Sometimes I wonder if HDLs are really the right way to go. I mainly >use VHDL which we all know is a pig in many ways with its verbosity >and arcane type conversion gyrations. I usually find that the gyrations are a hint to step back and see what aspect of the design I have missed... I end up needing a few, but YMMV. > But what bothers me most of all >is that I have to learn how to tell the tools in their "language" how >to construct the efficient logic I can picture in my mind. By >"language" I don't mean the HDL language, but actually the specifics >of a given inference tool. > >What I mean is, if I want a down counter that uses the carry out to >give me an "end of count" flag, why can't I get that in a simple and >clear manner? Here the issue appears to be how to get at the carry out of a counter... the syntax of integer arithmetic doesn't provide an easy way to do that by default, in any language I know (other than assembler for pre-RISC CPUs, with their flag registers). It seems to me that you have two choices ... (1) implement an n-bit counter, and augment it in some way to recreate the carry out (unfortunately you are fighting the synthesis tool in the process) (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and trust the synthesis tool to eliminate the excess flip-flop at the optimisation stage... I am willing to guess the second approach would be simpler. Even if the obvious optimisation doesn't happen (and I bet it does) it's worth asking if your design is sensitive to the cost of that FF. Can you boil down what you are trying to do (and doesn't work) into a test case? > In an ideal design world, shouldn't it be pretty >easy to infer logic and to actually know what logic to expect? I would say so. And I'm still hoping to live to see it! - Brian From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 12:43:12 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> NNTP-Posting-Host: 83.188.245.33 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292100195 5473 127.0.0.1 (11 Dec 2010 20:43:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 20:43:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=83.188.245.33; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4489 Thanks for the answers. An enable won=92t solve the problem of crossing clock domains. With an enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC would still be clocked by clk_28. clk_28 =3D 35/31*clk_25. I=92m aware of the problem with logic generated clocks, but I hope that Rick is right here. Putting the clock on a low skew global clock net should be enough to ensure that hold and setup times are met. Actually, when synthesizing the design, XST infers a BUFG on the clk_250k, as you predicted Rick, and the design seems to be working fine in hardware although I haven=92t made any extensive tests yet. I was first thinking that it would be okay to put the clk_250k on a non-dedicated clock net because of its low frequency, but the frequency doesn=92t matter here if I=92m right when rethinking it. The output of a flip-flop (as a result of the flip-flop being clocked by a clock edge) could be propagating to the next flip-flop before the same clock edge clocks the next flip-flop and thus leading to a hold time violation no matter the frequency. Right? On a side note, a solution for clocks with excessive skew (on non- global clock nets) should be to alternate between positive and negative clock edges on every other register. That would cut the performance by half, but if it=92s applied on low frequency clocks it doesn=92t really matter. Is this a no, no technique or would I be fine using it? As for the original question I guess I could simply find the minimum distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is what ISE/XST should do if I understand the documentation correctly). That time would be the =93new=94 timing constraint. If it=92s impossible to meet this new timing I need to use asynchronous clock domain techniques, otherwise it would be just fine. > In the posted code, the > signals reset, byte_received and data_in probably originate in some > other domain and are crossing; reg1, as noted by the OP definitely > does come from a foreign clock domain and is not treated properly. data_in and byte_received are registers clocked by clk_250k and originate from a MIDI UART. The clk_250k frequency is eight times the 31.25 kbaud rate of the MIDI interface and used to retrieve the asynchronous serial MIDI data. Beppe From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: process vs instance Date: Sat, 11 Dec 2010 22:13:26 +0100 Lines: 80 Message-ID: <8mi7rkFue0U1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> <4D031CD0.2070208@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 43OlmDpPQbTr9OvVGCiMKwQ4+x4tZAcgFU9t2AMKsgUG64gY+g Cancel-Lock: sha1:e4N4O8yXrYabNgb37o6Oc3nX1QA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <4D031CD0.2070208@gmail.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4490 On 12/11/2010 7:40 AM, Mike Treseler wrote: > On Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote: > > Dear Mr. Treseler, > > few years ago I followed quite closely the comp.arch.fpga and > comp.lang.vhdl > > groups and I was fascinated by your template project especially the > > testbench style, that I adopted since then. > ... > > Talking about your template, how do you see multiple component > instantiation > > and port mapping, as opposed to your procedural template? > > > My top entity is a collection of direct > instances of single process entities with port maps. Understood. Indeed one of my biggest problem is where to put the boundaries of a component to allow for reusability. But I got your point of having top levels (which may as well be part of a bigger project) populated only by components instantiation through port mapping, while hiding the logic as much as possible. > I use the Quartus rtl viewer to draw a block diagram > from my functional code. Do you know of any open-source software capable of doing that? > > > I believe that component instantiation offers a black-box view pretty > much > > like a schematic entry and it's easy to me to follow, while I don't have > > that picture through your procedural template. Am I missing something? > > I agree at the top level. > I like to see the wired view, but I let quartus draw it for me. > I also click on on one of the top blocks on the rtl viewer > to verify the structural view of my procedural entity. > Actually this is the hardest part for me. If I see pretty well the single flops and gates in a multi-process and concurrent assignments style, I lack the overall structure view and most of the time I need to draw down (what I call "paper simulation") the datapath. Indeed your template collects all the flops and the assignments in one single tidy place. procedure template_v_rst is -- My default. begin -- a_rst is logically equivalent if reset = '1' then -- Assumes synched trailing edge reset pulse init_regs; -- reg_v := init_c; Variables only, ports below. elsif rising_edge(clock) then update_regs; -- reg_v := f(reg_v);Variables only, ports below. end if; -- Synchronous init optional (state_v = idle_c) update_ports; -- will infer port wires ok for reset and clock end procedure template_v_rst; -- out_port <= reg_v; ports only, -- no signals which is only saying that a reset will initialize all the registers and the clock will update them all, instead of doing this for every single flop/register/counter in the architecture. > > What is the gain of having variables as opposed to signals? > > I can write functional/procedural code for synthesis > using standard vhdl source code. > Apologize but I didn't get your answer. What do you mean with functional/procedural code? and what is standard vhdl? Is there a non-standard vhdl? > > I hope I haven't bother you too much with my questions. > > Best regards, > > > > Al > > Not a bother in the least. > > -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sat, 11 Dec 2010 13:21:57 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <733eea6c-b8b0-4809-9073-5e6910ac9aca@f20g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 188.28.106.60 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292102517 30991 127.0.0.1 (11 Dec 2010 21:21:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 21:21:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=188.28.106.60; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; InfoPath.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4491 On 11 Dec, 04:25, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. =A0But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. I find the tools wierd sometimes, but they have their own style for logic minimization. Like I only considered doubling the memory size by having two routines to do 2 hi bits of jump, and then use bytes instead of 16 bit words. Strange but it also makes the hardware smaller!! I have also been considering using preseting special values in the cycle before a general load, instead of an if/else in the same cycle. I also think the hardest part is specifying to the sythesis tool, how external memory supplies a result after an access delay, and how to make this delay relative to the synthesized fmax., not just in ns. Cheers Jacko From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: process vs instance Date: Sat, 11 Dec 2010 14:53:19 -0800 Lines: 99 Message-ID: <4D0400DF.6050507@gmail.com> References: <8ma3hpF3caU1@mid.individual.net> <4D031CD0.2070208@gmail.com> <8mi7rkFue0U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net gfP35MmZWq9MZ4V2b8v75gSz+1HyUyKAqChRWDQqqTCFLzJQb+ Cancel-Lock: sha1:3uQJHZi1PCNwClKr2M0lyjuUMYc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <8mi7rkFue0U1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4492 On 12/11/2010 1:13 PM, Alessandro Basili wrote: >> > Talking about your template, how do you see multiple component >> instantiation >> > and port mapping, as opposed to your procedural template? >> My top entity is a collection of direct >> instances of single process entities with port maps. > > Understood. Indeed one of my biggest problem is where to put the > boundaries of a component to allow for reusability. But I got your point > of having top levels (which may as well be part of a bigger project) > populated only by components instantiation through port mapping, while > hiding the logic as much as possible. That's it. Note that direct instances do not require a component declaration. >> I use the Quartus rtl viewer to draw a block diagram >> from my functional code. > Do you know of any open-source software capable of doing that? No, but the free version of quartus/modelsim has it. That is a good starting point for a trial design. >> > I believe that component instantiation offers a black-box view pretty >> much >> > like a schematic entry and it's easy to me to follow, while I don't >> have >> > that picture through your procedural template. Am I missing something? >> I agree at the top level. >> I like to see the wired view, but I let quartus draw it for me. >> I also click on on one of the top blocks on the rtl viewer >> to verify the structural view of my procedural entity. > Actually this is the hardest part for me. If I see pretty well the > single flops and gates in a multi-process and concurrent assignments > style, I lack the overall structure view and most of the time I need to > draw down (what I call "paper simulation") the datapath. Imagine a vhdl description of the muxes and registers in this schematic of a register stack: http://mysite.ncnetwork.net/reszotzl/stack.pdf Now compare that description to the 13 lines of code in the update_regs procedure here: http://mysite.ncnetwork.net/reszotzl/stack.vhd > Indeed your template collects all the flops and the assignments in one > single tidy place. Yes. That's the idea. > procedure template_v_rst is -- My default. > begin -- a_rst is logically equivalent > if reset = '1' then -- Assumes synched trailing edge reset pulse > init_regs; -- reg_v := init_c; Variables only, ports below. > elsif rising_edge(clock) then > update_regs; -- reg_v := f(reg_v);Variables only, ports below. > end if; -- Synchronous init optional (state_v = idle_c) > update_ports; -- will infer port wires ok for reset and clock > end procedure template_v_rst; -- out_port <= reg_v; ports only, > -- no signals > > which is only saying that a reset will initialize all the registers and > the clock will update them all, instead of doing this for every single > flop/register/counter in the architecture. Yes, I still have to write the 3 procedures and run a sim to check them, but note that the stack code is working on an abstract array of 32 bit registers. >> > What is the gain of having variables as opposed to signals? >> >> I can write functional/procedural code for synthesis >> using standard vhdl source code. >> > > Apologize but I didn't get your answer. What do you mean with > functional/procedural code? Code using variables, functions and procedures for hardware synthesis. > Is there a > non-standard vhdl? There are functional languages based on c or python that can *generate* vhdl code. That is different than just using vhdl source code to do the same thing. Good luck. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:55:55 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!k3g2000vbp.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 14:57:27 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <0c238b88-4be4-49bb-8aba-d82ba72af2b1@k3g2000vbp.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 83.188.245.33 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292108248 12319 127.0.0.1 (11 Dec 2010 22:57:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 22:57:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000vbp.googlegroups.com; posting-host=83.188.245.33; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4493 > (Hm, exactly this is > what ISE/XST should do if I understand the documentation correctly). And it does. Another good reason for using clock enables in this particular case (and probably in other cases as well) and not the derived clock is that XST sees the relationship between clk_25 and clk_28 when a source register is clocked by the first and the destination register is clocked by the second. A test (not with the exact processes above) reveals this. Timing report: Slack: -5.319ns (requirement =96 (data path - clock path skew + uncertainty)) Source: test_cnt_1 (FF) Destination: led_2 (FF) Requirement: 1.140ns Data Path Delay: 6.059ns (Levels of Logic =3D 10) (Component delays alone exceeds constraint) Clock Path Skew: -0.400ns (1.832 - 2.232) Source Clock: clk_25 rising at 1169000.000ns Destination Clock: clk_28 rising at 1169001.140ns Clock Uncertainty: 0.000ns So, the minimum distance is 1.140 ns and that=92s the new requirement, which of course is not met. /B From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p38g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Sun, 12 Dec 2010 00:31:19 -0800 (PST) Organization: http://groups.google.com Lines: 76 Message-ID: <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292142679 31976 127.0.0.1 (12 Dec 2010 08:31:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 08:31:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p38g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4494 On Dec 8, 9:28=A0am, Martin Thompson wrote: > Benjamin Couillard writes: > > Hi everyone, > > > I have a simple question. Assuming we have this process : > > > MY_PROCESS : process(CLK) > > variable cnt : natural range 0 to 255; > > begin > > =A0 =A0if rising_edge(CLK) then > > =A0 =A0 output_signal <=3D '0'; > > =A0 =A0 if (srst =3D '1') then > > =A0 =A0 =A0 cnt :=3D 0; > > =A0 =A0else > > =A0 =A0 if (cnt =3D 100) then > > =A0 =A0 =A0 =A0output_signal <=3D '1'; > > =A0 =A0end if; > > =A0 =A0cnt :=3D cnt + 1; > > =A0 =A0end if; > > =A0 end if; > > end process; > > > In simulation, I will get an error at the rising edge of CLK when cnt > > is 255. > > Quite right too, you're trying to push 256 into that variable and > you've said "it can't happen" when you defined the range. =A0 > > > However, what happens in synthesis? Will the synthesizer add > > logic to prevent cnt from wrapping aroung ? Or will it simply > > implement the "usual" wraparound behavior? Is it synthesizer > > specific? > > In theory it's completely undefined - you've told the synthesiser that > that variable can't be bigger than 255, so if you try and make it so, > the synthesiser is probably within its rights to generate logic that > shorts the power supplies and makes magic smoke issue forth from your > FPGA :) > > In reality, no synthesiser I know of would implement this as anything > other than an 8 bit counter which wraps around. > > HOWEVER... in order to keep your simulation matching your synthesis > (which IMHO you must do), you should either: > > 1) Use an unsigned vector, for which wraparound behaviour is the > defined behaviour on overflow. > > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. > > As an aside - if you find yourself using a different maximum for cnt > (say 200 for example), and you don't do option 2) you'll likely find the > synthesiser generating an 8 bit wraparound counter which will still > count up to 255, making your sim and synth completely different... How exactly would my simulation be different from synthesis if I used a max of 200 for a counter? If my simulation tries to increment the counter past 200 it stops! That would not be an issue of different results, that would be my simulation failing to complete! If my usage of the counter never pushes it past 200, then the simulation and synth match. I think people are making far too big of an issue about this. An HDL is supposed to be describing hardware, hence the name HDL. If you take the position that the simulation and synthesis should always match 10% you can never design anything real. If I have a counter that is only needed for values of 200 or less and I don't care what happens when the value is over 200, then case 2 is perfectly ok. The OP has not responded, but I think he is just asking what the synthesizer does. I don't think his issue is about what the "correct" thing to do is. Rick From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sun, 12 Dec 2010 01:15:31 -0800 (PST) Organization: http://groups.google.com Lines: 86 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292145331 23151 127.0.0.1 (12 Dec 2010 09:15:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:15:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4495 On Dec 11, 11:44=A0am, Brian Drummond wrote: > On Fri, 10 Dec 2010 20:25:58 -0800 (PST), rickman wrot= e: > >Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > >use VHDL which we all know is a pig in many ways with its verbosity > >and arcane type conversion gyrations. > > I usually find that the gyrations are a hint to step back and see what as= pect of > the design I have missed... I end up needing a few, but YMMV. > > > But what bothers me most of all > >is that I have to learn how to tell the tools in their "language" how > >to construct the efficient logic I can picture in my mind. By > >"language" I don't mean the HDL language, but actually the specifics > >of a given inference tool. > > >What I mean is, if I want a down counter that uses the carry out to > >give me an "end of count" flag, why can't I get that in a simple and > >clear manner? =A0 > > Here the issue appears to be how to get at the carry out of a counter... > the syntax of integer arithmetic doesn't provide an easy way to do that b= y > default, in any language I know (other than assembler for pre-RISC CPUs, = with > their flag registers). Well, no, I'm not trying to force the tool to generate a carry out since I am not using it for anything. I just want a simple counter and logic to make it detect a final count value of 1. I am pretty sure I would have gotten that from my original code. But I also want the counter to roll over to zero at the max value of the counter which will give me a max count range of 2**N by specifying a value of 0 in the limit register. To use the carry out for the final count detection I would have to require the user to program M-1 rather than programming M or 0 for max M. > It seems to me that you have two choices ... > (1) implement an n-bit counter, and augment it in some way to recreate th= e carry > out (unfortunately you are fighting the synthesis tool in the process) > > (2) implement an n+1 bit counter, with the excess bit assigned to the car= ry, and > trust the synthesis tool to eliminate the excess flip-flop at the optimis= ation > stage... > > I am willing to guess the second approach would be simpler. Even if the o= bvious > optimisation doesn't happen (and I bet it does) it's worth asking if your= design > is sensitive to the cost of that FF. > > Can you boil down what you are trying to do (and doesn't work) into a tes= t case? Jan doesn't get what I am saying. I'm not that worried about the particulars of this case. I am just lamenting that everything I do in an HDL is about describing the behavior of the logic and not actually describing the logic itself. I am an old school hardware designer. I cut my teeth on logic in TO packages, hand soldering the wire leads. I still think in terms of the hardware, not the software to describe the hardware. Many of my designs need to be efficient in terms of hardware used and so I have to waste time learning how to get what I want from the tools. Sometimes I just get tired of having to work around the tools rather than with them. > > In an ideal design world, shouldn't it be pretty > >easy to infer logic and to actually know what logic to expect? > > I would say so. And I'm still hoping to live to see it! I'm not sure I will still be working then if it ever happens. As hardware becomes more and more cost efficient, I think there is less incentive to make the tools hardware efficient. I guess speed that will always be important and minimal hardware is usually the fastest. But that's not the case when the tools are doing the optimization. I recently reduced my LUT count 20% by changing the optimization from speed to area. Rick From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m11g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sun, 12 Dec 2010 01:19:09 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <5de904da-a2c3-4dc9-9633-dde231b88cf9@m11g2000vbs.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <733eea6c-b8b0-4809-9073-5e6910ac9aca@f20g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292145550 17441 127.0.0.1 (12 Dec 2010 09:19:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:19:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m11g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4496 On Dec 11, 4:21=A0pm, jacko wrote: > I also think the hardest part is specifying to the sythesis tool, how > external memory supplies a result after an access delay, and how to > make this delay relative to the synthesized fmax., not just in ns. I'm not sure what you are trying to do, but you should be able to specify a delay in terms of your target fmax. Just define a set of constants that calculate the values you want. I assume you mean a delay value to use in simulation such as a <=3D b after x ns? Rick From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i18g2000yqn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 01:28:39 -0800 (PST) Organization: http://groups.google.com Lines: 87 Message-ID: <8f1566a6-4f98-4f8e-94bb-05c6f0dacea2@i18g2000yqn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292146119 29777 127.0.0.1 (12 Dec 2010 09:28:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:28:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000yqn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4497 On Dec 11, 11:29=A0am, KJ wrote: > On Dec 10, 11:44=A0pm, rickman wrote: > > > I can't say I totally agree with the doom and gloom predictions of > > KJ... > > > clk_250k will be a problem in an FPGA. =A0In an FPGA environment, you > > > basically almos never want to generate a clock with logic. =A0Even wh= en > > > it comes out of a flip flop you're most likely doomed. > > > I agree that generating a clock from a counter is not a good idea. > > But it is not a fatal flaw if handled correctly. =A0 > > The only way to 'handle it correctly' will be to treat it as an > independent clock domain and design in clock domain crossing logic. > Without that, you'll be running into hold time issues with any signal > originating from the high speed clock domain that enters the generated > clock domain. =A0You can't do anything about those issues except re- > route, cross your fingers and hope. =A0Yes you can hand hold a design > and get it to work, but before you do so there should be a compelling > reason to do so. =A0No such reason was posted. I expect there are tons of facts involve that he didn't post. Why not assume the guy has a brain in his head and discuss the issue without being extreme about it? > > > > CTRL_PROC : process (clk_250k) > > > > begin > > > > =A0if rising_edge(clk_250k) then > > > > Yep...doomed > > > Isn't that a bit dramatic? =A0 > > No. =A0I would characterize the OP's odds of success as 'low'. =A0At best= , > he would find that he is never able to get the design working right > out of the shoot, abandon the approach and will end up with more > knowledge. =A0That would be a good outcome. =A0At worst, the design would > be going into production when there starts to become a growing pile of > boards that seem to have a 'temperature sensitivity' or 'date code > issue'. > > What is your definition of 'doomed'? > > >If the tools properly recognize this > > signal as a clock and routes it on a clock spline, and you treat it as > > a separate clock with no clear timing relation to the clock it is > > generated from, > > But the OP clearly doesn't know this if you read the post. I think you are missing the point. The OP is asking the question. Of course he doesn't "know" for sure that he has to treat the new clock as an independent clock, otherwise he wouldn't be asking the question. But clearly he is aware of the issues involved. So yes, "doomed" is being overly dramatic. > > There are times when you don't want to use an enable. =A0A design I did > > generates a clock enable to control some circuitry. =A0But the input an= d > > output of the data signals need to be done on the actual clock edges > > to optimize the setup and hold times of the external signals. =A0So the > > data input and output are run through a FF clocked by the clock I am > > generating and then I deal with the data timing as required. > > But in those situations, you don't have any logic being implemented in > the clock domain crossing as was in the OP. =A0In the posted code, the > signals reset, byte_received and data_in probably originate in some > other domain and are crossing; reg1, as noted by the OP definitely > does come from a foreign clock domain and is not treated properly. > > The clock domain crossing looks like this... > > Synced_To_Clock_Signal <=3D Synced_To_Other_Clock_Signal when > rising_edge(Clock); > > Kevin Jennings Yes, the OP is asking if he needs to add that sort of code. The answer is "yes". No need to say his design is "doomed" or otherwise be dramatic about it. If the guy didn't have a clue, he wouldn't have asked the question. Rick From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 02:01:13 -0800 (PST) Organization: http://groups.google.com Lines: 113 Message-ID: <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292148074 14857 127.0.0.1 (12 Dec 2010 10:01:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 10:01:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4498 On Dec 11, 3:43 pm, Beppe wrote: > Thanks for the answers. > > An enable won=92t solve the problem of crossing clock domains. With an > enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC > would still be clocked by clk_28. clk_28 =3D 35/31*clk_25. > > I=92m aware of the problem with logic generated clocks, but I hope that > Rick is right here. Putting the clock on a low skew global clock net > should be enough to ensure that hold and setup times are met. > Actually, when synthesizing the design, XST infers a BUFG on the > clk_250k, as you predicted Rick, and the design seems to be working > fine in hardware although I haven=92t made any extensive tests yet. Don't count on the fact that the design works on your lab bench as proof that it works in any real sense! You can never prove a design works by testing it!!! You can only use test to prove that a design doesn't work. To prove that it works requires that you test all possible conditions and that's not really possible much less practical. > I was first thinking that it would be okay to put the clk_250k on a > non-dedicated clock net because of its low frequency, but the > frequency doesn=92t matter here if I=92m right when rethinking it. The > output of a flip-flop (as a result of the flip-flop being clocked by a > clock edge) could be propagating to the next flip-flop before the same > clock edge clocks the next flip-flop and thus leading to a hold time > violation no matter the frequency. Right? > > On a side note, a solution for clocks with excessive skew (on non- > global clock nets) should be to alternate between positive and > negative clock edges on every other register. That would cut the > performance by half, but if it=92s applied on low frequency clocks it > doesn=92t really matter. Is this a no, no technique or would I be fine > using it? Yes, I think you understand the issue here. I've never considered using a low speed clock in this manner, but I expect it would work ok as long as you account for ***ALL*** possible logic paths. For example, if you have any sort of counter, you would need to use two sets of FFs in the feedback loop, one positive edge triggered and one negative edge triggered. Otherwise clock skew can cause one output to change before another bit that depends on the first is clocked. As you say, clock skew causes hold time problems. > As for the original question I guess I could simply find the minimum > distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is > what ISE/XST should do if I understand the documentation correctly). > That time would be the =93new=94 timing constraint. If it=92s impossible = to > meet this new timing I need to use asynchronous clock domain > techniques, otherwise it would be just fine. I'm not sure what you are getting at. If the clocks are not simply related, I'm not sure you can assume there is any useful relationship between their timing. To generate the 28 MHz clock the 125 MHz input clock is multiplied up to 825 before being divided down to 28.xxx. How would you expect the tools to consider the timing relationship between two clocks divided down from an 825 MHz (~1.2 ns period) clock? > > In the posted code, the > > signals reset, byte_received and data_in probably originate in some > > other domain and are crossing; reg1, as noted by the OP definitely > > does come from a foreign clock domain and is not treated properly. > > data_in and byte_received are registers clocked by clk_250k and > originate from a MIDI UART. The clk_250k frequency is eight times the > 31.25 kbaud rate of the MIDI interface and used to retrieve the > asynchronous serial MIDI data. I recently discussed a multiple clock design with my customer. He said he had more than 50 clocks in this design and wanted details on how I deal with syncing multiple clock domains. I explained that I do all my work in one clock domain and use a particular logic circuit to transport clocks, enables and data into that one domain. I solve the synchronization problem once at the interface and never have to worry about it again. That logic uses two processes, one in each clock domain. If the FROM domain uses a clock enable, the data is registered in the FROM domain. Data is normally also registered in the TO domain but it depends on the rates. Clocks and/or clock enables run through a simple circuit that deals with metastability and provides a clock enable in the new domain that suits the situation. The circuit is just three FFs, one in the FROM clock domain and two in the TO clock domain. The FROM domain FF and one of the TO domain FFs have the data inputs and outputs connected in a feedback loop with one inverter in the loop. If syncing a clock the FROM domain FF has no enable. If syncing a clock enable, that enable is used on the FROM domain FF. The TO domain FF in the feedback loop feeds the second FF for metastability minimization. Every FROM domain clock edge or clock enable causes the feedback loop to toggle state. An XOR gate on the output of the two TO FFs gives you a clock enable in the TO domain. The FROM domain clock can be faster than the TO domain clock as long as the FROM clock enable is less frequent than half the TO domain clock rate. It may even be possible to have an enable rate up to the TO domain clock rate, but I won't swear to that unless I analyzed this carefully. This is a lot simpler to think about looking at a diagram. Maybe I need to write this up. I didn't think of this circuit myself. A co- worker told me about it and it was given to him by his brother I think. It is very versatile and is the only circuit I use for clock domain crossing with varying data registers depending on the particulars. My customer found this to work for him with his 50+ clocks. Rick From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 12 Dec 2010 13:42:20 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 59 Message-ID: <4d04c32c$0$14250$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 03b0f900.news.skynet.be X-Trace: 1292157740 news.skynet.be 14250 91.177.205.212:49433 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4500 rickman wrote: > > Jan doesn't get what I am saying. I'm not that worried about the > particulars of this case. I am just lamenting that everything I do in > an HDL is about describing the behavior of the logic and not actually > describing the logic itself. I am an old school hardware designer. I > cut my teeth on logic in TO packages, hand soldering the wire leads. > I still think in terms of the hardware, not the software to describe > the hardware. Many of my designs need to be efficient in terms of > hardware used and so I have to waste time learning how to get what I > want from the tools. Sometimes I just get tired of having to work > around the tools rather than with them. Ok, let's talk about the overall message then. I remember an article from the early days were some guy "proved" that HDL-based design would never otherthrow schematic entry, because it is obviously better to describe what something *is* than what it *does*. All ideas come back, also the bad ones :-) HDL-based design was adopted by old school hardware designers, for lack of other ones. They must have been extremely skeptical. How did it happen? Synopsys took manually optimized designs from expert designers and showed that Design Compiler consistently made them both smaller and faster, and permitted trade-off optimizations between the two. The better result was obviously *not* like the original designer imagined it. The truth is that HDL-based design works better in all respects than handcrafted logic. It is a no-compromises-required technology, which is very rare. Look no further than this newsgroup for active designers who understand this very well. Their designs must probably be as efficient as yours. Yet they use coding styles that are much more abstract, and they are certainly not concerned about the where the last mux or carry-out goes. In other words, when you make claims about ineffiencies and requirements to fight tools all the time, you better come up with some very strong examples - the evidence is against you. What do you give us? A vague problem with an example of a modulo operation on a decrementer. Instead of posting the code and resolve the issue immediately, you give some verbose description in prose so that we now all can start the guessing game. The example has a critical problem, but you don't know what it is and you refuse to track it down. Yet you still refer to it to back up your claims. If that is your standard, why should I take any of your claims seriously? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:56 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 12 Dec 2010 19:05:09 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 29 Message-ID: <4d050ed4$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 3cef954e.news.skynet.be X-Trace: 1292177108 news.skynet.be 14247 91.177.205.212:55974 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4501 rickman wrote: > Jan doesn't get what I am saying. I'm not that worried about the > particulars of this case. I'm sorry to bother you with this again, but I am actually worried. >From your description, I tried to reproduce your problem, to no avail. With or without modulo, it doesn't make the slightest difference. (Quartus Linux web edition v.10.0). Perhaps you stumbled on some problematic use case that we definitely should know about. After all, HDL-based design is not about specifying an exact gate level implementation, but about understanding which patterns work well. Perhaps you stumbled upon a pattern that doesn't and that we should avoid. Please post your code. Let's not spoil an opportunity to advance the state of the art. Of course, you may have good reasons not to post your code, for example because you found a bug in the mean time. Perhaps you did modulo 2^N-1 instead of 2*N, just to mention a mistake that I once made. Let us know, so that we can stop worrying. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!xlned.com!feeder1.xlned.com!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 21:37:16 +0100 Lines: 116 Message-ID: <8mkq3rFo01U1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net b6OlAfcN3tEeikVDCUPMNgYFX+kDCFak+Ki85D6R8fa/9PF+JU Cancel-Lock: sha1:/9niAbA8UIbdnru7PtYHL7vwKB0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4502 On 12/12/2010 11:01 AM, rickman wrote: > On Dec 11, 3:43 pm, Beppe wrote: >> Thanks for the answers. [snip] > > Don't count on the fact that the design works on your lab bench as > proof that it works in any real sense! You can never prove a design > works by testing it!!! You can only use test to prove that a design > doesn't work. To prove that it works requires that you test all > possible conditions and that's not really possible much less > practical. > I am sorry but I disagree with you on this point. There are "good practices" that help a lot in guaranteeing the quality of your project. I believe that coding is just part of the story. Having the possibility to test the design by a different team from the designers one will make a huge difference. To do that a very precise (not necessarily detailed) documentation is of course mandatory, since the verification team should not go in the rtl details, or even the timing constraints and place & route details of the project (the concept behind the design will also benefit of a well structured documentation). This is why there are standardized procedures, for avionics, space applications, military applications (to mention some of them), which go beyond the vhdl and define a work flow that should be as much independent as possible from the individual skills of the designers team. And also limiting the focus only on the coding side, there are a lot of dos and don'ts that should be followed thoroughly. Here for instance a good article on common hdl mistakes (and IMHO misconceptions): http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > >> I was first thinking that it would be okay to put the clk_250k on a >> non-dedicated clock net because of its low frequency, but the >> frequency doesn’t matter here if I’m right when rethinking it. The >> output of a flip-flop (as a result of the flip-flop being clocked by a >> clock edge) could be propagating to the next flip-flop before the same >> clock edge clocks the next flip-flop and thus leading to a hold time >> violation no matter the frequency. Right? >> >> On a side note, a solution for clocks with excessive skew (on non- >> global clock nets) should be to alternate between positive and >> negative clock edges on every other register. That would cut the >> performance by half, but if it’s applied on low frequency clocks it >> doesn’t really matter. Is this a no, no technique or would I be fine >> using it? Why do you need to go in such a complicated pathway when you don't need to? It has been already suggested a very easy and robust solution that will avoid any of the problems you mentioned: On 12/10/2010 11:28 PM, KJ wrote: > - What you should do is generate a clock enable for rather than a > clock for the 250k. Then both processes are running in the same clock > domain...no clock crossings at all. > In my opinion the use of both rising and falling edges should have a stronger motivation (like to minimize the peak current during clock transitions in large SoC). > >> As for the original question I guess I could simply find the minimum >> distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is >> what ISE/XST should do if I understand the documentation correctly). >> That time would be the “new” timing constraint. If it’s impossible to >> meet this new timing I need to use asynchronous clock domain >> techniques, otherwise it would be just fine. > Even though your solution may work, that doesn't mean it is the right one. I would recommend going through a clock domain crossing technique as already suggested. Again, following "good practices" not only help us having better chances our systems work, it also (and more important) helps spreading the use of them with invaluable returns to the whole community. > I'm not sure what you are getting at. If the clocks are not simply > related, I'm not sure you can assume there is any useful relationship > between their timing. To generate the 28 MHz clock the 125 MHz input > clock is multiplied up to 825 before being divided down to 28.xxx. > How would you expect the tools to consider the timing relationship > between two clocks divided down from an 825 MHz (~1.2 ns period) > clock? > > >>> In the posted code, the >>> signals reset, byte_received and data_in probably originate in some >>> other domain and are crossing; reg1, as noted by the OP definitely >>> does come from a foreign clock domain and is not treated properly. >> >> data_in and byte_received are registers clocked by clk_250k and >> originate from a MIDI UART. The clk_250k frequency is eight times the >> 31.25 kbaud rate of the MIDI interface and used to retrieve the >> asynchronous serial MIDI data. That is data_in and byte_received are from a different clock domain and they should by resync'ed to be used in the clk_25 domain. > > I recently discussed a multiple clock design with my customer. He > said he had more than 50 clocks in this design and wanted details on > how I deal with syncing multiple clock domains. I explained that I do > all my work in one clock domain and use a particular logic circuit to > transport clocks, enables and data into that one domain. I solve the > synchronization problem once at the interface and never have to worry > about it again. > I would recommend an alternative to the 50 clocks domains, instead. Al From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!fu15g2000vbb.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 13:17:18 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> NNTP-Posting-Host: 83.185.113.81 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292188638 20892 127.0.0.1 (12 Dec 2010 21:17:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 21:17:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fu15g2000vbb.googlegroups.com; posting-host=83.185.113.81; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4503 > Don't count on the fact that the design works on your lab bench as > proof that it works in any real sense! You can never prove a design > works by testing it!!! You can only use test to prove that a design > doesn't work. To prove that it works requires that you test all > possible conditions and that's not really possible much less > practical. Of course you=92re right. =93It=92s working in hardware=94 was more of a hi= nt that it might not be totally doomed. > How would you expect the tools to consider the timing relationship > between two clocks divided down from an 825 MHz (~1.2 ns period) > clock? Maybe I wasn=92t clear enough, but the two clocks are related by a known fraction. They are both derived from the 125 MHz input clock. clk_28 =3D 125*7/31 and clk_25 =3D 125/5 and hence clk_28 =3D 35/31*clk_25. And I expect the tools to consider the timing relationship because the ISE/ XST/DCM documentation states that the software derives a new PERIOD for each of the DCM output clocks and determines the clock relationships between the output clock domains. And that is also what the timing report in my previous post reflects. > I solve the synchronization problem once at the interface > and never have to worry about it again. Seems like a good idea. > This is a lot simpler to think about looking at a diagram. Maybe I > need to write this up. Please do that! I lost you somewhere in between the domains..., but I would very much like to see how you solve the clock domain crossing. /B From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i17g2000vbq.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 13:45:45 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> NNTP-Posting-Host: 83.185.113.81 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292190345 3554 127.0.0.1 (12 Dec 2010 21:45:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 21:45:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i17g2000vbq.googlegroups.com; posting-host=83.185.113.81; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4504 > Why do you need to go in such a complicated pathway when you don't need > to? It has been already suggested a very easy and robust solution that > will avoid any of the problems you mentioned: > On 12/10/2010 11:28 PM, KJ wrote: > > - What you should do is generate a clock enable for rather than a > > clock for the 250k. Then both processes are running in the same clock > > domain...no clock crossings at all. I don=92t intend to. As I said it was just a side note. And as I also have said, that solution doesn=92t help since I still need to cross domains. With an enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC would still be clocked by clk_28. > That is data_in and byte_received are from a different clock domain and > they should by resync'ed to be used in the clk_25 domain. If you read the original post you will notice that the clk_25 domain isn=92t used in either of the two processes. data_in and byte_received are read in the CTRL_PROC, which is clocked by clk_250k and thus they don't cross domains and they don=92t need to be resynchronized. At least not in the given example. /B From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 00:20:42 +0100 Lines: 33 Message-ID: <8ml3mcFgg9U1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net C5pBy5PFH61uh4XUmhpc+wosL/kV8UYM0MOHX5VitHcWufX9Dz Cancel-Lock: sha1:koXmPfxMob7pyPARTvO7XrFw4d8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4505 On 12/12/2010 10:45 PM, Beppe wrote: >> Why do you need to go in such a complicated pathway when you don't need >> to? It has been already suggested a very easy and robust solution that >> will avoid any of the problems you mentioned: >> On 12/10/2010 11:28 PM, KJ wrote: >> > - What you should do is generate a clock enable for rather than a >> > clock for the 250k. Then both processes are running in the same clock >> > domain...no clock crossings at all. > > I don’t intend to. As I said it was just a side note. And as I also > have said, that solution doesn’t help since I still need to cross > domains. With an enable the CTRL_PROC would be clocked by clk_25, but > the CNT_PROC would still be clocked by clk_28. > That is the reason why you need to resync. >> That is data_in and byte_received are from a different clock domain and >> they should by resync'ed to be used in the clk_25 domain. > > If you read the original post you will notice that the clk_25 domain > isn’t used in either of the two processes. data_in and byte_received > are read in the CTRL_PROC, which is clocked by clk_250k and thus they > don't cross domains and they don’t need to be resynchronized. At least > not in the given example. > My fault, indeed it seems to me you do not need the clk_250k at all and can have data_in and byte_received directly in clk_25 domain (800 pulses per bit). > /B From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 00:23:30 +0100 Lines: 26 Message-ID: <8ml3riFgg9U2@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 4tq8qmqG2snB7i3mIHl4+gsc/Sg+sOxbcM6VsQQDrjxRl6X4pr Cancel-Lock: sha1:A/42fpNlS7L/0TxLMvG/P/XcEDw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4506 On 12/11/2010 5:25 AM, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. [snip] > I guess what I am trying to say is I would like to be able to specify > detailed logic rather than generically coding the function and letting > a tool try to figure out how to implement it. This should be possible > without the issues of instantiating logic (vendor specific, clumsy, > hard to read...). In an ideal design world, shouldn't it be pretty > easy to infer logic and to actually know what logic to expect? > IMHO using HDL as if we are using a schematic entry is rather limiting and does not provide any high level abstraction which is rather powerful in terms of description, implementation and maintainance of the code. I found the following readings very inspiring: http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm and http://mysite.ncnetwork.net/reszotzl/uart.vhd Al > Rick From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 02:05:19 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292234719 8390 127.0.0.1 (13 Dec 2010 10:05:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 10:05:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4508 > > I don t intend to. As I said it was just a side note. And as I also > > have said, that solution doesn t help since I still need to cross > > domains. With an enable the CTRL_PROC would be clocked by clk_25, but > > the CNT_PROC would still be clocked by clk_28. > > That is the reason why you need to resync. Exactly. And the reason why an enable doesn't help. However, an enable will get rid of the logic generated clk_250k although I haven't been convinced why it's so bad with a logic generated clock even when it is put on the low skew global clock line. > >> That is data_in and byte_received are from a different clock domain and > >> they should by resync'ed to be used in the clk_25 domain. > > > If you read the original post you will notice that the clk_25 domain > > isn t used in either of the two processes. data_in and byte_received > > are read in the CTRL_PROC, which is clocked by clk_250k and thus they > > don't cross domains and they don t need to be resynchronized. At least > > not in the given example. > > My fault, indeed it seems to me you do not need the clk_250k at all and > can have data_in and byte_received directly in clk_25 domain (800 pulses > per bit). That's right. So in any case I need to use a clock domain crossing technique unless I rewrite the MIDI UART and clock it with the clk_28. /B From newsfish@newsfish Fri Dec 24 22:55:57 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 04:48:00 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <1acc8c8f-bbc5-45dd-8e86-49b15abb5d76@30g2000yql.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292244480 18897 127.0.0.1 (13 Dec 2010 12:48:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 12:48:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4509 On Dec 13, 5:05=A0am, Beppe wrote: > > > That is the reason why you need to resync. > > Exactly. And the reason why an enable doesn't help. However, an enable > will get rid of the logic generated clk_250k although I haven't been > convinced why it's so bad with a logic generated clock even when it is > put on the low skew global clock line. > Because of the potential for hold time problems on a signal coming from the high speed clock domain into the generated clock domain. The low skew that you are talking about is between different flops clocked by that same clock. It does not address the skew between the two clock domains. The timing analysis will report it...but it won't fix it. While this is true of all timing problems, the solution to this particular timing problem is to add delays into the data path so that the minimum data delay is still faster than the clock (plus setup). Then ask yourself, how do you insert delays into an FPGA design? Do you want to be adding this delay potentially every time you re-route the design for some reason? Plus, when you get right down to it, it will likely take exactly the same amount of logic to generate the lower speed clock as it would to generate the clock enable...so ask yourself, other than more work and potential headaches what do you expect to get by using a generated clock? Kevin Jennings From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!n32g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Mon, 13 Dec 2010 06:40:11 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: <1909591f-171b-47bb-8233-793106dff97c@n32g2000pre.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <1k87g6pgurrcujr2hnhjl8pb6q5see2jj5@4ax.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292251211 13572 127.0.0.1 (13 Dec 2010 14:40:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 14:40:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000pre.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4510 On Dec 11, 10:21=A0am, Brian Drummond wrote: > If you want wrapround from 255 to 0, you want a modular type - as others = point > out, numeric_std.unsigned meets your needs. > > Or you could make the wrapround explicit using the "mod" operator. > This is more flexible since the "mod" value can be something other than 2= 56. Most synthesis tools will not accept a modulo or divide operation by a non-integer power of two. For other values, you have to use a conditional to test for the pending overflow and take appropriate actions to prevent it. Andy From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Mon, 13 Dec 2010 15:23:08 +0000 Organization: TRW Conekt Lines: 46 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net Y3Yqi8FAkffqNjjFyL+eFQyUz1/SUWZywRFH1mgtswJBt4M5o= Cancel-Lock: sha1:gI0a5NMZ7fXY2KWj/03y0Uwk8z8= sha1:e/P1plEtF+1ru9ECQW9opehUEJo= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4511 rickman writes: > How exactly would my simulation be different from synthesis if I used > a max of 200 for a counter? If my simulation tries to increment the > counter past 200 it stops! That would not be an issue of different > results, that would be my simulation failing to complete! If my usage > of the counter never pushes it past 200, then the simulation and synth > match. OK, yes, I think I expressed myself badly :) I was trying to talk about unexpected behaviour, and confused the issue by talking about mismatches. As I said to Jan, if the simulation doesn't test far enough, one might get different behaviour to what one (might) expect (however innaccurate that expectation may be). > I think people are making far too big of an issue about this. An HDL > is supposed to be describing hardware, hence the name HDL. If you > take the position that the simulation and synthesis should always > match 10% you can never design anything real. ^^^ I assume you mean 100% there? > If I have a counter that is only needed for values of 200 or less > and I don't care what happens when the value is over 200, then case > 2 is perfectly ok. Quite so, I never intended to say anything other. > > The OP has not responded, but I think he is just asking what the > synthesizer does. I don't think his issue is about what the "correct" > thing to do is. > On re-reading the OP with that in mind, I agree. Sorry for any confusion caused! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Mon, 13 Dec 2010 16:35:57 +0100 Lines: 62 Message-ID: <8mmsqvF12mU1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9LS9uv89g/IalggIlnPPnwZGJr0tZDvyqhDB8HvhVTe+3AN++9 Cancel-Lock: sha1:de5sRBOj2tR6Ztou27S03wUqHK8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:13692 comp.lang.vhdl:4512 comp.lang.verilog:2720 On 12/10/2010 3:57 PM, Thomas Stanka wrote: [snip] > Open cores tend to have a lack in documentation and verification, > which is a no-go for developing space electronics. There are documented results of projects that attracted space applications (http://opencores.org/newsletter,2010,09,#n5), proving that there is a certain interest in the open approach. > Even if you target on public science projects it is very likely that > you need to ensure the "space-readiness" in many aspects for a core > before you can use it. > The aim of the project is not to provide a "ready-to-use" solution, but to spread the use of spacewire protocol. The end-user is of course responsible for the entire process, but it can be foreseen a test campaign which will validate the IP on certain technologies (after all I am working at CERN and there are a lot of test-beams facilities here!). I just want to mention that on an FPGA based application the choice of the FPGA may guarantee certain level of radiation hardness, while specific design techniques may improve the level of hardness even further (TMR, data-scrubbing, EDAC.). > For spacewire interface I consider the effort to proof the quality of > a core clearly exceeding the effort for writting the core for your > own. > Indeed, nevertheless there are a good amount of projects which are neither proofing the quality of their cores, nor applying any standard protocol throughout their systems. > Are you firm with developing according to ECSS-Q 60 02? I would expect > a core development to be complaint to this before using it without > further quality checking in case of the core not beeing provided from > ESA for a ESA project. > Even though I believe that Space Agencies around the world are politically and technically bond to follow standardization processes based mostly on lessons learned, I also believe that a lot of industries and research institutes are buried under the burden of those standards where a good chunk of their budget goes. I am not advocating a deviation from the standards, on the contrary I believe that protocols (as can-bus, mil-std-1553, spi, I2C...) are key components of a reliable system and any effort should be made to make them popular. > In case of detailed questions you may also conntact me by sending an > email. You should change the receive-address to thomas > @domain_from_email when replying. > > best regards Thomas Al p.s.: I am just an enthusiast designer, willing to improve my skills and to share my knowledge. From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!35g2000prb.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 09:06:38 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292259998 6101 127.0.0.1 (13 Dec 2010 17:06:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 17:06:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 35g2000prb.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4513 On Dec 10, 8:25=A0pm, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. =A0But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. > > Rick Back in the 8086 days, I had to do the same thing with compilers. I spent a fair amount of time learning how the code generation phase worked so I could get the tools to work properly. I remember a "brand- name" 'C' compiler very carefully generating code to keep the loop control variable in the CX register, then at the end of the loop moving CX to AX and adding minus-one. (For those that don't program 86's in assembly, the CX register is a special purpose register for the 'LOOP' instruction.) Now that processors are real fast, and memory is very cheap, I don't worry so much about efficient code. I would draw a parallel to the frustrations you are having with HDLs. Another parallel I would draw is that when I wanted 'very fast tight code' I would code certain modules in assembly, and link them with 'C' routines. When the synthesizer just won't get it right, I draw it a picture. (Which is one advantage the Acme-Brand tool has over the Brand-X tool) Yeah, it's not portable, and it isn't "right". But I'm getting product out the door. RK. From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!f21g2000prn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 09:31:30 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292261490 7269 127.0.0.1 (13 Dec 2010 17:31:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 17:31:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f21g2000prn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4514 On Dec 11, 10:44=A0am, Brian Drummond wrote: > >What I mean is, if I want a down counter that uses the carry out to > >give me an "end of count" flag, why can't I get that in a simple and > >clear manner? =A0 > > Here the issue appears to be how to get at the carry out of a counter... > the syntax of integer arithmetic doesn't provide an easy way to do that b= y > default, in any language I know (other than assembler for pre-RISC CPUs, = with > their flag registers). > > It seems to me that you have two choices ... > (1) implement an n-bit counter, and augment it in some way to recreate th= e carry > out (unfortunately you are fighting the synthesis tool in the process) > > (2) implement an n+1 bit counter, with the excess bit assigned to the car= ry, and > trust the synthesis tool to eliminate the excess flip-flop at the optimis= ation > stage... > > I am willing to guess the second approach would be simpler. I have found the 1st approach far simpler, by using a natural subtype for the counter. Then (count - 1 < 0) is the carry out for a down counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit up counter. No fighting required. Andy From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 10:19:59 -0800 (PST) Organization: http://groups.google.com Lines: 45 Message-ID: <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292264400 12680 127.0.0.1 (13 Dec 2010 18:20:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 18:20:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4515 On Dec 12, 3:15=A0am, rickman wrote: > I'm not that worried about the > particulars of this case. =A0I am just lamenting that everything I do in > an HDL is about describing the behavior of the logic and not actually > describing the logic itself. =A0I am an old school hardware designer. =A0= I > cut my teeth on logic in TO packages, hand soldering the wire leads. > I still think in terms of the hardware, not the software to describe > the hardware. =A0Many of my designs need to be efficient in terms of > hardware used and so I have to waste time learning how to get what I > want from the tools. =A0Sometimes I just get tired of having to work > around the tools rather than with them. I seem to recall a similar argument when assemblers gave way to higher level language compilers... This change in digital hardware design is not unlike the change from one-man furniture shops to furniture factories. The craftsmen of the one-man shops painstakingly treated every detail as critical to their product: a chair. And the result was an exquisite piece of furniture, albeit at a very high price, and very low volume (unless you hired a lot of one man shops at the same time). Circuit designers are no different (being one myself, dating back to those "I can do that function in one less part" days gone by). But the target has changed. We no longer need a chair, we need a stadium full of them. And we need the elevators, climate control, fire suppression, lighting, and all the other support systems, to go along with them. Perhaps we should take a step back, and look at what we really need (hint: a place for a lot of people to watch an event, while seated most of the time). Now I can optimize my stadium to recognize that all of my seats don't need to be finely crafted pieces of furniture. But I don't know that until I focus on the requirements: "What must my project do?" So, instead of finding a way to describe the project as a collection of specific chairs, elevators and fire extinguishers, we need to describe it as a set of desired behaviors, and then, through some process (hopefully semi-automated), convert that description into an optimized design for the stadium. Could the craftsman and his tools have done that? What do you want from the tools, a collection of exquisitely crafted chairs, or an efficient stadium? Andy From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!15g2000vbz.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 10:34:13 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> <1acc8c8f-bbc5-45dd-8e86-49b15abb5d76@30g2000yql.googlegroups.com> NNTP-Posting-Host: 90.130.237.152 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292265253 20700 127.0.0.1 (13 Dec 2010 18:34:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 18:34:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 15g2000vbz.googlegroups.com; posting-host=90.130.237.152; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4516 > Because of the potential for hold time problems on a signal coming > from the high speed clock domain into the generated clock domain. But if there=92s no data coming from the high speed clock domain into the generated clock domain I don=92t see the problem. That is actually the case in the given example. The clock domain crossing is between clk_250k and clk_28 not between clk_250k and clk_25. > Then ask yourself, how do you insert delays into an FPGA design? Clocking on both positive and negative clock edge...! Ok, I won=92t do that I will use enables. > what do you expect to get by using a generated clock? Lower power consumption? /B From newsfish@newsfish Fri Dec 24 22:55:58 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 13 Dec 2010 16:43:09 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 22:44:19 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-V0eVJ02ziUG3BFUoIuad4BzbjqgrXy3NGyJHsUIu1tRgsxfc1yPHAhsNhlQ37gzEbxwPeXYpnLTOHgN!ggpJibO3Jz5JqpSWzzRoZKS06GGmF+2VgEQ8wN07FYPT/7JGjREEqbyajId7UK+Kou67hQc/dRpP!lpg= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2577 Xref: feeder.eternal-september.org comp.lang.vhdl:4517 On Mon, 13 Dec 2010 09:31:30 -0800 (PST), Andy wrote: >On Dec 11, 10:44 am, Brian Drummond >wrote: >> Here the issue appears to be how to get at the carry out of a counter... >> It seems to me that you have two choices ... >> (1) implement an n-bit counter, and augment it in some way to recreate the carry >> out (unfortunately you are fighting the synthesis tool in the process) >> >> (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and >> trust the synthesis tool to eliminate the excess flip-flop at the optimisation >> stage... >> >> I am willing to guess the second approach would be simpler. > >I have found the 1st approach far simpler, by using a natural subtype >for the counter. Then (count - 1 < 0) is the carry out for a down >counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit >up counter. No fighting required. In which case it is the expression (count - 1) or (count + 1) which must be n+1 bits; then perhaps its size (and its type - integer - for count-1) need not be explicitly expressed. I believe some synthesis tools used to generate rather large elaborations of this expression (inc/decrement, then comparator), hence fighting - but perhaps none do so any longer. - Brian From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z19g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 19:56:25 -0800 (PST) Organization: http://groups.google.com Lines: 106 Message-ID: <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292298985 26001 127.0.0.1 (14 Dec 2010 03:56:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 03:56:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4518 On Dec 12, 3:37 pm, Alessandro Basili wrote: > On 12/12/2010 11:01 AM, rickman wrote: > > > On Dec 11, 3:43 pm, Beppe wrote: > >> Thanks for the answers. > [snip] > > > Don't count on the fact that the design works on your lab bench as > > proof that it works in any real sense! You can never prove a design > > works by testing it!!! You can only use test to prove that a design > > doesn't work. To prove that it works requires that you test all > > possible conditions and that's not really possible much less > > practical. > > I am sorry but I disagree with you on this point. There are "good > practices" that help a lot in guaranteeing the quality of your project. I never said testing isn't useful. I said that testing can't assure that something works unless you test every possible condition and that is not possible in an absolute sense. Besides, you snipped the OP's comment I was responding to... "the design seems to be working fine in hardware although I haven=92t made any extensive tests yet." The problem we are discussing is ***exactly*** the sort of thing you may not find in testing. The way the OP has constructed the circuit it may work in 99.99% of the systems he builds. Or it may work 99.99% of the time in all of the systems. But testing can't validate timing since you can't control all of the variables. The only thing testing can really do is to verify that your design meets your requirements... if your requirements are testable! I've been trained in quality process development and after seeing it in action, I realize that much of it is not a better than intelligent thinking. Just like many of the tools provided in engineering, this is one that seems to provide benefit when used by the "masses" rather than by the skilled. > I believe that coding is just part of the story. Having the possibility > to test the design by a different team from the designers one will make > a huge difference. "a huge difference"... I understand there are lots of ways to improve testing, but that doesn't change the fundamental limitation of testing. > To do that a very precise (not necessarily detailed) > documentation is of course mandatory, since the verification team should > not go in the rtl details, or even the timing constraints and place & > route details of the project (the concept behind the design will also > benefit of a well structured documentation). > > This is why there are standardized procedures, for avionics, space > applications, military applications (to mention some of them), which go > beyond the vhdl and define a work flow that should be as much > independent as possible from the individual skills of the designers team. > > And also limiting the focus only on the coding side, there are a lot of > dos and don'ts that should be followed thoroughly. > Here for instance a good article on common hdl mistakes (and IMHO > misconceptions): > > http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF I'm not sure what to say about this article. It is actually a bit shallow in my opinion. But it also contains errors! Much of it is really just the opinion of the author. > Even though your solution may work, that doesn't mean it is the right > one. I would recommend going through a clock domain crossing technique > as already suggested. > Again, following "good practices" not only help us having better chances > our systems work, it also (and more important) helps spreading the use > of them with invaluable returns to the whole community. I think that terms like "good practices" are some of the least useful concepts I've ever seen. First, where are "good practices" defined? Without a clear, detailed definition of the term, it doesn't communicate anything. Usually it is used to mean "what I do". It may be defined within a company, in some limited ways it may be defined within a sector. But in general this is a term that has little meaning as used by most people. This is much like recommending to design "carefully". I can't say how many times I have seen that word used in engineering without actually saying anything. > > I recently discussed a multiple clock design with my customer. He > > said he had more than 50 clocks in this design and wanted details on > > how I deal with syncing multiple clock domains. I explained that I do > > all my work in one clock domain and use a particular logic circuit to > > transport clocks, enables and data into that one domain. I solve the > > synchronization problem once at the interface and never have to worry > > about it again. > > I would recommend an alternative to the 50 clocks domains, instead. What alternative would that be??? Is that different than the solution I recommended? Rick From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 20:25:05 -0800 (PST) Organization: http://groups.google.com Lines: 83 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292300705 8513 127.0.0.1 (14 Dec 2010 04:25:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 04:25:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4519 On Dec 12, 4:17=A0pm, Beppe wrote: > > Don't count on the fact that the design works on your lab bench as > > proof that it works in any real sense! =A0You can never prove a design > > works by testing it!!! =A0You can only use test to prove that a design > > doesn't work. =A0To prove that it works requires that you test all > > possible conditions and that's not really possible much less > > practical. > > Of course you=92re right. =93It=92s working in hardware=94 was more of a = hint > that it might not be totally doomed. > > > How would you expect the tools to consider the timing relationship > > between two clocks divided down from an 825 MHz (~1.2 ns period) > > clock? > > Maybe I wasn=92t clear enough, but the two clocks are related by a known > fraction. They are both derived from the 125 MHz input clock. clk_28 =3D > 125*7/31 and clk_25 =3D 125/5 and hence clk_28 =3D 35/31*clk_25. And I > expect the tools to consider the timing relationship because the ISE/ > XST/DCM documentation states that the software derives a new PERIOD > for each of the DCM output clocks and determines the clock > relationships between the output clock domains. And that is also what > the timing report in my previous post reflects. > > > I solve the synchronization problem once at the interface > > and never have to worry about it again. > > Seems like a good idea. > > > This is a lot simpler to think about looking at a diagram. =A0Maybe I > > need to write this up. > > Please do that! I lost you somewhere in between the domains..., but I > would very much like to see how you solve the clock domain crossing. I don't have time to draw a diagram, but here is some code. I've had to edit out a lot of support circuitry which is not related, I hope I didn't screw this up. Scfg_Sync : process (SysClk, SysRst) begin if (SysRst =3D '1') then Scfg_SysClk <=3D '0'; elsif (falling_edge(SysClk)) then if (Clk_en =3D '1') then Scfg_SysClk <=3D not Scfg_StbLatch; -- Sync across clock domains end if; end if; end process Scfg_Sync; -- Control register interface -- Clock interface and synchronize to system clock CntrlReg : process (Scfg_Str, IF_EN) begin if (IF_EN =3D '1') then Scfg_StbLatch <=3D '0'; Scfg_StbLatch_D <=3D '0'; elsif (rising_edge(Scfg_Str)) then Scfg_StbLatch <=3D Scfg_SysClk; -- Sync across clock domains Scfg_StbLatch_D <=3D Scfg_StbLatch; end if; end process CntrlReg; Scfg_clk_en <=3D Scfg_StbLatch xor Scfg_StbLatch_D; Every time the clock enable in the SysClk domain is asserted, the loop signal Scfg_SysClk toggles generating an edge which is detected by the concurrent statement at the end. That logic can also be registered to help with metastability issues since Scfg_StbLatch will go metastable. To convey the clock SysClk to the other domain, just remove the if (Clk_en =3D '1') and let every rising edge send an transition to the other domain. The Scfg_Str domain has to be clocked at least as fast as the edge rate of Scfg_SysClk for an enable or twice as fast for a clock. Getting data across just requires that the data be held stable until it is clocked into the receiving domain. Sometimes this does not require an interface register at all depending on the particulars of the interface timing, etc. Rick From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 20:40:33 -0800 Organization: solani.org Lines: 36 Message-ID: <20101213204033.7c01f784@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292301634 32540 eJwFwQkBwDAIA0BLFEho5TAe/xJ2B+NhhRN0LFbwzuBWvrgfbCuaKeGuJpkhs60ZltShq/YPEq4Qyg== (14 Dec 2010 04:40:34 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Tue, 14 Dec 2010 04:40:34 +0000 (UTC) X-User-ID: eJwNw4kNwDAIBLCVCP+NQ4HsP0JjySZ+vEPdXO3aHQiI+aVCHOGsXbRR7XxDiMq3krZxU/EDCqEQ4Q== X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:terNPMwX1t3Vnqytxc/RQWbg7BA= X-NNTP-Posting-Host: eJwFwYEBwCAIA7CX7KAV3qmT/08wYQg6O0UlhyODXc6FgW9Vi5+98Cew63S0MkHcnuhLPwMxECA= Xref: feeder.eternal-september.org comp.lang.vhdl:4520 On Mon, 13 Dec 2010 00:23:30 +0100 Alessandro Basili wrote: > http://mysite.ncnetwork.net/reszotzl/uart.vhd > > Al > > Am I missing something, or is the transmitter slightly flawed in this code? I seem to see the following: 1. At some point, TxState_v is SEND, and you reach TxBitSampleCount_v = tic_per_bit_g and hence bit_done is true. Also, TxBitCount_v is 7. 2. You enter the "if" block in the SEND case in procedure tx_state. You set TxBitSampleCount_v to 0, serial_out_v to Tx_v(TxBitCount_v) = Tx_v(7). You set TxBitCount_v to TxBitCount_v+1 = 8. You notice that TxBitCount_v=char_len_g=8 and hence set TxState_v to STOP. 3. tic_per_bit_g clocks later, you enter the "if" block in the STOP case. You set serial_out_v to '1' and TxState_v to IDLE. 4. From this moment, if the application queries the status register, you will see that TxState_v is IDLE and hence report transmitter ready. The application could thus immediately strobe another byte of data into the transmit data register. Then tx_state will transition to TxState_v = START and, on the next clock, set serial_out_v to '0'. Problem: this might not have been a full bit-time since you started sending the '1' stop bit! You never actually guarantee to wait for the full stop bit to pass before accepting new data from the application in the transmit data register! Or am I missing something? Chris From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 21:32:44 -0800 (PST) Organization: http://groups.google.com Lines: 65 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292304764 11885 127.0.0.1 (14 Dec 2010 05:32:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 05:32:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4521 On Dec 13, 12:31=A0pm, Andy wrote: > On Dec 11, 10:44=A0am, Brian Drummond > wrote: > > > > > >What I mean is, if I want a down counter that uses the carry out to > > >give me an "end of count" flag, why can't I get that in a simple and > > >clear manner? =A0 > > > Here the issue appears to be how to get at the carry out of a counter..= . > > the syntax of integer arithmetic doesn't provide an easy way to do that= by > > default, in any language I know (other than assembler for pre-RISC CPUs= , with > > their flag registers). > > > It seems to me that you have two choices ... > > (1) implement an n-bit counter, and augment it in some way to recreate = the carry > > out (unfortunately you are fighting the synthesis tool in the process) > > > (2) implement an n+1 bit counter, with the excess bit assigned to the c= arry, and > > trust the synthesis tool to eliminate the excess flip-flop at the optim= isation > > stage... > > > I am willing to guess the second approach would be simpler. > > I have found the 1st approach far simpler, by using a natural subtype > for the counter. Then (count - 1 < 0) is the carry out for a down > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit > up counter. No fighting required. I won't argue that, both of these will utilize the carry out of an adder. But that may or may not be the same adder I am using to update count with. I have looked at the logic produced and at some time found two, apparently identical adder chains used, one of which had all outputs unconnected other than the carry out of the top and the other used the sum outputs to feed the register with the top carry ignored. Sure, there may have been something about my code that prevented these two adders being merged, but I couldn't figure out what it was. I see a number of posts that don't really get what I am trying to say. I'm not arguing that you can't do what you want in current HDLs. I am not saying I want to use something similar to assembly language to provide the maximum optimization possible. I am saying I find it not infrequent that HDL gives nothing close to optimal results because the coding style required was not obvious. I'm saying that it seems like it should be easier to get the sort of simple structures that are commonly used without jumping through hoops. Heck, reading the Lattice HDL user guide (not sure if that is the actual name or not) they say you shouldn't try to infer memory at all, instead you should instantiate it! Memory seems like it should be so easy to infer... I don't know Verilog that well, but I do know VHDL is a pig in many ways. It just seems like it could have been much simpler rather than being such a pie-in-the-sky language. Rick From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!l17g2000yqe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 21:47:43 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: <51c54fde-234b-4b8e-853c-69216afae05e@l17g2000yqe.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292305663 7889 127.0.0.1 (14 Dec 2010 05:47:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 05:47:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l17g2000yqe.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4522 On Dec 13, 12:06=A0pm, d_s_klein wrote: > On Dec 10, 8:25=A0pm, rickman wrote: > > > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > > use VHDL which we all know is a pig in many ways with its verbosity > > and arcane type conversion gyrations. =A0But what bothers me most of al= l > > is that I have to learn how to tell the tools in their "language" how > > to construct the efficient logic I can picture in my mind. By > > "language" I don't mean the HDL language, but actually the specifics > > of a given inference tool. > > =A0 =A0 > > > Rick > > Back in the 8086 days, I had to do the same thing with compilers. =A0I > spent a fair amount of time learning how the code generation phase > worked so I could get the tools to work properly. =A0I remember a "brand- > name" 'C' compiler very carefully generating code to keep the loop > control variable in the CX register, then at the end of the loop > moving CX to AX and adding minus-one. =A0(For those that don't program > 86's in assembly, the CX register is a special purpose register for > the 'LOOP' instruction.) =A0Now that processors are real fast, and > memory is very cheap, I don't worry so much about efficient code. > > I would draw a parallel to the frustrations you are having with HDLs. > Another parallel I would draw is that when I wanted 'very fast tight > code' I would code certain modules in assembly, and link them with 'C' > routines. =A0When the synthesizer just won't get it right, I draw it a > picture. =A0(Which is one advantage the Acme-Brand tool has over the > Brand-X tool) > > Yeah, it's not portable, and it isn't "right". =A0But I'm getting > product out the door. > > RK. I never said I don't get a working design. I just feel that HDLs are more complex than useful. BTW, I don't agree with the analogy between HDLs and compilers. For one, you are considering the case of PCs where speed and memory are virtually unlimited. My apps tend to be more like coding for a PIC with 8K Flash and 1K RAM. A perfect target for a Forth cross- compiler, but likely a poor target for a C compiler. Where is the Forth equivalent for hardware design? Rick From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w18g2000vbe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 00:54:28 -0800 (PST) Organization: http://groups.google.com Lines: 85 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292316869 10183 127.0.0.1 (14 Dec 2010 08:54:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 08:54:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w18g2000vbe.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4523 On Dec 14, 5:32=A0am, rickman wrote: > On Dec 13, 12:31=A0pm, Andy wrote: > > > > > On Dec 11, 10:44=A0am, Brian Drummond > > wrote: > > > > >What I mean is, if I want a down counter that uses the carry out to > > > >give me an "end of count" flag, why can't I get that in a simple and > > > >clear manner? =A0 > > > > Here the issue appears to be how to get at the carry out of a counter= ... > > > the syntax of integer arithmetic doesn't provide an easy way to do th= at by > > > default, in any language I know (other than assembler for pre-RISC CP= Us, with > > > their flag registers). > > > > It seems to me that you have two choices ... > > > (1) implement an n-bit counter, and augment it in some way to recreat= e the carry > > > out (unfortunately you are fighting the synthesis tool in the process= ) > > > > (2) implement an n+1 bit counter, with the excess bit assigned to the= carry, and > > > trust the synthesis tool to eliminate the excess flip-flop at the opt= imisation > > > stage... > > > > I am willing to guess the second approach would be simpler. > > > I have found the 1st approach far simpler, by using a natural subtype > > for the counter. Then (count - 1 < 0) is the carry out for a down > > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit > > up counter. No fighting required. > > I won't argue that, both of these will utilize the carry out of an > adder. =A0But that may or may not be the same adder I am using to update > count with. =A0I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. =A0Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. > > I see a number of posts that don't really get what I am trying to > say. =A0I'm not arguing that you can't do what you want in current > HDLs. =A0I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. =A0I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. =A0I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! =A0Memory seems like it should be so > easy to infer... > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. =A0It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. > > Rick >From all this reading, Im guessing its not a problem with the language you have, its more the synthesisors. So my two thoughts: 1. Try AHDL - its pretty explicit (but you'll be stuck with Altera). 2. Instead of getting pissed off with the tools and pretending its an HDL problem, how about raising the issue with the vendors and asking them why they've done it the way the have. Personally, I have never had too much of a problem with the tools. The Firmware works as I intend. Im not usually interested in the detail because it works, it ships, the customer pays and we make a profit. I dont care if a counter has used efficient carry out logic or not - it works and thats all the customer cares about. When its working, or I have fit problems I can then go into the finer detail. From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.85.MISMATCH!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-ID: <4D075258.7010904@jandecaluwe.com> Date: Tue, 14 Dec 2010 12:17:44 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Andy Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> In-Reply-To: <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 70 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b99fdfda.news.skynet.be X-Trace: 1292325465 news.skynet.be 14256 91.177.199.237:37361 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4524 Andy wrote: > On Dec 12, 3:15 am, rickman wrote: >> I'm not that worried about the >> particulars of this case. I am just lamenting that everything I do in >> an HDL is about describing the behavior of the logic and not actually >> describing the logic itself. I am an old school hardware designer. I >> cut my teeth on logic in TO packages, hand soldering the wire leads. >> I still think in terms of the hardware, not the software to describe >> the hardware. Many of my designs need to be efficient in terms of >> hardware used and so I have to waste time learning how to get what I >> want from the tools. Sometimes I just get tired of having to work >> around the tools rather than with them. > > I seem to recall a similar argument when assemblers gave way to higher > level language compilers... > > This change in digital hardware design is not unlike the change from > one-man furniture shops to furniture factories. The craftsmen of the > one-man shops painstakingly treated every detail as critical to their > product: a chair. And the result was an exquisite piece of furniture, > albeit at a very high price, and very low volume (unless you hired a > lot of one man shops at the same time). > > Circuit designers are no different (being one myself, dating back to > those "I can do that function in one less part" days gone by). But the > target has changed. We no longer need a chair, we need a stadium full > of them. And we need the elevators, climate control, fire suppression, > lighting, and all the other support systems, to go along with them. > > Perhaps we should take a step back, and look at what we really need > (hint: a place for a lot of people to watch an event, while seated > most of the time). Now I can optimize my stadium to recognize that all > of my seats don't need to be finely crafted pieces of furniture. But I > don't know that until I focus on the requirements: "What must my > project do?" So, instead of finding a way to describe the project as > a collection of specific chairs, elevators and fire extinguishers, we > need to describe it as a set of desired behaviors, and then, through > some process (hopefully semi-automated), convert that description into > an optimized design for the stadium. Could the craftsman and his tools > have done that? > > What do you want from the tools, a collection of exquisitely crafted > chairs, or an efficient stadium? This analogy suggests the need for a compromise, which I think isn't there. I don't see a case where the schematic entry craftsman can realistically hope to beat the guy with the HDL tools. For example, for smallish designs, it can be shown that logic synthesis can generate a solution close to the optimum, *regardless* of the quality of the starting point. The craftsman can draw any pictures he wants, even if the tool guy writes the worst possible code, the synthesis result will still be as good or better. Of course, for realistic, larger designs, the structure of the input code becomes more and more significant. But thanks to powerful heuristics, local optimization algorithms, and the ability to recognize higher level structures, this is a gradual process. In contrast, the craftsman's ability to cope with complexity quickly detoriates beyond a certain point. As a result, he has to rely on logic-wise inefficient strategies, such as excessive hierarchy. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:55:59 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 14 Dec 2010 13:50:37 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 69 Message-ID: <4d07681e$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 1c276260.news.skynet.be X-Trace: 1292331038 news.skynet.be 14247 91.177.199.237:56170 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4525 rickman wrote: > On Dec 13, 12:31 pm, Andy wrote: >> On Dec 11, 10:44 am, Brian Drummond >> wrote: >> >> >> >>>> What I mean is, if I want a down counter that uses the carry out to >>>> give me an "end of count" flag, why can't I get that in a simple and >>>> clear manner? >>> Here the issue appears to be how to get at the carry out of a counter... >>> the syntax of integer arithmetic doesn't provide an easy way to do that by >>> default, in any language I know (other than assembler for pre-RISC CPUs, with >>> their flag registers). >>> It seems to me that you have two choices ... >>> (1) implement an n-bit counter, and augment it in some way to recreate the carry >>> out (unfortunately you are fighting the synthesis tool in the process) >>> (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and >>> trust the synthesis tool to eliminate the excess flip-flop at the optimisation >>> stage... >>> I am willing to guess the second approach would be simpler. >> I have found the 1st approach far simpler, by using a natural subtype >> for the counter. Then (count - 1 < 0) is the carry out for a down >> counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit >> up counter. No fighting required. > > I won't argue that, both of these will utilize the carry out of an > adder. But that may or may not be the same adder I am using to update > count with. I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. > > I see a number of posts that don't really get what I am trying to > say. Probably because many people don't see what you say you are seeing, so they must think you don't have a case. I'm not arguing that you can't do what you want in current > HDLs. I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! Memory seems like it should be so > easy to infer... > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. I think Verilog will suit you better as a language, you really should consider switching one of these days. However, there is no reason why it would help you with the issues that you say you are seeing here. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!f20g2000vbc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 06:09:42 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> <4D075258.7010904@jandecaluwe.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292335782 26728 127.0.0.1 (14 Dec 2010 14:09:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 14:09:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000vbc.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4526 On Dec 14, 5:17=A0am, Jan Decaluwe wrote: > Andy wrote: > > On Dec 12, 3:15 am, rickman wrote: > >> I'm not that worried about the > >> particulars of this case. =A0I am just lamenting that everything I do = in > >> an HDL is about describing the behavior of the logic and not actually > >> describing the logic itself. =A0I am an old school hardware designer. = =A0I > >> cut my teeth on logic in TO packages, hand soldering the wire leads. > >> I still think in terms of the hardware, not the software to describe > >> the hardware. =A0Many of my designs need to be efficient in terms of > >> hardware used and so I have to waste time learning how to get what I > >> want from the tools. =A0Sometimes I just get tired of having to work > >> around the tools rather than with them. > > > I seem to recall a similar argument when assemblers gave way to higher > > level language compilers... > > > This change in digital hardware design is not unlike the change from > > one-man furniture shops to furniture factories. The craftsmen of the > > one-man shops painstakingly treated every detail as critical to their > > product: a chair. And the result was an exquisite piece of furniture, > > albeit at a very high price, and very low volume (unless you hired a > > lot of one man shops at the same time). > > > Circuit designers are no different (being one myself, dating back to > > those "I can do that function in one less part" days gone by). But the > > target has changed. We no longer need a chair, we need a stadium full > > of them. And we need the elevators, climate control, fire suppression, > > lighting, and all the other support systems, to go along with them. > > > Perhaps we should take a step back, and look at what we really need > > (hint: a place for a lot of people to watch an event, while seated > > most of the time). Now I can optimize my stadium to recognize that all > > of my seats don't need to be finely crafted pieces of furniture. But I > > don't know that until I focus on the requirements: "What must my > > project do?" =A0So, instead of finding a way to describe the project as > > a collection of specific chairs, elevators and fire extinguishers, we > > need to describe it as a set of desired behaviors, and then, through > > some process (hopefully semi-automated), convert that description into > > an optimized design for the stadium. Could the craftsman and his tools > > have done that? > > > What do you want from the tools, a collection of exquisitely crafted > > chairs, or an efficient stadium? > > This analogy suggests the need for a compromise, which I think isn't > there. > > I don't see a case where the schematic entry craftsman can > realistically hope to beat the guy with the HDL tools. For example, > for smallish designs, it can be shown that logic synthesis can > generate a solution close to the optimum, *regardless* of the quality > of the starting point. The craftsman can draw any pictures he wants, > even if the tool guy writes the worst possible code, the synthesis > result will still be as good or better. > > Of course, for realistic, larger designs, the structure of the > input code becomes more and more significant. But thanks to > powerful heuristics, local optimization algorithms, and the > ability to recognize higher level structures, this is a > gradual process. In contrast, the craftsman's ability to > cope with complexity quickly detoriates beyond a certain > point. As a result, he has to rely on logic-wise inefficient > strategies, such as excessive hierarchy. > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0 Python as a HDL:http://www.myhdl.org > =A0 =A0 VHDL development, the modern way:http://www.sigasi.com > =A0 =A0 Analog design automation:http://www.mephisto-da.com > =A0 =A0 World-class digital design:http://www.easics.com- Hide quoted tex= t - > > - Show quoted text - I've seen too many examples where a bit more performance can be obtained by either tweaking the code, or "hard-coding" the solution. They are getting fewer and farther between, but they are still there. My point was that the extra performance is seldom, but not never, needed, and on a larger scale, letting the synthesis tool do the heavy lifting results in a better overall design MOST of the time. There're ain't no 100% solutions. If you try to hard code 100%, you lose; if you try to let the synthesis tool do 100%, you lose. Compromise is necessary. Andy From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c17g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 07:04:22 -0800 (PST) Organization: http://groups.google.com Lines: 73 Message-ID: <7a3d3125-07cf-4434-b484-cdeecb444339@c17g2000prm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292339095 23985 127.0.0.1 (14 Dec 2010 15:04:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:04:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c17g2000prm.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4527 On Dec 13, 11:32=A0pm, rickman wrote: > > I won't argue that, both of these will utilize the carry out of an > adder. =A0But that may or may not be the same adder I am using to update > count with. =A0I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. =A0Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. I have very seldom have that problem (two adders), and when I do, the reason (usually some extra condition on one adder that was not there on the other) is easily found and fixed. To be fair, the synthesis tools do not always implement a simple carry chain for either, but what they do implement is at least as fast and compact as a simple carry chain. > > I see a number of posts that don't really get what I am trying to > say. =A0I'm not arguing that you can't do what you want in current > HDLs. =A0I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. =A0I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. =A0I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. I think "obvious" is related closely to the experience level of the observer. What appears obvious to me may not be obvious (yet) to you. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! =A0Memory seems like it should be so > easy to infer... Either their documentation is woefully out of date, or their synthesis tool is far from the state of the industry. > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. =A0It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. > Trust me; about 18 years ago, I was in exactly the same boat WRT to VHDL synthesis. Why do I need this much "stuff" to do what I can do in a sheet of schematics, and know without hardly thinking about it that it is correct? And at the time, the synthesis tools were not nearly as good as they are now, and FPGA performance was also not nearly as good, so much more of my typical design work needed to be done at a lower level. But sythesis and FPGA performance are now vastly superior to what they were then, and I can do the vast majority of a design without having to deal too much at the gates and flops level. It is a difficult paradigm to embrace when you come from a structural, schematic based design background. As for whether Verilog might work better for you, perhaps. I know I could not be nearly as productive with the constraints of what you cannot do in verilog at the higher levels of abstraction. Something like the fixed and floating point capabilities of VHDL is completely beyond the capabilities of verilog without major changes to the language, but all it took was a couple of packages in VHDL. The only problem any synthesis tools had with it was tied to the fact that they assumed (improperly) that only non-negative indices would ever be used for vectors. Andy From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!postnews.google.com!35g2000prt.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Tue, 14 Dec 2010 07:04:39 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292339111 12332 127.0.0.1 (14 Dec 2010 15:05:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:05:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 35g2000prt.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4528 On 13 d=E9c, 10:23, Martin Thompson wrote: > rickman writes: > > How exactly would my simulation be different from synthesis if I used > > a max of 200 for a counter? =A0If my simulation tries to increment the > > counter past 200 it stops! =A0That would not be an issue of different > > results, that would be my simulation failing to complete! =A0If my usag= e > > of the counter never pushes it past 200, then the simulation and synth > > match. > > OK, yes, I think I expressed myself badly :) > > I was trying to talk about unexpected behaviour, and confused the > issue by talking about mismatches. =A0As I said to Jan, if the > simulation doesn't test far enough, one might get different behaviour > to what one (might) expect (however innaccurate that expectation may be). > > > I think people are making far too big of an issue about this. =A0An HDL > > is supposed to be describing hardware, hence the name HDL. =A0If you > > take the position that the simulation and synthesis should always > > match 10% you can never design anything real. =A0 > > =A0 =A0 =A0 =A0 ^^^ > I assume you mean 100% there? > > > If I have a counter that is only needed for values of 200 or less > > and I don't care what happens when the value is over 200, then case > > 2 is perfectly ok. > > Quite so, I never intended to say anything other. > > > > > The OP has not responded, but I think he is just asking what the > > synthesizer does. =A0I don't think his issue is about what the "correct= " > > thing to do is. > > On re-reading the OP with that in mind, I agree. > > Sorry for any confusion caused! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.co.uk/capabilities/39-electronic-hardware Thnaks for the answers. My question was mostly out of curiosity, I tried it with ISE and I got a regular 8-bit wrapround counter. From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 07:57:07 -0800 (PST) Organization: http://groups.google.com Lines: 122 Message-ID: <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292342228 18999 127.0.0.1 (14 Dec 2010 15:57:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:57:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4529 On Dec 14, 3:54=A0am, Tricky wrote: > On Dec 14, 5:32=A0am, rickman wrote: > > > > > On Dec 13, 12:31=A0pm, Andy wrote: > > > > On Dec 11, 10:44=A0am, Brian Drummond > > > wrote: > > > > > >What I mean is, if I want a down counter that uses the carry out t= o > > > > >give me an "end of count" flag, why can't I get that in a simple a= nd > > > > >clear manner? =A0 > > > > > Here the issue appears to be how to get at the carry out of a count= er... > > > > the syntax of integer arithmetic doesn't provide an easy way to do = that by > > > > default, in any language I know (other than assembler for pre-RISC = CPUs, with > > > > their flag registers). > > > > > It seems to me that you have two choices ... > > > > (1) implement an n-bit counter, and augment it in some way to recre= ate the carry > > > > out (unfortunately you are fighting the synthesis tool in the proce= ss) > > > > > (2) implement an n+1 bit counter, with the excess bit assigned to t= he carry, and > > > > trust the synthesis tool to eliminate the excess flip-flop at the o= ptimisation > > > > stage... > > > > > I am willing to guess the second approach would be simpler. > > > > I have found the 1st approach far simpler, by using a natural subtype > > > for the counter. Then (count - 1 < 0) is the carry out for a down > > > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bi= t > > > up counter. No fighting required. > > > I won't argue that, both of these will utilize the carry out of an > > adder. =A0But that may or may not be the same adder I am using to updat= e > > count with. =A0I have looked at the logic produced and at some time > > found two, apparently identical adder chains used, one of which had > > all outputs unconnected other than the carry out of the top and the > > other used the sum outputs to feed the register with the top carry > > ignored. =A0Sure, there may have been something about my code that > > prevented these two adders being merged, but I couldn't figure out > > what it was. > > > I see a number of posts that don't really get what I am trying to > > say. =A0I'm not arguing that you can't do what you want in current > > HDLs. =A0I am not saying I want to use something similar to assembly > > language to provide the maximum optimization possible. =A0I am saying I > > find it not infrequent that HDL gives nothing close to optimal results > > because the coding style required was not obvious. =A0I'm saying that i= t > > seems like it should be easier to get the sort of simple structures > > that are commonly used without jumping through hoops. > > > Heck, reading the Lattice HDL user guide (not sure if that is the > > actual name or not) they say you shouldn't try to infer memory at all, > > instead you should instantiate it! =A0Memory seems like it should be so > > easy to infer... > > > I don't know Verilog that well, but I do know VHDL is a pig in many > > ways. =A0It just seems like it could have been much simpler rather than > > being such a pie-in-the-sky language. > > > Rick > > From all this reading, Im guessing its not a problem with the language > you have, its more the synthesisors. > > So my two thoughts: > > 1. Try AHDL - its pretty explicit (but you'll be stuck with Altera). > 2. Instead of getting pissed off with the tools and pretending its an > HDL problem, how about raising the issue with the vendors and asking > them why they've done it the way the have. > > Personally, I have never had too much of a problem with the tools. The > Firmware works as I intend. Im not usually interested in the detail > because it works, it ships, the customer pays and we make a profit. I > dont care if a counter has used efficient carry out logic or not - it > works and thats all the customer cares about. When its working, or I > have fit problems I can then go into the finer detail. Ok, so there ARE times when you care if the synthesis uses two carry chains instead of one or if it used a set of LUTs to check terminal case rather than the carry chain. You are just saying that is not so often. That's not the same as saying, "It works, it ships". The same is true for most people I'm sure and I expect no small number of them virtually never look past the HDL. But when you do need speed or minimal area this can be important. I recently did a design where I had to cram five pounds of logic into a 4 pound FPGA. It ended up working, but I had to optimize every module. That worked out ok for the most part as I typically test bench each module anyway, so I just had to do a synthesis on it as well and work the code to get a good size result. That is how I found things like double carry chains, etc. That is also why I am now wondering why we have a language that is so far removed from the end product. I don't agree that this is a matter for the synthesis vendors. Like I said somewhere else, if you want a particular solution, the vendors tell you to instantiate. Instantiation is very undesirable since it is not portable across vendors and often not portable across product lines within a vendor! The language is flexible, that's for sure. But it seems to be flexible without purpose. Many of the changes currently being suggested in VHDL is to provide an easier to use language by getting a bit closer to what engineers want to use it for. I just think that in many ways the language is way too far removed from what we want to do with it. Rick From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q8g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 10:47:51 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292352471 12618 127.0.0.1 (14 Dec 2010 18:47:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 18:47:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q8g2000prm.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4530 The last time I had to cram too much logic into too little FPGA, I optimized the architecture, not the implementation. Among other changes, I took a half dozen separate UARTs, and replaced them with a six channel time-division-multiplexed UART using distributed RAM (it could have been a sixteen channel UART for virtually the same amount of resources excluding IO). Each channel still had independent baud rate, word length, parity, #stop bits, interrupts, etc. The design placed and routed in no time, with plenty of resources to share (it had been about 125% utilization). The reason I bring this up is that often we have challenges that are better addressed at the architectural level, rather than the implementation level. In these cases, a description farther above the gates and flops is preferable, becuase it is easier to re-work. You can bet I did not instantiate any RAMs in that design! That is not to say that it is never necessary to deal with the gates and flops (and carry chains, etc.). Sometimes we do, but it is relatively rare. So we rarely need a language that is "closer to the end product", and we often need a language that allows us to design at a higher level. I'm not really sure exactly what you want in your new flavor of HDL. Do you have any specific ideas? How would you make it closer to the end product? Andy From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!ecngs!feeder2.ecngs.de!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 14 Dec 2010 20:16:12 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> In-Reply-To: <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 34 Message-ID: <4d07c27b$0$14258$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: d7bf9db0.news.skynet.be X-Trace: 1292354171 news.skynet.be 14258 91.177.199.237:46068 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4531 Andy wrote: > The last time I had to cram too much logic into too little FPGA, I > optimized the architecture, not the implementation. Among other > changes, I took a half dozen separate UARTs, and replaced them with a > six channel time-division-multiplexed UART using distributed RAM (it > could have been a sixteen channel UART for virtually the same amount > of resources excluding IO). Each channel still had independent baud > rate, word length, parity, #stop bits, interrupts, etc. The design > placed and routed in no time, with plenty of resources to share (it > had been about 125% utilization). > > The reason I bring this up is that often we have challenges that are > better addressed at the architectural level, rather than the > implementation level. In these cases, a description farther above the > gates and flops is preferable, becuase it is easier to re-work. You > can bet I did not instantiate any RAMs in that design! > > That is not to say that it is never necessary to deal with the gates > and flops (and carry chains, etc.). Sometimes we do, but it is > relatively rare. So we rarely need a language that is "closer to the > end product", and we often need a language that allows us to design at > a higher level. Finally a breath of fresh air :-) Thanks for sharing a great story that should remind all of us where the true opportunities for optimization are to be found. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Dec 24 22:56:00 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!w18g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 14:40:04 -0800 (PST) Organization: http://groups.google.com Lines: 64 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 108.8.13.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292366404 6336 127.0.0.1 (14 Dec 2010 22:40:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 22:40:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w18g2000vbe.googlegroups.com; posting-host=108.8.13.125; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4532 On Dec 14, 1:47=A0pm, Andy wrote: > The last time I had to cram too much logic into too little FPGA, I > optimized the architecture, not the implementation. Among other > changes, I took a half dozen separate UARTs, and replaced them with a > six channel time-division-multiplexed UART using distributed RAM (it > could have been a sixteen channel UART for virtually the same amount > of resources excluding IO). Each channel still had independent baud > rate, word length, parity, #stop bits, interrupts, etc. The design > placed and routed in no time, with plenty of resources to share (it > had been about 125% utilization). > > The reason I bring this up is that often we have challenges that are > better addressed at the architectural level, rather than the > implementation level. In these cases, a description farther above the > gates and flops is preferable, becuase it is easier to re-work. You > can bet I did not instantiate any RAMs in that design! > > That is not to say that it is never necessary to deal with the gates > and flops (and carry chains, etc.). Sometimes we do, but it is > relatively rare. So we rarely need a language that is "closer to the > end product", and we often need a language that allows us to design at > a higher level. > > I'm not really sure exactly what you want in your new flavor of HDL. > Do you have any specific ideas? How would you make it closer to the > end product? > > Andy You keep saying things like "a description farther above the gates and flops is preferable". I have not said I want to place LUTs and FFs. I would like to *know* what the logic will be for a given piece of code without having to run it through the tool and wading through a machine drawn schematic. I am all in favor of a language that allows higher level constructs. But that does not require that visibility to and knowledge of the lower levels be blocked. The current languages are much like C compilers in that the take entire design, break it down to its lowest level and then builds it back up in a way that it chooses. I think that philosophy is wrong. I don't think I need to work with total abstraction to be effective as a designer. Ray Andraka has made a career of designing efficient designs in an efficient way. He uses VHDL, but he uses a lot of instantiation, which to him is very much like written schematics. That is not what I want. I wish I could tell you how I'd like to see this solved. If I could do that, I'd likely start a company doing it. I guess it would be something like instantiation but without all the hassle of instantiation at the VHDL level. Heck, maybe what I am trying to describe is C? or maybe even Forth? I have thought before that Forth would make an interesting HDL. It is very hierarchical and it most likely could support very efficient simulation by compiling the original program to native machine code, but with extremely fast compiles too. I was hoping to get some input from others on this rather than a lot of reasons why the current HDLs are so good. I know their strengths, but I can also see their weaknesses. That is what I am discussing here, the weaknesses. Rick From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 16:34:36 -0800 Lines: 15 Message-ID: <8mqgorFls9U1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9GCVCfWB2uNssNa1VyTNJQkgTUqX2u6Kq1OO9jRoJjTxFVCsyl Cancel-Lock: sha1:co13jrYnwxsyF4Rjl1TEkiXiWzw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <20101213204033.7c01f784@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4533 On 12/13/2010 8:40 PM, Christopher Head wrote: > Problem: this might not have been a full bit-time since you started > sending the '1' stop bit! You never actually guarantee to wait for the > full stop bit to pass before accepting new data from the application in > the transmit data register! > > Or am I missing something? Note the source comment: -- reads anytime, expects smart,handshaking reader Click on waves or zoom for the sim details -- Mike From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 21:39:50 -0800 Organization: solani.org Lines: 42 Message-ID: <20101214213950.4f7e9e1b@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mqgorFls9U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292391591 26078 eJwNyMEBwEAEBMCW4thFOXLov4RkngOl8LoRNCz27mOv1plwl9a5EGFP5DhPWmtYN/4QZFXpByAPET0= (15 Dec 2010 05:39:51 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Wed, 15 Dec 2010 05:39:51 +0000 (UTC) X-User-ID: eJwNysEBwCAIA8CVCiahjCNQ9x/B3vu4ZOqAKPDwAG3sb5mHSXvctSKLj++sROX/AxbzDhOnL/8hEBk= X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:lTUooLcDx/2bRytfz2OSHGU+gD0= X-NNTP-Posting-Host: eJwNxMkVADAEBcCWLB9POYj0X0IyhzF19gm4OezaFZUddEz+sog5RZWnzlmqRm8wCCVqTsh6FqsQsA== Xref: feeder.eternal-september.org comp.lang.vhdl:4534 On Tue, 14 Dec 2010 16:34:36 -0800 Mike Treseler wrote: > On 12/13/2010 8:40 PM, Christopher Head wrote: > > > Problem: this might not have been a full bit-time since you started > > sending the '1' stop bit! You never actually guarantee to wait for > > the full stop bit to pass before accepting new data from the > > application in the transmit data register! > > > > Or am I missing something? > > Note the source comment: > -- reads anytime, expects smart,handshaking reader > > Click on waves or zoom for the sim details > > -- Mike Sorry, I still don't see it. Looking at the write of 0x83 (the second write in the zoom example), I see the data going out over serialout_s, and I watch the txstate_v. There's a low between time 9900 and 10us for the start bit, then two bits of high time for bits 0 and 1, then a pile of low time, then you see serialout_s go high just before time 10200. That's bit 7 (MSb), which for data 0x83 is high. Looking down at txstate_v, it changes from "send" to "stop" right at the start of that bit, then changes from "stop" to "idle" one bit time later. But that wasn't the stop bit, that was data bit 7! The stop bit has only just started, right where txstate_v became "idle". If the application polls the status register right then, because txstate_v=idle, it will see TxReady asserted, indicating the transmitter is willing to accept another data byte. If it immediately sends that next byte, the start bit will happen only a cycle or two later. With only three clock cycles per bit, the system probably can't actually turn around fast enough for the start bit to trample on the stop bit, but it could with a faster system clock or lower baud rate. Or did the idea of a "smart, handshaking reader" mean something else? I took it to mean that the application should poll the status register and wait for TxReady before sending data. Chris From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q18g2000vbm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 00:55:49 -0800 (PST) Organization: http://groups.google.com Lines: 88 Message-ID: <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292403349 29479 127.0.0.1 (15 Dec 2010 08:55:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 08:55:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4535 On Dec 14, 10:40=A0pm, rickman wrote: > On Dec 14, 1:47=A0pm, Andy wrote: > > > > > The last time I had to cram too much logic into too little FPGA, I > > optimized the architecture, not the implementation. Among other > > changes, I took a half dozen separate UARTs, and replaced them with a > > six channel time-division-multiplexed UART using distributed RAM (it > > could have been a sixteen channel UART for virtually the same amount > > of resources excluding IO). Each channel still had independent baud > > rate, word length, parity, #stop bits, interrupts, etc. The design > > placed and routed in no time, with plenty of resources to share (it > > had been about 125% utilization). > > > The reason I bring this up is that often we have challenges that are > > better addressed at the architectural level, rather than the > > implementation level. In these cases, a description farther above the > > gates and flops is preferable, becuase it is easier to re-work. You > > can bet I did not instantiate any RAMs in that design! > > > That is not to say that it is never necessary to deal with the gates > > and flops (and carry chains, etc.). Sometimes we do, but it is > > relatively rare. So we rarely need a language that is "closer to the > > end product", and we often need a language that allows us to design at > > a higher level. > > > I'm not really sure exactly what you want in your new flavor of HDL. > > Do you have any specific ideas? How would you make it closer to the > > end product? > > > Andy > > You keep saying things like "a description farther above the gates and > flops is preferable". =A0I have not said I want to place LUTs and FFs. > I would like to *know* what the logic will be for a given piece of > code without having to run it through the tool and wading through a > machine drawn schematic. > > I am all in favor of a language that allows higher level constructs. > But that does not require that visibility to and knowledge of the > lower levels be blocked. > > The current languages are much like C compilers in that the take > entire design, break it down to its lowest level and then builds it > back up in a way that it chooses. =A0I think that philosophy is wrong. > I don't think I need to work with total abstraction to be effective as > a designer. =A0Ray Andraka has made a career of designing efficient > designs in an efficient way. =A0He uses VHDL, but he uses a lot of > instantiation, which to him is very much like written schematics. > That is not what I want. > > I wish I could tell you how I'd like to see this solved. =A0If I could > do that, I'd likely start a company doing it. =A0I guess it would be > something like instantiation but without all the hassle of > instantiation at the VHDL level. =A0Heck, maybe what I am trying to > describe is C? =A0or maybe even Forth? =A0I have thought before that Fort= h > would make an interesting HDL. =A0It is very hierarchical and it most > likely could support very efficient simulation by compiling the > original program to native machine code, but with extremely fast > compiles too. > > I was hoping to get some input from others on this rather than a lot > of reasons why the current HDLs are so good. =A0I know their strengths, > but I can also see their weaknesses. =A0That is what I am discussing > here, the weaknesses. > > Rick Personally, I still dont see why this is needed, or how it would be done. HDLs offer the user the option to either abstract their designs with behavioural code or create a schematic like design with instantiations, or a mixture of both. The big problem with what you are suggesting is that Different vendors, and different parts across the same vendor, have LUTs, FFS, multipliers etc that behave differently, with different number of IOs. To cover all cases, the only way to ensure the same code works across a range is with behavioural code. The only way to know what will come out in advance is either with experience or instantiation. To get what you are suggesting would require all vendors to produce their FPGAs with the same base parts, but that will never happen. Vendors provide code templates for various things, so you should know what you are getting with these. Recently, the only things I have had to directly instantiate are Dual clock dual port RAMs, because Altera still cannot infer them from code. Im pretty sure that one day they will. From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 01:55:55 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: <1c90bd70-a381-4a05-901c-24eb095d9a93@30g2000yql.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292406955 12518 127.0.0.1 (15 Dec 2010 09:55:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 09:55:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4536 > I don't have time to draw a diagram, but here is some code. That makes it easier. Here=92s the XST RTL schematic of the circuit: http://www.mypicx.com/uploadimg/1078299247_12152010_1.jpg And a wave diagram: http://www.mypicx.com/uploadimg/694346392_12152010_2.jpg Any particular reason for using the negative edge in the Scfg_Sync process? I used the positive edge. data_in is clocked on the positive sysclk edge without enable. data_out is clocked on the positive scfg_str edge when scfg_clk_en is high. Am I using this in a way you recognize? /B From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z17g2000prz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 06:22:15 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> <1c90bd70-a381-4a05-901c-24eb095d9a93@30g2000yql.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292422936 26508 127.0.0.1 (15 Dec 2010 14:22:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 14:22:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000prz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4537 On Dec 15, 4:55 am, Beppe wrote: > > I don't have time to draw a diagram, but here is some code. > > That makes it easier. Here=92s the XST RTL schematic of the circuit: > > http://www.mypicx.com/uploadimg/1078299247_12152010_1.jpg > > And a wave diagram: > > http://www.mypicx.com/uploadimg/694346392_12152010_2.jpg This is why I hate these machine drawn schematics. The machine has no clue about the logical flow. Scfg_StbLatch should be in the same line with the other blocks clearly showing the flow with the feedback loop back to the other clock domain. The feedback loop is what makes it work (each side is not armed until the other acknowledges) and the following logic is just to reconstruct the enable or clock. > Any particular reason for using the negative edge in the Scfg_Sync > process? I used the positive edge. data_in is clocked on the positive > sysclk edge without enable. data_out is clocked on the positive > scfg_str edge when scfg_clk_en is high. > > Am I using this in a way you recognize? Yes, Scfg_Sync was required to use the falling edge in my design as it is an external interface. This looks exactly as it should look for a clock enable circuit. Metastability precautions are required for the signal Scfg_StbLatch. The only other note is to make sure the data is held stable long enough for it to be registered in the destination domain. This may require a register in the data path driven by SysClk. There are a lot of details dependent on the relative clock speeds. If you need to convey a clock enable just add that to the Scfg_SysClk register. Rick From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 19:02:09 +0100 Lines: 28 Message-ID: <8mse51FtmjU1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Dt+uXbgbID+MqghcRXH2aQoak80YCtBTyoMn1c/kZQmDiZwiO7 Cancel-Lock: sha1:cVDzXo4hbmqV/2Cyfw2x7QY1eTY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <20101213204033.7c01f784@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4538 On 12/14/2010 5:40 AM, Christopher Head wrote: > On Mon, 13 Dec 2010 00:23:30 +0100 > Alessandro Basili wrote: > >> http://mysite.ncnetwork.net/reszotzl/uart.vhd >> >> Al >> >> > > Am I missing something, or is the transmitter slightly flawed in this > code? I seem to see the following: [snip] > 4. From this moment, if the application queries the status register, > you will see that TxState_v is IDLE and hence report transmitter ready. I believe only 1 clock after TxState_v is IDLE, hence you have a 1 bit stop. > The application could thus immediately strobe another byte of data into > the transmit data register. Then tx_state will transition to TxState_v > = START and, on the next clock, set serial_out_v to '0'. > The application needs to read the 0x04 as status register and if you check the zoom file you find that read_data_v is 0x04 only one clock after the TxState_v is idle. Hence the 1 bit stop is guaranteed. Al From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!216.196.98.146.MISMATCH!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n32g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 10:40:51 -0800 (PST) Organization: http://groups.google.com Lines: 26 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292438452 3617 127.0.0.1 (15 Dec 2010 18:40:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 18:40:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000pre.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4539 To be able to "know" what hardware you are going to get requires having a language and description that, from the same code, will always produce the exact same logic, regardless of required performance, space, and target architecture. Unfortunately it also means having a language and description which will not produce reasonably optimal hardware over all combinations of those same constraints, given the same code. You can't have it both ways. I think we may have a disconnect with regards to the meaning of "higher level constructs". If you mean things like hierarchy, etc. I agree that it should not get in the way of a deterministic hardware description (and I don't think it does, though your methods of using the language may not be optimal for this). However, I take "higher level constructs" as being those that support a behavioral description ("what does the circuit do?", not "what is the circuit?"), with necessarily less direct mapping to implemented hardware. It is the use of these constructs that provides the tremendous increase in productivity over past methods (more primitive languages and schematics). You would not consider creating a word processor or spreadsheet in assembler, so why would you create a complex FPGA design with what amounts to a netlist? Andy From newsfish@newsfish Fri Dec 24 22:56:01 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!news.buerger.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 20:50:49 +0100 Lines: 118 Message-ID: <8mskgpF4joU1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net NmAUBzjkATvTLM/xQEMAow2+cbHD/rc9ZbSfCitpc1zP9HE35n Cancel-Lock: sha1:+DnXFJYXDQqgecW/B15BEW19HX8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4540 On 12/14/2010 4:56 AM, rickman wrote: [snip] >> I am sorry but I disagree with you on this point. There are "good >> practices" that help a lot in guaranteeing the quality of your project. > > I never said testing isn't useful. I said that testing can't assure > that something works unless you test every possible condition and that > is not possible in an absolute sense. > I don't get that. What you call as "every possible condition" is intended as every possible state of a particular set of logic. If your logic cannot be described as a well defined number of states then I agree that testing will never be enough (but in this case I suggest a rework of the design). If your states are not controllable (i.e. by an external control signal) then there's little you can do in testing. If your states are even not observable then I believe you are "doomed" (as somebody said earlier...). > Besides, you snipped the OP's comment I was responding to... > > "the design seems to be working fine in hardware although I haven’t > made any extensive tests yet." > I snipped the OP's comment because didn't add anything that wasn't already said in your sentence. > The problem we are discussing is ***exactly*** the sort of thing you > may not find in testing. The way the OP has constructed the circuit > it may work in 99.99% of the systems he builds. Or it may work 99.99% > of the time in all of the systems. But testing can't validate timing > since you can't control all of the variables. > This is why the way OP constructed the circuit was suboptimal and that is why it was suggested not to use a generated clock, but an enable signal (or even clock the UART with the original 25MHz clock). > The only thing testing can really do is to verify that your design > meets your requirements... if your requirements are testable! If something cannot be testable, how would you accept those requirements? And how can than be said the system doesn't work? according to which requirement violation? > >> I believe that coding is just part of the story. Having the possibility >> to test the design by a different team from the designers one will make >> a huge difference. > > "a huge difference"... I understand there are lots of ways to improve > testing, but that doesn't change the fundamental limitation of > testing. > The fundamental limitation of testing are most probably due to a very poor description of the device under test. That is why documentation should be the first step in a work flow, rather then the last one where the designer tend to leave out all the "unnecessary" details which eventually lead to misunderstanding. How hard is to test one single flip-flop? Not much, only because if fully described. >> >> http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > > I'm not sure what to say about this article. It is actually a bit > shallow in my opinion. But it also contains errors! Much of it is > really just the opinion of the author. > Could you please post the errors? Since I haven't found them, most probably your reading was deeper than mine and it would be very helpful to me. The author not only gives an opinion, it lays down an approach which is at a higher level of abstraction than the flops and gates. > > I think that terms like "good practices" are some of the least useful > concepts I've ever seen. First, where are "good practices" defined? In many books, standards, proceedings, articles and you may be lucky that your company has already defined a set of them. > Without a clear, detailed definition of the term, it doesn't > communicate anything. Usually it is used to mean "what I do". It may > be defined within a company, in some limited ways it may be defined > within a sector. But in general this is a term that has little > meaning as used by most people. This is much like recommending to > design "carefully". I can't say how many times I have seen that word > used in engineering without actually saying anything. > Usually it means "what most of the people do" as opposed of what you suggested. Of course circumstances and requirements maybe some how very demanding but an alternative architectural approach will surely have an higher impact. > >>> I recently discussed a multiple clock design with my customer. He >>> said he had more than 50 clocks in this design and wanted details on >>> how I deal with syncing multiple clock domains. I explained that I do >>> all my work in one clock domain and use a particular logic circuit to >>> transport clocks, enables and data into that one domain. I solve the >>> synchronization problem once at the interface and never have to worry >>> about it again. >> >> I would recommend an alternative to the 50 clocks domains, instead. > > What alternative would that be??? Is that different than the solution > I recommended? > As in the OP example, instead of suggesting how to control the timing of the clk_250k I would recommend not to use it at all (that means one clock less). > Rick From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w21g2000vby.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 13:35:19 -0800 (PST) Organization: http://groups.google.com Lines: 156 Message-ID: <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292448920 14547 127.0.0.1 (15 Dec 2010 21:35:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 21:35:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w21g2000vby.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4541 On Dec 15, 2:50=A0pm, Alessandro Basili wrote: > On 12/14/2010 4:56 AM, rickman wrote: > > I never said testing isn't useful. =A0I said that testing can't assure > > that something works unless you test every possible condition and that > > is not possible in an absolute sense. > > I don't get that. What you call as "every possible condition" is > intended as every possible state of a particular set of logic. If your > logic cannot be described as a well defined number of states then I > agree that testing will never be enough (but in this case I suggest a > rework of the design). > If your states are not controllable (i.e. by an external control signal) > then there's little you can do in testing. If your states are even not > observable then I believe you are "doomed" (as somebody said earlier...). If you are only talking about testing logic, yes, you can do that exhaustively assuming a few conditions. But testing in general takes on a lot more than that and the condition the OP was not a logic issue, rather it would depend on uncontrolled variables and potentially very intermittent. > > Besides, you snipped the OP's comment I was responding to... > > > "the design seems to be working fine in hardware although I haven t > > made any extensive tests yet." > > I snipped the OP's comment because didn't add anything that wasn't > already said in your sentence. It gave the context. Without the relevant context, which seems to be the issue we are not communicating on, the points mean nothing. > > The problem we are discussing is ***exactly*** the sort of thing you > > may not find in testing. =A0The way the OP has constructed the circuit > > it may work in 99.99% of the systems he builds. =A0Or it may work 99.99= % > > of the time in all of the systems. =A0But testing can't validate timing > > since you can't control all of the variables. > > This is why the way OP constructed the circuit was suboptimal and that > is why it was suggested not to use a generated clock, but an enable > signal (or even clock the UART with the original 25MHz clock). > > > The only thing testing can really do is to verify that your design > > meets your requirements... if your requirements are testable! > > If something cannot be testable, how would you accept those > requirements? And how can than be said the system doesn't work? > according to which requirement violation? > > > > >> I believe that coding is just part of the story. Having the possibilit= y > >> to test the design by a different team from the designers one will mak= e > >> a huge difference. > > > "a huge difference"... I understand there are lots of ways to improve > > testing, but that doesn't change the fundamental limitation of > > testing. > > The fundamental limitation of testing are most probably due to a very > poor description of the device under test. That is why documentation > should be the first step in a work flow, rather then the last one where > the designer tend to leave out all the "unnecessary" details which > eventually lead to misunderstanding. How hard is to test one single > flip-flop? Not much, only because if fully described. > > > > >>http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > > > I'm not sure what to say about this article. =A0It is actually a bit > > shallow in my opinion. =A0But it also contains errors! =A0Much of it is > > really just the opinion of the author. > > Could you please post the errors? Since I haven't found them, most > probably your reading was deeper than mine and it would be very helpful > to me. > The author not only gives an opinion, it lays down an approach which is > at a higher level of abstraction than the flops and gates. I don't have time to do that now. Maybe I can come back to this over the weekend. > > I think that terms like "good practices" are some of the least useful > > concepts I've ever seen. =A0First, where are "good practices" defined? > > In many books, standards, proceedings, articles and you may be lucky > that your company has already defined a set of them. My experience is that most "good practices" are really just experience. When they are "codified" they often loose their impact because of being applied poorly. Yes, "good practices" is clearly good. But it is a term that has no real definition except within some specific context and so is not really useful in a conversation about a concrete issue. > > Without a clear, detailed definition of the term, it doesn't > > communicate anything. =A0Usually it is used to mean "what I do". =A0It = may > > be defined within a company, in some limited ways it may be defined > > within a sector. =A0But in general this is a term that has little > > meaning as used by most people. =A0This is much like recommending to > > design "carefully". =A0I can't say how many times I have seen that word > > used in engineering without actually saying anything. > > Usually it means "what most of the people do" as opposed of what you > suggested. Of course circumstances and requirements maybe some how very > demanding but an alternative architectural approach will surely have an > higher impact. I see no value in doing "what most people do". I have seen the same mistakes made over and over with people reciting their mantras. Mostly these mistakes are just time wasters, but they are mistakes none the less. I expect you will ask me for an example. One I see often is the poor application of decoupling caps on devices. Many people use all sorts of rules of thumb and claim that their rule must not be violated or you aren't using "good practices". Meanwhile the electric fields ignore their good practices and instead obey the laws of physics. > >>> I recently discussed a multiple clock design with my customer. =A0He > >>> said he had more than 50 clocks in this design and wanted details on > >>> how I deal with syncing multiple clock domains. =A0I explained that I= do > >>> all my work in one clock domain and use a particular logic circuit to > >>> transport clocks, enables and data into that one domain. =A0I solve t= he > >>> synchronization problem once at the interface and never have to worry > >>> about it again. > > >> I would recommend an alternative to the 50 clocks domains, instead. > > > What alternative would that be??? =A0Is that different than the solutio= n > > I recommended? > > As in the OP example, instead of suggesting how to control the timing of > the clk_250k I would recommend not to use it at all (that means one > clock less). I'm not sure we are communicating on this one. That is what I told my customer, use one clock on the inside and cross the clock domain at the interface. This often makes the design much simpler and in the customer's design allows the tools to figure out much simpler timing and routing constraints. Rick From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 13:46:53 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292449614 20760 127.0.0.1 (15 Dec 2010 21:46:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 21:46:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prn.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4542 On Dec 15, 1:40=A0pm, Andy wrote: > To be able to "know" what hardware you are going to get requires > having a language and description that, from the same code, will > always produce the exact same logic, regardless of required > performance, space, and target architecture. Unfortunately it also > means having a language and description which will not produce > reasonably optimal hardware over all combinations of those same > constraints, given the same code. You can't have it both ways. I don't think you conclusions come from the facts. An HDL can unambiguously describe a counter with a carry out and allow that counter and carry to implemented in any manner the device can support. If I am using a device that can't implement a counter, why would I attempt to describe a counter? How could any HDL code that counts possibly be portable in a system that can't implement a counter? > I think we may have a disconnect with regards to the meaning of > "higher level constructs". If you mean things like hierarchy, etc. I > agree that it should not get in the way of a deterministic hardware > description (and I don't think it does, though your methods of using > the language may not be optimal for this). Not only should hierarchical design not get in the way of deterministic design, it is mandatory, otherwise you *would* need to design every logic element. > However, I take "higher level constructs" as being those that support > a behavioral description ("what does the circuit do?", not "what is > the circuit?"), with necessarily less direct mapping to implemented > hardware. It is the use of these constructs that provides the > tremendous increase in productivity over past methods (more primitive > languages and schematics). You would not consider creating a word > processor or spreadsheet in assembler, so why would you create a > complex FPGA design with what amounts to a netlist? I think you are drawing too fine a line between behavioral and structural. I am not saying I want to design gates. I am saying I want to clearly know how my code will be implemented. No, I don't know exactly how this would be done, but like I've said before, when I figure it out, I'll start a company and get rich from it. The first step to developing something new is to realize that there is an opportunity. Some folks are trying to convince me that my editor is not adequate and I should consider another tool that "understands" the language. Before I will evaluate that, I have to recognize that I'm not happy with my editor. I think a lot of people are very complacent about their tools. I see things a bit differently. Rick From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e20g2000vbn.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 14:36:57 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> NNTP-Posting-Host: 77.218.224.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292452621 1207 127.0.0.1 (15 Dec 2010 22:37:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 22:37:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbn.googlegroups.com; posting-host=77.218.224.36; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.10 (maverick) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4543 > As in the OP example, instead of suggesting how to control the timing of > the clk_250k I would recommend not to use it at all (that means one > clock less). What are you're arguments against using the clk_250k apart from having one clock less? clk_25 is only used for generating the clk_250k. No data is passing from the clk_25 domain to the clk_250k domain and clk_250k is put on a low skew global clock net. /B From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 17:03:51 -0800 (PST) Organization: http://groups.google.com Lines: 42 Message-ID: <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292461432 15719 127.0.0.1 (16 Dec 2010 01:03:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Dec 2010 01:03:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4544 On Dec 15, 3:46=A0pm, rickman wrote: > On Dec 15, 1:40=A0pm, Andy wrote: > > > To be able to "know" what hardware you are going to get requires > > having a language and description that, from the same code, will > > always produce the exact same logic, regardless of required > > performance, space, and target architecture. Unfortunately it also > > means having a language and description which will not produce > > reasonably optimal hardware over all combinations of those same > > constraints, given the same code. You can't have it both ways. > > I don't think you conclusions come from the facts. =A0An HDL can > unambiguously describe a counter with a carry out and allow that > counter and carry to implemented in any manner the device can > support. =A0If I am using a device that can't implement a counter, why > would I attempt to describe a counter? =A0How could any HDL code that > counts possibly be portable in a system that can't implement a > counter? I don't think you understand that knowing whether a carry output is used or not is almost worthless if you don't know which way that carry output should be created, which then gets us back to performance, resources, and target architectures. You have a pre-conceived notion that using a carry output will, in all cases of performance, resources, and target architecture, be an optimal solution. This is simply not true. Using my method (count - 1 < 0), I have seen the same synthesis tool, for the same target architecture, use the the built-in carry-chain output (shared), use combination of sub-carry outputs and LUTS, and just LUTS, depending on what it thought would be optimal (and when I checked them, I found it had made very good choices!) I would prefer the synthesis tools figure out for themselves that if I am testing the output of a down counter with count=3D0 (which is more readable/ understandable than count-1<0), it could use a carry out if it was optimal. I would really prefer that it figure out that, if count is not used anywhere else, it could translate a behavior of counting from 1 to n (which is even more readable/understandable) into a down counter from n-1 to zero (if doing so would be more optimal). But these are synthesis tool issues, not language issues. Andy From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 21:30:54 -0800 Organization: solani.org Lines: 41 Message-ID: <20101215213054.2cdbe4d2@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292477455 6726 eJwNwoERADEEBMCWiBxSjuH0X8L/7MJcveM6/GJ/KRbHsue0CbHJN4znqISt0KaHNVpasrwfFg8Rkw== (16 Dec 2010 05:30:55 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Thu, 16 Dec 2010 05:30:55 +0000 (UTC) X-User-ID: eJwFwYEBwDAEBMCVCP4ZR7T2HyF3YVAMHQGPjYWJZLcS8C+rKcZhnX9wQ7c7a+bcAuE20Q8IFhCr X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Vib3wtTiFvhcNSKbzQy9XsDfpno= X-NNTP-Posting-Host: eJwNx8EBwCAIA8CVEEyAcRBl/xHa+x2Mi+2b4MZgdKtzsvj+Vrlckah811JaPSas8xxHBHS1fxVoELU= Xref: feeder.eternal-september.org comp.lang.vhdl:4545 On Wed, 15 Dec 2010 19:02:09 +0100 Alessandro Basili wrote: > On 12/14/2010 5:40 AM, Christopher Head wrote: > > On Mon, 13 Dec 2010 00:23:30 +0100 > > Alessandro Basili wrote: > > > >> http://mysite.ncnetwork.net/reszotzl/uart.vhd > >> > >> Al > >> > >> > > > > Am I missing something, or is the transmitter slightly flawed in > > this code? I seem to see the following: > [snip] > > 4. From this moment, if the application queries the status register, > > you will see that TxState_v is IDLE and hence report transmitter > > ready. > > I believe only 1 clock after TxState_v is IDLE, hence you have a 1 > bit stop. > > > The application could thus immediately strobe another byte of data > > into the transmit data register. Then tx_state will transition to > > TxState_v = START and, on the next clock, set serial_out_v to '0'. > > > > The application needs to read the 0x04 as status register and if you > check the zoom file you find that read_data_v is 0x04 only one clock > after the TxState_v is idle. Hence the 1 bit stop is guaranteed. > > Al Each bit is actually three clocks wide. As I pointed out in my other message, you can't actually stomp on the stop bit at these particular choices of timing, but the UART code nowhere suggests that it's only usable with values of (clocks/baud) <= 3. Why else would tic_per_bit_g be a generic parameter instead of a constant? Chris From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!news2.glorb.com!postnews.google.com!15g2000vbz.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 06:00:52 -0800 (PST) Organization: http://groups.google.com Lines: 7 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292508052 22221 127.0.0.1 (16 Dec 2010 14:00:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Dec 2010 14:00:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 15g2000vbz.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4547 I haven't seen the code, but this would be an excellent place to use a range constraint on the generic tic_per_bit_g. Failing that, a concurrent assertion that verifies useable values of the generic(s) would work. It could actually work better than a range constraint if there are interdependencies between the values of multiple generics. Andy From newsfish@newsfish Fri Dec 24 22:56:02 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 12:12:40 -0800 Lines: 16 Message-ID: <8mva5lFvlqU1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /Cc0sv9LVChCLcrveTT6OwWMipIzWG53z1CNRRfDbQC8RJ5oQv Cancel-Lock: sha1:8MYVysTExBxfxwKGGhmrteClhbg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <20101215213054.2cdbe4d2@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4548 On 12/15/2010 9:30 PM, Christopher Head wrote: > Each bit is actually three clocks wide. As I pointed out in my other > message, you can't actually stomp on the stop bit at these particular > choices of timing, but the UART code nowhere suggests that it's only > usable with values of (clocks/baud)<= 3. Why else would tic_per_bit_g > be a generic parameter instead of a constant? This example works fine for baud rates slower than two ticks per bit. I left it a constant so I could play with it without having to explain it. Chris, you have the source and a testbench, so feel free to make any changes you like. My goal was only to demonstrate that variables may be used for synthesis of luts and flops. -- Mike Treseler From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 13:03:13 -0800 Organization: solani.org Lines: 26 Message-ID: <20101216130313.49b0eb3c@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> <8mva5lFvlqU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292533394 16245 eJwFwYEBwDAEBMCVhPeNcQj2H6F3bjx8H+iEr+9W1kQoU29NU+KMFrtNDFCNRUNas4P3rf0sWxFh (16 Dec 2010 21:03:14 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Thu, 16 Dec 2010 21:03:14 +0000 (UTC) X-User-ID: eJwFwQENADAIAzBLI2cM5MAf/Et4yxMWVx4M53JlRVHrd57OlbzZ6EnHJLZRMiS7+YCt/BAaEKE= X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:BPLWv2PbAztajh2i+5243SfJyTA= X-NNTP-Posting-Host: eJwFwQcBwEAIBDBLUGblcAz/Ej4xcfYOdXO1s0tMoAsD1AqdfDy121npGbo8GSNlRj9dEB5KCxIY Xref: feeder.eternal-september.org comp.lang.vhdl:4549 On Thu, 16 Dec 2010 12:12:40 -0800 Mike Treseler wrote: > On 12/15/2010 9:30 PM, Christopher Head wrote: > > > Each bit is actually three clocks wide. As I pointed out in my other > > message, you can't actually stomp on the stop bit at these > > particular choices of timing, but the UART code nowhere suggests > > that it's only usable with values of (clocks/baud)<= 3. Why else > > would tic_per_bit_g be a generic parameter instead of a constant? > > This example works fine for baud rates slower than two ticks per bit. > I left it a constant so I could play with it without having to > explain it. Chris, you have the source and a testbench, so feel free > to make any changes you like. My goal was only to demonstrate that > variables may be used for synthesis of luts and flops. > > -- Mike Treseler > Oh, sure, it didn't cause any trouble. I read the code out of curiosity, liked the style, and then noticed what I thought looked like a possible problem and wondered if anyone had seen it. So, no big deal :) Chris From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 13:36:53 +0100 Lines: 20 Message-ID: <8n13r2FdueU1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net DXALSvhnTO7SU+HKjnR5hgsRU5AuI/uUFvq7IL1qvckZvivFtT Cancel-Lock: sha1:/cw2yivH9PhNx1p5ZfZ/Macz43o= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4551 On 12/15/2010 11:36 PM, Beppe wrote: >> As in the OP example, instead of suggesting how to control the timing of >> the clk_250k I would recommend not to use it at all (that means one> clock less). > > What are you're arguments against using the clk_250k apart from having > one clock less? clk_25 is only used for generating the clk_250k. No > data is passing from the clk_25 domain to the clk_250k domain and > clk_250k is put on a low skew global clock net. > I believe the reason of having an additional clock should be motivated. All what I see reduces portability and invalidates a simple behavioral description, since you need to instance the low skew clock directly in your description. What would be your gain instead? The direct use of clk_25 in your uart suits perfectly and the argument to reduce the amount of power consumption on a bunch of flops (what, like 50???) is not worth the effort. > /B From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!c2g2000yqc.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 05:43:26 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <6a78e56f-76d9-40a7-8c30-dbec6d2730ca@c2g2000yqc.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> <8n13r2FdueU1@mid.individual.net> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292593406 29588 127.0.0.1 (17 Dec 2010 13:43:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Dec 2010 13:43:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c2g2000yqc.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4552 Well, I can see the point of using an enable instead of a divided clock even if this clock is on a low skew clock net. It=92s good design practice and you don=92t introduce an additional clock. Fine. However, I think you should always question good design practice and understand why it=92s better to do it the =93good=94 way rather than the unknown, unexplored, uncommon, etc. way. At least if you want to get some deeper understanding of the subject. Also, what was good design practice yesterday is not always good design practice today. E.g. Xilinx have changed their recommended coding styles quite a lot since the introduction of the 6-input LUTs. > I believe the reason of having an additional clock should be motivated. > All what I see reduces portability and invalidates a simple behavioral > description, since you need to instance the low skew clock directly in > your description. What would be your gain instead? The direct use of > clk_25 in your uart suits perfectly and the argument to reduce the > amount of power consumption on a bunch of flops (what, like 50???) is > not worth the effort. How would it reduce portability? The DCM has already reduced the portability and I don=92t see how the clock divider would reduce it even more. Well, I can agree that instantiating a design element somehow invalidates a behavioral description (if that=92s what you meant), but how do you go through a design without instantiating a single vendor specific component? BTW, I didn=92t have to instantiate the BUFG, the tool inferred it! /B From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r8g2000prm.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 05:52:13 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292593933 9028 127.0.0.1 (17 Dec 2010 13:52:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Dec 2010 13:52:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r8g2000prm.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4553 On Dec 15, 5:36 pm, Beppe wrote: > > As in the OP example, instead of suggesting how to control the timing of > > the clk_250k I would recommend not to use it at all (that means one > clock less). > > What are you're arguments against using the clk_250k apart from having > one clock less? clk_25 is only used for generating the clk_250k. No > data is passing from the clk_25 domain to the clk_250k domain and > clk_250k is put on a low skew global clock net. I'm not trying to argue or convince you, so I don't have an argument. You asked for opinions, I am offering mine. I don't know how much logic you have in the various clock domains or if there are others. I think you have said there is very little in the 28 MHz domain, but I'm not at all clear on what is in the 25 MHz and 250 kHz domains. I know little about letting the timing tools figure out how to handle dual outputs from a DCM. Unless there is some compelling reason, I would use clock crossing logic going between any of these clock domains. On the other hand, it is entirely possible to use a single clock domain for the entire design. You have a 125 MHz clock domain which is a super set of each of the slower clocks. A clock does not need to be an integer multiple to use a clock enable. For that matter, it doesn't even need to be 2x. In this design if the Midi code uses a clock enable to set the rate, you could easily use the 28 MHz clock with a 25 MHz enable. But a lot depends on how much interface you have vs. the hassle of converting code to work with enabled clocks. Clock crossing logic is not large or complex. I mainly find it unpleasant in that it clutters up a design somewhat. A recent design I did had expanded an existing design running on a 12.288 MHz clock from off board PLL controlled based on an interface FIFO. So this clock had to be used to establish interface timing, both sides in fact. The code I was adding had to have a section that ran on a 32 MHz clock to operate a digital PLL for a third interface. I had planned to provide a clock crossing interface between the two new sections of logic. But at some point this became a PITA and I ended up making the entire new design run on the 32 MHz clock and turned the 12.288 into an enable for the two exiting interfaces. OTOH, the previous circuit was working fine and had little to do with the new circuit (different modes of operation) so it was left alone clocking off the 12.288. Yet another interface for configuration was clocked off the interface clock (sort of a bastard SPI) and was also not changed for the new section. So multiple clocks are not bad, but I find it easier to live with if I convert at the external interface and run on one clock as much as possible. Rick From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!news2.glorb.com!usenet.stanford.edu!ctu-gate!news.nctu.edu.tw!newsfeed.nthu.edu.tw!news.cs.nthu.edu.tw!MapleBBS From: ppacc.bbs@bbs.cs.nthu.edu.tw (ccapp) Newsgroups: comp.lang.vhdl Subject: =?big5?Q?=ABC=A6~=AC=A1=B0=CA=A5=F8=B9=BA=AEv=B0=F6=B0V=AFZ=A8=B3=B3t=C3z=BA=A1=A4=A4!=BF=F9=B9L=B3o=A6=B8=A6A=B5=A5=A5b=A6~?= Date: 24 Dec 2010 05:58:14 GMT Organization: ·¬¾ôÅ毸 Lines: 44 Message-ID: NNTP-Posting-Host: bbs.cs.nthu.edu.tw Mime-Version: 1.0 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: 8bit X-Trace: news.cs.nthu.edu.tw 1293169221 23264 140.114.87.5 (24 Dec 2010 05:40:21 GMT) X-Complaints-To: manager@cs.nthu.edu.tw NNTP-Posting-Date: Fri, 24 Dec 2010 05:40:21 +0000 (UTC) Xref: feeder.eternal-september.org comp.lang.vhdl:4555 ¢l±j¤j®v¸ê°}®e´N¦bCCAPP«C¦~¬¡°Ê¥ø¹º®v¡I ¢l    ¢l²{³õ¬¡°Ê¥ø¹ºª¾¯à¡A¥R¹q«ü¼ÆÅý§AÀþ¶¡º¡®æ¡I¡I<(¡Ã¡`¡Ã)b ¢l ¾÷·|¥i¹J¤£¥i¨D¡A¥»¦¸½Òµ{ÁÜ½Ð¨ì ¢~¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢¡  ¢x ªá³Õ³õÀ]³]­pªÌ¡G³¯«T¸q¦Ñ®v¡÷Åý§A·P¨ü¨ì¤å¤Æ³Ð·N²£·~ªº«Â¤O¡I¡I  ¢x ¢¢¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢£ ¢~¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢¡  ¢x ¥@³Õ¥xÆW¥N²z¶ø¬ü¤½Ãö¨Æ·~¡GÁÂÄɼz¦Ñ®v¡÷¶Kªñ¥@¬É¯Å¬¡°Ê¡I¡I¡I  ¢x ¢¢¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢£ ¢~¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢¡  ¢x ª¾¦W¼s§i¤½¥q¡u´N¬O¼s§i¡v³Ð·NÁ`ºÊ¡G¶À¤å³Õ¦Ñ®v¡÷³Ð·N¦æ¾P³N¡AÅý«È¤á¦Û°Ê¤Wªù¡I¢x ¢¢¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢w¢£ ÁܽЪñ15¦ì·~¬É¬¡°Ê¡BÆ[¥ú¡B®iÄý¡B¦æ¾P¡B¼s§i©M¤½Ãöª¾¦W¤½¥qCEO¶Ç±Â±M·~¯µÓD¡A²{³õ¹ê °È¾Þ§@Åý±z³þ©w¬¡°Ê¥ø¹º°ò¦¡C ------ CCAPP²Ä51¡B52´Á ´H°²¶}½Ò¡A³õ¦¸¦³­­ ¡m§ìºò®É¶¡¡A§Ú­n³ø¦W¡÷http://ppt.cc/evBY ¡n Àu´f®É¶¡¡G2010¦~12¤ë31¤é«e  ¡m±ýª¾§ó¦hÀu´f¸ê°T½Ð¬¢¡÷feng@planning.com.tw¡n ¡i¨É ­Ó¤HÀu´f¤K¤­§é¡j ¡i¤T¤H¥H¤W¹Î³ø§ó¨É¤C¤­§é³Ì¨ÎÀu´f + ¥[Ãج¡°Ê¥ø¹º¹ê¾Ô¿ý¡j ¡»¥R¹q®É¶¡¡»    51´Á¡G2011¦~1¤ë17(¤@)¡B18(¤G)¡B20(¥|)¡B21(¤­)¡B24(¤@) ¤õ³tÃzº¡¡I     52´Á¡G2011¦~1¤ë22(¤»)¡B23(¤é)¡B28(¤­)¡B29(¤»)¡B30(¤é) §Y±NÃBº¡¡I     »OÆW®v½d¤j¾Ç ¶i­×±À¼s³¡ ²±¤j¶}½Ò §Ö¤W¬¡°Êºô¯¸¡Ghttp://www.planning.com.tw/ccapp/ ½Òµ{¸ß°Ý02-23650930 -- ¡° Origin: ·¬¾ôÅ毸 ¡» From: ppacc @ 59-125-98-32.HINET-IP.hinet.net  From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Fri, 24 Dec 2010 16:51:24 +0000 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <8ma3hpF3caU1@mid.individual.net> <8mmsqvF12mU1@mid.individual.net> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="26846"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/AUett3Vj6KoPGwCrAHyvaynX8S5bFxNCXfiXWm3ZoDg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <8mmsqvF12mU1@mid.individual.net> Cancel-Lock: sha1:AbRlFTWuV8iPoTKtqqH2Lv88JTU= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.arch.fpga:13775 comp.lang.vhdl:4556 comp.lang.verilog:2735 Alessandro Basili sent on December 13th, 2010: |-------------------------------------------------------------------------------| |"On 12/10/2010 3:57 PM, Thomas Stanka wrote: | |[snip] | |> Open cores tend to have a lack in documentation and verification, | |> which is a no-go for developing space electronics. | | | |[..]" | |-------------------------------------------------------------------------------| Verification is not always tried, though it has been dishonestly claimed to have been achieved in publications such as Sergio Saponara; Francesco Vitullo; Esa Petri; and Luca Fanucci, "A Reusable Pseudo-Random Verification Environment for Complex Digital Designs: the SpaceWire Interface Case Study", IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications 21-23 September 2009, Rende (Cosenza), Italy. Testing some examples instead of proving is not verification. |--------------------------------------------------------------------------------| |"I just want to mention that on an FPGA based application the choice of the FPGA| |may guarantee certain level of radiation hardness," | |--------------------------------------------------------------------------------| Choose Aeroflex: WWW.Aeroflex.com/ams/pagesproduct/prods-hirel-fpga.cfm |-------------------------------------------------------------------------------| |" while specific design | |techniques may improve the level of hardness even further (TMR, [..]" | |-------------------------------------------------------------------------------| TMR could actually be harmful when using technologies with small feature sizes, if sufficient care is not taken: Blum and Delgado-Frias, "Schemes for Eliminating Transient-Width Clock Overhead From SET-Tolerant Memory-Based Systems", "I.E.E.E. Transactions on Nuclear Science", June 2006. |-------------------------------------------------------------------------------| |"[..] | | | |Even though I believe that Space Agencies around the world are politically and | |technically bond to follow standardization processes based mostly on lessons | |learned, [..] | |[..] | | | |[..]" | |-------------------------------------------------------------------------------| The European Space Agency does not adhere to its own standards. Yours sincerely, Paul Colin Gloster From newsfish@newsfish Fri Dec 24 22:56:03 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 18:35:13 +0000 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <4d07681e$0$14247$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="19278"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19BQ2Vo5oHbGFVeOaXYUVm3yUL88UULIbQi+c25SwHYBA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <4d07681e$0$14247$ba620e4c@news.skynet.be> Cancel-Lock: sha1:Q2lL4BSMfiWhdc+W5mWYHD/D0LE= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4557 Jan Decaluwe sent on December 14th, 2010: |---------------------------------------------------------------------| |"[..] | | | |I think Verilog will suit you better as a language, you really should| |consider switching one of these days. However, there is no reason why| |it would help you with the issues that you say you are seeing here." | |---------------------------------------------------------------------| He did try Verilog many months ago, but he has resumed with VHDL. From newsfish@newsfish Fri Dec 24 22:56:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 18:46:15 +0000 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx01.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="3594"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+CaUeNsV881PMSu0QITUeaJ9kZ5bx+YQhRB3ahxe8Pzg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> Cancel-Lock: sha1:+pHQEvnWyiT0+rGJjiiRJpOjH8c= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4558 Andy sent on December 15th, 2010: |----------------------------------------------------------------------| |"[..] | | | |[..] | |[..] You have a pre-conceived notion | |that using a carry output will, in all cases of performance, | |resources, and target architecture, be an optimal solution. This is | |simply not true. | | | |Using my method (count - 1 < 0), I have seen the same synthesis tool, | |for the same target architecture, use the the built-in carry-chain | |output (shared), use combination of sub-carry outputs and LUTS, and | |just LUTS, depending on what it thought would be optimal (and when I | |checked them, I found it had made very good choices!) [..] | |[..] | |[..] But | |these are synthesis tool issues, not language issues. | | | |Andy" | |----------------------------------------------------------------------| Yes, these are good examples of why Rick is naive to expect to know in advance the efficient output of a synthesizer. If one variable is always the sum of two other particular variables and these "variables" are always constant, then the corresponding hardware (if any) should naturally be less than for three changing variables. Rick was proposing something which in reality would be uniform and hence not generally efficient. From newsfish@newsfish Fri Dec 24 22:56:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 19:00:53 +0000 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="24946"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1857eN8/LnGS0dnp+zelTvnGO2eiIBymTC1cRCreY2EjA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> Cancel-Lock: sha1:R5b3Y/6LrZnBY1havfyUNycB4Co= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4559 Tricky sent on December 15th, 2010: |---------------------------------------------------------------------| |"[..] | |[..] The only way to know what will come out in advance | |is either with experience or instantiation. [..] | |[..] | | | |[..]" | |---------------------------------------------------------------------| It is not possible to know. From newsfish@newsfish Fri Dec 24 22:56:04 2010 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 19:44:44 +0000 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Injection-Info: mx01.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="16816"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fzECZARF0m1FAk/cV0mj2cf41GWy5opVcXVvFkbcYfg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> Cancel-Lock: sha1:J9C00uX93MYtbjKbVsMAfdU+02o= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4560 Rick Collins had sent on December 10th, 2010: |----------------------------------------------------------------------| |"[..] | | | |What I mean is, if I want a down counter that uses the carry out to | |give me an "end of count" flag, why can't I get that in a simple and | |clear manner? It seems like every time I want to design a circuit I | |have to experiment with the exact style to get the logic I want and it| |often is a real PITA to make that happen. | | | |[..] | | | |I guess what I am trying to say is I would like to be able to specify | |detailed logic rather than generically coding the function and letting| |a tool try to figure out how to implement it. [..] | |[..]" | |----------------------------------------------------------------------| On December 13th, 2010, Rick has claimed: |-----------------------------------------------------------------| |"[..] | | | |[..] | |[..] I am not saying I want to use something similar to assembly| |language [..] | |[..] | | | |[..]" | |-----------------------------------------------------------------| Rick Collins sent on December 14th, 2010: |---------------------------------------------------------------------| |"[..] | | | |[..] | |[..] Like I said somewhere else, if you want a | |particular solution, the vendors tell you to instantiate. | |Instantiation is very undesirable since it is not portable across | |vendors and often not portable across product lines within a vendor!"| |---------------------------------------------------------------------| As with many assembly languages for different models in a single processor family. |--------------------------------------------------------------------| |"The language is flexible, that's for sure. [..] | |[..]" | |--------------------------------------------------------------------| As flexible as Lisp or Confluence or Lava?